US20090096482A1 - Integrated circuit having a configurable logic gate - Google Patents
Integrated circuit having a configurable logic gate Download PDFInfo
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- US20090096482A1 US20090096482A1 US11/872,831 US87283107A US2009096482A1 US 20090096482 A1 US20090096482 A1 US 20090096482A1 US 87283107 A US87283107 A US 87283107A US 2009096482 A1 US2009096482 A1 US 2009096482A1
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- integrated circuit
- request
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- power domain
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
Abstract
Description
- This description relates to integrated circuits that may share a common resource.
- An electronic device may use multiple integrated circuits on a printed circuit board (PCB) that provide various functions to operate the electronic device. For example, in a cellular phone there may be a cellular baseband integrated circuit and a Bluetooth/WLAN (wireless local area network) integrated circuit on the printed circuit board.
- The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims.
-
FIG. 1 is an exemplary block diagram illustrating an example system for integrated circuits to share a common resource. -
FIG. 2 is an exemplary block diagram illustrating an example system for integrated circuits to share a common resource. -
FIG. 3 is an exemplary block diagram of a circuit board illustrating an example system for integrated circuits to share a common resource. -
FIG. 4 is an exemplary flowchart illustrating a process for sharing a common external resource. - In general, a system may include multiple integrated circuits that may be configured and arranged to access a common resource that may be external to the integrated circuits. At least one of the multiple integrated circuits may include a logic gate that is configured to receive internal requests and external requests from the other integrated circuits for access to the external resource. The integrated circuit with the logic gate may include multiple power domains. The operation of the logic gate may reside in a power domain that is tied to a system or PCB level power, such that the operation of the logic gate does not require powering up or waking up the entire integrated circuit on which the logic gate resides. Thus, for example, the multiple integrated circuits may share access to a common external resource through the operation of a logic gate on just one of the integrated circuits. An external request for access to the common external resource may be processed through the logic gate on one of the integrated circuits without having to power up the integrated circuit. A system configured in this exemplary manner may reduce the overall power consumption of the system and may reduce the overall number of components in a system making it a more cost efficient solution.
- Referring to
FIG. 1 , acircuit board 100 includesintegrated circuit 102,integrated circuit 104 andexternal resource 106.Circuit board 100 may include a printed circuit board (PCB) or any other type of circuit board that is configured for use in any type of device including, for example, a cellular phone, a personal digital assistant (PDA), a computer, an MP3 player, an iPod® mobile digital device, and any other type of device that may use a circuit board.Circuit board 100 may provide one or more functions for the operation of a device.Circuit board 100 is exemplary in illustration and may include other components that are not shown. -
Integrated circuit 102 may be attached to, mounted on or otherwise made a part of thecircuit board 100.Integrated circuit 102 may be configured to provide one or more functions for thecircuit board 100 that may contribute to the operation of a device. -
Integrated circuit 104 may be attached to, mounted on or otherwise made a part of thecircuit board 100.Integrated circuit 104 may be configured to provide one or more functions for thecircuit board 100 that may contribute to the operation of a device.Integrated circuit 104 may be an integrated circuit that is separate fromintegrated circuit 102. In one exemplary implementation,integrated circuit 104 may be configured to provide functions that are different fromintegrated circuit 102. In other exemplary implementations,integrated circuit 104 may provide the functions that are the same as or functions that overlap withintegrated circuit 102.Integrated circuit 104 andintegrated circuit 102 may be configured to operate on thesame circuit board 100 and may be configured to communicate with each other or otherwise connected to each other through thecircuit board 100. - In other exemplary implementations,
integrated circuit 102 andintegrated circuit 104 may be a part of the same integrated circuit component to provide the functionality of both integrated circuits in a single integrated circuit. -
External resource 106 may be a component that may be attached to, mounted on or otherwise made a part of thecircuit board 100.External resource 106 may be a component on thecircuit board 100 that is commonly shared byintegrated circuit 102 andintegrated circuit 104. Sharing theexternal resource 106 byintegrated circuit 102 andintegrated circuit 104 may eliminate any need or requirement for eachintegrated circuit circuit board 100. The reduction of the number of components on thecircuit board 100 may realize a cost savings for the production of thecircuit board 100. Sharing theexternal resource 106 also may reduced the overall system power consumption.External resource 106 may include any type of component that may be used on a circuit board including, for example, an integrated circuit, a clock source, or any other type of component. -
Integrated circuit 104 may include multiple power domains such that afirst section 108 of theintegrated circuit 104 is part of a first power domain and asecond section 110 of theintegrated circuit 104 is part of a second power domain.Integrated circuit 104 may include more than two power domains with components of the integrated circuit being located in different power domains. Multiple power domains may enable theintegrated circuit 104 to be configured to operate different parts of the circuit at different power levels and to receive the power for the different power domains from different power sources. For example, thefirst section 108 that may be powered by the first power domain may operate at a different power level than thesecond section 110 that may be powered by the second power domain. The power source for thefirst section 108 also may be different than the power source for thesecond section 110. Multiple power domains that have different power sources may enable an integrated circuit to be configured such that just a portion of the integrated circuit needs to be powered up when a particular component on the integrated circuit is used. - In one exemplary implementation, the
first section 108 may be within an input/output (I/O) power domain and thesecond section 110 may be within a core power domain. For example, the I/O power domain may operate at a lower power level than the core power domain. The I/O power domain and the core power domain also may receive power from different power sources. For instance, the I/O power domain may receive power from circuit board 100 (e.g., voltage, vddo, at the PCB level) and the core power domain may receive power from within the integratedcircuit 104. Since thefirst section 108 may be within the I/O power domain, thefirst section 108 may be powered up independently and separate from thesecond section 110 and any other sections that may exist. Thus, thesecond section 110 may remain in a powered down or sleep state when thefirst section 108 is powered up. -
Integrated circuit 104 may include alogic gate 112.Logic gate 112 may include an OR gate, an AND gate, a NAND gate or any other type of logic gate. In one exemplary implementation,logic gate 112 may be located within thefirst section 108 of theintegrated circuit 104 and within the first power domain. In one exemplary implementation, thelogic gate 112 may be configured to receive and process requests fromintegrated circuit 102 and integratedcircuit 104 for access toexternal resource 106. For instance, thelogic gate 112 may receive and processexternal requests 114 fromintegrated circuit 102 andinternal requests 116 fromintegrated circuit 104 for access to the commonexternal resource 106. Theexternal resource 106 may provide a function or services to the requesting integrated circuit in response to the request. -
Logic gate 112 may be configurable to receive and processexternal requests 114 andinternal requests 116 of different or opposite polarities. For instance,logic gate 112 may be configurable to receive and processexternal requests 114 andinternal requests 116 that are either an active high request or an active low request. For example, if integratedcircuit 102 is designed to request theexternal resource 106 using an active high request, thenlogic gate 112 may be configured to receive and process theexternal request 114 as an active high request. Alternatively, for example, if integratedcircuit 102 is designed to request theexternal resource 106 using an active low request, thenlogic gate 112 may be configured to receive and process theexternal request 114 as an active low request. In this manner, for instance, if integratedcircuit 102 andintegrated circuit 104 are manufactured and designed by different entities, then thelogic gate 112 on theintegrated circuit 104 may be configured to receive and process anexternal request 114 fromintegrated circuit 102 without have to change the design ofintegrated circuit 102 or reconfigure howintegrated circuit 102 requestsexternal resource 106. - In one exemplary implementation,
external resource 106 may be a clock source and thelogic gate 112 may be an OR gate.Integrated circuit 102 andintegrated circuit 104 may share the same clock source by sending requests for the clock source through the OR gate located in thesecond section 110 of theintegrated circuit 104. For instance, when integratedcircuit 102 wants to request access to the clock source, integratedcircuit 102 sends anexternal request 114 to the OR gate located onintegrated circuit 104. The OR gate may be located in thefirst section 108 of theintegrated circuit 104, where thefirst section 108 may be powered by the I/O power domain. The OR gate receives and processes theexternal request 114 and sends the request to the clock source. The clock source receives the request and provides a clocking function to theintegrated circuit 102. - In the above exemplary implementation, if the
first section 108 is powered in the I/O power domain, then theexternal request 114 may be received and processed by the OR gate without waking up or powering upintegrated circuit 104 or at the least by just partially powering upintegrated circuit 104. Thus, integratedcircuit 102 may request the OR gate through integratedcircuit 104 without waking up or powering upintegrated circuit 104 or at the least by only partially powering upintegrated circuit 104. - In one exemplary implementation, integrated
circuit 104 may be configured to operate in one or more modes. For example, integratedcircuit 104 may be configured to operate in a mode that uses the functionality of thelogic gate 112. Alternatively, integratedcircuit 104 may be configured to operate in a mode that does not use the functionality of thelogic gate 112 even though thelogic gate 112 is present on theintegrated circuit 104. - Referring to
FIG. 2 ,circuit board 200 is illustrated.Circuit board 200 includes cellular baseband integratedcircuit 202, Bluetooth integratedcircuit 204 and aclock source 206. In this exemplary implementation,circuit board 200 may be a circuit board that is included in a cellular phone device or any other electronic device that includes a cellular baseband integratedcircuit 202 and a Bluetooth integratedcircuit 204.FIG. 2 is provided as an exemplary illustration and is not meant to be limiting in any manner. - Cellular baseband integrated
circuit 202 may be attached to, mounted on or otherwise made a part of thecircuit board 200. Cellular baseband integratedcircuit 202 may be configured to provide one or more cellular baseband-related functions to the operation of a device. - Bluetooth integrated
circuit 204 may be attached to, mounted on or otherwise made a part of thecircuit board 200. Bluetooth integratedcircuit 204 may be configured to provide one or more Bluetooth-related functions to the operation of the device. Bluetooth integratedcircuit 204 may be an integrated circuit that is separate from cellular baseband integratedcircuit 202. In other exemplary implementations, cellular baseband integratedcircuit 202 and Bluetooth integratedcircuit 204 may be a part of the same integrated circuit component to provide the functionality of both integrated circuits in a single integrated circuit. -
Clock source 206 may be attached to, mounted on or otherwise made a part of thecircuit board 200.Clock source 206 may be a single clock source that is configured to provide clocking functions to both cellular baseband integratedcircuit 202 and Bluetooth integratedcircuit 204. Sharing theclock source 206 by cellular baseband integratedcircuit 202 and Bluetooth integratedcircuit 204 may eliminate any need or requirement for each circuit to have a dedicated clock source. This may lead to a reduction of the number components oncircuit board 200. The reduction of the number of components on thecircuit board 200 may realize a cost savings for the production of thecircuit board 200 and/or also may realize a reduction in the overall system power consumption. In one exemplary implementation, theclock source 206 includes a temperature compensation crystal oscillator (TCXO). - Bluetooth integrated
circuit 204 may include multiple power domains such that afirst section 208 of the Bluetooth integratedcircuit 204 is part of a first power domain and asecond section 210 of theintegrated circuit 204 is part of a second power domain. Bluetooth integratedcircuit 204 may include more than two power domains with components of the integrated circuit being located in different power domains. Multiple power domains may enable the Bluetooth integratedcircuit 204 to be configured to operate different parts of the circuit at different power levels and to receive the power for the different power domains from different power sources. For example, thefirst section 208 that may be powered by the first power domain may operate at a different power level than thesecond section 210 that may be powered by the second power domain. The power source for thefirst section 208 also may be different than the power source for thesecond section 210. Multiple power domains that have different power sources may enable an integrated circuit to be configured such that just a portion of the integrated circuit needs to be powered up when a particular component on the integrated circuit is used. - In one exemplary implementation, the
first section 208 may be within an input/output (I/O) power domain and thesecond section 210 may be within a core power domain. For example, the I/O power domain may operate at a lower power level than the core power domain. The I/O power domain and the core power domain also may receive power from different power sources. For instance, the I/O power domain may receive power fromcircuit board 200 and the core power domain may receive power from within the Bluetooth integratedcircuit 204. Since thefirst section 208 may be within the I/O power domain, thefirst section 208 may be powered up independently and separate from thesecond section 210 and any other sections that may exist. Thus, thesecond section 210 may remain in a powered down or sleep state when thefirst section 208 is powered up. - Bluetooth integrated
circuit 204 includes an ORlogic gate 212. In one exemplary implementation, theOR logic gate 212 may be configured to receive and process requests from cellular baseband integratedcircuit 202 and Bluetooth integratedcircuit 204 for access toclock source 206. For instance, theOR logic gate 212 may receive and processexternal requests 214 from cellular baseband integratedcircuit 202 andinternal requests 216 from Bluetooth integratedcircuit 204 for access to thecommon clock source 206. Theclock source 206 may provide a clocking function to the requesting integrated circuit in response to the request. The ORlogic gate 212 may be located in thefirst section 208 of the Bluetooth integratedcircuit 204, where thefirst section 208 may be powered by the I/O power domain. The ORlogic gate 212 receives and processes theexternal request 214 and sends the request to theclock source 206. Theclock source 206 receives the request and provides a clocking function to the baseband integratedcircuit 202. - In the above exemplary implementation, if the
first section 208 is powered in the I/O power domain, then theexternal request 214 may be received and processed by theOR logic gate 212 without waking up or powering up Bluetooth integratedcircuit 204 or at the least by just partially powering up Bluetooth integratedcircuit 204. Thus, baseband integratedcircuit 202 may request theOR logic gate 212 through Bluetooth integratedcircuit 204 without waking up or powering up Bluetooth integratedcircuit 204 or at the least by only partially powering up Bluetooth integratedcircuit 204. - OR
logic gate 212 may be configurable to receive and processexternal requests 214 andinternal requests 216 of different or opposite polarities. For instance, ORlogic gate 212 may be configurable to receive and processexternal requests 214 andinternal requests 216 that are either an active high request or an active low request. For example, if cellular baseband integratedcircuit 202 is designed to request theclock source 206 using an active high request, then ORlogic gate 212 may be configured to receive and process theexternal request 214 as an active high request. Alternatively, for example, if cellular baseband integratedcircuit 202 is designed to request theclock source 206 using an active low request, then ORlogic gate 212 may be configured to receive and process theexternal request 214 as an active low request. In this manner, for instance, if cellular basedintegrated circuit 202 and Bluetooth integratedcircuit 204 are manufactured and designed by different entities, then theOR logic gate 212 on the Bluetooth integratedcircuit 204 may be configured to receive and process anexternal request 214 from cellular baseband integratedcircuit 202 without have to change the design of cellular baseband integratedcircuit 202 or reconfigure how cellular baseband integratedcircuit 202requests clock source 206. - In one exemplary implementation, Bluetooth integrated
circuit 204 may be configured to operate in one or more modes. For example, Bluetooth integratedcircuit 204 may be configured to operate in a mode that uses the functionality of theOR logic gate 212. Alternatively, Bluetooth integratedcircuit 204 may be configured to operate in a mode that does not use the functionality of theOR logic gate 212 even though theOR logic gate 212 is present on the Bluetooth integratedcircuit 204. - In other exemplary implementations, cellular baseband integrated
circuit 202 and Bluetooth integratedcircuit 204 may share theclock source 206, but with theOR logic gate 212 located on the cellularintegrated circuit 202 instead of on the Bluetooth integratedcircuit 204. - In other exemplary implementations, cellular baseband integrated
circuit 202 and Bluetooth integratedcircuit 204 may share theclock source 206, but with theOR logic gate 212 located on both the cellularintegrated circuit 202 and on the Bluetooth integratedcircuit 204. In this exemplary implementation, the integrated circuits may be set in different modes, with one of the integrated circuits configured to operate in a mode where theOR logic gate 212 is active and the other integrated circuit configured to operate in a mode where theOR logic gate 212 is inactive, even though theOR logic gate 212 is present on that integrated circuit. - Referring to
FIG. 3 , acircuit board 300 includesintegrated circuit 302, integratedcircuit 304 andexternal resource 306 that may, for example, operate and function likecircuit board 100, integratedcircuit 102, integratedcircuit 104 andexternal resource 106 as described above with respect toFIG. 1 . Thus, for example, integratedcircuit 302 andintegrated circuit 304 may share a common external resource, where alogic gate 312 onintegrated circuit 304 may receive and processexternal requests 314 fromintegrated circuit 302 andinternal requests 316 fromintegrated circuit 304 for access toexternal resource 306. -
Integrated circuit 304 may include one or more pads such as, for example,pad 1 320,pad 2 322,pad 3 324 andpad 4 326. Thepads pads first section 308 in the I/O power domain and asecond section 310 in the core power domain. In one exemplary implementation, thefirst section 308 may be at a first voltage level and thesecond section 310 may be at a second voltage level. In one implementation, thefirst section 308 associated with the I/O power domain may be tied to ground or the voltage (e.g., vddo) at thecircuit board 300 level. Components or functions that operate or perform in thefirst section 308 may need power only from the I/O power domain in order to operate. -
Pad 1 320 may include aconnection pad 328 to receive an input for theexternal request 314 fromintegrated circuit 302.Pad 1 320 also may include amode switch 330 that may operate to switchpad 1 320 between a normal mode and a mode that directs theexternal request 314 through abuffer 332 to pad 2 322. -
Pad 2 322 may include alevel shifter 334 that receives an input for theinternal request 316 and that shifts the voltage level from the core power domain in thesecond section 310 to the voltage level in the I/O power domain in thefirst section 308.Pad 2 322 also includeslogic gate 312.Logic gate 312 may include any type of logic gate. In one exemplary implementation,logic gate 312 includes an OR logic gate.Pad 2 322 includes aconnection point 336 that may tiepad 2 322 either to ground or to vddo at thecircuit board 300 level.Pad 2 322 includes amode function gate 338 that may be configured to control the modes of operation of thepads pad 2 322 is tied to ground, thenmode function gate 338 sends a signal to pad 1 320 andpad 3 324 to operate in a normal mode. Whenpad 2 322 is tied to vddo, thenmode function gate 338 sends a signal to pad 1 320 andpad 3 324 to operate in a mode that enables theexternal requests 314 andinternal requests 316 to be received and processed through thelogic gate 312 to requestexternal resource 306. -
Pad 3 324 includes amode switch 340 that may operate to switchpad 3 324 between a normal mode and a mode that directs the output oflogic gate 312 out through aconnection point 342 toexternal resource 306. -
Pad 4 326 includes apolarity output 344 that may be used as an input tologic gate 312 to control the polarity input recognized by thelogic gate 312. For example,logic gate 312 may be configured to receive an active high polarity or an active low polarity. - In one exemplary implementation, the
external resource 306 may include a clock source and thelogic gate 312 may include an OR logic gate. When integratedcircuit 302 needs to request theclock source 306, anexternal request 314 is sent to pad 1 320 throughconnection point 328. Theexternal request 314 may go throughbuffer 332 and then to ORlogic gate 312 onpad 2 322. The ORlogic gate 312 then sends the request for theclock source 306 throughpad 3 324 throughconnection point 342. In this exemplary implementation,pad 2 322 may be tied to vddo throughconnection point 336 and the I/O power domain may provide the power for theOR logic gate 312 to receive and process theexternal request 314 such thatintegrated circuit 304 does not need to be powered up to handle theexternal request 314. When integratedcircuit 304 needs to request theclock source 306, aninternal request 316 is sent tolevel shifter 334 and then to ORlogic gate 312. ORlogic gate 312 may receive and process the request and send the request for theclock source 306 throughpad 3 324 throughconnection point 342. - Referring to
FIG. 4 , anexemplary process 400 is illustrated for sharing a common external resource.Process 400 may include generating an internal request at an integrated circuit for a common external resource for use by the integrated circuit (402), receiving at the integrated circuit an external request for the common external resource (404), and processing at the integrated circuit the external request using power from an I/O power domain (406). - In one exemplary implementation, the common external resource may include a clock source. For instance,
external resource 106 ofFIG. 1 ,clock source 206 ofFIG. 2 andexternal resource 306 ofFIG. 3 are examples of the common external resource. The internal request that is generated for the common external resource (402) may include, for example, theinternal requests 116 ofFIG. 1 , 216 ofFIG. 2 , and 316 ofFIG. 3 that are generated byintegrated circuit 104 ofFIG. 1 , 204 ofFIG. 2 and 304 ofFIG. 3 , respectively. - The external request for the common external resource that is received at the integrated circuit (404) may include for example,
external request 114 ofFIG. 1 , 214 ofFIG. 2 and 314 ofFIG. 3 that is received atintegrated circuit 104 ofFIG. 1 , 204 ofFIG. 2 and 304 ofFIG. 3 , respectively. The external request may be processed at the integrated circuit using power from the I/O power domain (406) using, for example,logic gate 112 located in thefirst section 108 ofintegrated circuit 104, ORlogic gate 212 located in thefirst section 208 ofintegrated circuit 204, orlogic gate 312 located in the I/O power domain 308 ofintegrated circuit 304 ofFIGS. 1 , 2, and 3, respectively. - Implementations of the various techniques described herein may be implemented in digital electronic circuitry, or in computer hardware, firmware, software, or in combinations of them. Implementations may be implemented as a computer program product, i.e., a computer program tangibly embodied in an information carrier, e.g., in a machine-readable storage device or in a propagated signal, for execution by, or to control the operation of, data processing apparatus, e.g., a programmable processor, a computer, or multiple computers. A computer program, such as the computer program(s) described above, can be written in any form of programming language, including compiled or interpreted languages, and can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program can be deployed to be executed on one computer or on multiple computers at one site or distributed across multiple sites and interconnected by a communication network.
- Method steps may be performed by one or more programmable processors executing a computer program to perform functions by operating on input data and generating output. Method steps also may be performed by, and an apparatus may be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit).
- Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read-only memory or a random access memory or both. Elements of a computer may include at least one processor for executing instructions and one or more memory devices for storing instructions and data. Generally, a computer also may include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto-optical disks, or optical disks. Information carriers suitable for embodying computer program instructions and data include all forms of non-volatile memory, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks. The processor and the memory may be supplemented by, or incorporated in special purpose logic circuitry.
- To provide for interaction with a user, implementations may be implemented on a computer having a display device, e.g., a cathode ray tube (CRT) or liquid crystal display (LCD) monitor, for displaying information to the user and a keyboard and a pointing device, e.g., a mouse or a trackball, by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback, e.g., visual feedback, auditory feedback, or tactile feedback; and input from the user can be received in any form, including acoustic, speech, or tactile input.
- Implementations may be implemented in a computing system that includes a back-end component, e.g., as a data server, or that includes a middleware component, e.g., an application server, or that includes a front-end component, e.g., a client computer having a graphical user interface or a Web browser through which a user can interact with an implementation, or any combination of such back-end, middleware, or front-end components. Components may be interconnected by any form or medium of digital data communication, e.g., a communication network. Examples of communication networks include a local area network (LAN) and a wide area network (WAN), e.g., the Internet.
- While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the embodiments.
Claims (20)
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US9323312B2 (en) | 2012-09-21 | 2016-04-26 | Atmel Corporation | System and methods for delaying interrupts in a microcontroller system |
US9507406B2 (en) | 2012-09-21 | 2016-11-29 | Atmel Corporation | Configuring power domains of a microcontroller system |
US9383807B2 (en) | 2013-10-01 | 2016-07-05 | Atmel Corporation | Configuring power domains of a microcontroller system |
US9684367B2 (en) * | 2014-06-26 | 2017-06-20 | Atmel Corporation | Power trace port for tracing states of power domains |
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US7305646B2 (en) * | 2005-05-09 | 2007-12-04 | Lsi Corporation | Relocatable mixed-signal functions |
US7369815B2 (en) * | 2003-09-19 | 2008-05-06 | Qualcomm Incorporated | Power collapse for a wireless terminal |
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US6784718B2 (en) * | 2001-10-29 | 2004-08-31 | Renesas Technology Corp. | Semiconductor device adaptable to a plurality of kinds of interfaces |
US7369815B2 (en) * | 2003-09-19 | 2008-05-06 | Qualcomm Incorporated | Power collapse for a wireless terminal |
US7305646B2 (en) * | 2005-05-09 | 2007-12-04 | Lsi Corporation | Relocatable mixed-signal functions |
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