US20090130801A1 - Resin-encapsulated semiconductor device and lead frame, and method for manufacturing the same - Google Patents
Resin-encapsulated semiconductor device and lead frame, and method for manufacturing the same Download PDFInfo
- Publication number
- US20090130801A1 US20090130801A1 US12/355,075 US35507509A US2009130801A1 US 20090130801 A1 US20090130801 A1 US 20090130801A1 US 35507509 A US35507509 A US 35507509A US 2009130801 A1 US2009130801 A1 US 2009130801A1
- Authority
- US
- United States
- Prior art keywords
- resin
- inner lead
- portions
- terminals
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
- H01L21/566—Release layers for moulds, e.g. release layers, layers against residue during moulding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/645—Inductive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05664—Palladium [Pd] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/16257—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/16258—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the bump connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/95001—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1029—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being a lead frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01037—Rubidium [Rb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
- H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/10—Methods of surface bonding and/or assembly therefor
Definitions
- the present invention relates to a resin-encapsulated semiconductor device in which a semiconductor element is bonded on inner leads of a lead frame and the surroundings thereof are encapsulated with a resin, and that allows other semiconductor devices or functional components such as a resistor to be stacked in a vertical direction.
- FIGS. 18A to 18D illustrate the conventional QFN-type resin-encapsulated semiconductor device; FIG. 18B is a plan view and FIG. 18A is a cross-sectional view taken along line I-I in FIG. 18B .
- FIGS. 18C and 18D illustrate a most commonly used QFP (Quad Flat Package)-type resin-encapsulated semiconductor device, in which external terminals protrude from a packaging resin toward a periphery thereof; FIG. 18C is a cross-sectional view and FIG. 18D is a plan view.
- QFP Quad Flat Package
- the conventional QFN-type resin-encapsulated semiconductor device has a structure in which a semiconductor element 52 is bonded on a die pad 51 of a lead frame and a plurality of inner lead portions 53 are arranged so that ends thereof are opposed to the die pad 51 . Electrodes of the semiconductor element 52 are connected electrically with surfaces of the inner lead portions 53 via thin metal wires 54 .
- the surroundings of the semiconductor element 52 , the die pad 51 , the inner lead portions 53 , and the thin metal wires 54 are encapsulated with an encapsulating resin 55 . Bottom surfaces and outer lateral surfaces of the inner lead portions 53 are exposed on a bottom surface and lateral surfaces, respectively, of the package from the encapsulating resin 55 , so as to be arranged as external terminals 56 .
- the conventional QFP type resin-encapsulated semiconductor device also has a structure in which the semiconductor element 52 is bonded on a die pad 57 of a lead frame and a plurality of inner lead portions 58 are arranged so that ends thereof are opposed to the die pad 57 . Electrodes of the semiconductor element 52 are connected electrically with surfaces of the inner lead portions 58 via thin metal wires 59 .
- the surroundings of the semiconductor element 52 , the die pad 57 , the inner lead portions 58 , and the thin metal wires 59 are encapsulated with an encapsulating resin 60 . Trailing ends of the inner lead portions 58 protrude from lateral surfaces of the encapsulating resin 60 , so as to be arranged as external terminals 61 on outer lateral surfaces of the package.
- the lead frame used in the conventional resin-encapsulated semiconductor device which is not shown in the figures, includes the die pad 51 arranged substantially at the center in an opening region of a frame, hanging lead portions 62 for supporting the die pad 51 , one end of each of them being connected to each corner of the die pad 51 , the other end thereof being connected to the frame, and the plurality of inner lead portions 53 arranged so that ends thereof are opposed to corresponding edges of the die pad 51 .
- the peripheral type semiconductor devices such as QFN, in which external terminals are arranged on the periphery of the semiconductor devices, have been replaced by area array type semiconductor devices having higher density, such as BGA (Ball Grid Array), in which external terminals are arranged in a grid pattern on a bottom surface of the semiconductor devices.
- BGA All Grid Array
- the smallest possible pitch of the external terminals that allows these semiconductor devices to be mounted on the substrate is 0.4 mm in the case of the peripheral type semiconductor devices such as QFN and 0.65 mm in the case of the area array type semiconductor devices such as BGA.
- the peripheral type semiconductor devices such as QFN
- 0.65 mm in the case of the area array type semiconductor devices such as BGA.
- An object of the present invention is to provide a resin-encapsulated semiconductor device in which a plurality of semiconductor elements or coils and resistors for supporting the function of the semiconductor elements can be incorporated, and that allows other semiconductor devices to be stacked, and a method for manufacturing the same.
- a resin-encapsulated semiconductor device includes: a lead frame including a plurality of first external terminal portions provided on a plane, inner lead portions that are formed of back surfaces of the respective first external terminal portions and arranged at regular intervals so as to surround a region inside the inner lead portions, and second external terminal portions formed of uppermost surfaces of convex portions positioned outside the respective inner lead portions; a semiconductor element whose connection pads are flip-chip bonded to the inner lead portions via bumps; and an encapsulating resin that encapsulates at least a part of surroundings of the semiconductor element including the inner lead portions and connection parts via the bumps.
- the first external terminal portions are arranged in a lower surface region of the encapsulating resin along a periphery of the region, and the second external terminal portions are exposed on an upper surface of the encapsulating resin. Further, a plurality of terminals for electrical connection are provided in a grid pattern in a region inside the first external terminal portions and exposed on a lower surface of the encapsulating resin.
- a lead frame includes: a plurality of first external terminal portions provided on a plane; inner lead portions that are formed of back surfaces of the respective first external terminal portions and arranged at regular intervals so as to surround a region inside the inner lead portions; and second external terminal portions formed of uppermost surfaces of convex portions positioned outside the respective inner lead portions.
- a plurality of terminals for electrical connection are provided in a grid pattern in the region inside the inner lead portions.
- a method for manufacturing a resin-encapsulated semiconductor device includes: preparing a lead frame having the above-mentioned configuration; forming conductive bumps on electrodes of a first semiconductor element; connecting the electrodes of the first semiconductor element with predetermined positions of the inner lead portions and the terminals for electrical connection, respectively, via the conductive bumps; encapsulating the inner lead portions, the first semiconductor element, and the conductive bumps with a resin; and separating the encapsulated structure from a frame.
- a method for manufacturing a lead frame according to the present invention is a method for manufacturing a lead frame having the above-mentioned configuration.
- the method includes: preparing a lead frame in which terminals to be independent of each other are connected; forming a plated layer on the lead frame; applying a protective sheet to a surface on one side of the lead frame in which the terminals to be independent of each other are connected; separating connected parts between the terminals to be independent of each other; and providing a plurality of terminals for electrical connection in the region inside the arranged inner lead portions.
- FIG. 1A is a plan view illustrating a resin-encapsulated semiconductor device according to Embodiment 1
- FIG. 1B is a back view thereof
- FIG. 1C is a cross-sectional view thereof taken along line A-A in FIG. 1A .
- FIG. 2A is a plan view of a lead frame for illustrating a part of a manufacturing process of the resin-encapsulated semiconductor device
- FIG. 2B is a back view of the resin-encapsulated semiconductor device manufactured by the process
- FIGS. 2C to 2F are cross-sectional views of respective steps of the process.
- FIG. 3 is a plan view illustrating a part of a lead frame for use in the resin-encapsulated semiconductor device.
- FIGS. 4A to 4E are cross-sectional views showing examples of the shape of the lead frame in the vicinity of an inner lead portion.
- FIG. 5A is a plan view illustrating an exemplary resin-encapsulated semiconductor device in which a semiconductor element is stacked
- FIG. 5B is a back view thereof
- FIG. 5C is a cross-sectional view thereof taken along line C-C in FIG. 5A .
- FIGS. 6A to 6D illustrate a part of a manufacturing process of the resin-encapsulated semiconductor device
- FIGS. 6A and 6B are perspective views illustrating respective steps of the process
- FIG. 6C is an enlarged perspective view of a part of FIG. 6A
- FIG. 6D is an enlarged side view of a part of FIG. 6C .
- FIG. 7A is a plan view illustrating a resin-encapsulated semiconductor device according to Embodiment 2
- FIG. 7B is a back view thereof
- FIG. 7C is a cross-sectional view thereof taken along line D-D in FIG. 7A .
- FIG. 8A is a plan view of a lead frame for illustrating a part of a manufacturing process of the resin-encapsulated semiconductor device
- FIG. 8B is a back view of the resin-encapsulated semiconductor device manufactured by the process
- FIGS. 8C to 8G are cross-sectional views of respective steps of the process.
- FIGS. 9A and 9B are a cross-sectional view and a plan view, respectively, illustrating the step of FIG. 8F in detail.
- FIGS. 10A and 10B are a cross-sectional view and a back view, respectively, showing an example of the packaging of the resin-encapsulated semiconductor device shown in FIGS. 7A to 7C .
- FIG. 11A is a plan view illustrating a resin-encapsulated semiconductor device according to Embodiment 3
- FIG. 11B is a back view thereof
- FIG. 11C is a cross-sectional view thereof taken along line F-F in FIG. 11A .
- FIG. 12A is a plan view of a lead frame for illustrating a part of a manufacturing process of the resin-encapsulated semiconductor device
- FIG. 12B is a back view of the resin-encapsulated semiconductor device manufactured by the process
- FIGS. 12C to 12F are cross-sectional views of respective steps of the process.
- FIG. 13A is a plan view illustrating a resin-encapsulated semiconductor device according to Embodiment 4, FIG. 13B is a back view thereof, and FIG. 13C is a cross-sectional view thereof taken along line G-G in FIG. 13A .
- FIG. 14 is a view showing an example of the relationship between a frequency (GHz) and a Q value of an inductor.
- FIG. 15 is a plan view illustrating a lead frame used to manufacture the resin-encapsulated semiconductor device according to Embodiment 4.
- FIGS. 16A to 16F are cross-sectional views illustrating a part of a manufacturing process of the resin-encapsulated semiconductor device.
- FIGS. 17A and 17B are a cross-sectional view and a plan view, respectively, illustrating a resin-encapsulated semiconductor device according to Embodiment 5.
- FIGS. 18A to 18D illustrate a conventional resin-encapsulated semiconductor device; FIGS. 18A and 18C are cross-sectional views and FIGS. 18B and 18D are back views.
- a resin-encapsulated semiconductor device of the present invention it is possible to form external terminals on an upper and a lower surfaces of a peripheral type resin-encapsulated semiconductor device in which external terminals are arranged on the periphery of the semiconductor device, provide coils or resistors in the semiconductor device, and stack semiconductor devices having a different number of pins and the like freely.
- each of the terminals for electrical connection can be used for a power source GND and have a larger area than the other terminals.
- the plurality of terminals for electrical connection that comprise two terminals can form a starting point and an ending point, respectively, of a spiral coil.
- the plurality of terminals for electrical connection can comprise two terminals with a resin having a high dielectric constant sandwiched therebetween.
- the semiconductor element may have a plurality of electrode pads in a region inside the flip-chip bonded region, and a second semiconductor element that is smaller than a region inside inner ends of the inner lead portions and thinner than the inner lead portions of the lead frame further may be flip-chip bonded to the electrode pads.
- a back surface of a third semiconductor element may be bonded on the second external terminal portions via an adhesive, and a plurality of inner lead posts may be provided in a region outside the inner lead portions, the inner lead posts being connected electrically with electrode pads of the third semiconductor element via thin metal wires, and having their opposite surfaces exposed in the lower surface region of the encapsulating resin.
- spiral wiring can be provided in the region inside the inner lead portions and the terminals for electrical connection can form a starting point and an ending point, respectively, of the spiral wiring.
- the plurality of terminals for electrical connection can comprise two terminals with a resin having a high dielectric constant sandwiched therebetween.
- the lead frame having the above-mentioned configuration further can include an insulating protective sheet for supporting the other elements.
- the method for manufacturing a resin-encapsulated semiconductor device further can include: preparing a second semiconductor element that is smaller than a region inside inner ends of the inner lead portions and thinner than the inner lead portions of the lead frame; forming a plurality of electrode pads in a region inside a region for flip-chip bonding via the conductive bumps in the first semiconductor element; connecting the second semiconductor element to the electrode pads formed in the inside region when the first semiconductor element is in a wafer state; and dividing the wafer into units of the first semiconductor element.
- the first semiconductor element to which the second semiconductor element is connected is supplied.
- the method for manufacturing a lead frame according to the present invention can further include: providing two terminals for electrical connection, injecting a resin with a high dielectric constant between the two terminals, and curing the resin.
- the inner lead portions can be arranged at regular intervals on a periphery of a region in which a semiconductor device is to be mounted, and a resistor with two terminals can be provided in the region inside the inner lead, each of the two terminals of the resistor having a region to be an upper surface that is sufficiently large so as to allow bump bonding.
- FIG. 1A is a plan view illustrating a resin-encapsulated semiconductor device according to Embodiment 1
- FIG. 1B is a back view thereof
- FIG. 1C is a cross-sectional view thereof taken along line A-A in FIG. 1A .
- the resin-encapsulated semiconductor device has structure in which a first semiconductor element 2 is mounted on an upper surface of a lead frame 1 via metal bumps 3 by flip-chip bonding and a connection part located between the lead frame 1 and the first semiconductor element 2 is encapsulated with an encapsulating resin 4 .
- the lead frame 1 includes a plurality of first external terminal portions 5 arranged on a plane as shown in FIG. 1B and inner lead portions 6 formed of surfaces opposite to the first external terminal portions 5 . Further, as shown in FIGS. 1A and 1C , second external terminal portions 7 are formed of uppermost surfaces of convex portions positioned in a part of the respective inner lead portions 6 . The inner lead portions 6 are arranged at regular intervals so as to surround a region inside the inner lead portions. The lead frame 1 further includes a plurality of terminals 8 for electrical connection provided in the region inside the inner lead portions 6 . The first external terminal portions 5 , the second external terminal portions 7 , and the terminals 8 are exposed from the encapsulating resin 4 .
- a distance in which high-frequency electric signals are transmitted is shorter.
- a design layout of the semiconductor element 2 allows the terminals 8 to be arranged at positions to which signals are allowed to be transmitted more directly, preferable electrical characteristics can be obtained.
- a power source ground also is located according to the design layout of the semiconductor element 2 .
- FIGS. 2A to 2F are views illustrating a part of a manufacturing process of the resin-encapsulated semiconductor device shown in FIGS. 1A to 1C .
- FIG. 2A is a plan view of the lead frame 1 .
- FIG. 2B is a back view of the resin-encapsulated semiconductor device manufactured by the process.
- FIGS. 2C to 2F are cross-sectional views taken along line B-B in FIG. 2B that illustrate respective steps of the process.
- the lead frame 1 is prepared. A lower surface of the lead frame 1 is held by a lead frame holding sheet 1 a . Then, as shown in FIG. 2D , the semiconductor element 2 is mounted on the lead frame 1 . In other words, electrode pads 2 a of the semiconductor element 2 are connected with the inner lead portions 6 of the lead frame 1 via the bumps 3 .
- the semiconductor element 2 and the inner lead portions 6 of the lead frame 1 are encapsulated with the encapsulating resin. More specifically, the lead frame 1 to which the semiconductor element 2 has been bonded is placed between resin encapsulating molds 9 a and 9 b , which is then filled with the encapsulating resin. Although only one semiconductor device is shown in the figure, actually resin-encapsulated semiconductor devices arranged adjacent to each other in a grid pattern may be encapsulated with the resin in a block form. At this time, an encapsulating sheet 10 may be provided between the lead frame 1 and the encapsulating mold 9 b .
- the first external terminal portions 5 , the second external terminal portions 7 , and the terminals 8 of the lead frame 1 are exposed on a surface of the resin.
- a thermosetting epoxy resin for example, is used as the encapsulating resin, and a resin molding temperature is set in a range of 150 to 250° C.
- the adjacent resin-encapsulated semiconductor devices are divided along dividing lines.
- the resin-encapsulated semiconductor devices when they have a total thickness of not more than 0.2 mm, they can be divided by a laser-cutting method.
- the resin-encapsulated semiconductor devices when they have a total thickness of more than 0.2 mm, they are divided using a saw, since when the laser cutting method is used, the handling of dross of a molten metal on laser dividing surfaces becomes a problem in terms of dividing time (index) and quality.
- the encapsulating sheet 10 In encapsulating, as shown in FIG. 2E , when the encapsulating sheet 10 is applied to a surface on one side of the lead frame 1 , the encapsulating sheet 10 contacts with portions that are to become the second external terminal portions 7 when the encapsulation is carried out, thereby preventing resin burr. Further, since the lead frame 1 slightly intrudes into the encapsulating sheet 10 , a standoff can be formed. For example, when the encapsulating sheet 10 has a thickness of 30 ⁇ m, a standoff of 2 ⁇ m to 10 ⁇ m is formed.
- the thickness of the material of the lead frame 1 amounts to the total thickness of the resin-encapsulated semiconductor device, and thus a compressive force of the resin encapsulating molds 9 a and 9 b can be provided stably. Therefore, resin burr can be eliminated sufficiently by a process using conventional chemicals.
- FIG. 3 is a plan view illustrating a part of an exemplary lead frame used in this embodiment.
- a lead frame 11 includes a plurality of positioning holes (circular holes) 12 and positioning holes (elliptical holes) 13 on both ends thereof in a shorter direction.
- a region 14 to be encapsulated with the resin is indicated inside the positioning holes 12 and 13 , and a plurality of regions 15 for mounting the elements are arranged in a grid pattern inside the region 14 to be encapsulated with the resin.
- the number of the regions 15 for mounting the elements to be arranged depends upon the size of the semiconductor device. Further, the number of external terminals (the number of pins) and a design within the regions 15 for mounting the elements vary depending upon the size, the number of output and input terminals, and the like of the semiconductor elements to be mounted.
- the lead frame 11 of this embodiment has, for example, lengths of 30 to 80 mm in the shorter direction and 50 to 260 mm in a longitudinal direction, and a thickness of 0.1 to 0.4 mm. Further, the lead frame 11 is made of an Fe—Ni material, a Cu alloy, or the like. The size of the resin-encapsulated semiconductor device to be arranged generally is 3.0 ⁇ 3.0 mm to 20.0 ⁇ 20.0 mm.
- An Fe—Ni material, a Cu alloy, or the like as a material of the lead frame 11 of this embodiment may be provided with a plated metal, which is required for the bonding or the mounting of the semiconductor element.
- a plating material Ag, Au, Ni—Pd, or the like is used.
- Sn—Pb plating or Sn—Bi plating is required to be provided on portions that are to become the external terminal portions formed of surfaces opposite to the inner lead portions.
- the thickness of the plating provided on the lead frame 11 is not more than 1 ⁇ M in the case of Au plating and Pd plating, and not more than several ⁇ m in the case of Ag plating.
- a heat-resistant base material such as polyimide or an aluminum foil may be applied temporarily to a surface of the lead frame 11 opposed to a surface to which semiconductor elements are to be bonded.
- FIGS. 4A to 4E are cross-sectional views of the vicinity of the inner lead portion in the region 15 for mounting the element of the lead frame 11 in combination with the semiconductor element 2 provided with the bump 3 .
- FIG. 4A illustrates an inner lead portion 16 a as a first example.
- a convex second external terminal portion 17 that has a rectangular, elliptical, or cylindrical shape and has a width equal to or smaller than that of the inner lead portion 16 a is provided in a region apart from an end portion of the inner lead portion 16 a .
- the end portion of the inner lead portion 16 a has a region broader than a lead that is to become a first external terminal portion 18 .
- a circular trapezoidal convex portion 19 a protruding is formed on a plane of the broad region at the end of the inner lead portion 16 a .
- the convex portion 19 a is positioned so as to correspond to a position of the bump 3 provided on an electrode pad of the semiconductor element 2 .
- FIG. 4B shows the state where the semiconductor element 2 with the bump 3 is bonded to the convex portion 19 a.
- FIG. 4C illustrates an inner lead portion 16 b as a second example.
- the inner lead portion 16 b has a convex portion 19 b having a different shape from that shown in the first example. Except for this point, the inner lead portion 16 b is formed in the same manner as that in the first example.
- the convex portion 19 b has its upper surface formed in a concave shape.
- FIG. 4D shows the state where the semiconductor element 2 with the bump 3 is bonded to the convex portion 19 b.
- FIG. 4E illustrates an inner lead portion 16 c as a third example.
- the inner lead portion 16 c has the same configuration as that in the first example except for circular concave portions 19 c having a pointed protrusion lower than an upper surface of the inner lead portion 16 c .
- the pointed protrusion at the center thereof intrudes into the bump 3 in a wedge shape.
- the first external terminal portion 18 in this embodiment has a length of, for example, 0.2 to 0.6 mm.
- the inner lead portions 16 a to 16 c have a length of, for example, 0.5 to 2.0 mm and a width of, for example, 0.1 to 0.40 mm.
- the inner lead portions 16 a to 16 c have a thickness of, for example, 0.1 to 0.20 mm.
- the thickness of each of the inner lead portions 16 a to 16 c including the convex portion formed as the second external terminal portion 17 amounts to 0.1 to 0.4 mm. This thickness is approximately within a range of a resin thickness of the resin-encapsulated semiconductor device.
- the semiconductor element 2 usually has a size in a range of 1.0 ⁇ 1.0 mm to 12.0 ⁇ 12.0 mm and a thickness of approximately 0.05 to 0.15 mm.
- the level difference generated by the circular concave portions 19 c in the inner lead portion 16 c in FIG. 4E is approximately 0.02 to 0.10 mm.
- FIGS. 5A to 5C illustrates an exemplary resin-encapsulated semiconductor device in which semiconductor elements are stacked;
- FIG. 5A is a plan view,
- FIG. 5B is a back view, and
- FIG. 5C is a cross-sectional view taken along line C-C in FIG. 5A .
- the resin-encapsulated semiconductor device has a configuration in which a first semiconductor element 2 is mounted on an upper surface of a lead frame 20 and a second semiconductor element 21 is mounted on a lower surface of the first semiconductor element 2 .
- a connection part located between the lead frame 20 and the first semiconductor element 2 and a connection part located between the first and second semiconductor elements 2 and 21 are encapsulated with an encapsulating resin 4 .
- the lead frame 20 includes a plurality of first external terminal portions 5 arranged on a back surface of the encapsulating resin 4 as shown in FIG. 5B , inner lead portions 6 formed of back surfaces of the first external terminal portions 5 , and second external terminal portions 7 formed of uppermost surfaces of convex portions positioned in a part of the respective inner lead portions 6 .
- the inner lead portions 6 are arranged at regular intervals so as to surround a region inside the inner lead portions.
- the first semiconductor element 2 is flip-chip bonded to ends of the inner lead portions 6 via metal bumps 3 .
- the second semiconductor element 21 smaller than the first semiconductor element 2 is flip-chip bonded in advance to a region inside the flip-chip bonded parts of the first semiconductor element 2 .
- the thickness of the laminate formed of the first and second semiconductor elements 2 and 21 is set not to be greater than the total thickness of the lead frame 20 .
- the first external terminal portions 5 and the second external terminal portions 7 are exposed on surfaces of the encapsulating resin 4 , which allows a plurality of semiconductor devices having external terminals at corresponding positions to be stacked.
- FIGS. 6A to 6D illustrate a part of a manufacturing process of the resin-encapsulated semiconductor device shown in FIGS. 5A to 5C , i.e., a step of flip-chip bonding between the first and second semiconductor elements.
- FIGS. 6A and 6B are perspective views illustrating the step
- FIG. 6C is an enlarged perspective view of a part of FIG. 6A
- FIG. 6D is an enlarged side view of a part of FIG. 6C .
- Au stud bumps are formed on electrode pads 2 a of each of the first semiconductor elements 2 on a semiconductor wafer 22 examined in advance, and the second semiconductor element 21 is flip-chip bonded thereto.
- the semiconductor wafer 22 to which each of the second semiconductor elements 21 is flip-chip bonded is subjected to dicing with a blade 23 along a dividing line 24 shown in FIG. 6D , thereby dividing the semiconductor wafer 22 into each of the first semiconductor elements 2 .
- the semiconductor wafer 22 is held by a holding ring 25 and a dicing sheet 26 .
- the bumps 3 formed on the electrode pads 2 a of the first semiconductor element 2 have, for example, a diameter in a planar shape of approximately ⁇ 0.05 to 0.1 mm and a height of approximately 0.02 to 0.1 mm.
- Each of the first and second semiconductor elements 2 and 21 is prepared in the following manner: circuits are formed on a surface of a semiconductor substrate made of a single crystal silicon base material, then Cu wiring patterns with a thickness of 30 nm to 1000 nm, for example, are formed, and the circuits are connected with respective electrode pads.
- the electrode pads 2 a are provided with a plurality of (3 to 4) ALCu layers that are brought into conduction by W, Ti, TiN, or the like, the uppermost surface thereof being covered with AL or Pd, Au, or the like by a CVD method or the like.
- the bumps 3 are made of, for example, SnPb by a plating method, and Au at a purity not less than 99.99%, which is a material for forming a bump called a stud bump, by a mechanical method.
- a conductive paste such as an AgPd paste may be used when the bumps 3 are bonded to the ends of the inner lead portions 6 , thereby ensuring the bonding property.
- FIG. 7A is a plan view illustrating a resin-encapsulated semiconductor device according to Embodiment 2
- FIG. 7B is a back view thereof
- FIG. 7C is a cross-sectional view thereof taken along line D-D in FIG. 7A
- FIGS. 8A to 8G illustrate a manufacturing process of the resin-encapsulated semiconductor device shown in FIGS. 7A to 7C .
- second external terminal portions 28 of a lead frame 27 have a slightly different shape from that shown in the above embodiment, that is, have larger areas, on which solder balls 29 are provided.
- an encapsulating resin 30 is provided by potting as shown in FIG. 8E , although injection molding is conducted in the case shown in FIG. 2E .
- FIGS. 9A and 9B a step of grinding the resin is carried out.
- FIG. 8A is a plan view of the lead frame 27 .
- FIG. 8B is a plan view of the resin-encapsulated semiconductor device manufactured by the process.
- FIGS. 8C to 8G are cross-sectional views taken along line E-E in FIG. 8B that illustrate respective steps of the process.
- the lead frame 27 and a semiconductor element 2 provided with bumps 3 are prepared. Then, as shown in FIG. 8D , the semiconductor element 2 is mounted on the lead frame 27 . In other words, electrode pads 2 a of the semiconductor element 2 are connected with inner lead portions 6 of the lead frame 27 via the bumps 3 .
- the semiconductor element 2 and the inner lead portions 6 of the lead frame 27 are encapsulated with the resin 30 through a potting step.
- first external terminal portions 5 , second external terminal portions 28 , and terminals 8 of the lead frame 27 are exposed on a surface of the resin 30 .
- the potting makes it unnecessary to use an expensive encapsulating mold.
- the lead frame to which the semiconductor element is bonded is disposed on a bench and filled with the resin 30 by the potting method. Thereafter, the resin 30 is cured by heat at a temperature of 150° C. for 2 hours, for example.
- solder balls 29 may be provided.
- FIGS. 9A and 9B show more specifically an example of the grinding step for removing the unwanted resin as shown in FIG. 8F .
- FIG. 9A is a cross sectional view
- FIG. 9B is a plan view illustrating the semiconductor device obtained after the grinding.
- a belt grinding method using a grinding belt 31 is used.
- the grinding belt 31 whose surface is impregnated with a grinding agent is rotated at a high velocity of 7000 rpm to 30000 rpm.
- the semiconductor device 2 is placed on a grinding board 32 , and the grinding board 32 is driven back and forth.
- cutting oil is used conventionally to grind metal materials
- wash water is used to grind semiconductor devices.
- the grinding belt 31 goes down in steps of several ⁇ M to grind the encapsulating resin 30 .
- the belt grinding method is very efficient in grinding a strip-shaped work such as the lead frame that is encapsulated with the resin in a block form, as compared with a back grinding method with a grinding stone wheel that is used generally to grind semiconductor wafers.
- a conventionally used printing encapsulating system using a squeegee also may be used in the resin encapsulating step.
- the unwanted resin is removed by the squeegee before it is cured, which eliminates the need for the grinding step.
- a resin used in the potting or printing method has lower moisture resistance and physical strength than those of a thermosetting epoxy resin containing silica, which is used in injection molding.
- semiconductor devices become considerably thinner than conventional ones and thus requires a smaller amount of encapsulating resin, there is an increasing acceptability in using such a resin used in the potting or printing method.
- FIGS. 10A and 10B illustrate an example of packaging the resin-encapsulated semiconductor device shown in FIGS. 7A and 7C ;
- FIG. 10A is a cross-sectional view and
- FIG. 10B is a back view.
- a semiconductor device 33 of this embodiment is packaged in combination with an SON (Small Outline Package) semiconductor device 34 with small pins and a QFP semiconductor device 35 that are provided on the semiconductor device 33 .
- the semiconductor device of this embodiment allows commercially available semiconductor devices to be stacked thereon easily. Therefore, such a semiconductor device can be obtained at a lower cost than a semiconductor device in which a plurality of semiconductor elements are incorporated.
- SON Small Outline Package
- FIG. 11A is a plan view illustrating a resin-encapsulated semiconductor device according to Embodiment 3
- FIG. 11B is a back view thereof
- FIG. 11C is a cross-sectional view thereof taken along line F-F in FIG. 11A .
- the resin-encapsulated semiconductor device basically has the same structure as that shown in FIGS. 1A to 1C .
- a resin 37 with a high dielectric constant is sandwiched between two terminals 36 provided in a region inside inner lead portions 6 .
- a resistor square shape
- a thick film paste As the thick film paste to become a resistor, a ruthenium-oxide(RuO 2 )-based paste is used.
- a ruthenium-oxide (RuO 2 )-based paste also can be used as the resin 37 with a high dielectric constant of this embodiment, and it is injected between the two terminals by a dispenser system and then cured.
- a manufacturing process of the resin-encapsulated semiconductor device is shown in FIGS. 12A to 12F .
- FIG. 12A is a plan view of a lead frame 38 .
- FIG. 12B is a back view of the resin-encapsulated semiconductor device manufactured by the process.
- FIGS. 12C to 12F are cross-sectional views of respective steps of the process.
- the lead frame 38 is prepared.
- a lower surface of the lead frame 38 is held by a lead frame holding sheet 39 .
- a ruthenium-oxide (RuO 2 )-based paste 40 for example, is injected between the terminals 36 of the lead frame 38 by a dispenser 41 and then cured.
- the resin 37 with a high dielectric constant is formed.
- Subsequent steps shown in FIGS. 12D to 12F are the same as those shown in FIGS. 2D to 2F .
- a resistor with two terminals may be provided.
- the two terminals of the resistor are provided such that regions to be an upper surface of the resistor are large enough to allow bump bonding.
- a capacitor instead of the resistor.
- a dielectric material with a high dielectric constant is used.
- the dielectric material various materials such as titanium oxide and barium titanate can be used.
- a ceramic capacitor it is required to make a dielectric material thin so as to increase a capacity, as well as to stack the dielectric material and an electrode material alternately. Consequently, it costs less to use commercially available capacitors than the configuration in which the resin with a high dielectric constant is injected between the two terminals.
- FIG. 13A is a plan view illustrating a resin-encapsulated semiconductor device according to Embodiment 4, FIG. 13B is a back view thereof, and FIG. 13C is a cross-sectional view thereof taken along line G-G in FIG. 13A .
- the resin-encapsulated semiconductor device basically has the same structure as that shown in FIGS. 1A to 1C .
- two terminals 42 provided in a region inside inner lead portions 6 serve as a starting point and an ending point, respectively, of a coil 43 .
- the formation of the coil 43 allows a Q value of an inductor representing the high frequency characteristics to be increased, thereby improving the signal output characteristics.
- the two terminals 42 as the starting point and the ending point, respectively are bump-bonded to electrode pads of a semiconductor device 2 directly, output is improved by, for example, 5 dB in the case of a driver with electric signals having a high frequency of 2 GHz, as compared with the case of conventional bonding with thin metal wires.
- the coil 43 may affect other electric signals, and thus it is required to determine appropriately the design pattern layout of the semiconductor element 2 or the position of the coil.
- FIG. 14 shows an example of the relationship between a frequency (GHz) and the Q value of an inductor. The Q value on this curve increases as the number of turns and the thickness of the coil are increased.
- FIG. 15 is a plan view illustrating a lead frame used to manufacture the resin-encapsulated semiconductor device of this embodiment.
- the shape of its periphery formed of the inner lead portions 6 , second external terminal portions 7 , and the like is the same as that shown in FIG. 2A .
- the difference from the structure shown in FIG. 2A is that the terminals 42 and the coil 43 are provided in the region inside the inner lead portions 6 .
- the resin-encapsulated semiconductor device of this embodiment can be manufactured using this lead frame through respective steps shown in FIGS. 16A to 16F .
- FIGS. 16A to 16F are cross-sectional views taken along line G-G in FIG. 13A that illustrate a process for manufacturing the resin-encapsulated semiconductor device shown in FIGS. 13A to 13C .
- a lead frame 44 with a coil 43 provided between terminals 42 is prepared.
- a lower surface of the lead frame 44 is held by a lead frame holding sheet 45 .
- semiconductor elements 2 are mounted on the lead frame 44 .
- electrode pads 2 a of each of the semiconductor elements 2 are connected with the inner lead portions 6 of the lead frame 44 via bumps 3 .
- the semiconductor elements 2 and the inner lead portions 6 of the lead frame 44 are encapsulated with an encapsulating resin 4 . More specifically, as shown in FIG. 16C , the lead frame 44 to which the semiconductor elements 2 have been bonded is placed between resin encapsulating molds 46 a and 46 b , which is then filled with the encapsulating resin 4 . At this time, an encapsulating sheet 47 may be provided between the lead frame 44 and the encapsulating mold 46 b . A molded body taken out from the resin encapsulating molds 46 a and 46 b as shown in FIG. 16D is cut by a blade 23 along a dividing line 24 as shown in FIG. 16E , thereby obtaining individual resin-encapsulated semiconductor devices as shown in FIG. 16F .
- FIG. 17A is a cross sectional view illustrating a resin-encapsulated semiconductor device according to Embodiment 5, and FIG. 17B is a plan view thereof.
- FIG. 17A shows a cross section taken along line H-H in FIG. 17B .
- a third semiconductor element 48 further is adhered with an adhesive 49 to upper surfaces of second external terminal portions 7 provided on the periphery of the semiconductor device as shown in FIGS. 5A to 5C , and terminals (inner lead posts) 50 are provided outside the second external terminal portions 7 .
- the third semiconductor element 48 is connected electrically with the terminals 50 via thin metal wires 54 .
- the external terminal portions in accordance with the design based on the external standards of a semiconductor device created by the IEC (International Electrotechnical Commission) or the JEITA (Japan Electronics and Information Technology Industries Association), it is also possible to mount commercially available electronic components or semiconductors on the resin-encapsulated semiconductor device of the present invention.
- IEC International Electrotechnical Commission
- JEITA Japanese Electronics and Information Technology Industries Association
Abstract
There are provided a lead frame including a plurality of first external terminal portions 5 provided on a plane, inner lead portions 6 formed of back surfaces of the respective first external terminal portions and arranged so as to surround a region inside the inner lead portions, and second external terminal portions 7 formed of uppermost surfaces of convex portions positioned outside the respective inner lead portions; a semiconductor element 2 flip-chip bonded to the inner lead portions via bumps 3; and an encapsulating resin 4 encapsulating surroundings of the semiconductor element and the inner lead portions. The first external terminal portions are arranged in a lower surface region of the encapsulating resin along a periphery of the region, and the second external terminal portions are exposed on an upper surface of the encapsulating resin. A plurality of terminals 8 for electrical connection are provided in a grid pattern in a region inside the first external terminal portions and exposed on a lower surface of the encapsulating resin. A plurality of semiconductor elements or coils and resistors can be incorporated, and further semiconductor devices can be stacked.
Description
- This application is a division of U.S. Ser. No. 11/071,343, filed Mar. 3, 2005 which application is incorporated herein by reference.
- 1. Field of the Invention
- The present invention relates to a resin-encapsulated semiconductor device in which a semiconductor element is bonded on inner leads of a lead frame and the surroundings thereof are encapsulated with a resin, and that allows other semiconductor devices or functional components such as a resistor to be stacked in a vertical direction.
- 2. Description of the Related Art
- In recent years, in order to cope with miniaturized and high-density electronic equipment, high-density packaging of semiconductor components such as a resin-encapsulated semiconductor device has been demanded, and accordingly smaller and thinner semiconductor components have been developed. For example, the type of a package is being changed from a peripheral package in which external terminals are provided on the periphery of a semiconductor device to an area array package in which external terminals are provided in a grid pattern on a mounting surface of a semiconductor device. Further, semiconductor devices that are small and thin and yet have a large number of pins also have been developed.
- Hereinafter, a conventional resin-encapsulated semiconductor device will be described. In recent years, a resin-encapsulated semiconductor device called “QFN (Quad Flat No-lead Package)” in which one side thereof is molded actually has been developed as a small and thin resin-encapsulated semiconductor device (see JP 2001-77277 A, for example).
- Initially, the QFN-type resin-encapsulated semiconductor device in which a die pad is exposed on a bottom surface of a package will be described as a conventional resin-encapsulated semiconductor device.
FIGS. 18A to 18D illustrate the conventional QFN-type resin-encapsulated semiconductor device;FIG. 18B is a plan view andFIG. 18A is a cross-sectional view taken along line I-I inFIG. 18B . In addition,FIGS. 18C and 18D illustrate a most commonly used QFP (Quad Flat Package)-type resin-encapsulated semiconductor device, in which external terminals protrude from a packaging resin toward a periphery thereof;FIG. 18C is a cross-sectional view andFIG. 18D is a plan view. - As shown in
FIGS. 18A and 18B , the conventional QFN-type resin-encapsulated semiconductor device has a structure in which asemiconductor element 52 is bonded on adie pad 51 of a lead frame and a plurality ofinner lead portions 53 are arranged so that ends thereof are opposed to thedie pad 51. Electrodes of thesemiconductor element 52 are connected electrically with surfaces of theinner lead portions 53 viathin metal wires 54. The surroundings of thesemiconductor element 52, thedie pad 51, theinner lead portions 53, and thethin metal wires 54 are encapsulated with anencapsulating resin 55. Bottom surfaces and outer lateral surfaces of theinner lead portions 53 are exposed on a bottom surface and lateral surfaces, respectively, of the package from theencapsulating resin 55, so as to be arranged asexternal terminals 56. - Further, as shown in
FIGS. 18C and 18D , the conventional QFP type resin-encapsulated semiconductor device also has a structure in which thesemiconductor element 52 is bonded on adie pad 57 of a lead frame and a plurality ofinner lead portions 58 are arranged so that ends thereof are opposed to thedie pad 57. Electrodes of thesemiconductor element 52 are connected electrically with surfaces of theinner lead portions 58 viathin metal wires 59. The surroundings of thesemiconductor element 52, thedie pad 57, theinner lead portions 58, and thethin metal wires 59 are encapsulated with anencapsulating resin 60. Trailing ends of theinner lead portions 58 protrude from lateral surfaces of theencapsulating resin 60, so as to be arranged asexternal terminals 61 on outer lateral surfaces of the package. - The lead frame used in the conventional resin-encapsulated semiconductor device, which is not shown in the figures, includes the
die pad 51 arranged substantially at the center in an opening region of a frame, hanginglead portions 62 for supporting thedie pad 51, one end of each of them being connected to each corner of thedie pad 51, the other end thereof being connected to the frame, and the plurality ofinner lead portions 53 arranged so that ends thereof are opposed to corresponding edges of thedie pad 51. - In an attempt to make the conventional resin-encapsulated semiconductor device with these structures smaller and have higher density, the peripheral type semiconductor devices, such as QFN, in which external terminals are arranged on the periphery of the semiconductor devices, have been replaced by area array type semiconductor devices having higher density, such as BGA (Ball Grid Array), in which external terminals are arranged in a grid pattern on a bottom surface of the semiconductor devices. However, due to limitations on the processing of a line and space (design of a wiring pattern) of a substrate to be mounted and limitations imposed by a method of mounting by a reflow process using a solder cream, the smallest possible pitch of the external terminals that allows these semiconductor devices to be mounted on the substrate is 0.4 mm in the case of the peripheral type semiconductor devices such as QFN and 0.65 mm in the case of the area array type semiconductor devices such as BGA. Thus, further miniaturization and high-density packaging of the resin-encapsulated semiconductor devices are becoming difficult.
- Further, there is a need for a semiconductor device commensurate with a higher functionality of sets typified by mobile phones and the like. In the case of a mobile phone, for example, a frequency band of not less than 1 GHz in use has been utilized already to realize stable communications or large-capacity data communications in a current industrial field of mobile communications (mobile phones, PDAs, and the like). In the future, there will be an increasing need for signal communications in a higher frequency band.
- An object of the present invention is to provide a resin-encapsulated semiconductor device in which a plurality of semiconductor elements or coils and resistors for supporting the function of the semiconductor elements can be incorporated, and that allows other semiconductor devices to be stacked, and a method for manufacturing the same.
- A resin-encapsulated semiconductor device according to the present invention includes: a lead frame including a plurality of first external terminal portions provided on a plane, inner lead portions that are formed of back surfaces of the respective first external terminal portions and arranged at regular intervals so as to surround a region inside the inner lead portions, and second external terminal portions formed of uppermost surfaces of convex portions positioned outside the respective inner lead portions; a semiconductor element whose connection pads are flip-chip bonded to the inner lead portions via bumps; and an encapsulating resin that encapsulates at least a part of surroundings of the semiconductor element including the inner lead portions and connection parts via the bumps. The first external terminal portions are arranged in a lower surface region of the encapsulating resin along a periphery of the region, and the second external terminal portions are exposed on an upper surface of the encapsulating resin. Further, a plurality of terminals for electrical connection are provided in a grid pattern in a region inside the first external terminal portions and exposed on a lower surface of the encapsulating resin.
- A lead frame according to the present invention includes: a plurality of first external terminal portions provided on a plane; inner lead portions that are formed of back surfaces of the respective first external terminal portions and arranged at regular intervals so as to surround a region inside the inner lead portions; and second external terminal portions formed of uppermost surfaces of convex portions positioned outside the respective inner lead portions. A plurality of terminals for electrical connection are provided in a grid pattern in the region inside the inner lead portions.
- A method for manufacturing a resin-encapsulated semiconductor device according to the present invention includes: preparing a lead frame having the above-mentioned configuration; forming conductive bumps on electrodes of a first semiconductor element; connecting the electrodes of the first semiconductor element with predetermined positions of the inner lead portions and the terminals for electrical connection, respectively, via the conductive bumps; encapsulating the inner lead portions, the first semiconductor element, and the conductive bumps with a resin; and separating the encapsulated structure from a frame.
- A method for manufacturing a lead frame according to the present invention is a method for manufacturing a lead frame having the above-mentioned configuration. The method includes: preparing a lead frame in which terminals to be independent of each other are connected; forming a plated layer on the lead frame; applying a protective sheet to a surface on one side of the lead frame in which the terminals to be independent of each other are connected; separating connected parts between the terminals to be independent of each other; and providing a plurality of terminals for electrical connection in the region inside the arranged inner lead portions.
-
FIG. 1A is a plan view illustrating a resin-encapsulated semiconductor device according toEmbodiment 1,FIG. 1B is a back view thereof, andFIG. 1C is a cross-sectional view thereof taken along line A-A inFIG. 1A . -
FIG. 2A is a plan view of a lead frame for illustrating a part of a manufacturing process of the resin-encapsulated semiconductor device,FIG. 2B is a back view of the resin-encapsulated semiconductor device manufactured by the process, andFIGS. 2C to 2F are cross-sectional views of respective steps of the process. -
FIG. 3 is a plan view illustrating a part of a lead frame for use in the resin-encapsulated semiconductor device. -
FIGS. 4A to 4E are cross-sectional views showing examples of the shape of the lead frame in the vicinity of an inner lead portion. -
FIG. 5A is a plan view illustrating an exemplary resin-encapsulated semiconductor device in which a semiconductor element is stacked,FIG. 5B is a back view thereof, andFIG. 5C is a cross-sectional view thereof taken along line C-C inFIG. 5A . -
FIGS. 6A to 6D illustrate a part of a manufacturing process of the resin-encapsulated semiconductor device;FIGS. 6A and 6B are perspective views illustrating respective steps of the process,FIG. 6C is an enlarged perspective view of a part ofFIG. 6A , andFIG. 6D is an enlarged side view of a part ofFIG. 6C . -
FIG. 7A is a plan view illustrating a resin-encapsulated semiconductor device according toEmbodiment 2,FIG. 7B is a back view thereof, andFIG. 7C is a cross-sectional view thereof taken along line D-D inFIG. 7A . -
FIG. 8A is a plan view of a lead frame for illustrating a part of a manufacturing process of the resin-encapsulated semiconductor device,FIG. 8B is a back view of the resin-encapsulated semiconductor device manufactured by the process, andFIGS. 8C to 8G are cross-sectional views of respective steps of the process. -
FIGS. 9A and 9B are a cross-sectional view and a plan view, respectively, illustrating the step ofFIG. 8F in detail. -
FIGS. 10A and 10B are a cross-sectional view and a back view, respectively, showing an example of the packaging of the resin-encapsulated semiconductor device shown inFIGS. 7A to 7C . -
FIG. 11A is a plan view illustrating a resin-encapsulated semiconductor device according toEmbodiment 3,FIG. 11B is a back view thereof, andFIG. 11C is a cross-sectional view thereof taken along line F-F inFIG. 11A . -
FIG. 12A is a plan view of a lead frame for illustrating a part of a manufacturing process of the resin-encapsulated semiconductor device,FIG. 12B is a back view of the resin-encapsulated semiconductor device manufactured by the process, andFIGS. 12C to 12F are cross-sectional views of respective steps of the process. -
FIG. 13A is a plan view illustrating a resin-encapsulated semiconductor device according toEmbodiment 4,FIG. 13B is a back view thereof, andFIG. 13C is a cross-sectional view thereof taken along line G-G inFIG. 13A . -
FIG. 14 is a view showing an example of the relationship between a frequency (GHz) and a Q value of an inductor. -
FIG. 15 is a plan view illustrating a lead frame used to manufacture the resin-encapsulated semiconductor device according toEmbodiment 4. -
FIGS. 16A to 16F are cross-sectional views illustrating a part of a manufacturing process of the resin-encapsulated semiconductor device. -
FIGS. 17A and 17B are a cross-sectional view and a plan view, respectively, illustrating a resin-encapsulated semiconductor device according toEmbodiment 5. -
FIGS. 18A to 18D illustrate a conventional resin-encapsulated semiconductor device;FIGS. 18A and 18C are cross-sectional views andFIGS. 18B and 18D are back views. - According to a resin-encapsulated semiconductor device of the present invention, it is possible to form external terminals on an upper and a lower surfaces of a peripheral type resin-encapsulated semiconductor device in which external terminals are arranged on the periphery of the semiconductor device, provide coils or resistors in the semiconductor device, and stack semiconductor devices having a different number of pins and the like freely.
- In the resin-encapsulated semiconductor device according to the present invention, each of the terminals for electrical connection can be used for a power source GND and have a larger area than the other terminals. Alternatively, the plurality of terminals for electrical connection that comprise two terminals can form a starting point and an ending point, respectively, of a spiral coil. Alternatively, the plurality of terminals for electrical connection can comprise two terminals with a resin having a high dielectric constant sandwiched therebetween.
- The semiconductor element may have a plurality of electrode pads in a region inside the flip-chip bonded region, and a second semiconductor element that is smaller than a region inside inner ends of the inner lead portions and thinner than the inner lead portions of the lead frame further may be flip-chip bonded to the electrode pads.
- A back surface of a third semiconductor element may be bonded on the second external terminal portions via an adhesive, and a plurality of inner lead posts may be provided in a region outside the inner lead portions, the inner lead posts being connected electrically with electrode pads of the third semiconductor element via thin metal wires, and having their opposite surfaces exposed in the lower surface region of the encapsulating resin.
- In the lead frame according to the present invention, for example, spiral wiring can be provided in the region inside the inner lead portions and the terminals for electrical connection can form a starting point and an ending point, respectively, of the spiral wiring. Alternatively, the plurality of terminals for electrical connection can comprise two terminals with a resin having a high dielectric constant sandwiched therebetween. Further, the lead frame having the above-mentioned configuration further can include an insulating protective sheet for supporting the other elements.
- The method for manufacturing a resin-encapsulated semiconductor device according to the present invention further can include: preparing a second semiconductor element that is smaller than a region inside inner ends of the inner lead portions and thinner than the inner lead portions of the lead frame; forming a plurality of electrode pads in a region inside a region for flip-chip bonding via the conductive bumps in the first semiconductor element; connecting the second semiconductor element to the electrode pads formed in the inside region when the first semiconductor element is in a wafer state; and dividing the wafer into units of the first semiconductor element. In the step of connecting the electrodes of the first semiconductor element with predetermined positions of the inner lead portions and the terminals for electrical connection, the first semiconductor element to which the second semiconductor element is connected is supplied.
- The method for manufacturing a lead frame according to the present invention can further include: providing two terminals for electrical connection, injecting a resin with a high dielectric constant between the two terminals, and curing the resin. Alternatively, the inner lead portions can be arranged at regular intervals on a periphery of a region in which a semiconductor device is to be mounted, and a resistor with two terminals can be provided in the region inside the inner lead, each of the two terminals of the resistor having a region to be an upper surface that is sufficiently large so as to allow bump bonding.
- Hereinafter, the resin-encapsulated semiconductor device and a lead frame used therein according to each embodiment of the present invention will be described with reference to the drawings.
-
FIG. 1A is a plan view illustrating a resin-encapsulated semiconductor device according toEmbodiment 1,FIG. 1B is a back view thereof, andFIG. 1C is a cross-sectional view thereof taken along line A-A inFIG. 1A . - As shown in
FIG. 1C , the resin-encapsulated semiconductor device has structure in which afirst semiconductor element 2 is mounted on an upper surface of alead frame 1 viametal bumps 3 by flip-chip bonding and a connection part located between thelead frame 1 and thefirst semiconductor element 2 is encapsulated with an encapsulatingresin 4. - The
lead frame 1 includes a plurality of firstexternal terminal portions 5 arranged on a plane as shown inFIG. 1B andinner lead portions 6 formed of surfaces opposite to the firstexternal terminal portions 5. Further, as shown inFIGS. 1A and 1C , secondexternal terminal portions 7 are formed of uppermost surfaces of convex portions positioned in a part of the respectiveinner lead portions 6. Theinner lead portions 6 are arranged at regular intervals so as to surround a region inside the inner lead portions. Thelead frame 1 further includes a plurality ofterminals 8 for electrical connection provided in the region inside theinner lead portions 6. The firstexternal terminal portions 5, the secondexternal terminal portions 7, and theterminals 8 are exposed from the encapsulatingresin 4. - Herein, in the semiconductor device, it is preferable that a distance in which high-frequency electric signals are transmitted is shorter. When a design layout of the
semiconductor element 2 allows theterminals 8 to be arranged at positions to which signals are allowed to be transmitted more directly, preferable electrical characteristics can be obtained. A power source ground also is located according to the design layout of thesemiconductor element 2. -
FIGS. 2A to 2F are views illustrating a part of a manufacturing process of the resin-encapsulated semiconductor device shown inFIGS. 1A to 1C .FIG. 2A is a plan view of thelead frame 1.FIG. 2B is a back view of the resin-encapsulated semiconductor device manufactured by the process.FIGS. 2C to 2F are cross-sectional views taken along line B-B inFIG. 2B that illustrate respective steps of the process. - Initially, as shown in
FIG. 2C , thelead frame 1 is prepared. A lower surface of thelead frame 1 is held by a leadframe holding sheet 1 a. Then, as shown inFIG. 2D , thesemiconductor element 2 is mounted on thelead frame 1. In other words,electrode pads 2 a of thesemiconductor element 2 are connected with theinner lead portions 6 of thelead frame 1 via thebumps 3. - Then, as shown in
FIG. 2E , thesemiconductor element 2 and theinner lead portions 6 of thelead frame 1 are encapsulated with the encapsulating resin. More specifically, thelead frame 1 to which thesemiconductor element 2 has been bonded is placed betweenresin encapsulating molds sheet 10 may be provided between thelead frame 1 and the encapsulatingmold 9 b. The firstexternal terminal portions 5, the secondexternal terminal portions 7, and theterminals 8 of thelead frame 1 are exposed on a surface of the resin. Herein, a thermosetting epoxy resin, for example, is used as the encapsulating resin, and a resin molding temperature is set in a range of 150 to 250° C. - After the encapsulation, as shown in
FIG. 2F , the adjacent resin-encapsulated semiconductor devices are divided along dividing lines. In this step, when the resin-encapsulated semiconductor devices have a total thickness of not more than 0.2 mm, they can be divided by a laser-cutting method. On the other hand, when the resin-encapsulated semiconductor devices have a total thickness of more than 0.2 mm, they are divided using a saw, since when the laser cutting method is used, the handling of dross of a molten metal on laser dividing surfaces becomes a problem in terms of dividing time (index) and quality. - In encapsulating, as shown in
FIG. 2E , when the encapsulatingsheet 10 is applied to a surface on one side of thelead frame 1, the encapsulatingsheet 10 contacts with portions that are to become the secondexternal terminal portions 7 when the encapsulation is carried out, thereby preventing resin burr. Further, since thelead frame 1 slightly intrudes into the encapsulatingsheet 10, a standoff can be formed. For example, when the encapsulatingsheet 10 has a thickness of 30 μm, a standoff of 2 μm to 10 μm is formed. However, even when the encapsulatingsheet 10 is not used, the thickness of the material of thelead frame 1 amounts to the total thickness of the resin-encapsulated semiconductor device, and thus a compressive force of theresin encapsulating molds -
FIG. 3 is a plan view illustrating a part of an exemplary lead frame used in this embodiment. Alead frame 11 includes a plurality of positioning holes (circular holes) 12 and positioning holes (elliptical holes) 13 on both ends thereof in a shorter direction. Aregion 14 to be encapsulated with the resin is indicated inside the positioning holes 12 and 13, and a plurality ofregions 15 for mounting the elements are arranged in a grid pattern inside theregion 14 to be encapsulated with the resin. The number of theregions 15 for mounting the elements to be arranged depends upon the size of the semiconductor device. Further, the number of external terminals (the number of pins) and a design within theregions 15 for mounting the elements vary depending upon the size, the number of output and input terminals, and the like of the semiconductor elements to be mounted. - Herein, the
lead frame 11 of this embodiment has, for example, lengths of 30 to 80 mm in the shorter direction and 50 to 260 mm in a longitudinal direction, and a thickness of 0.1 to 0.4 mm. Further, thelead frame 11 is made of an Fe—Ni material, a Cu alloy, or the like. The size of the resin-encapsulated semiconductor device to be arranged generally is 3.0×3.0 mm to 20.0×20.0 mm. - An Fe—Ni material, a Cu alloy, or the like as a material of the
lead frame 11 of this embodiment may be provided with a plated metal, which is required for the bonding or the mounting of the semiconductor element. As a plating material, Ag, Au, Ni—Pd, or the like is used. However, in the case of Ag plating in particular, it is provided only on the inner lead portions, and in a later step of manufacturing the semiconductor device, Sn—Pb plating or Sn—Bi plating is required to be provided on portions that are to become the external terminal portions formed of surfaces opposite to the inner lead portions. The thickness of the plating provided on thelead frame 11 is not more than 1 μM in the case of Au plating and Pd plating, and not more than several μm in the case of Ag plating. Although not shown inFIG. 3 , in order to assemble the semiconductor device stably, a heat-resistant base material such as polyimide or an aluminum foil may be applied temporarily to a surface of thelead frame 11 opposed to a surface to which semiconductor elements are to be bonded. -
FIGS. 4A to 4E are cross-sectional views of the vicinity of the inner lead portion in theregion 15 for mounting the element of thelead frame 11 in combination with thesemiconductor element 2 provided with thebump 3. -
FIG. 4A illustrates aninner lead portion 16 a as a first example. A convex secondexternal terminal portion 17 that has a rectangular, elliptical, or cylindrical shape and has a width equal to or smaller than that of theinner lead portion 16 a is provided in a region apart from an end portion of theinner lead portion 16 a. The end portion of theinner lead portion 16 a has a region broader than a lead that is to become a firstexternal terminal portion 18. A circular trapezoidalconvex portion 19 a protruding is formed on a plane of the broad region at the end of theinner lead portion 16 a. Theconvex portion 19 a is positioned so as to correspond to a position of thebump 3 provided on an electrode pad of thesemiconductor element 2.FIG. 4B shows the state where thesemiconductor element 2 with thebump 3 is bonded to theconvex portion 19 a. -
FIG. 4C illustrates aninner lead portion 16 b as a second example. Theinner lead portion 16 b has aconvex portion 19 b having a different shape from that shown in the first example. Except for this point, theinner lead portion 16 b is formed in the same manner as that in the first example. Theconvex portion 19 b has its upper surface formed in a concave shape.FIG. 4D shows the state where thesemiconductor element 2 with thebump 3 is bonded to theconvex portion 19 b. -
FIG. 4E illustrates aninner lead portion 16 c as a third example. Theinner lead portion 16 c has the same configuration as that in the first example except for circularconcave portions 19 c having a pointed protrusion lower than an upper surface of theinner lead portion 16 c. When the circularconcave portions 19 c are bonded to thebump 3, the pointed protrusion at the center thereof intrudes into thebump 3 in a wedge shape. - The first
external terminal portion 18 in this embodiment has a length of, for example, 0.2 to 0.6 mm. Theinner lead portions 16 a to 16 c have a length of, for example, 0.5 to 2.0 mm and a width of, for example, 0.1 to 0.40 mm. Theinner lead portions 16 a to 16 c have a thickness of, for example, 0.1 to 0.20 mm. The thickness of each of theinner lead portions 16 a to 16 c including the convex portion formed as the secondexternal terminal portion 17 amounts to 0.1 to 0.4 mm. This thickness is approximately within a range of a resin thickness of the resin-encapsulated semiconductor device. The concave/convex protrusions inner lead portions semiconductor element 2 usually has a size in a range of 1.0×1.0 mm to 12.0×12.0 mm and a thickness of approximately 0.05 to 0.15 mm. The level difference generated by the circularconcave portions 19 c in theinner lead portion 16 c inFIG. 4E is approximately 0.02 to 0.10 mm. -
FIGS. 5A to 5C illustrates an exemplary resin-encapsulated semiconductor device in which semiconductor elements are stacked;FIG. 5A is a plan view,FIG. 5B is a back view, andFIG. 5C is a cross-sectional view taken along line C-C inFIG. 5A . - The resin-encapsulated semiconductor device has a configuration in which a
first semiconductor element 2 is mounted on an upper surface of alead frame 20 and asecond semiconductor element 21 is mounted on a lower surface of thefirst semiconductor element 2. A connection part located between thelead frame 20 and thefirst semiconductor element 2 and a connection part located between the first andsecond semiconductor elements resin 4. Thelead frame 20 includes a plurality of firstexternal terminal portions 5 arranged on a back surface of the encapsulatingresin 4 as shown inFIG. 5B ,inner lead portions 6 formed of back surfaces of the firstexternal terminal portions 5, and secondexternal terminal portions 7 formed of uppermost surfaces of convex portions positioned in a part of the respectiveinner lead portions 6. Theinner lead portions 6 are arranged at regular intervals so as to surround a region inside the inner lead portions. - As shown in
FIG. 5C , thefirst semiconductor element 2 is flip-chip bonded to ends of theinner lead portions 6 via metal bumps 3. Thesecond semiconductor element 21 smaller than thefirst semiconductor element 2 is flip-chip bonded in advance to a region inside the flip-chip bonded parts of thefirst semiconductor element 2. The thickness of the laminate formed of the first andsecond semiconductor elements lead frame 20. - A bottom surface, an upper surface, and outer lateral surfaces of the
lead frame 20 exposed from the encapsulatingresin 4 form the firstexternal terminal portions 5 and the secondexternal terminal portions 7. As shown inFIGS. 5A and 5B , the firstexternal terminal portions 5 and the secondexternal terminal portions 7 are exposed on surfaces of the encapsulatingresin 4, which allows a plurality of semiconductor devices having external terminals at corresponding positions to be stacked. -
FIGS. 6A to 6D illustrate a part of a manufacturing process of the resin-encapsulated semiconductor device shown inFIGS. 5A to 5C , i.e., a step of flip-chip bonding between the first and second semiconductor elements.FIGS. 6A and 6B are perspective views illustrating the step,FIG. 6C is an enlarged perspective view of a part ofFIG. 6A , andFIG. 6D is an enlarged side view of a part ofFIG. 6C . - Initially, as shown in
FIGS. 6A and 6C , Au stud bumps are formed onelectrode pads 2 a of each of thefirst semiconductor elements 2 on asemiconductor wafer 22 examined in advance, and thesecond semiconductor element 21 is flip-chip bonded thereto. Then, as shown inFIG. 6B , thesemiconductor wafer 22 to which each of thesecond semiconductor elements 21 is flip-chip bonded is subjected to dicing with ablade 23 along adividing line 24 shown inFIG. 6D , thereby dividing thesemiconductor wafer 22 into each of thefirst semiconductor elements 2. At this time, thesemiconductor wafer 22 is held by a holdingring 25 and adicing sheet 26. - The
bumps 3 formed on theelectrode pads 2 a of thefirst semiconductor element 2 have, for example, a diameter in a planar shape of approximately φ 0.05 to 0.1 mm and a height of approximately 0.02 to 0.1 mm. Each of the first andsecond semiconductor elements - In order to maintain the bonding reliability against impacts such as ultrasonic waves, loads, and heat applied when the
electrode pads 2 a are bonded to ends of the inner lead portions and the bonding reliability after the semiconductor device is assembled, theelectrode pads 2 a are provided with a plurality of (3 to 4) ALCu layers that are brought into conduction by W, Ti, TiN, or the like, the uppermost surface thereof being covered with AL or Pd, Au, or the like by a CVD method or the like. Thebumps 3 are made of, for example, SnPb by a plating method, and Au at a purity not less than 99.99%, which is a material for forming a bump called a stud bump, by a mechanical method. When Au is used for thebumps 3, a conductive paste such as an AgPd paste may be used when thebumps 3 are bonded to the ends of theinner lead portions 6, thereby ensuring the bonding property. -
FIG. 7A is a plan view illustrating a resin-encapsulated semiconductor device according toEmbodiment 2,FIG. 7B is a back view thereof, andFIG. 7C is a cross-sectional view thereof taken along line D-D inFIG. 7A .FIGS. 8A to 8G illustrate a manufacturing process of the resin-encapsulated semiconductor device shown inFIGS. 7A to 7C . - In this embodiment, as shown in
FIG. 7C , second externalterminal portions 28 of alead frame 27 have a slightly different shape from that shown in the above embodiment, that is, have larger areas, on whichsolder balls 29 are provided. Further, in this embodiment, an encapsulatingresin 30 is provided by potting as shown inFIG. 8E , although injection molding is conducted in the case shown inFIG. 2E . Furthermore, as shown inFIGS. 9A and 9B , a step of grinding the resin is carried out. -
FIG. 8A is a plan view of thelead frame 27.FIG. 8B is a plan view of the resin-encapsulated semiconductor device manufactured by the process. -
FIGS. 8C to 8G are cross-sectional views taken along line E-E inFIG. 8B that illustrate respective steps of the process. - Initially, as shown in
FIG. 8C , thelead frame 27 and asemiconductor element 2 provided withbumps 3 are prepared. Then, as shown inFIG. 8D , thesemiconductor element 2 is mounted on thelead frame 27. In other words,electrode pads 2 a of thesemiconductor element 2 are connected withinner lead portions 6 of thelead frame 27 via thebumps 3. - Then, as shown in
FIG. 8E , thesemiconductor element 2 and theinner lead portions 6 of thelead frame 27 are encapsulated with theresin 30 through a potting step. Herein, firstexternal terminal portions 5, second externalterminal portions 28, andterminals 8 of thelead frame 27 are exposed on a surface of theresin 30. The potting makes it unnecessary to use an expensive encapsulating mold. The lead frame to which the semiconductor element is bonded is disposed on a bench and filled with theresin 30 by the potting method. Thereafter, theresin 30 is cured by heat at a temperature of 150° C. for 2 hours, for example. - Then, as shown in
FIG. 8F , unwanted resin is removed in a grinding step. After that, as shown inFIG. 8G , thesolder balls 29 may be provided. -
FIGS. 9A and 9B show more specifically an example of the grinding step for removing the unwanted resin as shown inFIG. 8F .FIG. 9A is a cross sectional view, andFIG. 9B is a plan view illustrating the semiconductor device obtained after the grinding. As shown inFIG. 9A , a belt grinding method using a grindingbelt 31 is used. The grindingbelt 31 whose surface is impregnated with a grinding agent is rotated at a high velocity of 7000 rpm to 30000 rpm. Thesemiconductor device 2 is placed on a grindingboard 32, and the grindingboard 32 is driven back and forth. Although cutting oil is used conventionally to grind metal materials, wash water is used to grind semiconductor devices. The grindingbelt 31 goes down in steps of several μM to grind the encapsulatingresin 30. The belt grinding method is very efficient in grinding a strip-shaped work such as the lead frame that is encapsulated with the resin in a block form, as compared with a back grinding method with a grinding stone wheel that is used generally to grind semiconductor wafers. - Although not shown in the figures, a conventionally used printing encapsulating system using a squeegee also may be used in the resin encapsulating step. In the printing encapsulating system, the unwanted resin is removed by the squeegee before it is cured, which eliminates the need for the grinding step. In general, a resin used in the potting or printing method has lower moisture resistance and physical strength than those of a thermosetting epoxy resin containing silica, which is used in injection molding. However, as semiconductor devices become considerably thinner than conventional ones and thus requires a smaller amount of encapsulating resin, there is an increasing acceptability in using such a resin used in the potting or printing method.
-
FIGS. 10A and 10B illustrate an example of packaging the resin-encapsulated semiconductor device shown inFIGS. 7A and 7C ;FIG. 10A is a cross-sectional view andFIG. 10B is a back view. Asemiconductor device 33 of this embodiment is packaged in combination with an SON (Small Outline Package)semiconductor device 34 with small pins and aQFP semiconductor device 35 that are provided on thesemiconductor device 33. In this manner, the semiconductor device of this embodiment allows commercially available semiconductor devices to be stacked thereon easily. Therefore, such a semiconductor device can be obtained at a lower cost than a semiconductor device in which a plurality of semiconductor elements are incorporated. -
FIG. 11A is a plan view illustrating a resin-encapsulated semiconductor device according toEmbodiment 3,FIG. 11B is a back view thereof, andFIG. 11C is a cross-sectional view thereof taken along line F-F inFIG. 11A . The resin-encapsulated semiconductor device basically has the same structure as that shown inFIGS. 1A to 1C . In the resin-encapsulated semiconductor device of this embodiment, aresin 37 with a high dielectric constant is sandwiched between twoterminals 36 provided in a region insideinner lead portions 6. - This configuration allows a formation of a resistor. In general, a resistor (square shape) is formed by printing and baking a thick film paste on an aluminum ceramic substrate. As the thick film paste to become a resistor, a ruthenium-oxide(RuO2)-based paste is used. Such a ruthenium-oxide (RuO2)-based paste also can be used as the
resin 37 with a high dielectric constant of this embodiment, and it is injected between the two terminals by a dispenser system and then cured. A manufacturing process of the resin-encapsulated semiconductor device is shown inFIGS. 12A to 12F . -
FIG. 12A is a plan view of alead frame 38.FIG. 12B is a back view of the resin-encapsulated semiconductor device manufactured by the process.FIGS. 12C to 12F are cross-sectional views of respective steps of the process. Initially, as shown inFIG. 12C , thelead frame 38 is prepared. A lower surface of thelead frame 38 is held by a leadframe holding sheet 39. A ruthenium-oxide (RuO2)-basedpaste 40, for example, is injected between theterminals 36 of thelead frame 38 by adispenser 41 and then cured. As a result, theresin 37 with a high dielectric constant is formed. Subsequent steps shown inFIGS. 12D to 12F are the same as those shown inFIGS. 2D to 2F . - Instead of providing the
resin 37 with a high dielectric constant between the twoterminals 36, a resistor with two terminals may be provided. In such a case, the two terminals of the resistor are provided such that regions to be an upper surface of the resistor are large enough to allow bump bonding. Further, it is also possible to provide a capacitor instead of the resistor. In the case of a chip capacitor, a dielectric material with a high dielectric constant is used. As the dielectric material, various materials such as titanium oxide and barium titanate can be used. In the case of a ceramic capacitor, it is required to make a dielectric material thin so as to increase a capacity, as well as to stack the dielectric material and an electrode material alternately. Consequently, it costs less to use commercially available capacitors than the configuration in which the resin with a high dielectric constant is injected between the two terminals. -
FIG. 13A is a plan view illustrating a resin-encapsulated semiconductor device according toEmbodiment 4,FIG. 13B is a back view thereof, andFIG. 13C is a cross-sectional view thereof taken along line G-G inFIG. 13A . The resin-encapsulated semiconductor device basically has the same structure as that shown inFIGS. 1A to 1C . In the resin-encapsulated semiconductor device of this embodiment, twoterminals 42 provided in a region insideinner lead portions 6 serve as a starting point and an ending point, respectively, of acoil 43. - The formation of the
coil 43 allows a Q value of an inductor representing the high frequency characteristics to be increased, thereby improving the signal output characteristics. In addition, since the twoterminals 42 as the starting point and the ending point, respectively, are bump-bonded to electrode pads of asemiconductor device 2 directly, output is improved by, for example, 5 dB in the case of a driver with electric signals having a high frequency of 2 GHz, as compared with the case of conventional bonding with thin metal wires. However, thecoil 43 may affect other electric signals, and thus it is required to determine appropriately the design pattern layout of thesemiconductor element 2 or the position of the coil.FIG. 14 shows an example of the relationship between a frequency (GHz) and the Q value of an inductor. The Q value on this curve increases as the number of turns and the thickness of the coil are increased. -
FIG. 15 is a plan view illustrating a lead frame used to manufacture the resin-encapsulated semiconductor device of this embodiment. The shape of its periphery formed of theinner lead portions 6, secondexternal terminal portions 7, and the like is the same as that shown inFIG. 2A . The difference from the structure shown inFIG. 2A is that theterminals 42 and thecoil 43 are provided in the region inside theinner lead portions 6. The resin-encapsulated semiconductor device of this embodiment can be manufactured using this lead frame through respective steps shown inFIGS. 16A to 16F .FIGS. 16A to 16F are cross-sectional views taken along line G-G inFIG. 13A that illustrate a process for manufacturing the resin-encapsulated semiconductor device shown inFIGS. 13A to 13C . - Initially, as shown in
FIG. 16A , alead frame 44 with acoil 43 provided betweenterminals 42 is prepared. A lower surface of thelead frame 44 is held by a leadframe holding sheet 45. Then, as shown inFIG. 16B ,semiconductor elements 2 are mounted on thelead frame 44. In other words,electrode pads 2 a of each of thesemiconductor elements 2 are connected with theinner lead portions 6 of thelead frame 44 viabumps 3. - Then, the
semiconductor elements 2 and theinner lead portions 6 of thelead frame 44 are encapsulated with an encapsulatingresin 4. More specifically, as shown inFIG. 16C , thelead frame 44 to which thesemiconductor elements 2 have been bonded is placed betweenresin encapsulating molds resin 4. At this time, an encapsulatingsheet 47 may be provided between thelead frame 44 and the encapsulatingmold 46 b. A molded body taken out from theresin encapsulating molds FIG. 16D is cut by ablade 23 along adividing line 24 as shown inFIG. 16E , thereby obtaining individual resin-encapsulated semiconductor devices as shown inFIG. 16F . -
FIG. 17A is a cross sectional view illustrating a resin-encapsulated semiconductor device according toEmbodiment 5, andFIG. 17B is a plan view thereof.FIG. 17A shows a cross section taken along line H-H inFIG. 17B . In the resin-encapsulated semiconductor device of this embodiment, athird semiconductor element 48 further is adhered with an adhesive 49 to upper surfaces of secondexternal terminal portions 7 provided on the periphery of the semiconductor device as shown inFIGS. 5A to 5C , and terminals (inner lead posts) 50 are provided outside the secondexternal terminal portions 7. Thethird semiconductor element 48 is connected electrically with theterminals 50 viathin metal wires 54. - Further, by arranging the external terminal portions in accordance with the design based on the external standards of a semiconductor device created by the IEC (International Electrotechnical Commission) or the JEITA (Japan Electronics and Information Technology Industries Association), it is also possible to mount commercially available electronic components or semiconductors on the resin-encapsulated semiconductor device of the present invention.
- The invention may be embodied in other forms without departing from the spirit or essential characteristics thereof. The embodiments disclosed in this application are to be considered in all respects as illustrative and not limiting. The scope of the invention is indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are intended to be embraced therein.
Claims (6)
1-10. (canceled)
11. A method for manufacturing a resin-encapsulated semiconductor device, comprising:
preparing a lead frame having a plurality of first external terminal portions provided on a plane, inner lead portions that are formed on back surfaces of the respective first external terminal portions and arranged at regular intervals so as to surround a region inside the inner lead portions, second external terminal portions formed of uppermost surfaces of convex portions positioned outside the respective inner lead portions, and a plurality of terminals for electrical connection provided in a grid pattern in the region inside the inner lead portions;
forming conductive bumps on electrodes of a first semiconductor element;
connecting the electrodes of the first semiconductor element with predetermined positions of the inner lead portions and the terminals for electrical connection, respectively, via the conductive bumps;
encapsulating the inner lead portions, the first semiconductor element, and the conductive bumps with a resin; and
separating the encapsulated structure from a frame.
12. The method for manufacturing a resin-encapsulated semiconductor device according to claim 11 , further comprising:
preparing a second semiconductor element that is smaller than a region inside inner ends of the inner lead portions and thinner than the inner lead portions of the lead frame;
forming a plurality of electrode pads in a region inside a region for flip-chip bonding via the conductive bumps in the first semiconductor element;
connecting the second semiconductor element to the electrode pads formed in the inside region when the first semiconductor element is in a wafer state; and
dividing the wafer into units of the first semiconductor element;
wherein in the step of connecting the electrodes of the first semiconductor element with predetermined positions of the inner lead portions and the terminals for electrical connection, the first semiconductor element to which the second semiconductor element is connected is supplied.
13. A method for manufacturing a lead frame including a plurality of first external terminal portions provided on a plane, inner lead portions that are formed on back surfaces of the respective first external terminal portions and arranged at regular intervals so as to surround a region inside the inner lead portions, second external terminal portions formed of uppermost surfaces of convex portions positioned outside the respective inner lead portions, two terminals provided in the region inside the inner lead portions, and a resin with a high dielectric constant sandwiched between the two terminals, comprising:
preparing a lead frame in which terminals to be independent of each other are connected;
forming a plated layer on the lead frame;
applying a protective sheet to a surface on one side of the lead frame in which the terminals to be independent of each other are connected;
separating the connected terminals to be independent of each other; and
providing a plurality of terminals for electrical connection in the region inside the arranged inner lead portions.
14. The method for manufacturing a lead frame according to claim 13 , further comprising:
providing two terminals for electrical connection, injecting a resin with a high dielectric constant between the two terminals, and curing the resin.
15. The method for manufacturing a lead frame according to claim 13 , wherein the inner lead portions are arranged at regular intervals on a periphery of a region in which a semiconductor device is to be mounted, and a resistor with two terminals is provided in the region inside the inner lead portions, each of the two terminals of the resistor having a region to be an upper surface that is sufficiently large so as to allow bump bonding.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/355,075 US20090130801A1 (en) | 2004-03-04 | 2009-01-16 | Resin-encapsulated semiconductor device and lead frame, and method for manufacturing the same |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004-060943 | 2004-03-04 | ||
JP2004060943A JP3910598B2 (en) | 2004-03-04 | 2004-03-04 | Resin-sealed semiconductor device and manufacturing method thereof |
US11/071,343 US7495319B2 (en) | 2004-03-04 | 2005-03-03 | Resin-encapsulated semiconductor device and lead frame, and method for manufacturing the same |
US12/355,075 US20090130801A1 (en) | 2004-03-04 | 2009-01-16 | Resin-encapsulated semiconductor device and lead frame, and method for manufacturing the same |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/071,343 Division US7495319B2 (en) | 2004-03-04 | 2005-03-03 | Resin-encapsulated semiconductor device and lead frame, and method for manufacturing the same |
Publications (1)
Publication Number | Publication Date |
---|---|
US20090130801A1 true US20090130801A1 (en) | 2009-05-21 |
Family
ID=34909218
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/071,343 Active US7495319B2 (en) | 2004-03-04 | 2005-03-03 | Resin-encapsulated semiconductor device and lead frame, and method for manufacturing the same |
US12/355,075 Abandoned US20090130801A1 (en) | 2004-03-04 | 2009-01-16 | Resin-encapsulated semiconductor device and lead frame, and method for manufacturing the same |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/071,343 Active US7495319B2 (en) | 2004-03-04 | 2005-03-03 | Resin-encapsulated semiconductor device and lead frame, and method for manufacturing the same |
Country Status (4)
Country | Link |
---|---|
US (2) | US7495319B2 (en) |
JP (1) | JP3910598B2 (en) |
CN (1) | CN1665023A (en) |
TW (1) | TW200531249A (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080296759A1 (en) * | 2007-06-04 | 2008-12-04 | Stats Chippac, Inc. | Semiconductor packages |
US20100314728A1 (en) * | 2009-06-16 | 2010-12-16 | Tung Lok Li | Ic package having an inductor etched into a leadframe thereof |
US20130049217A1 (en) * | 2011-08-31 | 2013-02-28 | Zhiwei Gong | Semiconductor device packaging having pre-encapsulation through via formation using drop-in signal conduits |
US8597983B2 (en) | 2011-11-18 | 2013-12-03 | Freescale Semiconductor, Inc. | Semiconductor device packaging having substrate with pre-encapsulation through via formation |
US8916421B2 (en) | 2011-08-31 | 2014-12-23 | Freescale Semiconductor, Inc. | Semiconductor device packaging having pre-encapsulation through via formation using lead frames with attached signal conduits |
US20150041979A1 (en) * | 2013-08-06 | 2015-02-12 | Motorola Mobility Llc | Method to enhance reliability of through mold via tmva part on part pop devices |
US11355470B2 (en) * | 2020-02-27 | 2022-06-07 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor device and methods of manufacturing semiconductor devices |
Families Citing this family (87)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7386656B2 (en) | 2006-07-31 | 2008-06-10 | Metaram, Inc. | Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit |
US20080028136A1 (en) | 2006-07-31 | 2008-01-31 | Schakel Keith R | Method and apparatus for refresh management of memory modules |
WO2007002324A2 (en) | 2005-06-24 | 2007-01-04 | Metaram, Inc. | An integrated memory core and memory interface circuit |
US9171585B2 (en) | 2005-06-24 | 2015-10-27 | Google Inc. | Configurable memory circuit system and method |
US8130560B1 (en) | 2006-11-13 | 2012-03-06 | Google Inc. | Multi-rank partial width memory modules |
US8089795B2 (en) | 2006-02-09 | 2012-01-03 | Google Inc. | Memory module with memory stack and interface with enhanced capabilities |
US20080082763A1 (en) | 2006-10-02 | 2008-04-03 | Metaram, Inc. | Apparatus and method for power management of memory circuits by a system or component thereof |
US8060774B2 (en) | 2005-06-24 | 2011-11-15 | Google Inc. | Memory systems and memory modules |
US8327104B2 (en) | 2006-07-31 | 2012-12-04 | Google Inc. | Adjusting the timing of signals associated with a memory system |
US8796830B1 (en) * | 2006-09-01 | 2014-08-05 | Google Inc. | Stackable low-profile lead frame package |
US8081474B1 (en) | 2007-12-18 | 2011-12-20 | Google Inc. | Embossed heat spreader |
US8055833B2 (en) | 2006-10-05 | 2011-11-08 | Google Inc. | System and method for increasing capacity, performance, and flexibility of flash storage |
US7609567B2 (en) | 2005-06-24 | 2009-10-27 | Metaram, Inc. | System and method for simulating an aspect of a memory circuit |
US8386722B1 (en) | 2008-06-23 | 2013-02-26 | Google Inc. | Stacked DIMM memory interface |
US9542352B2 (en) | 2006-02-09 | 2017-01-10 | Google Inc. | System and method for reducing command scheduling constraints of memory circuits |
US9507739B2 (en) | 2005-06-24 | 2016-11-29 | Google Inc. | Configurable memory circuit system and method |
US8397013B1 (en) | 2006-10-05 | 2013-03-12 | Google Inc. | Hybrid memory module |
US8438328B2 (en) | 2008-02-21 | 2013-05-07 | Google Inc. | Emulation of abstracted DIMMs using abstracted DRAMs |
US8111566B1 (en) | 2007-11-16 | 2012-02-07 | Google, Inc. | Optimal channel design for memory devices for providing a high-speed memory interface |
US8041881B2 (en) | 2006-07-31 | 2011-10-18 | Google Inc. | Memory device with emulated characteristics |
US10013371B2 (en) | 2005-06-24 | 2018-07-03 | Google Llc | Configurable memory circuit system and method |
US8077535B2 (en) | 2006-07-31 | 2011-12-13 | Google Inc. | Memory refresh apparatus and method |
US8090897B2 (en) | 2006-07-31 | 2012-01-03 | Google Inc. | System and method for simulating an aspect of a memory circuit |
US8244971B2 (en) | 2006-07-31 | 2012-08-14 | Google Inc. | Memory circuit system and method |
US8359187B2 (en) | 2005-06-24 | 2013-01-22 | Google Inc. | Simulating a different number of memory circuit devices |
US8335894B1 (en) | 2008-07-25 | 2012-12-18 | Google Inc. | Configurable memory system with interface circuit |
DE112006002300B4 (en) | 2005-09-02 | 2013-12-19 | Google, Inc. | Device for stacking DRAMs |
CN100395888C (en) * | 2005-09-30 | 2008-06-18 | 矽品精密工业股份有限公司 | Semiconductor packer and its production |
US7361531B2 (en) * | 2005-11-01 | 2008-04-22 | Allegro Microsystems, Inc. | Methods and apparatus for Flip-Chip-On-Lead semiconductor package |
US20070132075A1 (en) * | 2005-12-12 | 2007-06-14 | Mutsumi Masumoto | Structure and method for thin single or multichip semiconductor QFN packages |
US9632929B2 (en) | 2006-02-09 | 2017-04-25 | Google Inc. | Translating an address associated with a command communicated between a system and memory circuits |
US7990727B1 (en) * | 2006-04-03 | 2011-08-02 | Aprolase Development Co., Llc | Ball grid array stack |
US8310060B1 (en) | 2006-04-28 | 2012-11-13 | Utac Thai Limited | Lead frame land grid array |
US8487451B2 (en) | 2006-04-28 | 2013-07-16 | Utac Thai Limited | Lead frame land grid array with routing connector trace under unit |
US8492906B2 (en) | 2006-04-28 | 2013-07-23 | Utac Thai Limited | Lead frame ball grid array with traces under die |
JP4882562B2 (en) * | 2006-07-13 | 2012-02-22 | パナソニック株式会社 | Thermally conductive substrate, manufacturing method thereof, power supply unit, and electronic device |
US7667308B2 (en) | 2006-07-24 | 2010-02-23 | Stats Chippac, Ltd. | Leaded stacked packages having integrated upper lead |
US7724589B2 (en) | 2006-07-31 | 2010-05-25 | Google Inc. | System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits |
US9711343B1 (en) | 2006-12-14 | 2017-07-18 | Utac Thai Limited | Molded leadframe substrate semiconductor package |
US9761435B1 (en) | 2006-12-14 | 2017-09-12 | Utac Thai Limited | Flip chip cavity package |
US20080157302A1 (en) * | 2006-12-27 | 2008-07-03 | Lee Seungju | Stacked-package quad flat null lead package |
KR100893939B1 (en) * | 2007-02-16 | 2009-04-21 | 삼성전자주식회사 | Electronic device having a bonding pad structure and method of fabrication thereof |
JP2008235401A (en) | 2007-03-19 | 2008-10-02 | Spansion Llc | Semiconductor device and manufacturing method therefor |
KR100874923B1 (en) * | 2007-04-02 | 2008-12-19 | 삼성전자주식회사 | Multi-stack package, manufacturing method thereof and semiconductor package mold for manufacturing same |
US8209479B2 (en) | 2007-07-18 | 2012-06-26 | Google Inc. | Memory circuit system and method |
US8080874B1 (en) | 2007-09-14 | 2011-12-20 | Google Inc. | Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween |
US20090115070A1 (en) * | 2007-09-20 | 2009-05-07 | Junji Tanaka | Semiconductor device and method for manufacturing thereof |
JP2009094118A (en) * | 2007-10-04 | 2009-04-30 | Panasonic Corp | Lead frame, electronic component with the same, and manufacturing method thereof |
US7790512B1 (en) | 2007-11-06 | 2010-09-07 | Utac Thai Limited | Molded leadframe substrate semiconductor package |
US8063474B2 (en) | 2008-02-06 | 2011-11-22 | Fairchild Semiconductor Corporation | Embedded die package on package (POP) with pre-molded leadframe |
US9947605B2 (en) | 2008-09-04 | 2018-04-17 | UTAC Headquarters Pte. Ltd. | Flip chip cavity package |
US8288845B2 (en) | 2008-11-14 | 2012-10-16 | Triquint Semiconductor, Inc. | Package including proximately-positioned lead frame |
US20100230792A1 (en) * | 2009-03-12 | 2010-09-16 | Scott Irving | Premolded Substrates with Apertures for Semiconductor Die Packages with Stacked Dice, Said Packages, and Methods of Making the Same |
WO2010144624A1 (en) | 2009-06-09 | 2010-12-16 | Google Inc. | Programming of dimm termination resistance values |
US8236607B2 (en) * | 2009-06-19 | 2012-08-07 | Stats Chippac Ltd. | Integrated circuit packaging system with stacked integrated circuit and method of manufacture thereof |
US9449900B2 (en) | 2009-07-23 | 2016-09-20 | UTAC Headquarters Pte. Ltd. | Leadframe feature to minimize flip-chip semiconductor die collapse during flip-chip reflow |
US9355940B1 (en) | 2009-12-04 | 2016-05-31 | Utac Thai Limited | Auxiliary leadframe member for stabilizing the bond wire process |
US8368189B2 (en) | 2009-12-04 | 2013-02-05 | Utac Thai Limited | Auxiliary leadframe member for stabilizing the bond wire process |
US8575732B2 (en) | 2010-03-11 | 2013-11-05 | Utac Thai Limited | Leadframe based multi terminal IC package |
CN101834163A (en) * | 2010-04-29 | 2010-09-15 | 南通富士通微电子股份有限公司 | Semiconductor flip-chip bonding packaging heat radiation improved structure |
CN201838585U (en) * | 2010-06-17 | 2011-05-18 | 国碁电子(中山)有限公司 | Stackable chip packaging structure and base plate thereof |
KR101354894B1 (en) * | 2011-10-27 | 2014-01-23 | 삼성전기주식회사 | Semiconductor package and method for manufacturing the same and semiconductor package module having the same |
CN103441115B (en) * | 2011-11-29 | 2017-04-26 | 矽力杰半导体技术(杭州)有限公司 | Lead-wire framework and chip inversion packaging device applying the lead-wire framework |
US8643166B2 (en) | 2011-12-15 | 2014-02-04 | Stats Chippac Ltd. | Integrated circuit packaging system with leads and method of manufacturing thereof |
US8629539B2 (en) | 2012-01-16 | 2014-01-14 | Allegro Microsystems, Llc | Methods and apparatus for magnetic sensor having non-conductive die paddle |
US9812588B2 (en) | 2012-03-20 | 2017-11-07 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with integral ferromagnetic material |
US9666788B2 (en) | 2012-03-20 | 2017-05-30 | Allegro Microsystems, Llc | Integrated circuit package having a split lead frame |
US10234513B2 (en) | 2012-03-20 | 2019-03-19 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with integral ferromagnetic material |
US9494660B2 (en) | 2012-03-20 | 2016-11-15 | Allegro Microsystems, Llc | Integrated circuit package having a split lead frame |
US9029198B2 (en) | 2012-05-10 | 2015-05-12 | Utac Thai Limited | Methods of manufacturing semiconductor devices including terminals with internal routing interconnections |
US9449905B2 (en) | 2012-05-10 | 2016-09-20 | Utac Thai Limited | Plated terminals with routing interconnections semiconductor device |
US9006034B1 (en) | 2012-06-11 | 2015-04-14 | Utac Thai Limited | Post-mold for semiconductor package having exposed traces |
JP2014143326A (en) * | 2013-01-24 | 2014-08-07 | Transphorm Japan Inc | Semiconductor device, method of manufacturing semiconductor device, lead, and method of manufacturing lead |
US9411025B2 (en) | 2013-04-26 | 2016-08-09 | Allegro Microsystems, Llc | Integrated circuit package having a split lead frame and a magnet |
CN104681504A (en) * | 2013-11-29 | 2015-06-03 | 意法半导体研发(深圳)有限公司 | Electronic equipment with first and second contact bonding pads and relevant method thereof |
CN103730428B (en) * | 2013-12-05 | 2017-09-08 | 通富微电子股份有限公司 | Encapsulating structure |
JP6515642B2 (en) * | 2015-04-02 | 2019-05-22 | スミダコーポレーション株式会社 | Method of manufacturing coil component and jig used for manufacturing coil component |
US9917038B1 (en) | 2015-11-10 | 2018-03-13 | Utac Headquarters Pte Ltd | Semiconductor package with multiple molding routing layers and a method of manufacturing the same |
CN117393441A (en) * | 2016-04-29 | 2024-01-12 | 库利克和索夫工业公司 | Connecting an electronic component to a substrate |
US10276477B1 (en) | 2016-05-20 | 2019-04-30 | UTAC Headquarters Pte. Ltd. | Semiconductor package with multiple stacked leadframes and a method of manufacturing the same |
JP6417466B1 (en) * | 2017-11-28 | 2018-11-07 | アオイ電子株式会社 | Semiconductor device and manufacturing method thereof |
EP3499552A1 (en) * | 2017-12-14 | 2019-06-19 | Nexperia B.V. | Semiconductor device and method of manufacture |
JP6842433B2 (en) * | 2018-01-25 | 2021-03-17 | 株式会社加藤電器製作所 | Electronic device |
CN108447840B (en) * | 2018-02-08 | 2020-04-10 | 积高电子(无锡)有限公司 | Semiconductor resistor bridge packaging structure and process |
JP7051508B2 (en) * | 2018-03-16 | 2022-04-11 | ローム株式会社 | Semiconductor devices and methods for manufacturing semiconductor devices |
CN112970198A (en) * | 2018-10-30 | 2021-06-15 | 埃赛力达加拿大有限公司 | High speed switching circuit arrangement |
US10991644B2 (en) | 2019-08-22 | 2021-04-27 | Allegro Microsystems, Llc | Integrated circuit package having a low profile |
Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5471088A (en) * | 1992-11-07 | 1995-11-28 | Goldstar Electron Co., Ltd. | Semiconductor package and method for manufacturing the same |
US6075284A (en) * | 1998-06-30 | 2000-06-13 | Hyundai Electronics Industries Co., Ltd. | Stack package |
US6337510B1 (en) * | 2000-11-17 | 2002-01-08 | Walsin Advanced Electronics Ltd | Stackable QFN semiconductor package |
US6388336B1 (en) * | 1999-09-15 | 2002-05-14 | Texas Instruments Incorporated | Multichip semiconductor assembly |
US6498392B2 (en) * | 2000-01-24 | 2002-12-24 | Nec Corporation | Semiconductor devices having different package sizes made by using common parts |
US20030038347A1 (en) * | 2001-08-22 | 2003-02-27 | Walton Advanced Electronics Ltd | Stackable-type semiconductor package |
US6552419B2 (en) * | 2001-01-25 | 2003-04-22 | Sharp Kabushiki Kaisha | Semiconductor device and liquid crystal module using the same |
US6630729B2 (en) * | 2000-09-04 | 2003-10-07 | Siliconware Precision Industries Co., Ltd. | Low-profile semiconductor package with strengthening structure |
US20030230792A1 (en) * | 2002-06-14 | 2003-12-18 | Siliconware Precision Industries Co., Ltd. | Flip-chip semiconductor package with lead frame as chip carrier and fabrication method thereof |
US20040089921A1 (en) * | 2002-11-01 | 2004-05-13 | Matsushita Electric Industrial Co., Ltd. | Lead frame and method of producing the same, and resin-encapsulated semiconductor device and method of producing the same |
US20040102037A1 (en) * | 2002-11-21 | 2004-05-27 | Kazumasa Tanida | Semiconductor device production method and semiconductor device |
US6812552B2 (en) * | 2002-04-29 | 2004-11-02 | Advanced Interconnect Technologies Limited | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
US20050110121A1 (en) * | 2002-08-30 | 2005-05-26 | Matsushita Electric Industrial Co., Ltd. | Lead frame, resin-encapsulated semiconductor device, and method of producing the same |
US7138707B1 (en) * | 2003-10-21 | 2006-11-21 | Amkor Technology, Inc. | Semiconductor package including leads and conductive posts for providing increased functionality |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07335804A (en) * | 1994-06-14 | 1995-12-22 | Dainippon Printing Co Ltd | Lead frame and its manufacture |
JP3921885B2 (en) | 1999-08-25 | 2007-05-30 | 松下電器産業株式会社 | Manufacturing method of resin-encapsulated semiconductor device |
JP2001077277A (en) | 1999-09-03 | 2001-03-23 | Sony Corp | Semiconductor package and its manufacture |
JP2001177007A (en) | 1999-12-21 | 2001-06-29 | Hitachi Ltd | Semiconductor device and manufacturing method thereof |
JP2001332866A (en) | 2000-05-24 | 2001-11-30 | Matsushita Electric Ind Co Ltd | Circuit board and method of production |
JP2002026181A (en) | 2000-07-05 | 2002-01-25 | Matsushita Electric Ind Co Ltd | Resin-sealed semiconductor device and its manufacturing method |
TW454309B (en) | 2000-07-17 | 2001-09-11 | Orient Semiconductor Elect Ltd | Package structure of CCD image-capturing chip |
JP2002170921A (en) | 2000-12-01 | 2002-06-14 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
JP2003197822A (en) | 2001-12-25 | 2003-07-11 | Sony Corp | Wiring board, multilayer wiring board and manufacturing method thereof |
JP2003249604A (en) | 2002-02-25 | 2003-09-05 | Kato Denki Seisakusho:Kk | Resin-sealed semiconductor device and method of the same, lead frame used in resin-sealed semiconductor device, and semiconductor module device |
-
2004
- 2004-03-04 JP JP2004060943A patent/JP3910598B2/en not_active Expired - Fee Related
-
2005
- 2005-02-25 TW TW094105705A patent/TW200531249A/en unknown
- 2005-03-03 US US11/071,343 patent/US7495319B2/en active Active
- 2005-03-04 CN CN2005100529995A patent/CN1665023A/en active Pending
-
2009
- 2009-01-16 US US12/355,075 patent/US20090130801A1/en not_active Abandoned
Patent Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5471088A (en) * | 1992-11-07 | 1995-11-28 | Goldstar Electron Co., Ltd. | Semiconductor package and method for manufacturing the same |
US6075284A (en) * | 1998-06-30 | 2000-06-13 | Hyundai Electronics Industries Co., Ltd. | Stack package |
US6388336B1 (en) * | 1999-09-15 | 2002-05-14 | Texas Instruments Incorporated | Multichip semiconductor assembly |
US6498392B2 (en) * | 2000-01-24 | 2002-12-24 | Nec Corporation | Semiconductor devices having different package sizes made by using common parts |
US6630729B2 (en) * | 2000-09-04 | 2003-10-07 | Siliconware Precision Industries Co., Ltd. | Low-profile semiconductor package with strengthening structure |
US6337510B1 (en) * | 2000-11-17 | 2002-01-08 | Walsin Advanced Electronics Ltd | Stackable QFN semiconductor package |
US6552419B2 (en) * | 2001-01-25 | 2003-04-22 | Sharp Kabushiki Kaisha | Semiconductor device and liquid crystal module using the same |
US20030038347A1 (en) * | 2001-08-22 | 2003-02-27 | Walton Advanced Electronics Ltd | Stackable-type semiconductor package |
US6812552B2 (en) * | 2002-04-29 | 2004-11-02 | Advanced Interconnect Technologies Limited | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
US20030230792A1 (en) * | 2002-06-14 | 2003-12-18 | Siliconware Precision Industries Co., Ltd. | Flip-chip semiconductor package with lead frame as chip carrier and fabrication method thereof |
US20050110121A1 (en) * | 2002-08-30 | 2005-05-26 | Matsushita Electric Industrial Co., Ltd. | Lead frame, resin-encapsulated semiconductor device, and method of producing the same |
US20040089921A1 (en) * | 2002-11-01 | 2004-05-13 | Matsushita Electric Industrial Co., Ltd. | Lead frame and method of producing the same, and resin-encapsulated semiconductor device and method of producing the same |
US20040102037A1 (en) * | 2002-11-21 | 2004-05-27 | Kazumasa Tanida | Semiconductor device production method and semiconductor device |
US7138707B1 (en) * | 2003-10-21 | 2006-11-21 | Amkor Technology, Inc. | Semiconductor package including leads and conductive posts for providing increased functionality |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080296759A1 (en) * | 2007-06-04 | 2008-12-04 | Stats Chippac, Inc. | Semiconductor packages |
US8106496B2 (en) * | 2007-06-04 | 2012-01-31 | Stats Chippac, Inc. | Semiconductor packaging system with stacking and method of manufacturing thereof |
US20100314728A1 (en) * | 2009-06-16 | 2010-12-16 | Tung Lok Li | Ic package having an inductor etched into a leadframe thereof |
US20130049217A1 (en) * | 2011-08-31 | 2013-02-28 | Zhiwei Gong | Semiconductor device packaging having pre-encapsulation through via formation using drop-in signal conduits |
US8916421B2 (en) | 2011-08-31 | 2014-12-23 | Freescale Semiconductor, Inc. | Semiconductor device packaging having pre-encapsulation through via formation using lead frames with attached signal conduits |
US9142502B2 (en) * | 2011-08-31 | 2015-09-22 | Zhiwei Gong | Semiconductor device packaging having pre-encapsulation through via formation using drop-in signal conduits |
US8597983B2 (en) | 2011-11-18 | 2013-12-03 | Freescale Semiconductor, Inc. | Semiconductor device packaging having substrate with pre-encapsulation through via formation |
US20150041979A1 (en) * | 2013-08-06 | 2015-02-12 | Motorola Mobility Llc | Method to enhance reliability of through mold via tmva part on part pop devices |
US9082766B2 (en) * | 2013-08-06 | 2015-07-14 | Google Technology Holdings LLC | Method to enhance reliability of through mold via TMVA part on part POP devices |
US11355470B2 (en) * | 2020-02-27 | 2022-06-07 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor device and methods of manufacturing semiconductor devices |
Also Published As
Publication number | Publication date |
---|---|
CN1665023A (en) | 2005-09-07 |
US20050194676A1 (en) | 2005-09-08 |
TW200531249A (en) | 2005-09-16 |
US7495319B2 (en) | 2009-02-24 |
JP2005252018A (en) | 2005-09-15 |
JP3910598B2 (en) | 2007-04-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7495319B2 (en) | Resin-encapsulated semiconductor device and lead frame, and method for manufacturing the same | |
US5953589A (en) | Ball grid array semiconductor package with solder balls fused on printed circuit board and method for fabricating the same | |
KR100511728B1 (en) | Compact semiconductor device capable of mounting a plurality of semiconductor chips with high density and method of manufacturing the same | |
US6683795B1 (en) | Shield cap and semiconductor package including shield cap | |
US8471361B2 (en) | Integrated chip package structure using organic substrate and method of manufacturing the same | |
US7723852B1 (en) | Stacked semiconductor package and method of making same | |
US7541278B2 (en) | Interconnect substrate, semiconductor device, methods of manufacturing the same, circuit board, and electronic equipment | |
US7633144B1 (en) | Semiconductor package | |
US8067814B2 (en) | Semiconductor device and method of manufacturing the same | |
US6781240B2 (en) | Semiconductor package with semiconductor chips stacked therein and method of making the package | |
US7981796B2 (en) | Methods for forming packaged products | |
US8841759B2 (en) | Semiconductor package and manufacturing method thereof | |
JP2005183923A (en) | Semiconductor device and its manufacturing method | |
US6903449B2 (en) | Semiconductor component having chip on board leadframe | |
JP2001298115A (en) | Semiconductor device, manufacturing method for the same, circuit board as well as electronic equipment | |
US10741415B2 (en) | Thermosonically bonded connection for flip chip packages | |
KR100461718B1 (en) | Chip scale package and the method of fabricating the same | |
US7045893B1 (en) | Semiconductor package and method for manufacturing the same | |
JP4598316B2 (en) | Resin-sealed semiconductor device and manufacturing method thereof | |
JP3841135B2 (en) | Semiconductor device, circuit board and electronic equipment | |
JP2002353275A (en) | Semiconductor device and manufacturing method thereof and mounting method | |
KR102392784B1 (en) | Multi-chip Semiconductor Package | |
JP2004165314A (en) | Semiconductor device and its manufacturing method | |
KR101217375B1 (en) | Semiconductor package and fabricating method thereof | |
KR20030082129A (en) | A manufacturing method of a battery package for a portable terminal |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |
|
AS | Assignment |
Owner name: III HOLDINGS 12, LLC, DELAWARE Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PANASONIC CORPORATION;REEL/FRAME:042294/0727 Effective date: 20170324 |