US20090162982A1

US20090162982A1 - Array substrate, display device having the same and method of manufacturing the same

Info

Publication number: US20090162982A1
Application number: US12/392,629
Authority: US
Inventors: Je-Hun Lee; Do-Hyun Kim; Eun-Guk Lee; Chang-Oh Jeong
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2006-07-20
Filing date: 2009-02-25
Publication date: 2009-06-25
Also published as: EP1881366B1; KR20080008562A; CN101132011A; DE602007009162D1; JP2008028395A; US20080017862A1; US20110309510A1; EP1881366A1; US7511300B2

Abstract

An array substrate includes a switching element, a signal transmission line, a passivation layer and a pixel electrode. The switching element is disposed on an insulating substrate. The signal transmission line is connected to the switching element and includes a barrier layer, a conductive line, and a copper nitride layer. The barrier layer is disposed on the insulating substrate. The conductive line is disposed on the barrier layer and includes copper or copper alloy. The copper nitride layer covers the conductive line. The passivation layer covers the switching element and the signal transmission line and has a contact hole through which a drain electrode of the switching element is partially exposed. The pixel electrode is disposed on the insulating substrate, and is connected to the drain electrode of the switching element through the contact hole.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of prior application Ser. No. 11/779,534, filed Jul. 18, 2007, and claims priority from and the benefit of Korean Patent Application No. 2006-67979, filed on Jul. 20, 2006, which are all hereby incorporated by reference for all purposes as if fully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to an array substrate, a display device including the array substrate, and a method of manufacturing the array substrate. More particularly, the present invention relates to an array substrate capable of decreasing line resistance and the occurrence of line defects, a display device including the array substrate, and a simplified method of manufacturing the array substrate.
2. Discussion of the Background
An array substrate of a flat panel display device includes various lines for transmitting signals, which are formed through thin film deposition processes.
In the flat panel display device, the length of the lines has been increased, and the thickness of the lines has been decreased, thereby increasing the resistance of the lines.
In addition, the lines chemically react with an insulating substrate, an insulating layer, oxygen, etc., so that the resistance of the lines is greatly increased. Therefore, the image display quality is deteriorated.
Furthermore, when a metal layer is etched to form the lines, the etching uniformity of the metal layer may be deteriorated, which may deteriorate the etching profile of the lines.

SUMMARY OF THE INVENTION

The present invention provides an array substrate capable of decreasing line resistance and the occurrence of line defects.
The present invention also provides a display device including the above mentioned array substrate.
The present invention also provides a simplified method of manufacturing the array substrate.
The present invention discloses an array substrate including a switching element, a signal transmission line, a passivation layer, and a pixel electrode. The switching element is on an insulating substrate. The signal transmission line is connected to the switching element and includes a barrier layer, a conductive line, and a copper nitride layer. The barrier layer is on the insulating substrate. The conductive line is on the barrier layer and includes copper or copper alloy. The copper nitride layer covers the conductive line. The passivation layer covers the switching element and the signal transmission line and includes a contact hole through which a drain electrode of the switching element is partially exposed. The pixel electrode is on the insulating substrate and connected to the drain electrode of the switching element through the contact hole.
The present invention also discloses a display device including a switching element, a signal transmitting line, a pixel electrode, a passivation layer, a liquid crystal layer, an opposite electrode, and an opposite insulating substrate. The switching element is on an insulating substrate. The signal transmitting line is connected to the switching element. The signal transmitting line includes a barrier layer, a conductive line, and a copper nitride layer. The barrier layer is on the insulating substrate. The conductive line is on the barrier layer and includes copper or copper alloy. The copper nitride layer covers the conductive line. The pixel electrode is on the insulating substrate and is connected to a drain electrode of the switching element. The passivation layer covers the switching element and the signal transmission line. The liquid crystal layer is on the passivation layer. The opposite electrode is on the liquid crystal layer and faces the pixel electrode. The opposite insulating substrate is on the opposite electrode and faces the insulating substrate.
The present invention also discloses a method of manufacturing an array substrate that is provided as follows. A barrier layer is formed on an insulating substrate. A gate line and a gate electrode are formed on the barrier layer. The gate line includes copper or copper alloy and the gate electrode is connected to the gate line. Nitride plasma is applied to the gate line and the gate electrode. A gate insulating layer is deposited on the insulating substrate to cover the gate line and the gate electrode. A data line, a source electrode connected to the data line, a drain electrode spaced apart from the source electrode, and a semiconductor pattern are formed on the gate insulating layer. The source electrode is connected to the data line and the drain electrode is spaced apart from the source electrode. The semiconductor pattern is on the gate electrode between the source electrode and the drain electrode.
The present invention discloses another method of manufacturing an array substrate that is provided as follows. A gate line, a gate electrode, and a gate insulating layer are formed on an insulating substrate. The gate electrode is connected to the gate line. The gate insulating layer covers the gate line and the gate electrode. A semiconductor pattern is formed on the gate insulating layer corresponding to the gate electrode. A data line, a source electrode, and a drain electrode are formed on the gate insulating layer. The data line includes copper or copper alloy. The source electrode is connected to the data line. The drain electrode is spaced apart from the source electrode with respect to the semiconductor pattern. Nitride plasma is applied to the data line, the source electrode, and the drain electrode. A passivation layer is deposited on the gate insulating layer to cover the semiconductor pattern, the data line, the source electrode, and the drain electrode.
The present invention discloses still another method of manufacturing an array substrate that is provided as follows. A first barrier layer, a first conductive layer, and a first copper nitride layer are deposited on an insulating substrate, in sequence. The first conductive layer includes copper or copper alloy. The first barrier layer, the first conductive layer, and the first copper nitride layer are patterned to form a gate line and a gate electrode connected to the gate line. A gate insulating layer is deposited on the insulating substrate to cover the gate line and the gate electrode. A data line, a source electrode, a drain electrode, and a semiconductor pattern are formed on the gate insulating layer. The source electrode is connected to the data line and the drain electrode is spaced apart from the source electrode. The semiconductor pattern is on the gate electrode between the source electrode and the drain electrode.
The present invention discloses yet another method of manufacturing an array substrate that is provided as follows. A barrier layer is formed on an insulating substrate. A gate line and a gate electrode are formed on the barrier layer. The gate line includes copper or copper alloy and the gate electrode is connected to the gate line. Hydrogen plasma is applied to the gate line and the gate electrode. A first gas mixture is injected into a chamber to form a first gate insulating layer on the insulating substrate. The first gas mixture includes silane gas, nitrogen gas, and ammonia gas. The amount of silane gas in the first gas mixture is no more than about 6.43% by volume. A second gas mixture is injected into the chamber to form a second gate insulating layer on the insulating substrate. The second gas mixture includes silane gas, nitrogen gas, and ammonia gas. The amount of silane gas in the second gas mixture is no less than about 6.43% by volume. A third gas mixture is injected into the chamber to form a third gate insulating layer on the insulating substrate. The third gas mixture includes silane gas, nitrogen gas, and ammonia gas. The amount of silane gas in the third gas mixture is no more than about 6.43% by volume. A data line, a source electrode, a drain electrode, and a semiconductor pattern are formed on the third gate insulating layer. The source electrode is connected to the data line and the drain electrode is spaced apart from the source electrode. The semiconductor pattern is on the gate electrode between the source electrode and the drain electrode.
It is to be understood that both the foregoing and general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention, and together with the description serve to explain the principles of the invention.

FIG. 1 is a plan view showing an array substrate in accordance with one exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line I-I′ of FIG. 1.

FIG. 3 is an enlarged cross-sectional view showing portion ‘A’ of FIG. 2.

FIG. 4 is a cross-sectional view taken along line II-II′ of FIG. 1.

FIG. 5, FIG. 6, FIG. 7, FIG. 8, FIG. 9, FIG. 10, FIG. 11, FIG. 12, FIG. 13, FIG. 14, FIG. 15, FIG. 16, FIG. 17, FIG. 18, and FIG. 19 are cross-sectional views showing a method of manufacturing the array substrate of FIG. 1.

FIG. 20 is a cross-sectional view showing a display device in accordance with another exemplary embodiment of the present invention.

FIG. 21 is a cross-sectional view showing an array substrate in accordance with another embodiment of the present invention.

FIG. 22, FIG. 23, FIG. 24, FIG. 25, and FIG. 26 are cross-sectional views showing a method of manufacturing the array substrate shown in FIG. 21.

FIG. 27 is a cross-sectional view showing an array substrate in accordance with another exemplary embodiment of the present invention.

FIG. 28 is a cross-sectional view showing an array substrate in accordance with another exemplary embodiment of the present invention.

FIG. 29 is a cross-sectional view showing a display device in accordance with another exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

The invention is described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity.
It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numbers refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a plan view showing an array substrate in accordance with one exemplary embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line I-I′ of FIG. 1. FIG. 3 is an enlarged cross-sectional view showing portion ‘A’ of FIG. 2. FIG. 4 is a cross-sectional view taken along line II-II′ of FIG. 1.
Referring to FIG. 1, FIG. 2, and FIG. 4, the array substrate includes an insulating substrate 120, a gate line 131, a data line 133, a gate insulating layer 126, a passivation layer 116, and a pixel electrode 112. Alternatively, the array substrate may include a plurality of gate lines, a plurality of data lines, and a plurality of pixel electrodes.
The insulating substrate 120 may include a transparent glass that transmits light. The insulating substrate 120 may not include alkaline ions. When the insulating substrate 120 includes alkaline ions, the alkaline ions may be dissolved in a liquid crystal layer (not shown) and may decrease the resistance of the liquid crystal layer, which may decrease the image display quality and the adhesive strength between a sealant (not shown) and the insulating substrate 120. In addition, characteristics of a thin film transistor may be deteriorated.
The insulating substrate 120 may also include a high polymer that is optically transparent. Examples of optically transparent high polymers that may be included in the insulating substrate 120 include triacetylcellulose (TAC), polycarbonate (PC), polyethersulfone (PES), polyethyleneterephthalate (PET), polyethylenenaphthalate (PEN), polyvinylalcohol (PVA), polymethylmethacrylate (PMMA), cyclo-olefin polymer (COP), and combinations thereof.
The insulating substrate 120 may be optically isotropic. Alternatively, the insulating substrate 120 may be optically anisotropic.
The gate line 131 is disposed on the insulating substrate 120. The gate line 131 includes a gate barrier layer 131 a, a gate conductive layer 131 b, and a gate copper nitride layer 131 c.
The gate barrier layer 131 a is disposed on the insulating substrate 120. The gate barrier layer 131 a increases the adhesive strength between the gate line 131 and the insulating substrate 120. Examples of barrier material that may be used in the gate barrier layer 131 a include molybdenum (Mo), molybdenum-titanium (Mo—Ti) alloy, molybdenum-tungsten (Mo—W) alloy, molybdenum-chromium (Mo—Cr) alloy, molybdenum-niobium (Ni) alloy, and combinations thereof.
Copper nitride may be disposed on a side surface of the gate barrier layer 131 a.
The gate conductive layer 131 b is disposed on the gate barrier layer 131 a. The gate conductive layer 131 b may include copper or copper alloy. When the gate conductive layer 131 b includes copper, the resistance of the gate conductive layer 131 b is about 2.1 μΩcm to about 2.3 μΩcm. Thus, the resistance of the gate conductive layer 131 b is about 30% smaller than that of an aluminum layer, which has a resistance of about 3.1 μΩcm. In addition, the gate conductive layer 131 b has lower electro-migration than an aluminum layer.
The gate copper nitride layer 131 c is disposed on an upper surface and a side surface of the gate conductive layer 131 b. The gate copper nitride layer 131 c includes copper nitride. Nitride plasma may be implanted into a copper line to form the gate copper nitride layer 131 c. Examples of nitride plasma that may be implanted into the copper line include ammonia (NH₃) plasma, nitrogen (N₂) plasma, and combinations thereof.
The gate copper nitride layer 131 c prevents the copper of the gate conductive layer 131 b from mixing with impurities such as oxygen and silicon. In addition, the gate copper nitride layer 131 c has greater resistance to etching than the gate conductive layer 131 b and therefore, may protect the gate conductive layer 131 b from a subsequent process, such as an etching process or a stripping process.
A gate electrode 118 of the thin film transistor 155 is disposed on the insulating substrate 120. The gate electrode 118 may include copper or copper alloy. The gate electrode 118 may be formed on substantially the same layer as the gate line 131. The gate electrode 118 includes a gate barrier pattern 118 a, a gate conductive pattern 118 b, and a gate copper nitride pattern 118 c.
The gate barrier pattern 118 a is disposed on the insulating substrate 120. The gate barrier pattern 118 a may include molybdenum (Mo), molybdenum-titanium (Mo—Ti) alloy, molybdenum-tungsten (Mo—W) alloy, molybdenum-chromium (Mo—Cr) alloy, molybdenum-niobium (Ni) alloy, and combinations thereof. For example, the gate barrier pattern 118 a may include substantially the same material as the gate barrier layer 131 a of the gate line 131.
The gate conductive pattern 118 b is disposed on the gate barrier pattern 118 a. The gate conductive pattern 118 b may include copper or copper alloy. For example, the gate conductive pattern 118 b may include substantially the same material as the gate conductive layer 131 b of the gate line 131.
The gate copper nitride pattern 118 c is disposed on an upper surface and a side surface of the gate conductive pattern 118 b. The copper nitride pattern 118 c may include copper nitride. For example, the gate copper nitride pattern 118 c may include substantially the same material as the gate copper nitride layer 131 c of the gate line 131.
The gate insulating layer 126 is disposed on the insulating substrate 120 to cover the gate line 131 and the gate electrode 118.
Referring to FIG. 3, the gate insulating layer 126 includes a first gate insulating layer 126 a, a second gate insulating layer 126 b, and a third gate insulating layer 126 c. The gate insulating layer 126 may be formed through a chemical vapor deposition (CVD) method using silane gas and nitride mixture gas. The chemical vapor deposition method may be a plasma enhanced chemical vapor deposition (PECVD) method. The nitride mixture gas may contain nitrogen (N₂) gas, ammonia (NH₃) gas, and combinations thereof.
The first gate insulating layer 126 a is disposed on the insulating substrate 120 on which the gate line 131 and the gate electrode 118 are formed. The first gate insulating layer 126 a may include a low density silicon nitride and the density of the first gate insulating layer 126 a may be low. The amount of silane gas in the first gas mixture may be no more than about 6.43% by volume. Silicon atoms may be securely combined with nitrogen atoms in the low density silicon nitride. For example, the number of dangling bonds on which electrons may be trapped may be decreased in the low density silicon nitride, which may decrease the deposition speed. In addition, the surface structure of the low density silicon nitride may be dense making it a good electrical insulator.
The second gate insulating layer 126 b is disposed on the first gate insulating layer 126 a and may include a high density silicon nitride. The density of the second gate insulating layer 126 b may be higher than that of the first gate insulating layer 126 a. The amount of silane gas in the second gas mixture may be no less than about 6.43% by volume. The second gas mixture may contain more silane gas than the first gas mixture. Silicon atoms may be loosely combined with nitrogen atoms in the high density silicon nitride. For example, the number of dangling bonds may be increased in the high density silicon nitride such that electrons may be trapped in the dangling bonds. The deposition speed of the high density silicon nitride may be faster than that of low density silicon nitride. In addition, the surface structure of the low density silicon nitride may be loose and the high density silicon nitride may be a poorer electrical insulator than the low density silicon nitride.
The third gate insulating layer 126 c is disposed on the second gate insulating layer 126 b and may include substantially the same low density silicon nitride as the first gate insulating layer 126 a. Since the third gate insulating layer 126 c includes substantially the same material as the first gate insulating layer 126 a, any further explanation concerning the above elements will be omitted. When the third gate insulating layer 126 c includes low density silicon nitride, the electrical characteristics of the amorphous silicon pattern 137 a of the semiconductor pattern 137 may be improved.
The nitrogen density of the first gate insulating layer 126 a may be higher than that of the second gate insulating layer 126 b so that copper atoms in the gate line 131 and the gate electrode 118 may not be combined with silicon atoms. The deposition speed of the second gate insulating layer 126 b may be faster than that of the first gate insulating layer 126 b, thereby decreasing the manufacturing time of the array substrate. The third gate insulating layer 126 c may have a denser structure and therefore, more secure electrical characteristics, than the second gate insulating layer 126 b. Thus, the third gate insulating layer 126 c may improve the electrical characteristics of the amorphous silicon pattern 137 a.
Referring again to FIG. 1, FIG. 2, and FIG. 4, the semiconductor pattern 137 of the thin film transistor 155 is disposed on the gate insulating layer 126 corresponding to the gate electrode 118. The semiconductor pattern 137 includes the amorphous silicon pattern 137 a and an n+ amorphous silicon pattern 137 b.
The amorphous silicon pattern 137 a is disposed on the gate insulating layer 126 corresponding to the gate electrode 118. The amorphous silicon pattern 137 a may include a lower amorphous silicon pattern (not shown) and an upper amorphous silicon pattern (not shown). The lower amorphous silicon pattern may be deposited at a higher temperature and at a slower speed than the upper amorphous silicon pattern such that it has a denser structure than the upper amorphous silicon pattern.
When an electric field is applied between the gate electrode 118 and the source electrode 117, a channel is formed in the lower amorphous silicon pattern adjacent to the gate insulating layer 126. In FIG. 1, FIG. 2, FIG. 3, and FIG. 4, the lower amorphous silicon pattern has a denser structure than the upper amorphous silicon pattern and therefore, the number of the dangling bonds trapping electrons is smaller in the lower amorphous silicon pattern. Thus, the electrical characteristics of the semiconductor pattern 137 may be improved. In addition, the deposition speed of the upper amorphous silicon pattern may be faster than that of the lower amorphous silicon pattern, which may decrease the manufacturing time.
The n+ amorphous silicon pattern 137 b includes a first pattern and a second pattern. The first and second patterns are spaced apart from each other on the amorphous silicon pattern 137 a.
The data line 133 is disposed on the gate insulating layer 126. The data line 133 includes a data barrier layer 133 a, a data conductive layer 133 b, and a data copper nitride layer 133 c.
The data barrier layer 133 a is on the gate insulating layer 126, the amorphous silicon pattern 137 a, and the n+ amorphous silicon pattern 137 b. The data barrier layer 133 a prevents the silicon atoms of the gate insulating layer 126 from diffusing into the data conductive layer 133 b, which may prevent the resistance of the data conductive layer 133 b from increasing. Examples of a conductive material that may be included in the data barrier layer 133 a include molybdenum (Mo), molybdenum-titanium (Mo—Ti) alloy, molybdenum-tungsten (Mo—W) alloy, molybdenum-chromium (Mo—Cr) alloy, molybdenum-niobium (Mo—Nb) alloy, and combinations thereof. A metal nitride layer may be formed on a side surface of the data barrier layer 133 a.
The data conductive layer 133 b is disposed on the data barrier layer 133 a. The data conductive layer 133 b may include copper or copper alloy. For example, the data conductive layer 133 b may include substantially the same material as the gate conductive layer 131 b. Thus, any further explanation concerning the above elements will be omitted.
The data copper nitride layer 133 c is disposed on an upper surface and a side surface of the data conductive layer 133 b. The data copper nitride layer 133 c may include substantially the same copper nitride as the gate copper nitride layer 131 c. Alternatively, a data copper hydrogenated layer may be formed on the upper surface and the side surface of the data conductive layer 133 b.
A source electrode 117 of the thin film transistor 155 is disposed on a first pattern of the n+ amorphous silicon pattern. The source electrode 117 may include copper or copper alloy. The source electrode 117 may be formed on substantially the same layer as the data line 133. The source electrode 117 is connected to the data line 133 and includes a source barrier pattern 117 a, a source conductive pattern 117 b, and a source copper nitride pattern 117 c.
The source barrier pattern 117 a is disposed on the first pattern of the n+ amorphous silicon pattern. The source barrier pattern 117 a may include a conductive material such as molybdenum (Mo), molybdenum-titanium (Mo—Ti) alloy, molybdenum-tungsten (Mo—W) alloy, molybdenum-chromium (Mo—Cr) alloy, molybdenum-niobium (Ni) alloy, and combinations thereof. For example, the source barrier pattern 117 a may include substantially the same material as the data barrier layer 133 a of the data line 133.
The source conductive pattern 117 b is disposed on the source barrier pattern 117 a. The source conductive pattern 117 b may include copper or copper alloy. For example, the source conductive pattern 117 b may include substantially the same material as the data conductive layer 133 b of the data line 133.
The source copper nitride pattern 117 c is disposed on an upper surface and a side surface of the source conductive pattern 117 b. The source copper nitride pattern 117 c may include copper nitride. For example, the source copper nitride pattern 117 c may include substantially the same material as the data copper nitride layer 133 c of the data line 133.
A drain electrode 119 of the thin film transistor 155 is disposed on a second pattern of the n+ amorphous silicon pattern. The drain electrode 119 may include copper or a copper alloy. For example, the drain electrode 119 may be formed from substantially the same layer as the data line 133. The drain electrode 119 is electrically connected to the pixel electrode 112 and includes a drain barrier pattern 119 a, a drain conductive pattern 119 b, and a drain copper nitride pattern 119 c.
The drain barrier pattern 119 a is on the second pattern of the n+ amorphous silicon pattern. The drain barrier pattern 119 a may include molybdenum (Mo), molybdenum-titanium (Mo—Ti) alloy, molybdenum-tungsten (Mo—W) alloy, molybdenum-chromium (Mo—Cr) alloy, molybdenum-niobium (Ni) alloy, and combinations thereof. For example, the drain barrier pattern 119 a may include substantially the same material as the data barrier layer 133 a of the data line 133.
The drain conductive pattern 119 b is disposed on the drain barrier pattern 119 a. The drain conductive pattern 119 b may include copper or a copper alloy. For example, the drain conductive pattern 119 b may include substantially the same material as the data conductive layer 133 b of the data line 133.
The drain copper nitride pattern 119 c is disposed on an upper surface and a side surface of the drain conductive pattern 119 b. The drain copper nitride pattern 119 c may include copper nitride. For example, the drain copper nitride pattern 119 c may include substantially the same material as the data copper nitride layer 133 c of the data line 133.
The passivation layer 116 is disposed on the gate insulating layer 126 to cover the semiconductor pattern 137, the data line 133, the source electrode 117, and the drain electrode 119. The passivation layer 116 may include silicon nitride. Alternatively, the passivation layer 116 may have a double layered structure including a low density silicon nitride layer and a high density silicon nitride layer. The passivation layer 116 may have a contact hole 151 through which the drain electrode 119 is partially exposed.
The pixel electrode 112 is disposed on the passivation layer 116 and is connected to the drain electrode 119 through the contact hole 151. The pixel electrode 112 may include a transparent conductive material. Examples of the transparent conductive material that may be included in the pixel electrode 112 include indium tin oxide (ITO), indium zinc oxide (IZO), amorphous indium tin oxide (a-ITO), and combinations thereof.
According to the array substrate shown in FIG. 1, FIG. 2, FIG. 3, and FIG. 4, the gate line 131, the gate electrode 118, the data line 133, the source electrode 117, and the drain electrode 119 include the gate copper nitride line 131 c, the gate copper nitride pattern 118 c, the data copper nitride line 133 c, the source copper nitride pattern 117 c, and the drain copper nitride pattern 119 c, respectively, to decrease the occurrence of defects of the gate line 131, the gate electrode 118, the data line 133, the source electrode 117 and the drain electrode 119. In addition, the gate insulating layer 126 may have a triple layered structure, which may decrease the manufacturing time of the array substrate and improve the electrical characteristics of the amorphous silicon pattern 137 a of the array substrate.
FIG. 5, FIG. 6, FIG. 7, FIG. 8, FIG. 9, FIG. 10, FIG. 1, FIG. 12, FIG. 13, FIG. 14, FIG. 15, FIG. 16, FIG. 17, FIG. 18, and FIG. 19 are cross-sectional views showing a method of manufacturing the array substrate shown in FIG. 1.
Referring to FIG. 1 and FIG. 5, a primary gate barrier layer 141 and a primary gate conductive layer 142 are formed on the insulating substrate 120, in sequence. A copper nitride layer (not shown) may be formed on the primary gate conductive layer 142 through a sputtering process. A gate photoresist film 143 is coated on the primary gate conductive layer 142.
The gate photoresist film 143 is exposed through a gate mask 171. The gate mask 171 includes a light blocking portion 171 a and a transparent portion 171 b. The light blocking portion 171 a corresponds to the gate line 131 and the gate electrode 118.
Referring to FIG. 1 and FIG. 6, the exposed gate photoresist film 143 is developed to form a gate photoresist pattern 143 a on the primary gate conductive layer 142.
Referring to FIG. 1 and FIG. 7, the primary gate conductive layer 142 and the primary gate barrier layer 141 are partially etched, using the gate photoresist pattern 143 a as an etching mask, to form the gate barrier layer 131 a, a primary gate conductive layer 131 d, the gate barrier pattern 118 a, and a primary gate conductive pattern 118 d on the insulating substrate 120. The gate photoresist pattern 143 a is then removed from the primary gate conductive layer 131 d and the primary gate conductive pattern 118 c.
Referring to FIG. 1 and FIG. 8, nitride plasma is applied to the insulating substrate 120, on which the primary gate conductive layer 131 d, the gate barrier layer 131 a, the gate barrier pattern 118 a, and the primary gate conductive pattern 118 d are formed. For example, ammonia gas and nitrogen gas may be injected into a chamber (not shown) and an electric power of no less than about 300 W may be applied to the ammonia gas and the nitrogen gas for a period of no less than about 20 seconds.
Referring to FIG. 1 and FIG. 9, the nitride plasma 188 a (shown in FIG. 8) is injected onto an upper surface and a side surface of the primary gate conductive layer 131 d to form the gate conductive layer 131 b and the gate copper nitride layer 131 c on the gate barrier layer 131 a. In addition, the nitride plasma 188 a is also injected onto an upper surface and a lower surface of the primary gate conductive pattern 118 d to form the gate conductive pattern 118 b and the gate copper nitride pattern 118 c on the gate barrier pattern 118 a.
Furthermore, copper oxide that may be formed on surfaces of the primary gate conductive layer 131 d and the primary gate conductive pattern 118 d by oxygen or water vapor is converted into copper nitride by the nitride plasma 118 a. Copper nitride has better electrical and manufacturing characteristics than copper oxide. For example, copper nitride has less resistance and greater mechanical strength than copper oxide.
A gas mixture, including silane gas and a nitride mixture gas, may be injected onto the insulating substrate 120, on which the gate electrode 118, the gate line 131, and the gate insulating layer 126 (shown in FIG. 2) are formed, through a chemical vapor deposition (CVD) method. Examples of the nitride mixture gas that may be injected onto the insulating substrate 120 include nitrogen gas, ammonia gas, and combinations thereof. The chemical vapor deposition method may be a plasma enhanced chemical vapor deposition (PECVD) method.
FIG. 10, FIG. 11, FIG. 12, and FIG. 13 are cross-sectional views showing a method of disposing the gate insulating layer shown in FIG. 2.
Referring to FIG. 9 and FIG. 10, the first gas mixture is injected into the chamber. The amount of silane gas in the first gas mixture may be no more than about 6.43% by volume. An electric power is applied to the first gas mixture to generate a low density silicon nitride plasma 189 a, which is applied to the insulating substrate 120 on which the gate electrode 118 and the gate line 131 are formed. Thus, the first gate insulating layer 126 a (shown in FIG. 3), including low density silicon nitride, is formed on the insulating substrate 120 on which the gate electrode 118 and the gate line 131 are formed. For example, the gate insulating layer 126 may be formed in the chamber in which the nitride plasma is applied to the insulating substrate 120, in situ.
When the amount of silane gas in the first gas mixture for forming the first gate insulating layer 126 a is no more than about 6.43% by volume, enough nitrogen atoms may be present for the silicon atoms in the silane gas to react with the nitrogen atoms, thereby forming silicon nitride. Thus, the first gate insulating layer 126 a may have a dense structure and be a good electrical insulator. However, the deposition speed of the first gate insulating layer 126 a may be decreased.
When the amount of silane gas in the first gas mixture for disposing the first gate insulating layer 126 a is more than about 6.43% by volume, a portion of the silicon atoms in the silane gas may not react with nitrogen atoms and therefore, the silicon atoms may react with copper atoms of the gate line 131 and the gate electrode 118, forming silicon copper (CuSi). Silicon atoms of the silicon copper may be separated from the copper atoms of the silicon copper and may be implanted into the gate line 131 and the gate electrode 118. When the silicon atoms are implanted into the gate line 131 and the gate electrode 118, the resistance of the gate line 131 and the gate electrode 118 may be greatly increased. However, in FIG. 9 and FIG. 10, the amount of silane gas in the first gas mixture for forming the first gate insulating layer 126 a is no more than about 6.43% by volume and therefore, the copper nitride of the gate copper nitride layer 131 c and the gate copper nitride pattern 118 c may not react with the silicon atoms.
In FIG. 9 and FIG. 10, the amount of silane gas in the first gas mixture for forming the first gate insulating layer 126 a is about 2.24% by volume and the electric power applied to the chamber is about 900 W. In addition, the thickness of the first gate insulating layer 126 a is no less than about 10{acute over (Å)}.
Referring to FIG. 9 and FIG. 11, the second gas mixture for forming the second gate insulating layer 126 b (shown in FIG. 3) is injected into the chamber. The amount of silane gas in the second gas mixture is no less than about 6.43% by volume. An electric power is applied to the second gas mixture to generate high density silicon nitride plasma 189 b, and the high density silicon nitride plasma 189 b is applied to the first gate insulating layer 126 a. Thus, the second gate insulating layer 126 b (shown in FIG. 3), including high density silicon nitride, is disposed on the first gate insulating layer 126 a. For example, the first gate insulating layer 126 a and the second gate insulating layer 126 b may be formed in the chamber, in situ.
When the amount of silane gas in the second gas mixture for disposing the second gate insulating layer 126 b is no less than about 6.43% by volume, the silicon atoms in the silane gas may not sufficiently react with the nitrogen atoms in the nitride mixture gas. Thus, the second gate insulating layer 126 b may have a loose structure and the insulating characteristics of the second gate insulating layer 126 b may be poorer than that of the first gate insulating layer 126 a such that the second gate insulating layer 126 b has a smaller electrical resistance than the first gate insulating layer 126 a. However, the deposition speed of the second gate insulating layer 126 b may be faster than that of the first gate insulating layer 126 a.
In FIG. 9 and FIG. 11, the first gate insulating layer 126 a may block the silicon atoms to protect the gate electrode 118 and the gate line 131, even though the amount of the silane gas in the second gas mixture for forming the second gate insulating layer 126 b may be no less than about 6.43% by volume. Thus, the silicon atoms may not be implanted into the gate line 131 and the gate electrode 118.
For example, the amount of silane gas in the second gas mixture for forming the second gate insulating layer 126 b may be about 6.43% by volume and the electric power applied to the chamber may be about 1200 W.
Referring to FIG. 9 and FIG. 12, the third gas mixture for forming the third gate insulating layer 126 c (shown in FIG. 3) is injected into the chamber. The amount of silane gas in the third gas mixture is no more than about 6.43% by volume. Electric power is applied to the third gas mixture to generate a low density silicon nitride plasma 189 c, which is applied to the second gate insulating layer 126 b. Thus, the third gate insulating layer 126 c, including low density silicon nitride, is formed on the second gate insulating layer 126 b.
When the amount of silane gas in the third gas mixture for forming the third gate insulating layer 126 c is no more than about 6.43% by volume, the third gate insulating layer 126 c may have a dense structure and may be a good electrical insulator. However, the deposition speed of the third gate insulating layer 126 c may be decreased.
In FIG. 9 and FIG. 12, the amount of the silane gas in the third gas mixture for forming the third gate insulating layer 126 c may be about 2.24% by volume and the electric power applied to the chamber may be about 900 W.
Referring to FIG. 13 and FIG. 14, the gate insulating layer 126, including the first gate insulating layer 126 a, the second gate insulating layer 126 b, and the third gate insulating layer 126 c, is formed on the insulating substrate 120 on which the gate electrode 118 and the gate line 131 are formed.
Referring to FIG. 15, a lower amorphous silicon layer (not shown) and an upper amorphous silicon layer (not shown) are deposited on the gate insulating layer 126, in sequence. The upper amorphous silicon layer may have a looser structure than the lower amorphous silicon layer.
The lower amorphous silicon layer may be deposited at a low electric power and at a decreased speed so that the lower amorphous silicon layer may have a dense structure and good electrical characteristics. The upper amorphous silicon layer may be deposited at a high electric power and at an increased speed so that the upper amorphous silicon layer may have a loose structure. For example, the lower amorphous silicon layer may be formed at an electric power of about 150 W and the upper amorphous silicon layer may be formed at an electric power of about 300 W. The amorphous silicon layer is deposited on the gate insulating layer 126 and includes the lower amorphous silicon layer and the upper amorphous silicon layer.
Then, n+ impurities are implanted into an upper portion of the amorphous silicon layer to form an n+ amorphous silicon layer (not shown).
The n+ amorphous silicon layer and the amorphous silicon layer are partially etched to form a primary n+ amorphous silicon pattern 137 c and the amorphous silicon pattern 137 a.
Referring to FIG. 16, a primary data barrier layer (not shown) and a primary data conductive layer (not shown) are formed on the gate insulating layer 126, in sequence. The gate insulating layer 126 includes the primary n+ amorphous silicon pattern 137 c and the amorphous silicon pattern 137 a. Alternatively, a copper nitride layer (not shown) may be deposited on the primary data conductive layer through a sputtering process. A data photoresist film (not shown) is formed on the primary data conductive layer.
The primary data barrier layer and the primary data conductive layer are partially etched through a photolithography process using a data mask (not shown) to form the data barrier layer 133 a, a primary data conductive layer 133 d, the source barrier pattern 117 a, a primary source conductive pattern 117 d, the drain barrier pattern 119 a, and a primary drain conductive pattern 119 d.
The nitride plasma 188 b is implanted onto the gate insulating layer 126 including the primary n+ amorphous silicon pattern 137 c, the amorphous silicon pattern 137 a, the data barrier layer 133 a, a primary data conductive layer 133 d, the source barrier pattern 117 a, a primary source conductive pattern 117 d, the drain barrier pattern 119 a, and a primary drain conductive pattern 119 d.
Referring to FIG. 16 and FIG. 17, the nitride plasma 188 b is implanted onto upper and side surfaces of the primary data conductive layer 133 d, the primary source conductive pattern 117 d, and the primary drain conductive pattern 119 d to form the data conductive layer 133 b, the data copper nitride layer 133 c, the source conductive pattern 117 b, the source copper nitride pattern 117 c, the drain conductive pattern 119 b, and the drain copper nitride pattern 119 c. For example, ammonia gas and nitrogen gas may be injected into a chamber (not shown), and an electric power of about 300 W may be applied to the ammonia gas and the nitrogen gas for more than about 20 seconds.
Referring to FIG. 17, the primary n+ amorphous silicon pattern 137 c (shown in FIG. 16) interposed between the source electrode 117 and the drain electrode 119 is partially etched, using the source electrode 117 and the drain electrode 119 as an etching mask, to form the semiconductor pattern 137 including the n+ amorphous silicon pattern 137 b and the amorphous silicon pattern 137 a.
The data copper nitride layer 133 c, the source copper nitride pattern 117 c, and the drain copper nitride pattern 119 c may protect the data line 133, the source electrode 117, and the drain electrode 119, respectively, from the etchant for etching the primary n+ amorphous silicon pattern 137 c.
In FIG. 15, FIG. 16, and FIG. 17, the semiconductor pattern 137, the data line 133, the source electrode 117, and the drain electrode 119 are formed using two photo masks. Alternatively, the semiconductor pattern, the data line, the source electrode, and the drain electrode may be formed using one photo mask.
Referring to FIG. 18, the passivation layer 116 is formed on the gate insulating layer 126 to cover the semiconductor pattern 137, the data line 133, the source electrode 117, and the drain electrode 119. For example, silane gas and the nitride mixture gas may be injected onto the gate insulating layer 126, and the passivation layer 116 may be formed on the gate insulating layer 126 by a chemical vapor deposition (CVD) method.
As shown in FIG. 18, the passivation layer 116 may include a first passivation layer (not shown) and a second passivation layer (not shown). The second passivation layer may be disposed on the first passivation layer.
The first passivation layer may include low density silicon nitride. The method for forming the low density silicon nitride of the first passivation layer is substantially the same as that described with respect to FIG. 10. Thus, any further explanation concerning the above elements will be omitted.
The second passivation layer may include high density silicon nitride. The method for forming the high density silicon nitride of the second passivation layer is substantially the same as that described with respect to FIG. 11. Thus, any further explanation concerning the above elements will be omitted.
In FIG. 18, the passivation layer 116 has a double layered structure including first and second passivation layers. Alternatively, the passivation layer may have a single layered structure or a multi-layered structure including no less than three layers.
Referring to FIG. 19, the passivation layer 116 may be partially etched to form the contact hole 151 through which the drain electrode 119 is partially exposed. Alternatively, a laser beam may be irradiated onto the pixel electrode 112 corresponding to the drain electrode 119 to form the contact hole 151 after the pixel electrode 112 is formed.
The pixel electrode 112 connected to the drain electrode 119 is formed on the passivation layer 116 and the contact hole 151 is formed in the passivation layer 116.
According to the method of manufacturing the display substrate of FIG. 4, FIG. 5, FIG. 6, FIG. 7, FIG. 8, FIG. 9, FIG. 10, FIG. 1, FIG. 12, FIG. 13, FIG. 14, FIG. 15, FIG. 16, FIG. 17, FIG. 18, and FIG. 19, an additional protective layer for protecting an upper portion of the gate line 131, the gate electrode 118, the data line 133, the source electrode 117, and the drain electrode 119 may be omitted, thereby decreasing manufacturing time of the display substrate.
In addition, the copper nitride layer may cover the side surface of the data line 133, the source electrode 117, and the drain electrode 119 to prevent the data line 133, the source electrode 117, and the drain electrode 119 from the etchant for etching the primary n+ amorphous silicon pattern 137 c.

Example I

A primary gate conductive pattern 188 d (shown in FIG. 8) was treated by nitride plasma or hydrogen plasma. A gate insulating layer having a multilayered structure and including a low density silicon nitride layer and a high density silicon nitride layer was deposited on the substrate. The nitride plasma or the hydrogen plasma was generated by an electric power of about 600 W during about 20 seconds. An electric power of about 900 W was applied to a gas mixture including silane gas and a nitride mixture gas and the amount of silane gas in the gas mixture was about 2.24% by volume. An electric power of about 1200 W was applied to a gas mixture including silane gas and a nitride mixture gas and the amount of the silane gas in the gas mixture was about 6.43% by volume.
When a first low density silicon nitride layer, a high density silicon nitride layer, and a second low density silicon nitride layer were formed after the nitride plasma treatment, the resistance of the gate line was about 2.1 μΩcm to 2.3 μΩcm.
When a first low density silicon nitride layer, a high density silicon nitride layer, and a second low density silicon nitride layer were formed after the hydrogen plasma treatment, the resistance of the gate line was about 2.5 μΩcm to 2.8 μΩcm.
When a high density silicon nitride layer and a low density silicon nitride layer were formed after the nitride plasma treatment, the resistance of the gate line was about 2.9 μΩcm to 3.0 μΩcm.
When a high density silicon nitride layer and a low density silicon nitride layer were formed after the hydrogen plasma treatment, the resistance of the gate line was about 3.0 μΩcm to 3.1 μΩcm.
Therefore, when the first low density silicon nitride layer, the high density silicon nitride layer, and the second low density silicon nitride layer were formed, in sequence, after the nitride plasma treatment, the resistance of the gate line was minimized.
FIG. 20 is a cross-sectional view showing a display device in accordance with another exemplary embodiment of the present invention.
Referring to FIG. 20, the display device includes an array substrate 180, an opposite substrate 170, and a liquid crystal layer 108. The array substrate 180 of FIG. 20 is the same as that of FIG. 1, FIG. 2, FIG. 3, and FIG. 4. Thus, the same reference numerals will be used to refer to the same or like parts and any further explanation concerning the above elements will be omitted.
The opposite substrate 170 includes an opposite insulating substrate 100, a black matrix 102 b, a color filter 104, and a common electrode 106. The opposite substrate 170 may further include a plurality of color filters.
The opposite insulating substrate 100 includes a transparent insulating material. Examples of the transparent insulating material that may be included in the opposite insulating substrate 100 include glass, quartz, and synthetic resin. For example, the opposite insulating substrate 100 may include a transparent synthetic resin.
The black matrix 102 is on the opposite insulating substrate 100 to block light that is incident in a region in which liquid crystals are incontrollable. Thus, it may be possible to improve the contrast ratio of the display device.
The color filter 104 is on the opposite insulating substrate 100, on which the black matrix 102 is formed, to transmit color light having a wavelength corresponding to a color. The color filter 104 corresponds to a pixel electrode 112 of the array substrate 180.
The common electrode 106 is on the opposite insulating substrate 100 on which the black matrix 102 and the color filter 104 are formed. The common electrode 106 includes a transparent conductive material. Examples of the transparent conductive material include indium tin oxide (ITO), indium zinc oxide (IZO), amorphous indium tin oxide (a-ITO), and combinations thereof.
A spacer (not shown) may be interposed between the array substrate 180 and the opposite substrate 170 to maintain a distance between the array substrate 180 and the opposite substrate 170. The spacer may be a bead spacer, a ball spacer, or a column spacer.
A liquid crystal layer 108 is interposed between the array substrate 180 and the opposite substrate 170. When a voltage difference occurs between the common electrode 106 and the pixel electrode 112, an electric field is formed between the common electrode 106 and the pixel electrode 112. The orientations of the liquid crystals of the liquid crystal layer 108 vary in response to the electric field formed between the common electrode 106 and the pixel electrode 112. Thus, light transmittance of the liquid crystal layer 108 is changed and an image having a gray-scale is displayed.
A sealant (not shown) may seal the liquid crystal layer 108 between the array substrate 180 and the opposite substrate 170.
Accordingly, the occurrence of defects in the array substrate 180 of the display device of FIG. 20 may be decreased and the manufacturing process of the array substrate 180 may be simplified. Thus, the image display quality of the display device may be improved and the manufacturing cost of the display device may be decreased.
FIG. 21 is a cross-sectional view showing an array substrate in accordance with another embodiment of the present invention. The array substrate of FIG. 21 is substantially the same as that of FIG. 1, FIG. 2, FIG. 3, and FIG. 4, except for the gate line, the gate electrode, the data line, the source electrode, and the drain electrode. Thus, the same reference numerals will be used to refer to the same or like parts and any further explanation concerning the above elements will be omitted.
Referring to FIG. 21, the gate line 1131 is disposed on an insulating substrate 120 and includes a gate barrier layer 1131 a, a gate conductive layer 1131 b, and a gate copper nitride layer 1131 c.
The gate barrier layer 1131 a is disposed on the insulating substrate 120. The gate barrier layer 1131 a may include molybdenum (Mo), molybdenum-titanium (Mo—Ti) alloy, molybdenum-tungsten (Mo—W) alloy, molybdenum-chromium (Mo—Cr) alloy, molybdenum-niobium (Ni) alloy, and combinations thereof. The gate barrier layer 1131 a may increase the adhesive strength between the gate line 1131 and the insulating substrate 120.
The gate conductive layer 1131 b is disposed on the gate barrier layer 1131 a. The gate conductive layer 1131 b may include copper or copper alloy.
The gate copper nitride layer 1131 c is disposed on an upper surface of the gate conductive layer 1131 b. The gate copper nitride layer 1131 c may prevent copper of the gate conductive layer 1131 b from being combined with silicon of the gate insulating layer 126. The gate copper nitride layer 1131 c may include copper nitride. For example, the gate copper nitride layer 1131 c may be formed through a copper sputtering process in a nitrogen atmosphere.
The gate electrode 1118 of the thin film transistor 1155 is on the insulating substrate 120. The gate electrode 1118 is formed on substantially the same layer as the gate line 1131 and includes a gate barrier pattern 1118 a, a gate conductive pattern 1118 b, and a gate copper nitride pattern 1118 c.
The gate barrier pattern 1118 a is disposed on the insulating substrate 120. The gate barrier pattern 1118 a may include substantially the same material as the gate barrier layer 1131 a of the gate line 1131.
The gate conductive pattern 1118 b is disposed on the gate barrier pattern 1118 a. The gate conductive pattern 1118 b may include copper or copper alloy. For example, the gate conductive pattern 1118 b may include substantially the same material as the gate conductive layer 1131 b of the gate line 1131.
The gate copper nitride pattern 1118 c is disposed on an upper surface of the gate conductive pattern 1118 b. The gate copper nitride pattern 1118 c may include copper nitride. For example, the gate copper nitride pattern 1118 c may include substantially the same material as the gate copper nitride layer 1131 c of the gate line 1131.
The data line 1133 is disposed on the gate insulating layer 126. The data line 1133 includes a data barrier layer 1133 a, a data conductive layer 1133 b, and a data copper nitride layer 1133 c.
The data barrier layer 1133 a is disposed on the gate insulating layer 126, an amorphous silicon pattern 137 a, and an n+ amorphous silicon pattern 137 b. The data barrier layer 1133 a prevents the silicon atoms of the gate insulating layer 126 from diffusing into the data conductive layer 1133 b.
The data conductive layer 1133 b is disposed on the data barrier layer 1133 a. The data conductive layer 1133 b may include copper or copper alloy. For example, the data conductive layer 1133 b may include substantially the same material as the gate conductive layer 1131 b. Thus, any further explanation concerning the above elements will be omitted.
The data copper nitride layer 1133 c is formed on an upper surface of the data conductive layer 1133 b. The data copper nitride layer 1133 c may include copper nitride. For example, the data copper nitride layer 1133 c may include substantially the same copper nitride as the gate copper nitride layer 1131 c.
A source electrode 1117 of the thin film transistor 1155 is on a first pattern of the n+ amorphous silicon pattern. The source electrode 1117 may include copper or copper alloy. For example, the source electrode 1117 may be formed on substantially the same layer as the data line 1133. The source electrode 1117 is connected to the data line 1133 and includes a source barrier pattern 1117 a, a source conductive pattern 1117 b, and a source copper nitride pattern 1117 c.
The source barrier pattern 1117 a is on the first pattern of the n+ amorphous silicon pattern. The source barrier pattern 1117 a may include substantially the same material as the data barrier layer 1133 a of the data line 1133.
The source conductive pattern 1117 b is disposed on the source barrier pattern 1117 a. The source conductive pattern 1117 b may include copper or copper alloy. For example, the source conductive pattern 1117 b may include substantially the same material as the data conductive layer 1133 b of the data line 1133.
The source copper nitride pattern 1117 c is disposed on an upper surface of the source conductive pattern 1117 b. The source copper nitride pattern 1117 c may include copper nitride. For example, the source copper nitride pattern 1117 c may include substantially the same material as the data copper nitride layer 1133 c of the data line 1133.
A drain electrode 1119 of the thin film transistor 1155 is disposed on a second pattern of the n+ amorphous silicon pattern. The drain electrode 1119 is formed on substantially the same layer as the data line 1133. The drain electrode 1119 is connected to the pixel electrode 1112 and includes a drain barrier pattern 1119 a, a drain conductive pattern 1119 b, and a drain copper nitride pattern 1119 c.
The drain barrier pattern 1119 a is disposed on the second pattern of the n+ amorphous silicon pattern. The drain barrier pattern 1119 a may include substantially the same material as the data barrier layer 1133 a of the data line 1133.
The drain conductive pattern 1119 b is disposed on the drain barrier pattern 1119 a. The drain conductive pattern 1119 b may include copper or copper alloy. For example, the drain conductive pattern 119 b may include substantially the same material as the data conductive layer 1133 b of the data line 1133.
The drain copper nitride pattern 1119 c is disposed on an upper surface of the drain conductive pattern 1119 band may include copper nitride. For example, the drain copper nitride pattern 1119 c may include substantially the same material as the data copper nitride layer 1133 c of the data line 1133.
FIG. 22, FIG. 23, FIG. 24, FIG. 25, and FIG. 26 are cross-sectional views showing a method of manufacturing the array substrate shown in FIG. 21. The method of FIG. 22, FIG. 23, FIG. 24, FIG. 25, and FIG. 26 is substantially the same as in FIG. 5, FIG. 6, FIG. 7, FIG. 8, FIG. 9, FIG. 10, FIG. 11, FIG. 12, FIG. 13, FIG. 14, FIG. 15, FIG. 16, FIG. 17, FIG. 18, and FIG. 19, except with regard to the processes for forming the gate line, the gate electrode, the data line, the source electrode, and the drain electrode. Thus, the same reference numerals will be used to refer to the same or like parts and any further explanation concerning the above elements will be omitted.
Referring to FIG. 21 and FIG. 22, a primary gate barrier layer 1141 and a primary gate conductive layer 1142 are formed on the insulating substrate 120, in sequence. A primary copper nitride layer 1144 is deposited on the primary gate conductive layer 1142 through a sputtering process. A gate photoresist film 1143 is coated on the primary gate copper nitride layer 1144.
The gate photoresist film 1143 is exposed to ultraviolet light through a gate mask 1171. The gate mask 1171 includes a light blocking portion 1171 a and a transparent portion 1171 b. The light blocking portion 1171 blocks a portion of the ultraviolet light and the remaining portion of the ultraviolet light passes through the transparent portion 1171 b. The light blocking portion 1171 a corresponds to the gate line 1131 and the gate electrode 1118 and the transparent portion 1171 b corresponds to the remainder of the array substrate.
Referring to FIG. 23, the exposed gate photoresist film 1143 is developed, using a developing agent, to form a gate photoresist pattern 1143 a on the primary gate copper nitride layer 1144.
The primary gate conductive layer 1142, the primary gate barrier layer 1141, and the primary gate copper nitride layer 1144 are partially etched, using the gate photoresist pattern 1143 a as an etching mask, to form the gate line 1131 and the gate electrode 1118 on the insulating substrate 120.
The gate copper nitride layer 1131 c of the gate line 1131 may have substantially the same etching rate as the copper of the gate conductive layer 1131 b, thereby improving the etching uniformity of the gate line 1131. For example, when a molybdenum layer (not shown) on a gate conductive layer having a different etching rate than the gate conductive layer is formed on a gate conductive layer, the molybdenum layer may be over-etched such that a portion of the gate conductive layer may be exposed. However, in FIG. 23, the gate copper nitride layer 1131 c has substantially the same etching rate as the gate conductive layer 1131 b, thereby improving the etching profile of the gate line 1131.
The gate photoresist pattern 143 a is removed from the gate line 1131 and the gate electrode 1118.
Referring to FIG. 24, a gate insulating layer 126 is formed on the insulating substrate 120 to cover the gate line 1131 and the gate electrode 1118.
An amorphous silicon pattern 137 a is formed on the gate insulating layer corresponding to the gate electrode 1118. A primary n+ amorphous silicon pattern 137 c is formed on the amorphous silicon pattern 137 a.
Referring to FIG. 25, a primary data barrier layer (not shown) and a primary data conductive layer (not shown) are formed on the gate insulating layer 126, on which the amorphous silicon pattern 137 a and the primary n+ amorphous silicon pattern 137 c (shown in FIG. 24) are formed, in sequence. A primary data copper nitride layer (not shown) is deposited on the primary data conductive layer. For example, the primary data copper nitride layer may be deposited through a sputtering process. A data photoresist film (not shown) may be formed on the primary data copper nitride layer.
The primary data barrier layer, the primary data conductive layer, and the primary data copper nitride layer are partially etched through a photolithography process using a data mask (not shown) to form the data line 1133, the source electrode 1117, and the drain electrode 1119 on the gate insulating layer 126. Alternatively, nitride plasma may be implanted into each of the data line 1133, the source electrode 1117, and the drain electrode 1119 to form a copper nitride layer (not shown) on each of a side surface of the data conductive layer 1133 b of the data line 1133, a side surface of the source conductive pattern 1117 b of the source electrode 1117, and a side surface of the drain conductive pattern 1119 b of the drain electrode 1119.
The primary n+ amorphous silicon pattern 137 c (shown in FIG. 24) interposed between the source electrode 1117 and the drain electrode 1119 is partially etched, using the source electrode 1117 and the drain electrode 1119 as an etching mask, so that the amorphous silicon pattern 137 a is partially exposed between the source electrode 1117 and the drain electrode 1119. Also, the primary n+ amorphous silicon pattern 137 c is divided into two patterns spaced apart from each other and corresponding to the source electrode 1117 and the drain electrode 1119.
Referring to FIG. 26, the passivation layer 116 is formed on the gate insulating layer 126 to cover the semiconductor pattern 137, the data line 1133, the source electrode 1117, and the drain electrode 1119. The passivation layer 116 is partially etched to form a contact hole 151 through which the drain electrode 1119 is partially exposed.
The pixel electrode 112 is connected to the drain electrode 1119 through the contact hole 151 and is formed on the passivation layer 116 having the contact hole 151.
According to the method of manufacturing the array substrate of FIG. 22, FIG. 23, FIG. 24, FIG. 25, and FIG. 26, each of the gate line 1131, the gate electrode 1118, the data line 1133, the source electrode 1117, and the drain electrode 1119 includes a copper nitride layer that has substantially the same etching rate as the copper of the gate conductive layer 1131 b, which may improve the etching profile of the gate line 1131, the gate electrode 1118, the data line 1133, the source electrode 1117, and the drain electrode 1119. Thus, the occurrence of defects in the array substrate may be decreased.
FIG. 27 is a cross-sectional view showing an array substrate in accordance with another embodiment of the present invention. The array substrate of FIG. 27 is substantially the same as in FIG. 21 except for the data line, the source electrode, and the drain electrode. Thus, the same reference numerals will be used to refer to the same or like parts and any further explanation concerning the above elements will be omitted.
Referring to FIG. 27, the data line 533 includes a data barrier layer 533 a, a data conductive layer 533 b, a data copper nitride layer 533 c, and a side copper nitride layer 533 d.
The data copper nitride layer 533 c is disposed on an upper surface of the data conductive layer 533 b to protect the data line 533 during subsequent processes. The subsequent processes may include an etching process for forming an n+ amorphous silicon pattern 137 b, a cleaning process, and a deposition process.
The side copper nitride layer 533 d is disposed on a side surface of the data conductive layer 533 b to protect the data line 533 during the subsequent processes. For example, the side copper nitride layer 533 d protects the data line 533 during the etching process for forming the n+ amorphous silicon pattern 137 b such that the data line 533 may not be etched by an etchant for etching a primary n+ amorphous silicon pattern.
The source electrode 517 is formed on substantially the same layer as the data line 533. The source electrode 517 includes a source barrier pattern 517 a, a source conductive pattern 517 b, a source copper nitride pattern 517 c, and a first side surface copper nitride pattern 517 d.
The source copper nitride pattern 517 c is disposed on an upper surface of the source conductive pattern 517 b.
The first side copper nitride pattern 517 d is disposed on a side surface of the source conductive pattern 517 b to protect the source electrode 517 during the etching process for forming the n+ amorphous silicon pattern 137 b.
The drain electrode 519 is formed on substantially the same layer as the data line 533. The drain electrode 519 includes a drain barrier pattern 519 a, a drain conductive pattern 519 b, a drain copper nitride pattern 519 c, and a second copper nitride pattern 519 d.
The drain copper nitride pattern 519 c is disposed on an upper surface of the drain conductive pattern 519 b.
The second side copper nitride pattern 519 d is disposed on a side surface of the drain conductive pattern 519 b to protect the source electrode 519 during the etching process for forming the n+ amorphous silicon pattern 137 b. The second side copper nitride pattern 519 d may protect the source electrode 519 during subsequent processes including the cleaning process and the deposition process.
The data copper nitride layer 533 c, the source copper nitride pattern 517 c, and the drain copper nitride pattern 519 c of FIG. 27 may be formed through substantially the same sputtering process as described with respect to FIG. 25. The side copper nitride layer 533 d, the first side copper nitride pattern 517 d, and the second side copper nitride pattern 519 d of FIG. 27 may be formed using substantially the same nitride plasma as described with respect to FIG. 16. Alternatively, each of the upper and side surfaces of the data line 533, the source electrode 517, and the drain electrode 519 may be covered by a copper nitride layer.
Accordingly, in the array substrate of FIG. 27, the etching uniformity of the data line 533, the source electrode 517, and the drain electrode 519 may be improved, which may increase the yield of the array substrate.
FIG. 28 is a cross-sectional view showing an array substrate in accordance with another exemplary embodiment of the present invention.
Referring to FIG. 28, the array substrate includes an insulating substrate 220, a data line 233, a gate line 231, a thin film transistor 255, a gate insulating layer 226, a passivation layer 216, and a pixel electrode 212. Alternatively, the array substrate may include a plurality of data lines, a plurality of gate lines, a plurality of thin film transistors, and a plurality of pixel electrodes.
The data line 233 includes a data barrier layer 233 a, a data conductive layer 233 b, and a data copper nitride layer 233 c. The data barrier layer 233 a is disposed on the insulating substrate 220 and the data conductive layer 233 b is disposed on the data barrier layer 233 a. The data copper nitride layer 233 c is disposed on an upper surface and a side surface of the data conductive layer 233 b.
A source electrode 217 of the thin film transistor 255 is formed on substantially the same layer as the data line 233 and is connected to the data line 233.
The source electrode 217 includes a source barrier pattern 217 a, a source conductive pattern 217 b, and a source copper nitride pattern 217 c. The source copper nitride pattern 217 c is disposed on an upper surface and a side surface of the source conductive pattern 217 b.
A drain electrode 219 of the thin film transistor 255 is formed from substantially the same layer as the data line 233. The drain electrode 219 is spaced apart from the source electrode 217.
The drain electrode 219 includes a drain barrier pattern 219 a, a drain conductive pattern 219 b, and a drain copper nitride pattern 219 c. The drain copper nitride pattern 219 c is disposed on an upper surface and a side surface of the drain conductive pattern 219 b.
A semiconductor pattern 237 of the thin film transistor 255 is interposed between the source electrode 217 and the drain electrode 219. The semiconductor pattern 237 includes an n+ amorphous silicon pattern 237 b and an amorphous silicon pattern 237 a. The n+ amorphous silicon pattern 237 b includes a first pattern on the source electrode 217 and a second pattern on the drain electrode 219. The amorphous silicon pattern 234 a is disposed on the n+ amorphous silicon pattern 237 b and the portion of the insulating substrate 220 between the source electrode 217 and the drain electrode 219.
The gate insulating layer 226 is disposed on the insulating substrate 220 and covers the data line 233, the source electrode 217, the drain electrode 219, and the semiconductor pattern 237. The gate insulating layer 226 and the passivation layer 216 have a contact hole 251 through which the drain electrode 219 is partially exposed.
A gate electrode 218 of the thin film transistor 255 is disposed on the gate insulating layer 226 corresponding to the semiconductor pattern 237. The gate electrode 218 includes a gate barrier pattern 218 a, a gate conductive pattern 218 b, and a gate copper nitride pattern 218 c. The gate copper nitride pattern 218 c is disposed on an upper surface and a side surface of the gate conductive pattern 218 b.
The gate line 231 is formed on substantially the same layer as the gate electrode 218 and is connected to the gate electrode 218.
The gate line 231 includes a gate barrier layer 231 a, a gate conductive layer 231 b, and a gate copper nitride layer 231 c. The gate conductive layer 231 b is disposed on the gate barrier layer 231 a and the gate copper nitride layer 231 c is disposed on an upper surface and a side surface of the gate conductive layer 231 b.
The passivation layer 216 is disposed on the gate insulating layer 226 to cover the gate electrode 218 and the gate line 231. The drain electrode 219 is partially exposed through the contact hole 251 formed in the passivation layer and the gate insulating layer 226.
The pixel electrode 212 is disposed on the passivation layer 216. The pixel electrode 212 is connected to the drain electrode 219 through the contact hole 251 formed in the passivation layer 216.
Accordingly, in the array substrate of FIG. 28, the resistance of the data line 233 on the insulating substrate 220 and the gate line 231 on the gate insulating layer 226 may be decreased, which may improve the image display quality of a display device.
FIG. 29 is a cross-sectional view showing a display device in accordance with another exemplary embodiment of the present invention.
Referring to FIG. 29, the display device includes an insulating substrate 320, a black matrix 302, a gate line 331, a data line (not shown), a driving voltage line 333, a driving transistor 355, a switching transistor (not shown), a gate insulating layer 326, a passivation layer 316, a color filter 304, a pixel electrode 312, an organic light emitting layer 308, an opposite electrode 306, and a protecting layer 305. Alternatively, the display device may include a plurality of gate lines, a plurality of data lines, a plurality of driving voltage lines, a plurality of driving transistors, a plurality of switching transistors, a plurality of color filters, and a plurality of pixel electrodes.
The black matrix 302 is formed on the insulating substrate 320 to block light. The black matrix 302 includes a plurality of openings 348 arranged in a matrix. Each of the openings 348 of the black matrix 302 may correspond to a pixel electrode 312.
The gate line 331 is disposed on the black matrix 302 and includes a gate barrier layer 331 a, a gate conductive layer 331 b, and a gate copper nitride layer 331 c. The gate conductive layer 331 b is disposed on the gate barrier layer 331 a. The gate copper nitride layer 331 c is disposed on an upper surface and a side surface of the gate conductive layer 331 b. The gate line 331 is connected to a gate electrode (not shown) of the switching transistor.
A gate electrode 318 of the driving transistor 355 is formed on substantially the same layer as the gate line 331. The gate electrode 318 is connected to a drain electrode (not shown) of the switching transistor. The gate electrode 318 includes a gate barrier pattern 318 a, a gate conductive pattern 318 b, and a gate copper nitride pattern 318 c. The gate copper nitride pattern 318 c is disposed on an upper surface and a side surface of the gate conductive pattern 318 b.
The gate insulating layer 326 is disposed on the insulating substrate 320 on which the black matrix 302, the gate line 331, and the gate electrode 318 are formed. In FIG. 29, the gate insulating layer 326 includes a first gate insulating layer made of low density silicon nitride, a second gate insulating layer made of high density silicon nitride, and a third gate insulating layer made of low density silicon nitride.
A semiconductor pattern 337 of the driving transistor 355 is disposed on the gate insulating layer 326 corresponding to the gate electrode 318. The semiconductor pattern 337 includes an amorphous silicon pattern 337 a and an n+ amorphous silicon pattern 337 b.
The driving voltage line 333 is disposed on the gate insulating layer 326. The driving voltage line 333 includes a driving voltage barrier layer 333 a, a driving voltage conductive layer 333 b, and a driving voltage copper nitride layer 333 c. The driving voltage conductive layer 333 b is disposed on the driving voltage barrier layer 333 a and the driving voltage copper nitride layer 333 c is disposed on an upper surface and a side surface of the driving voltage conductive layer 333 b.
A source electrode 317 of the driving transistor 355 is disposed on the semiconductor pattern 337. The source electrode 317 is electrically connected to the driving voltage line 333. The source electrode 317 includes a source barrier pattern 317 a, a source conductive pattern 317 b, and a source copper nitride pattern 317 c. The source copper nitride pattern 317 c is disposed on an upper surface and a side surface of the source conductive pattern 317 b.
A drain electrode 319 of the driving transistor 355 is spaced apart from the source electrode 317 on the semiconductor pattern 337. The drain electrode 319 includes a drain barrier pattern 319 a, a drain conductive pattern 319 b, and a drain copper nitride pattern 319 c. The drain copper nitride pattern 319 c is disposed on an upper surface and a side surface of the drain conductive pattern 319 b.
The passivation layer 316 is disposed on the gate insulating layer 326 to cover the driving transistor 355, the switching transistor, and the driving voltage line 333.
The color filter 304 is disposed on the passivation layer 316 to transmit colored light having a wavelength corresponding to the color. Alternatively, an overcoating layer (not shown) may be formed on the color filter 304. The passivation layer 316 and the color filter 304 have a contact hole 351 through which the drain electrode 319 of the driving transistor 355 is partially exposed.
The pixel electrode 312 is disposed on the color filter 304, and is connected to the drain electrode 319 of the driving transistor 355 through the contact hole 351. The pixel electrode 312 may include a transparent conductive material.
The organic light emitting layer 308 is formed on the color filter 304 to cover the pixel electrode 312.
The opposite electrode 306 is disposed on the organic light emitting layer 308 and may include metal.
The protecting layer 305 is formed on the opposite electrode 306 to protect the opposite electrode 306.
When a current flows through the organic light emitting layer 308 between the pixel electrode 312 and the opposite electrode 306, the organic light emitting layer 308 generates light. The light generated from the organic light emitting layer 308 passes through the color filter 304, thereby displaying an image.
Accordingly, in the display device of FIG. 29, the resistance of the gate line 331, the driving voltage line 333, and the data line (not shown) may be decreased, which may improve the image display quality of the display device. In addition, the etching resistance of the source electrode 317 and the drain electrode 319 may be increased by the copper nitride patterns 317 c and 319 c that are formed on the side surfaces of the source and drain electrodes 317 and 319, which may decrease the occurrence of defects in the display device.
According to the present invention, the copper nitride patterns are formed on the upper surface and the side surface of the conductive patterns so that an additional protecting layer for protecting the copper lines may be omitted. Thus, the manufacturing time and the manufacturing cost of the array substrate may be decreased.
In addition, the copper nitride pattern formed through a sputtering process has substantially the same etching rate as the conductive pattern, which may improve the etching profile of the conductive patterns of the array substrate.
Furthermore, the copper nitride pattern formed through the nitride plasma process covers the side surface of the conductive patterns to protect the conductive patterns during the etching process for etching the n+ amorphous silicon pattern.
Also, since the resistance of the conductive patterns may be decreased, the image display quality of the display device may be improved.
The gate insulating layer may also have a multi-layered structure to improve the electrical characteristics of the semiconductor pattern.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Claims

1. A method for manufacturing an array substrate, comprising:

forming a barrier layer on an insulating substrate;

forming a gate line comprising copper or copper alloy and a gate electrode connected to the gate line on the barrier layer;

applying nitride plasma on the gate line and the gate electrode;

depositing a gate insulating layer on the insulating substrate to cover the gate line and the gate electrode; and

forming a data line, a source electrode connected to the data line, a drain electrode spaced apart from the source electrode, and a semiconductor pattern on the gate insulating layer, the semiconductor pattern being on the gate electrode between the source electrode and the drain electrode.

2. The method of claim 1, wherein the nitride plasma is applied in the same chamber in which the gate insulating layer is deposited, in situ.

3. The method of claim 2, wherein the nitride plasma is applied at an electric power of no less than about 300 W for no less than about 20 seconds in an ammonia atmosphere.

4. The method of claim 2, wherein depositing the gate insulating layer comprises:

injecting a first gas mixture comprising silane gas, nitrogen gas, and ammonia gas into a chamber to form a first gate insulating layer on the insulating substrate, the amount of silane gas in the first gas mixture being no more than about 6.43% by volume;

injecting a second gas mixture comprising silane gas, nitrogen gas, and ammonia gas into the chamber to form a second gate insulating layer on the insulating substrate, the amount of silane gas in the second gas mixture being no less than about 6.43% by volume; and

injecting a third gas mixture comprising silane gas, nitrogen gas, and ammonia gas into the chamber to form a third gate insulating layer on the insulating substrate, the amount of silane gas in the third gas mixture being no more than about 6.43% by volume.

5. The method of claim 4, wherein the thickness of the first gate insulating layer is no less than about 10 {acute over (Å)}.

6. A method of manufacturing an array substrate, comprising:

forming a gate line, a gate electrode connected to the gate line, and a gate insulating layer covering the gate line and the gate electrode on an insulating substrate;

forming a semiconductor pattern on the gate insulating layer corresponding to the gate electrode;

forming a data line comprising copper or copper alloy, a source electrode connected to the data line, and a drain electrode spaced apart from the source electrode with respect to the semiconductor pattern on the gate insulating layer;

applying nitride plasma on the data line, the source electrode, and the drain electrode; and

depositing a passivation layer on the gate insulating layer to cover the semiconductor pattern, the data line, the source electrode, and the drain electrode.

7. The method of claim 6, further comprising:

forming a conductive barrier layer on the gate insulating layer on which the semiconductor pattern is formed.

8. The method of claim 7, wherein the conductive barrier layer comprises metal or alloy.

9. The method of claim 6, wherein forming the semiconductor pattern on the gate insulating layer comprises:

forming an amorphous silicon layer on the gate insulating layer; and

forming an n+ amorphous silicon layer on the amorphous silicon layer.

10. The method of claim 9, further comprising:

partially etching the n+ amorphous silicon layer by using the source electrode and the drain electrode treated by the nitride plasma as an etching mask.

11. A method for manufacturing an array substrate, comprising:

depositing a first barrier layer, a first conductive layer comprising copper or copper alloy, and a first copper nitride layer on an insulating substrate, in sequence;

patterning the first barrier layer, the first conductive layer, and the first copper nitride layer to form a gate line and a gate electrode connected to the gate line;

12. The method of claim 11, wherein forming the data line, the source electrode, the drain electrode, and the semiconductor pattern comprises:

depositing a second barrier layer, a second conductive layer comprising copper or copper alloy, and a second copper nitride layer on the gate insulating layer, in sequence; and

patterning the second barrier layer, the second conductive layer, and the second copper nitride layer.

13. The method of claim 12, wherein forming the data line, the source electrode, the drain electrode, and the semiconductor pattern comprises:

applying nitride plasma on the data line, the source electrode, and the drain electrode.

14. A method for manufacturing an array substrate, comprising:

forming a barrier layer on an insulating substrate;

applying hydrogen plasma on the gate line and the gate electrode;

injecting a second gas mixture comprising silane gas, nitrogen gas and ammonia gas into the chamber to form a second gate insulating layer on the insulating substrate, the amount of silane gas in the second gas mixture being no less than about 6.43% by volume;

injecting a third gas mixture comprising silane gas, nitrogen gas and ammonia gas into the chamber to form a third gate insulating layer on the insulating substrate, the amount of silane gas in the third gas mixture being no more than about 6.43% by volume; and

forming a data line, a source electrode connected to the data line, a drain electrode spaced apart from the source electrode, and a semiconductor pattern on the third gate insulating layer, the semiconductor pattern being on the gate electrode between the source electrode and the drain electrode.