US20090175071A1 - Phase change memory dynamic resistance test and manufacturing methods - Google Patents
Phase change memory dynamic resistance test and manufacturing methods Download PDFInfo
- Publication number
- US20090175071A1 US20090175071A1 US11/970,348 US97034808A US2009175071A1 US 20090175071 A1 US20090175071 A1 US 20090175071A1 US 97034808 A US97034808 A US 97034808A US 2009175071 A1 US2009175071 A1 US 2009175071A1
- Authority
- US
- United States
- Prior art keywords
- memory cell
- sequence
- test
- test pulses
- coefficient
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50008—Marginal testing, e.g. race, voltage or current testing of impedance
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49004—Electrical device making including measuring or testing of device or component part
Definitions
- the present invention relates to high density memory devices based on phase change materials like chalcogenides and others, and to methods for manufacturing such devices.
- Phase change based memory materials like chalcogenide based materials and similar materials, can be caused to change phase between an amorphous solid phase and a crystalline solid phase by application of electrical current at levels suitable for implementation in integrated circuits.
- the generally amorphous state is characterized by higher resistivity than the generally crystalline state, which can be readily sensed to indicate data.
- phase change materials can be characterized as a type of programmable resistive memory material. These properties have generated interest in using phase change material and other programmable resistive memory material to form nonvolatile memory circuits, which can be read and written with random access.
- the change from the amorphous to the crystalline state is generally a lower current operation.
- the change from crystalline to amorphous referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure, after which the phase change material cools quickly, quenching the phase change process and allowing at least a portion of the phase change structure to stabilize in the amorphous state. It is desirable to minimize the magnitude of the reset current used to cause the transition of the phase change material from a crystalline state to an amorphous state.
- the memory cells using phase change material include an “active region” in the bulk of the phase change material of the cell in which the actual phase transitions are located. Techniques are applied to make the active region small, so that the amount of current needed to induce the phase change is reduced. Also, techniques are used to thermally isolate the active region in the phase change cell so that the resistive heating needed to induce the phase change is confined to the active region.
- the magnitude of the reset current needed for reset can also be reduced by reducing the size of the phase change material element in the cell and/or the contact area between electrodes and the phase change material, such that higher current densities are achieved with small absolute current values through the phase change material element.
- phase change bridge cell Another technology developed by the assignee of the present application is referred to as a phase change bridge cell, in which a very small patch of memory material is formed as a bridge across a thin film insulating member located between electrodes.
- the phase change bridge is easily integrated with logic and other types of circuitry on integrated circuits. See, U.S. application Ser. No. 11/155,067, filed 17 Jun. 2005, entitled “Thin Film Fuse Phase Change RAM and Manufacturing Method,” by Lung et al., incorporated by reference as if fully set forth herein, which application was owned at the time of invention and is currently owned by the same assignee.
- phase change memory devices require that efficient testing methodologies be provided for use during manufacturing. For example, it is desirable to detect faulty devices during manufacturing, such as before packaging of the individual die, in order to avoid packaging defective devices and wasting the expense of such packaging. Also, it is desirable to detect faulty devices during manufacturing, so that the manufacturing process can be tuned to improve yield.
- Testing methodologies can require significant processing overhead for large scale integrated circuit devices, and can slow down the manufacturing process. Thus it is desirable to provide methodologies that provide good information with low processing overhead.
- the present invention provides a testing and manufacturing technology for integrated circuit phase change memory devices based on the discovery that material properties of memory cells, such as the integrity of interfaces between contact and phase change material, voids in the phase change material and the like, and critical dimensions of memory cells, such as the area of contact between phase change material an electrode, can be detected by determining coefficients of a simple equation, such as the slope and intercept coefficients for a linear equation, fitted to the measurement of the dynamic resistance of the memory cell.
- a method for testing an integrated circuit memory device includes applying of test pulses to a memory cell on the device, where the test pulses result in current through the memory cell having an amplitude dependent on the test pulse. Resistance in the memory cell is measured in response to the sequence of test pulses. A parameter set is extracted from the measurements which includes at least one numerical coefficient that models dependency of the measured resistance on the amplitude of the current through the memory cell. The extracted numerical coefficient or coefficients are associated with the memory device, such as by storing the parameter set including the extracted numerical coefficient or coefficients in a computer readable medium on the integrated circuit or in a testing workstation to which the circuit is coupled.
- a gate to source voltage is applied to the transistor access device to bias it in a linear region of operation, during the step of applying the sequence of test pulses.
- the test pulses cause formation of a molten region within the phase change memory element near the bottom electrode having a volume dependent on the contact area and on the energy applied during the test.
- a different volume of molten material results.
- the resistance measurements therefore change dynamically with the test pulses.
- the slope A is a coefficient that depends primarily on the material properties of the memory cell. Therefore, when the slope A falls outside an expected range, the information can be used in deducing that the memory cell has a material fault, such as a void in a critical region of the phase change memory element, or a poor interface between one of the top and bottom electrodes.
- the intercept B is a coefficient that depends not only on material properties, but also on critical dimensions of the memory cell. Therefore, if the intercept B falls outside an expected range, or changes after stress is applied to the cell, the information can be used in deducing that a critical dimensions of the memory cell fall outside specified manufacturing tolerances, or other faults in interface structures are occurring.
- the sequence of test pulses used for the purposes of measuring the dynamic resistance comprises varying voltage pulses having magnitude sufficient to melt a portion of the phase change element in the memory cell, and durations sufficient for thermal transients to settle before measuring the resistance.
- the sequence of test pulses comprise more than 10, for example 40, varying voltage pulses having equal durations between about 20 and 100 ns, preferably about 40 ns, and increasing magnitude stepping in steps of about 0.1 to 0.01 V from about 0.6 V to about 1.5 V.
- an integrated circuit device can be discarded if the extracted numerical coefficient or coefficients indicate that the device is not reliable.
- the information in the parameter set can be used to stop a manufacturing process for additional devices if the extracted coefficients fall outside an acceptable range, and thereby indicate a fault has occurred in the manufacturing process.
- the memory cell after performing a first dynamic resistance measurement as described above, the memory cell is subjected to a stress, such as a long voltage pulse or a number of set/reset cycles, and then a second dynamic resistance measurement is executed to develop a second parameter set.
- a stress such as a long voltage pulse or a number of set/reset cycles
- a second dynamic resistance measurement is executed to develop a second parameter set.
- the first and second parameter sets can then be analyzed to determine characteristics of the memory cell.
- a method of manufacturing an integrated circuit memory device including first performing manufacturing steps to produce a testable memory cell, then performing a dynamic resistance measurement as described above. Based on results of the dynamic resistance measurement, manufacturing method includes either performing further manufacturing steps on the integrated circuit device if the extracted parameter set meets specified guidelines, else discarding the integrated circuit device. Alternatively, the manufacturing method may include suspending the manufacturing line for analysis if the extracted parameter set falls outside specified guidelines, or else allowing the manufacturing line to continue manufacturing.
- FIG. 1 is a simplified diagram of a mushroom style phase change memory cell including a molten region and a solid region as induced during dynamic resistance measurements described herein.
- FIG. 2 is a schematic diagram of a single memory device and access device at a cross point of a bit line and a word line in an array of such devices subjected to testing as described herein
- FIG. 3 is a graph of drain to source current versus drain to source voltage for an access device showing dynamic resistance measurements.
- FIGS. 4 a through 4 f show the results of measurements of dynamic resistance for six different memory cells fitted to a linear curve.
- FIG. 5 is a simplified block diagram of an integrated circuit memory device as described herein including a dynamic resistance test mode.
- FIG. 6 is a flowchart of a testing and manufacturing method as described herein.
- FIG. 7 has a flowchart of an alternative testing and manufacturing method as described herein.
- FIG. 8 is a simplified diagram of a manufacturing line including test station for dynamic resistance tests as described herein.
- FIG. 1 is a simplified diagram of a mushroom style phase change memory cell including a bottom electrode 100 , an element 101 comprising a phase change material, and a top electrode 102 .
- the bottom electrode 100 in the illustrated embodiment is a pillar having a radius r 0 at the interface having a contact area, roughly ⁇ r 0 2 , between element 101 and the bottom electrode 100 .
- the top electrode 102 contacts the element 101 over substantially greater area than the contact area at the interface between the bottom electrode 100 and element 101 .
- bias circuitry (See, for example, bias circuitry voltage and current sources 555 of FIG. 5 ) applying voltages to an access device coupled to the bottom electrode and a bit line coupled to the top electrode can induce current to flow the memory element 101 .
- bias circuitry (See, for example, bias circuitry voltage and current sources 555 of FIG. 5 ) applying voltages to an access device coupled to the bottom electrode and a bit line coupled to the top electrode can induce current to flow the memory element 101 .
- bias circuitry See, for example, bias circuitry voltage and current sources 555 of FIG. 5
- applying voltages to an access device coupled to the bottom electrode and a bit line coupled to the top electrode can induce current to flow the memory element 101 .
- magnitude of current flow is small and insufficient to cause a phase change in the active region of the memory element 101 .
- the current flow is adapted to cause a portion of memory element 101 to increase in temperature above a transition temperature sufficient to induce a phase transition between an amorphous state in active region and a crystalline state in the active
- an active region of the memory element 101 occurs adjacent to the interface between the bottom electrode 100 and a memory element 101 .
- a sequence of test pulses is applied to the memory cell.
- the test pulses have magnitudes and durations sufficient to cause formation of a molten region 103 within the element 101 , while the remainder of the memory only 101 remains in a solid phase.
- the test pulses have durations sufficient for thermal transients to dissipate in the element 101 , so that a dynamic resistance measurement can be taken on a relatively stable structure.
- dynamic resistance is defined as the resistance of the phase change cell when a constant current flows through the cell. This is a steady state measurement.
- Dynamic resistance can be measured using a simple scheme similar to that used to determine the R-I curve, while ensuring that the access transistor, or other access device, is biased in its linear region. This operation in the linear region enables us to subtract the transistor resistance and obtain the resistance of the phase change element 101 during programming.
- dynamic resistance is a steady state measurement
- the programming pulse can be relatively short, such as about 40 ns. All the thermal transients typically settle in less than 5 ns, so the measured resistance is the resistance of the cell when a constant current is flowing through the cell.
- the size of the molten region depends on a critical dimension r 0 , and the amount of power (VI) delivered by the test pulse.
- a sequence of test pulses having varying powers such as by having varying magnitudes and constant pulse widths, is applied to a memory cell.
- Each test pulse will induce a roughly hemispherical molten region 103 having a radius x.
- the sequence of test pulses includes a subset of test pulses which induce molten regions having a radius between about r 0 , and the thickness H of the element 101 . Because the resistivity ⁇ M of the molten phase change material is significantly different than the resistivity ⁇ S of the solid phase change material, a resistance measurement across the memory element will vary with the radius x.
- FIG. 2 illustrates the basic memory cell and access structure implemented within an array, including access transistor 105 having a gate coupled to a word line 106 , a source coupled to ground, and a drain coupled to the memory cell bottom electrode.
- the memory cell top electrode is coupled to the bit line 107 .
- the resistance R PCE of the phase change element 101 in the memory cell is represented by the resistor symbol in FIG. 2 .
- the sequence of test pulses is applied to the bit line 107 while the access transistor 105 is used to select a memory cell coupled to the bit line 107 . Current through the memory cell depends on the resistance R PCE of the memory element 101 , as well as the transistor 105 .
- a voltage V WL on the word line is set to bias the transistor in its linear region after the seen in FIG. 3 .
- FIG. 3 is a graph of drain-to-source current I DS versus drain-to-source voltage V DS , including trace 110 for a transistor having a linear region 111 and a saturated region for higher drain voltages.
- Lines 112 and 113 are load lines for dynamic resistance measurements where the memory element 101 has a first resistance R PCE and a second resistance R′ PCE , respectively. As can be seen, the current through the memory cell and access structure depends on the resistance of the memory element 101 .
- the bottom and top electrodes 100 and 102 may comprise TiAlN or TaAlN, or comprise, for further examples, one or more elements selected from the group consisting of Ti, W, Mo, Al, Ta, Cu, Pt, Ir, La, Ni, N, O and Ru and combinations thereof.
- TiN may be preferred because it makes a good contact with GST (discussed below) as a memory material, it is a common material used in semiconductor manufacturing, and it provides a good diffusion barrier at the higher temperatures at which GST transitions, typically in the 600-700 degree Celsius range.
- Embodiments of the memory element 101 include phase change based memory materials, including chalcogenide based materials and other materials.
- Chalcogens include any of the four elements oxygen (O), sulfur (S), selenium (Se), and tellurium (Te), forming part of group VIA of the periodic table.
- Chalcogenides comprise compounds of a chalcogen with a more electropositive element or radical.
- Chalcogenide alloys comprise combinations of chalcogenides with other materials such as transition metals.
- a chalcogenide alloy usually contains one or more elements from group IVa of the periodic table of elements, such as germanium (Ge) and tin (Sn).
- chalcogenide alloys include combinations including one or more of antimony (Sb), gallium (Ga), indium (In), and silver (Ag).
- Many phase change based memory materials have been described in technical literature, including alloys of: Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, In/Sb/Te, Ga/Se/Te, Sn/Sb/Te, In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te, Ge/Sb/Se/Te and Te/Ge/Sb/S.
- a wide range of alloy compositions may be workable.
- the compositions can be characterized as Te a Ge b Sb 100-(a+b) .
- Chalcogenides and other phase change materials are doped with impurities in some embodiments to modify conductivity, transition temperature, melting temperature, and other properties of memory elements using the doped chalcogenides.
- Representative impurities used for doping chalcogenides include nitrogen, silicon, oxygen, silicon dioxide, silicon nitride, copper, silver, gold, aluminum, aluminum oxide, tantalum, tantalum oxide, tantalum nitride, titanium and titanium oxide. See, for example U.S. Pat. No. 6,800,504, and U.S. Patent Application Publication No. US 2005/0029502.
- Phase change alloys are capable of being switched between a first structural state in which the material is in a generally amorphous solid phase, and a second structural state in which the material is in a generally crystalline solid phase in its local order in the active channel region of the cell.
- amorphous is used to refer to a relatively less ordered structure, more disordered than a single crystal, which has the detectable characteristics such as higher electrical resistivity than the crystalline phase.
- crystalline is used to refer to a relatively more ordered structure, more ordered than in an amorphous structure, which has detectable characteristics such as lower electrical resistivity than the amorphous phase.
- phase change materials may be electrically switched between different detectable states of local order across the spectrum between completely amorphous and completely crystalline states.
- material characteristics affected by the change between amorphous and crystalline phases include atomic order, free electron density and activation energy.
- the material may be switched either into different solid phases or into mixtures of two or more solid phases, providing a gray scale between completely amorphous and completely crystalline states.
- the electrical properties in the material may vary accordingly.
- test pulses used for measurements described herein can be determined empirically or by modeling, and specifically adapted to a particular phase change alloy and cell structure.
- a material useful for implementation of a PCRAM described herein is Ge 2 Sb 2 Te 5 .
- a collimator with an aspect ratio of 1 ⁇ 5 can be used to improve the fill-in performance.
- the DC bias of several tens to several hundreds of volts is also used.
- the combination of DC bias and the collimator can be used simultaneously.
- the post deposition annealing treatment with vacuum or N 2 ambient is sometimes needed to improve the crystallize state of chalcogenide material.
- the annealing temperature typically ranges 100° C. to 400° C. with an anneal time of less than 30 minutes.
- chalcogenide material depends on the design of cell structure.
- a chalcogenide material with thickness of higher than 8 nm can have a phase change characterization so that the material exhibits at least two stable resistance the states.
- FIGS. 4 a - 4 f are plots of measurements of dynamic resistance in six different memory cells, where the dots are measurements for individual test pulses in a sequence of 40 test pulses about 40 nsec long, which are stepped from 0.6 V to 1.5V in increments of 0.015 V.
- the plots show the linear region of the measurements, in which the radius of the molten region is believed to fall in the range between r 0 and H as explained above.
- the three components of this computation include first, the resistance of the molten hemispherical region having radius r 0 , second the resistance of the molten hemispherical region between radius r 0 and x, and the resistance of the solid material between x and H.
- the intercept B indicate material properties of the tested cells and critical dimensions of the selected cells.
- Table 1 below shows the results of extraction of the coefficients A and B for 12 selected memory cells.
- the mean value of A is about 0.5623 and the percent variation of A is about 5%.
- the mean value of B is about 60.36 and the percent variation of B is about 35%.
- the parameter A depends only on material properties of the cell, and is independent of cell dimensions in the plotted linear region. Therefore, the percent variation is much smaller than the percent variation in B, which also depends on the dimensions of the cell including r 0 .
- the molten region 103 has an electrical resistivity ⁇ M much less than the electrical resistivity ⁇ S of the surrounding solid material in the memory element 101 .
- the resistance of the cell can be derived from the following equation:
- R ⁇ m 4 ⁇ r 0 + ⁇ r 0 x ⁇ ⁇ m ⁇ 1 2 ⁇ ⁇ ⁇ ⁇ y 2 ⁇ ⁇ y + ⁇ x H ⁇ ⁇ s ⁇ 1 2 ⁇ ⁇ ⁇ ⁇ y 2 ⁇ ⁇ y
- the radius x is proportional to the amount of energy applied during the test pulse.
- the slope A depends only on the material properties k 1 , ⁇ S and ⁇ M .
- the intercept B depends on material properties plus critical dimensions of the memory element r 0 and H.
- the slope A is related to material properties of the memory cell being tested
- the intercept B is related to the material properties and to the physical structure of the cell.
- a healthy cell should have stable A and B values.
- a stable manufacturing line should have stable A and B values between the cells within the array, between die, between wafers and between lots.
- FIG. 5 is a simplified block diagram of an integrated circuit in accordance with an embodiment.
- the integrated circuit 500 includes a memory array 505 implemented using phase change memory cells as described.
- a row decoder 510 having read, set and reset modes is coupled to a plurality of word lines 515 arranged along rows in the memory array 505 .
- Block 505 a represents probe points on the array suitable for coupling to a testing machine for the measurement of dynamic resistance. Alternatively, circuitry may be provided on chip to provide output indicating such measurements.
- a column decoder 520 is coupled to a plurality of bit lines 525 arranged along columns in the memory array 505 for reading, setting and resetting memory cells in the memory array 505 .
- Addresses are supplied on bus 560 to column decoder 520 and row decoder 510 .
- Sense amplifiers and data-in structures in block 530 are coupled to the column decoder 520 via data bus 535 .
- Data is supplied via the data-in line 540 from input/output ports on the integrated circuit 500 or from other data sources internal or external to the integrated circuit 500 , to the data-in structures in block 530 .
- other circuitry 565 is included on the integrated circuit 500 , such as a general purpose processor or special purpose application circuitry, or a combination of modules providing system-on-a-chip functionality supported by the phase change memory cell array.
- Data is supplied via the data-out line 545 from the sense amplifiers in block 530 to input/output ports on the integrated circuit 500 , or to other data destinations internal or external to the integrated circuit 500 .
- a controller implemented in this example using bias arrangement state machine 550 controls the bias circuitry voltage and current sources 555 for the application of bias arrangements including read, set, reset and verify voltages and or currents for the word lines and bit lines, and controls the word line/source line operation using an access control process.
- the state machine 550 may include out logic supporting a process for measuring dynamic resistance as described herein, including the generation of sequences of test pulses in coordination with the bias circuitry voltage and current sources 555 , and other supporting logic functions, including parameter registers for storing the parameter sets in a machine-readable format extracted, as necessary.
- the controller can be implemented using special-purpose logic circuitry as known in the art.
- the controller comprises a general-purpose processor, which may be implemented on the same integrated circuit, which executes a computer program to control the operations of the device.
- a combination of special-purpose logic circuitry and a general-purpose processor may be utilized for implementation of the controller.
- Another embodiment consists of a similar integrated circuit as shown in FIG. 5 but without block 505 a.
- the dynamic resistance measurements are performed by a special test mode through the integrated circuit.
- a separated test structure to the main memory array is provided for the dynamic resistance measurement.
- This test structure can have the similar cell design as the memory array 505 in the integrated circuit 500 , or can have special design for testing purpose.
- FIG. 6 is a flow chart for a manufacturing and testing process according to the present invention. As illustrated, the process begins with performing manufacturing processes sufficient to produce a testable cell on a memory device (block 601 ). The device is coupled to a testing machine, and probes are applied the probe points on the device to which a sequence of test pulses is applied (block 602 ). The dynamic resistance is measured during the test pulses (block 603 ). A parameter set is extracted including the slope A and intercept B as explained above for a linear fitting equation (block 604 ). The parameter set is then associated with the memory device, by storing it in a machine-readable format in a register file on the chip, or in memory on the test workstation associated with the tested chip (block 605 ).
- a manufacturing step is performed in response to the parameter set (block 606 ).
- Representative manufacturing steps include, if the parameter set falls outside the specified range, discarding the memory device, or stopping the manufacturing of further devices pending analysis of the manufacturing line and reasons for the detected anomalies, and so on.
- FIG. 7 is a flow chart of an alternative manufacturing and testing process which measures changes in the parameter set after applying a stress to the memory device.
- the process begins with performing manufacturing processes sufficient to produce a testable cell on a memory device (block 701 ).
- the device is coupled to a testing machine, and probes are applied these probe points on the device to which a sequence of test pulses is applied (block 702 ).
- the dynamic resistance is measured during the test pulses (block 703 ).
- a first parameter set is extracted including the slope A and intercept B as explained above for a linear fitting equation (block 704 ).
- the first parameter set is then associated with the memory device, by storing in a machine-readable format and a register file on the chip, or in memory on the test workstation (block 705 ).
- a stress is applied to the memory cell, such as reset/set cycling, a long pulse, or the like (block 706 ).
- a second sequence of test pulses is applied to the memory cell (block 707 ).
- the dynamic resistance is measured during the second sequence of test pulses (block 708 ).
- a second parameter set is extracted including the slope A and intercept B as explained above for a linear fitting equation (block 709 ).
- the second parameter set is then associated with the memory device, by storing in a machine-readable format in a register file on the chip, or in memory on the test workstation (block 710 ).
- a manufacturing step is performed in response to the analysis of the first and second parameter sets (block 71 1 ). Representative manufacturing steps include, if the change in the parameter sets falls outside the specified range, discarding the memory device, or stopping the manufacturing of further devices pending analysis of the manufacturing line and reasons for the detected anomalies, and so on.
- FIG. 8 is a simplified block diagram of the manufacturing line including equipment for performing the dynamic resistance test as described above.
- Such manufacturing line includes fabrication equipment 800 for performing manufacturing steps to produce a testable cell on a wafer.
- the wafer including the testable cell is moved to test station 801 , in which the device is probed as explained above for measuring the dynamic resistance.
- the test station is coupled to a test workstation 802 which gathers the parameter sets as explained above, and performs such data processing has necessary to produce commands that affect a manufacturing operations.
- the memory device is passed to equipment 803 for further manufacturing steps, such as dicing the wafer containing the device, packaging the device and so on.
Abstract
Description
- International Business Machines Corporation, a New York corporation; and Macronix International Corporation, Ltd., a Taiwan R.O.C. corporation, are parties to a Joint Research Agreement.
- 1. Field of the Invention
- The present invention relates to high density memory devices based on phase change materials like chalcogenides and others, and to methods for manufacturing such devices.
- 2. Description of Related Art
- Phase change based memory materials, like chalcogenide based materials and similar materials, can be caused to change phase between an amorphous solid phase and a crystalline solid phase by application of electrical current at levels suitable for implementation in integrated circuits. The generally amorphous state is characterized by higher resistivity than the generally crystalline state, which can be readily sensed to indicate data. Thus, phase change materials can be characterized as a type of programmable resistive memory material. These properties have generated interest in using phase change material and other programmable resistive memory material to form nonvolatile memory circuits, which can be read and written with random access.
- The change from the amorphous to the crystalline state is generally a lower current operation. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure, after which the phase change material cools quickly, quenching the phase change process and allowing at least a portion of the phase change structure to stabilize in the amorphous state. It is desirable to minimize the magnitude of the reset current used to cause the transition of the phase change material from a crystalline state to an amorphous state. The memory cells using phase change material include an “active region” in the bulk of the phase change material of the cell in which the actual phase transitions are located. Techniques are applied to make the active region small, so that the amount of current needed to induce the phase change is reduced. Also, techniques are used to thermally isolate the active region in the phase change cell so that the resistive heating needed to induce the phase change is confined to the active region.
- The magnitude of the reset current needed for reset can also be reduced by reducing the size of the phase change material element in the cell and/or the contact area between electrodes and the phase change material, such that higher current densities are achieved with small absolute current values through the phase change material element.
- One direction of development has been toward forming small pores in an integrated circuit structure, and using small quantities of programmable resistive material to fill the small pores. Patents illustrating development toward small pores include: Ovshinsky, “Multibit Single Cell Memory Element Having Tapered Contact,” U.S. Pat. No. 5,687,112, issued Nov. 11, 1997; Zahorik et al., “Method of Making Chalogenide [sic] Memory Device,” U.S. Pat. No. 5,789,277, issued Aug. 4, 1998; Doan et al., “Controllable Ovonic Phase-Change Semiconductor Memory Device and Methods of Fabricating the Same,” U.S. Pat. No. 6,150,253, issued Nov. 21, 2000.
- Another technology developed by the assignee of the present application is referred to as a phase change bridge cell, in which a very small patch of memory material is formed as a bridge across a thin film insulating member located between electrodes. The phase change bridge is easily integrated with logic and other types of circuitry on integrated circuits. See, U.S. application Ser. No. 11/155,067, filed 17 Jun. 2005, entitled “Thin Film Fuse Phase Change RAM and Manufacturing Method,” by Lung et al., incorporated by reference as if fully set forth herein, which application was owned at the time of invention and is currently owned by the same assignee.
- Yet another approach to controlling the size of the active area in a phase change cell is to devise very small electrodes for delivering current to a body of phase change material. This small electrode structure induces phase change in the phase change material in a small area like the head of a mushroom, at the location of the contact. See, U.S. Pat. No. 6,429,064, issued Aug. 6, 2002, to Wicker, “Reduced Contact Areas of Sidewall Conductor;” U.S. Pat. No. 6,462,353, issued Oct. 8, 2002, to Gilgen, “Method for Fabricating a Small Area of Contact Between Electrodes;” U.S. Pat. No. 6,501,111, issued Dec. 31, 2002, to Lowrey, “Three-Dimensional (3D) Programmable Device;” U.S. Pat. No. 6,563,156, issued Jul. 1, 2003, to Harshfield, “Memory Elements and Methods for Making Same.”
- In co-pending U.S. Patent Application entitled PHASE CHANGE MEMORY CELL ARRAY WITH SELF-CONVERGED BOTTOM ELECTRODE AND METHOD FOR MANUFACTURING; application Ser. No. 11/855,983; filed 14 Sep. 2007; which is incorporated by reference as if fully set forth herein, a representative mushroom memory cell and manufacturing process are described in detail.
- Manufacturability of integrated circuit memory devices, such as phase change memory devices, requires that efficient testing methodologies be provided for use during manufacturing. For example, it is desirable to detect faulty devices during manufacturing, such as before packaging of the individual die, in order to avoid packaging defective devices and wasting the expense of such packaging. Also, it is desirable to detect faulty devices during manufacturing, so that the manufacturing process can be tuned to improve yield.
- Testing methodologies can require significant processing overhead for large scale integrated circuit devices, and can slow down the manufacturing process. Thus it is desirable to provide methodologies that provide good information with low processing overhead.
- The present invention provides a testing and manufacturing technology for integrated circuit phase change memory devices based on the discovery that material properties of memory cells, such as the integrity of interfaces between contact and phase change material, voids in the phase change material and the like, and critical dimensions of memory cells, such as the area of contact between phase change material an electrode, can be detected by determining coefficients of a simple equation, such as the slope and intercept coefficients for a linear equation, fitted to the measurement of the dynamic resistance of the memory cell.
- A method is described for testing an integrated circuit memory device. The method includes applying of test pulses to a memory cell on the device, where the test pulses result in current through the memory cell having an amplitude dependent on the test pulse. Resistance in the memory cell is measured in response to the sequence of test pulses. A parameter set is extracted from the measurements which includes at least one numerical coefficient that models dependency of the measured resistance on the amplitude of the current through the memory cell. The extracted numerical coefficient or coefficients are associated with the memory device, such as by storing the parameter set including the extracted numerical coefficient or coefficients in a computer readable medium on the integrated circuit or in a testing workstation to which the circuit is coupled.
- In embodiments having an access device like a transistor, a gate to source voltage is applied to the transistor access device to bias it in a linear region of operation, during the step of applying the sequence of test pulses.
- In an embodiment in which the memory can be characterized by having a bottom electrode contacting a phase change memory element in a contact area, the test pulses cause formation of a molten region within the phase change memory element near the bottom electrode having a volume dependent on the contact area and on the energy applied during the test. For each pulse in the sequence of pulses used in the test, a different volume of molten material results. The resistance measurements therefore change dynamically with the test pulses. For memory cells having the mushroom configuration and similar configurations, the extracted coefficients include a slope A and an intercept B for a function of the form R=A/I+B, where R is the measured resistance and I is the current in the device during a test pulse in the sequence. The slope A is a coefficient that depends primarily on the material properties of the memory cell. Therefore, when the slope A falls outside an expected range, the information can be used in deducing that the memory cell has a material fault, such as a void in a critical region of the phase change memory element, or a poor interface between one of the top and bottom electrodes. The intercept B is a coefficient that depends not only on material properties, but also on critical dimensions of the memory cell. Therefore, if the intercept B falls outside an expected range, or changes after stress is applied to the cell, the information can be used in deducing that a critical dimensions of the memory cell fall outside specified manufacturing tolerances, or other faults in interface structures are occurring.
- The sequence of test pulses used for the purposes of measuring the dynamic resistance comprises varying voltage pulses having magnitude sufficient to melt a portion of the phase change element in the memory cell, and durations sufficient for thermal transients to settle before measuring the resistance. For example, in a representative embodiment the sequence of test pulses comprise more than 10, for example 40, varying voltage pulses having equal durations between about 20 and 100 ns, preferably about 40 ns, and increasing magnitude stepping in steps of about 0.1 to 0.01 V from about 0.6 V to about 1.5 V.
- Based on analysis of the parameter set, an integrated circuit device can be discarded if the extracted numerical coefficient or coefficients indicate that the device is not reliable. Alternatively, the information in the parameter set can be used to stop a manufacturing process for additional devices if the extracted coefficients fall outside an acceptable range, and thereby indicate a fault has occurred in the manufacturing process.
- In other embodiments, after performing a first dynamic resistance measurement as described above, the memory cell is subjected to a stress, such as a long voltage pulse or a number of set/reset cycles, and then a second dynamic resistance measurement is executed to develop a second parameter set. The first and second parameter sets can then be analyzed to determine characteristics of the memory cell.
- A method of manufacturing an integrated circuit memory device is also described, including first performing manufacturing steps to produce a testable memory cell, then performing a dynamic resistance measurement as described above. Based on results of the dynamic resistance measurement, manufacturing method includes either performing further manufacturing steps on the integrated circuit device if the extracted parameter set meets specified guidelines, else discarding the integrated circuit device. Alternatively, the manufacturing method may include suspending the manufacturing line for analysis if the extracted parameter set falls outside specified guidelines, or else allowing the manufacturing line to continue manufacturing.
- These and other embodiments, features, aspects, and advantages of the invention will become better understood with reference to the following description, appended claims and accompanying drawings.
-
FIG. 1 is a simplified diagram of a mushroom style phase change memory cell including a molten region and a solid region as induced during dynamic resistance measurements described herein. -
FIG. 2 is a schematic diagram of a single memory device and access device at a cross point of a bit line and a word line in an array of such devices subjected to testing as described herein -
FIG. 3 is a graph of drain to source current versus drain to source voltage for an access device showing dynamic resistance measurements. -
FIGS. 4 a through 4 f show the results of measurements of dynamic resistance for six different memory cells fitted to a linear curve. -
FIG. 5 is a simplified block diagram of an integrated circuit memory device as described herein including a dynamic resistance test mode. -
FIG. 6 is a flowchart of a testing and manufacturing method as described herein. -
FIG. 7 has a flowchart of an alternative testing and manufacturing method as described herein. -
FIG. 8 is a simplified diagram of a manufacturing line including test station for dynamic resistance tests as described herein. - A detailed description is provided with reference to
FIGS. 1-8 .FIG. 1 is a simplified diagram of a mushroom style phase change memory cell including abottom electrode 100, anelement 101 comprising a phase change material, and atop electrode 102. Thebottom electrode 100 in the illustrated embodiment is a pillar having a radius r0 at the interface having a contact area, roughly πr0 2, betweenelement 101 and thebottom electrode 100. Thetop electrode 102 contacts theelement 101 over substantially greater area than the contact area at the interface between thebottom electrode 100 andelement 101. - In operation, bias circuitry (See, for example, bias circuitry voltage and
current sources 555 ofFIG. 5 ) applying voltages to an access device coupled to the bottom electrode and a bit line coupled to the top electrode can induce current to flow thememory element 101. During a read operation, and magnitude of current flow is small and insufficient to cause a phase change in the active region of thememory element 101. During a set operation, the current flow is adapted to cause a portion ofmemory element 101 to increase in temperature above a transition temperature sufficient to induce a phase transition between an amorphous state in active region and a crystalline state in the active region. During a reset operation, the current flow is adapted to cause a portion of thememory element 101 to melt and then cool off quickly enough that the active region remains in, or transitions to, an amorphous solid state. - In
FIG. 1 , an active region of thememory element 101 occurs adjacent to the interface between thebottom electrode 100 and amemory element 101. As described above, in order to measure dynamic resistance of the memory element for the purposes of testing and manufacturing as described herein, a sequence of test pulses is applied to the memory cell. The test pulses have magnitudes and durations sufficient to cause formation of amolten region 103 within theelement 101, while the remainder of the memory only 101 remains in a solid phase. Also, the test pulses have durations sufficient for thermal transients to dissipate in theelement 101, so that a dynamic resistance measurement can be taken on a relatively stable structure. Thus, dynamic resistance is defined as the resistance of the phase change cell when a constant current flows through the cell. This is a steady state measurement. Dynamic resistance can be measured using a simple scheme similar to that used to determine the R-I curve, while ensuring that the access transistor, or other access device, is biased in its linear region. This operation in the linear region enables us to subtract the transistor resistance and obtain the resistance of thephase change element 101 during programming. Although, dynamic resistance is a steady state measurement, the programming pulse can be relatively short, such as about 40 ns. All the thermal transients typically settle in less than 5 ns, so the measured resistance is the resistance of the cell when a constant current is flowing through the cell. - The size of the molten region depends on a critical dimension r0, and the amount of power (VI) delivered by the test pulse. Thus, in order to measure the dynamic resistance a sequence of test pulses having varying powers, such as by having varying magnitudes and constant pulse widths, is applied to a memory cell. Each test pulse will induce a roughly hemispherical
molten region 103 having a radius x. The sequence of test pulses includes a subset of test pulses which induce molten regions having a radius between about r0, and the thickness H of theelement 101. Because the resistivity ρM of the molten phase change material is significantly different than the resistivity ρS of the solid phase change material, a resistance measurement across the memory element will vary with the radius x. -
FIG. 2 illustrates the basic memory cell and access structure implemented within an array, includingaccess transistor 105 having a gate coupled to aword line 106, a source coupled to ground, and a drain coupled to the memory cell bottom electrode. The memory cell top electrode is coupled to thebit line 107. The resistance RPCE of thephase change element 101 in the memory cell is represented by the resistor symbol inFIG. 2 . The sequence of test pulses is applied to thebit line 107 while theaccess transistor 105 is used to select a memory cell coupled to thebit line 107. Current through the memory cell depends on the resistance RPCE of thememory element 101, as well as thetransistor 105. During the process of applying a sequence of test pulses, where the access device is atransistor 105 as illustrated inFIG. 2 , a voltage VWL on the word line is set to bias the transistor in its linear region after the seen inFIG. 3 . -
FIG. 3 is a graph of drain-to-source current IDS versus drain-to-source voltage VDS, includingtrace 110 for a transistor having alinear region 111 and a saturated region for higher drain voltages.Lines memory element 101 has a first resistance RPCE and a second resistance R′PCE, respectively. As can be seen, the current through the memory cell and access structure depends on the resistance of thememory element 101. - It will be understood that a wide variety of materials can be utilized in implementation of the bottom and
top electrodes top electrodes - Embodiments of the
memory element 101 include phase change based memory materials, including chalcogenide based materials and other materials. Chalcogens include any of the four elements oxygen (O), sulfur (S), selenium (Se), and tellurium (Te), forming part of group VIA of the periodic table. Chalcogenides comprise compounds of a chalcogen with a more electropositive element or radical. Chalcogenide alloys comprise combinations of chalcogenides with other materials such as transition metals. A chalcogenide alloy usually contains one or more elements from group IVa of the periodic table of elements, such as germanium (Ge) and tin (Sn). Often, chalcogenide alloys include combinations including one or more of antimony (Sb), gallium (Ga), indium (In), and silver (Ag). Many phase change based memory materials have been described in technical literature, including alloys of: Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, In/Sb/Te, Ga/Se/Te, Sn/Sb/Te, In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te, Ge/Sb/Se/Te and Te/Ge/Sb/S. In the family of Ge/Sb/Te alloys, a wide range of alloy compositions may be workable. The compositions can be characterized as TeaGebSb100-(a+b). - Chalcogenides and other phase change materials are doped with impurities in some embodiments to modify conductivity, transition temperature, melting temperature, and other properties of memory elements using the doped chalcogenides. Representative impurities used for doping chalcogenides include nitrogen, silicon, oxygen, silicon dioxide, silicon nitride, copper, silver, gold, aluminum, aluminum oxide, tantalum, tantalum oxide, tantalum nitride, titanium and titanium oxide. See, for example U.S. Pat. No. 6,800,504, and U.S. Patent Application Publication No. US 2005/0029502.
- One researcher has described the most useful alloys as having an average concentration of Te in the deposited materials well below 70%, typically below about 60% and ranged in general from as low as about 23% up to about 58% Te and most preferably about 48% to 58% Te. Concentrations of Ge were above about 5% and ranged from a low of about 8% to about 30% average in the material, remaining generally below 50%. Most preferably, concentrations of Ge ranged from about 8% to about 40%. The remainder of the principal constituent elements in this composition was Sb. These percentages are atomic percentages that total 100% of the atoms of the constituent elements. (Ovshinsky '112patent, cols 10-11.) Particular alloys evaluated by another researcher include Ge2Sb2Te5, GeSb2Te4 and GeSb4Te 7 . (Noboru Yamada, “Potential of Ge—Sb—Te Phase-Change Optical Disks for High-Data-Rate Recording”, SPIE v.3109, pp. 28-37 (1997).) More generally, a transition metal such as chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt) and mixtures or alloys thereof may be combined with Ge/Sb/Te to form a phase change alloy that has programmable resistive properties. Specific examples of memory materials that may be useful are given in Ovshinsky '112 at columns 11-13, which examples are hereby incorporated by reference.
- Phase change alloys are capable of being switched between a first structural state in which the material is in a generally amorphous solid phase, and a second structural state in which the material is in a generally crystalline solid phase in its local order in the active channel region of the cell. The term amorphous is used to refer to a relatively less ordered structure, more disordered than a single crystal, which has the detectable characteristics such as higher electrical resistivity than the crystalline phase. The term crystalline is used to refer to a relatively more ordered structure, more ordered than in an amorphous structure, which has detectable characteristics such as lower electrical resistivity than the amorphous phase. Typically, phase change materials may be electrically switched between different detectable states of local order across the spectrum between completely amorphous and completely crystalline states. Other material characteristics affected by the change between amorphous and crystalline phases include atomic order, free electron density and activation energy. The material may be switched either into different solid phases or into mixtures of two or more solid phases, providing a gray scale between completely amorphous and completely crystalline states. The electrical properties in the material may vary accordingly.
- Appropriate profiles for test pulses used for measurements described herein can be determined empirically or by modeling, and specifically adapted to a particular phase change alloy and cell structure. A material useful for implementation of a PCRAM described herein is Ge2Sb2Te5.
- Representative chalcogenide material can be characterized as follows: GexSbyTez, where x:y:z=2:2:5. Other compositions can be used with x: 0˜5; y: 0˜5; z: 0˜10. GeSbTe with doping, such as N—, Si—, Ti—, P—, As— or other element doping may also be used. These materials can be formed by PVD sputtering or magnetron-sputtering method with reactive gases of Ar, N2, and/or He, etc and chalcogenide at the pressure of 1 mtorr˜100 mtorr. The deposition is usually done at room temperature. A collimator with an aspect ratio of 1˜5 can be used to improve the fill-in performance. To improve the fill-in performance, the DC bias of several tens to several hundreds of volts is also used. Also, the combination of DC bias and the collimator can be used simultaneously. The post deposition annealing treatment with vacuum or N2 ambient is sometimes needed to improve the crystallize state of chalcogenide material. The annealing temperature typically ranges 100° C. to 400° C. with an anneal time of less than 30 minutes.
- The thickness of chalcogenide material depends on the design of cell structure. In general, a chalcogenide material with thickness of higher than 8 nm can have a phase change characterization so that the material exhibits at least two stable resistance the states.
- The
FIGS. 4 a-4 f are plots of measurements of dynamic resistance in six different memory cells, where the dots are measurements for individual test pulses in a sequence of 40 test pulses about 40 nsec long, which are stepped from 0.6 V to 1.5V in increments of 0.015 V. The plots show the linear region of the measurements, in which the radius of the molten region is believed to fall in the range between r0 and H as explained above. The lines on the plots represent a linear curve fitted to the measurements, of the form R=A/I+B, where R is the measured resistance and I is the current in the device during a test pulse, and the coefficients including the slope A and - The three components of this computation include first, the resistance of the molten hemispherical region having radius r0, second the resistance of the molten hemispherical region between radius r0 and x, and the resistance of the solid material between x and H.
- Performing the integration and expanding the equation results in the following:
-
- All of the values in this equation are constants, with the exception of x. It has been determined from simulations that the radius of the molten volume is linearly proportional to the current induced during the test pulse so that:
-
x=k1I - This phenomenon might be explained by the basic heat diffusion equation for the memory cell as follows:
-
- At steady state, with a molten volume of radius x, we assume that the energy being supplied by the current is used to maintain this volume above the melting temperature. Thus, we obtain the following:
-
- Since the input power density is equal to the amount of energy lost due to diffusion at steady state, we obtain equations for input power density as follows:
-
- the intercept B indicate material properties of the tested cells and critical dimensions of the selected cells.
- Table 1 below shows the results of extraction of the coefficients A and B for 12 selected memory cells. The mean value of A is about 0.5623 and the percent variation of A is about 5%. The mean value of B is about 60.36 and the percent variation of B is about 35%.
-
TABLE 1 A B 0.60287 26.049 0.54801 80.396 0.54859 59.396 0.50238 110.56 0.54205 55.382 0.53921 75.798 0.56577 48.71 0.58452 62.407 0.58018 40.884 0.55871 56.958 0.58769 53.065 0.5879 54.8 - The parameter A depends only on material properties of the cell, and is independent of cell dimensions in the plotted linear region. Therefore, the percent variation is much smaller than the percent variation in B, which also depends on the dimensions of the cell including r0.
- One possible explanation for this observation can be derived as follows. The
molten region 103 has an electrical resistivity ρM much less than the electrical resistivity ρS of the surrounding solid material in thememory element 101. The resistance of the cell can be derived from the following equation: -
- We also obtained the equation for diffusion loss as follows:
-
- As result we can see that the radius x can be characterized as follows:
-
- Thus, the radius x is proportional to the amount of energy applied during the test pulse.
- Therefore, it can be seen that dynamic resistance of the memory cell can be represented by an equation of the form R=A/I+B, where
-
- Therefore, the slope A depends only on the material properties k1, ρS and ρM. The intercept B depends on material properties plus critical dimensions of the memory element r0 and H.
- In summary, the slope A is related to material properties of the memory cell being tested, and the intercept B is related to the material properties and to the physical structure of the cell. A healthy cell should have stable A and B values. A stable manufacturing line should have stable A and B values between the cells within the array, between die, between wafers and between lots. Thus by extracting the parameter set including the coefficients A and B, reliability of a memory cell can be predicted including the likelihood of degradation in switching ratio, the average lifetime before failure, required reset power drift with cycling, and so on. Also, the parameter set can be used to monitor process uniformity and the degree of variation between cells, between die, between wafers and so on.
-
FIG. 5 is a simplified block diagram of an integrated circuit in accordance with an embodiment. Theintegrated circuit 500 includes amemory array 505 implemented using phase change memory cells as described. Arow decoder 510 having read, set and reset modes is coupled to a plurality ofword lines 515 arranged along rows in thememory array 505.Block 505 a represents probe points on the array suitable for coupling to a testing machine for the measurement of dynamic resistance. Alternatively, circuitry may be provided on chip to provide output indicating such measurements. Acolumn decoder 520 is coupled to a plurality ofbit lines 525 arranged along columns in thememory array 505 for reading, setting and resetting memory cells in thememory array 505. Addresses are supplied onbus 560 tocolumn decoder 520 androw decoder 510. Sense amplifiers and data-in structures inblock 530, including current sources for the read, set and reset modes, are coupled to thecolumn decoder 520 viadata bus 535. Data is supplied via the data-inline 540 from input/output ports on theintegrated circuit 500 or from other data sources internal or external to theintegrated circuit 500, to the data-in structures inblock 530. In the illustrated embodiment,other circuitry 565 is included on theintegrated circuit 500, such as a general purpose processor or special purpose application circuitry, or a combination of modules providing system-on-a-chip functionality supported by the phase change memory cell array. Data is supplied via the data-outline 545 from the sense amplifiers inblock 530 to input/output ports on theintegrated circuit 500, or to other data destinations internal or external to theintegrated circuit 500. - A controller implemented in this example using bias
arrangement state machine 550 controls the bias circuitry voltage andcurrent sources 555 for the application of bias arrangements including read, set, reset and verify voltages and or currents for the word lines and bit lines, and controls the word line/source line operation using an access control process. Also, thestate machine 550 may include out logic supporting a process for measuring dynamic resistance as described herein, including the generation of sequences of test pulses in coordination with the bias circuitry voltage andcurrent sources 555, and other supporting logic functions, including parameter registers for storing the parameter sets in a machine-readable format extracted, as necessary. The controller can be implemented using special-purpose logic circuitry as known in the art. In alternative embodiments, the controller comprises a general-purpose processor, which may be implemented on the same integrated circuit, which executes a computer program to control the operations of the device. In yet other embodiments, a combination of special-purpose logic circuitry and a general-purpose processor may be utilized for implementation of the controller. - Another embodiment consists of a similar integrated circuit as shown in
FIG. 5 but withoutblock 505 a. The dynamic resistance measurements are performed by a special test mode through the integrated circuit. - In another embodiment, a separated test structure to the main memory array is provided for the dynamic resistance measurement. This test structure can have the similar cell design as the
memory array 505 in theintegrated circuit 500, or can have special design for testing purpose. -
FIG. 6 is a flow chart for a manufacturing and testing process according to the present invention. As illustrated, the process begins with performing manufacturing processes sufficient to produce a testable cell on a memory device (block 601). The device is coupled to a testing machine, and probes are applied the probe points on the device to which a sequence of test pulses is applied (block 602). The dynamic resistance is measured during the test pulses (block 603). A parameter set is extracted including the slope A and intercept B as explained above for a linear fitting equation (block 604). The parameter set is then associated with the memory device, by storing it in a machine-readable format in a register file on the chip, or in memory on the test workstation associated with the tested chip (block 605). Finally, a manufacturing step is performed in response to the parameter set (block 606). Representative manufacturing steps include, if the parameter set falls outside the specified range, discarding the memory device, or stopping the manufacturing of further devices pending analysis of the manufacturing line and reasons for the detected anomalies, and so on. -
FIG. 7 is a flow chart of an alternative manufacturing and testing process which measures changes in the parameter set after applying a stress to the memory device. Thus, the process begins with performing manufacturing processes sufficient to produce a testable cell on a memory device (block 701). The device is coupled to a testing machine, and probes are applied these probe points on the device to which a sequence of test pulses is applied (block 702). The dynamic resistance is measured during the test pulses (block 703). A first parameter set is extracted including the slope A and intercept B as explained above for a linear fitting equation (block 704). The first parameter set is then associated with the memory device, by storing in a machine-readable format and a register file on the chip, or in memory on the test workstation (block 705). Next, a stress is applied to the memory cell, such as reset/set cycling, a long pulse, or the like (block 706). Then, a second sequence of test pulses is applied to the memory cell (block 707). The dynamic resistance is measured during the second sequence of test pulses (block 708). A second parameter set is extracted including the slope A and intercept B as explained above for a linear fitting equation (block 709). The second parameter set is then associated with the memory device, by storing in a machine-readable format in a register file on the chip, or in memory on the test workstation (block 710). Finally, a manufacturing step is performed in response to the analysis of the first and second parameter sets (block 71 1). Representative manufacturing steps include, if the change in the parameter sets falls outside the specified range, discarding the memory device, or stopping the manufacturing of further devices pending analysis of the manufacturing line and reasons for the detected anomalies, and so on. -
FIG. 8 is a simplified block diagram of the manufacturing line including equipment for performing the dynamic resistance test as described above. Such manufacturing line includesfabrication equipment 800 for performing manufacturing steps to produce a testable cell on a wafer. The wafer including the testable cell is moved totest station 801, in which the device is probed as explained above for measuring the dynamic resistance. The test station is coupled to atest workstation 802 which gathers the parameter sets as explained above, and performs such data processing has necessary to produce commands that affect a manufacturing operations. After testing, the memory device is passed toequipment 803 for further manufacturing steps, such as dicing the wafer containing the device, packaging the device and so on. - The invention has been described with reference to specific exemplary embodiments. Various modifications, adaptations, and changes may be made without departing from the spirit and scope of the invention. Accordingly, the specification and drawings are to be regarded as illustrative of the principles of this invention rather than restrictive, the invention is defined by the following appended claims.
Claims (21)
R=A/I+B,
R=A/I+B,
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/970,348 US7639527B2 (en) | 2008-01-07 | 2008-01-07 | Phase change memory dynamic resistance test and manufacturing methods |
TW097103164A TWI365293B (en) | 2008-01-07 | 2008-01-28 | Phase change memory dynamic resistance test and manufacturing methods |
CN200910001340.5A CN101562050B (en) | 2008-01-07 | 2009-01-07 | Phase change memory dynamic resistance test and manufacturing methods |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/970,348 US7639527B2 (en) | 2008-01-07 | 2008-01-07 | Phase change memory dynamic resistance test and manufacturing methods |
Publications (2)
Publication Number | Publication Date |
---|---|
US20090175071A1 true US20090175071A1 (en) | 2009-07-09 |
US7639527B2 US7639527B2 (en) | 2009-12-29 |
Family
ID=40844416
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/970,348 Expired - Fee Related US7639527B2 (en) | 2008-01-07 | 2008-01-07 | Phase change memory dynamic resistance test and manufacturing methods |
Country Status (3)
Country | Link |
---|---|
US (1) | US7639527B2 (en) |
CN (1) | CN101562050B (en) |
TW (1) | TWI365293B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130094276A1 (en) * | 2011-10-18 | 2013-04-18 | Micron Technology, Inc. | Apparatuses and methods for determining stability of a memory cell |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100998944B1 (en) * | 2008-12-26 | 2010-12-09 | 주식회사 하이닉스반도체 | Write driver circuit of a PRAM |
CN101777388B (en) * | 2010-01-08 | 2012-08-08 | 中国科学院上海微系统与信息技术研究所 | Method for obtaining phase-change memory phase-change resistance crystallization rate |
US8624217B2 (en) | 2010-06-25 | 2014-01-07 | International Business Machines Corporation | Planar phase-change memory cell with parallel electrical paths |
US8575008B2 (en) | 2010-08-31 | 2013-11-05 | International Business Machines Corporation | Post-fabrication self-aligned initialization of integrated devices |
CN102354537B (en) * | 2011-07-06 | 2014-03-05 | 华中科技大学 | Method for testing chip of phase change memory |
CN106558347B (en) * | 2015-09-25 | 2020-06-09 | 中芯国际集成电路制造(上海)有限公司 | Programming test method of phase change memory |
CN106824833B (en) * | 2017-02-28 | 2023-07-18 | 中国振华集团云科电子有限公司 | Resistor screening process |
CN108648782B (en) * | 2018-04-23 | 2020-11-13 | 中国科学院上海微系统与信息技术研究所 | Screening method for optimal pulse operating conditions of phase change memory |
CN111383705A (en) * | 2018-12-30 | 2020-07-07 | 中电海康集团有限公司 | Test circuit and test method of memory |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6584589B1 (en) * | 2000-02-04 | 2003-06-24 | Hewlett-Packard Development Company, L.P. | Self-testing of magneto-resistive memory arrays |
US20080198674A1 (en) * | 2007-02-21 | 2008-08-21 | Jan Keller | Method of testing an integrated circuit, method of determining defect resistivity changing cells, testing device, and computer program adapted to perform a method for testing an integrated circuit |
Family Cites Families (84)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3271591A (en) | 1963-09-20 | 1966-09-06 | Energy Conversion Devices Inc | Symmetrical current controlling device |
US3530441A (en) | 1969-01-15 | 1970-09-22 | Energy Conversion Devices Inc | Method and apparatus for storing and retrieving information |
IL61678A (en) | 1979-12-13 | 1984-04-30 | Energy Conversion Devices Inc | Programmable cell and programmable electronic arrays comprising such cells |
US4719594A (en) | 1984-11-01 | 1988-01-12 | Energy Conversion Devices, Inc. | Grooved optical data storage device including a chalcogenide memory layer |
US4876220A (en) | 1986-05-16 | 1989-10-24 | Actel Corporation | Method of making programmable low impedance interconnect diode element |
JP2685770B2 (en) | 1987-12-28 | 1997-12-03 | 株式会社東芝 | Nonvolatile semiconductor memory device |
JP2606857B2 (en) | 1987-12-10 | 1997-05-07 | 株式会社日立製作所 | Method for manufacturing semiconductor memory device |
US5534712A (en) | 1991-01-18 | 1996-07-09 | Energy Conversion Devices, Inc. | Electrically erasable memory elements characterized by reduced current and improved thermal stability |
US5166758A (en) | 1991-01-18 | 1992-11-24 | Energy Conversion Devices, Inc. | Electrically erasable phase change memory |
US5177567A (en) | 1991-07-19 | 1993-01-05 | Energy Conversion Devices, Inc. | Thin-film structure for chalcogenide electrical switching devices and process therefor |
JP2825031B2 (en) | 1991-08-06 | 1998-11-18 | 日本電気株式会社 | Semiconductor memory device |
US5166096A (en) | 1991-10-29 | 1992-11-24 | International Business Machines Corporation | Process for fabricating self-aligned contact studs for semiconductor structures |
JPH05206394A (en) | 1992-01-24 | 1993-08-13 | Mitsubishi Electric Corp | Field effect transistor and its manufacture |
US5958358A (en) | 1992-07-08 | 1999-09-28 | Yeda Research And Development Co., Ltd. | Oriented polycrystalline thin films of transition metal chalcogenides |
JP2884962B2 (en) | 1992-10-30 | 1999-04-19 | 日本電気株式会社 | Semiconductor memory |
US5785828A (en) | 1994-12-13 | 1998-07-28 | Ricoh Company, Ltd. | Sputtering target for producing optical recording medium |
US5831276A (en) | 1995-06-07 | 1998-11-03 | Micron Technology, Inc. | Three-dimensional container diode for use with multi-state material in a non-volatile memory cell |
US5869843A (en) | 1995-06-07 | 1999-02-09 | Micron Technology, Inc. | Memory array having a multi-state element and method for forming such array or cells thereof |
US6420725B1 (en) | 1995-06-07 | 2002-07-16 | Micron Technology, Inc. | Method and apparatus for forming an integrated circuit electrode having a reduced contact area |
US5789758A (en) | 1995-06-07 | 1998-08-04 | Micron Technology, Inc. | Chalcogenide memory cell with a plurality of chalcogenide electrodes |
US5879955A (en) | 1995-06-07 | 1999-03-09 | Micron Technology, Inc. | Method for fabricating an array of ultra-small pores for chalcogenide memory cells |
US5837564A (en) | 1995-11-01 | 1998-11-17 | Micron Technology, Inc. | Method for optimal crystallization to obtain high electrical performance from chalcogenides |
US5687112A (en) | 1996-04-19 | 1997-11-11 | Energy Conversion Devices, Inc. | Multibit single cell memory element having tapered contact |
US6025220A (en) | 1996-06-18 | 2000-02-15 | Micron Technology, Inc. | Method of forming a polysilicon diode and devices incorporating such diode |
US5866928A (en) | 1996-07-16 | 1999-02-02 | Micron Technology, Inc. | Single digit line with cell contact interconnect |
US5985698A (en) | 1996-07-22 | 1999-11-16 | Micron Technology, Inc. | Fabrication of three dimensional container diode for use with multi-state material in a non-volatile memory cell |
US5789277A (en) | 1996-07-22 | 1998-08-04 | Micron Technology, Inc. | Method of making chalogenide memory device |
US5814527A (en) | 1996-07-22 | 1998-09-29 | Micron Technology, Inc. | Method of making small pores defined by a disposable internal spacer for use in chalcogenide memories |
US5998244A (en) | 1996-08-22 | 1999-12-07 | Micron Technology, Inc. | Memory cell incorporating a chalcogenide element and method of making same |
US6147395A (en) | 1996-10-02 | 2000-11-14 | Micron Technology, Inc. | Method for fabricating a small area of contact between electrodes |
US6087674A (en) | 1996-10-28 | 2000-07-11 | Energy Conversion Devices, Inc. | Memory element with memory material comprising phase-change material and dielectric material |
US6015977A (en) | 1997-01-28 | 2000-01-18 | Micron Technology, Inc. | Integrated circuit memory cell having a small active area and method of forming same |
US5952671A (en) | 1997-05-09 | 1999-09-14 | Micron Technology, Inc. | Small electrode for a chalcogenide switching device and method for fabricating same |
US6031287A (en) | 1997-06-18 | 2000-02-29 | Micron Technology, Inc. | Contact structure and memory element incorporating the same |
US5933365A (en) | 1997-06-19 | 1999-08-03 | Energy Conversion Devices, Inc. | Memory element with energy control mechanism |
US5902704A (en) | 1997-07-02 | 1999-05-11 | Lsi Logic Corporation | Process for forming photoresist mask over integrated circuit structures with critical dimension control |
US6768165B1 (en) | 1997-08-01 | 2004-07-27 | Saifun Semiconductors Ltd. | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
US6617192B1 (en) | 1997-10-01 | 2003-09-09 | Ovonyx, Inc. | Electrically programmable memory element with multi-regioned contact |
US6087269A (en) | 1998-04-20 | 2000-07-11 | Advanced Micro Devices, Inc. | Method of making an interconnect using a tungsten hard mask |
US6372651B1 (en) | 1998-07-17 | 2002-04-16 | Advanced Micro Devices, Inc. | Method for trimming a photoresist pattern line for memory gate etching |
US6141260A (en) | 1998-08-27 | 2000-10-31 | Micron Technology, Inc. | Single electron resistor memory device and method for use thereof |
US6034882A (en) | 1998-11-16 | 2000-03-07 | Matrix Semiconductor, Inc. | Vertically stacked field programmable nonvolatile memory and method of fabrication |
US6351406B1 (en) | 1998-11-16 | 2002-02-26 | Matrix Semiconductor, Inc. | Vertically stacked field programmable nonvolatile memory and method of fabrication |
US6483736B2 (en) | 1998-11-16 | 2002-11-19 | Matrix Semiconductor, Inc. | Vertically stacked field programmable nonvolatile memory and method of fabrication |
JP2000164830A (en) | 1998-11-27 | 2000-06-16 | Mitsubishi Electric Corp | Manufacture of semiconductor storage device |
US6245669B1 (en) | 1999-02-05 | 2001-06-12 | Taiwan Semiconductor Manufacturing Company | High selectivity Si-rich SiON etch-stop layer |
US6177317B1 (en) | 1999-04-14 | 2001-01-23 | Macronix International Co., Ltd. | Method of making nonvolatile memory devices having reduced resistance diffusion regions |
US6314014B1 (en) | 1999-12-16 | 2001-11-06 | Ovonyx, Inc. | Programmable resistance memory arrays with reference cells |
TW586154B (en) | 2001-01-05 | 2004-05-01 | Macronix Int Co Ltd | Planarization method for semiconductor device |
US6420216B1 (en) | 2000-03-14 | 2002-07-16 | International Business Machines Corporation | Fuse processing using dielectric planarization pillars |
US6420215B1 (en) | 2000-04-28 | 2002-07-16 | Matrix Semiconductor, Inc. | Three-dimensional memory array and method of fabrication |
US6501111B1 (en) | 2000-06-30 | 2002-12-31 | Intel Corporation | Three-dimensional (3D) programmable device |
US6563156B2 (en) | 2001-03-15 | 2003-05-13 | Micron Technology, Inc. | Memory elements and methods for making same |
US6440837B1 (en) | 2000-07-14 | 2002-08-27 | Micron Technology, Inc. | Method of forming a contact structure in a semiconductor device |
US6339544B1 (en) | 2000-09-29 | 2002-01-15 | Intel Corporation | Method to enhance performance of thermal resistor device |
US6429064B1 (en) | 2000-09-29 | 2002-08-06 | Intel Corporation | Reduced contact area of sidewall conductor |
US6567293B1 (en) | 2000-09-29 | 2003-05-20 | Ovonyx, Inc. | Single level metal memory cell using chalcogenide cladding |
US6555860B2 (en) | 2000-09-29 | 2003-04-29 | Intel Corporation | Compositionally modified resistive electrode |
US6271090B1 (en) | 2000-12-22 | 2001-08-07 | Macronix International Co., Ltd. | Method for manufacturing flash memory device with dual floating gates and two bits per cell |
US6627530B2 (en) | 2000-12-22 | 2003-09-30 | Matrix Semiconductor, Inc. | Patterning three dimensional structures |
TW490675B (en) | 2000-12-22 | 2002-06-11 | Macronix Int Co Ltd | Control method of multi-stated NROM |
US6534781B2 (en) | 2000-12-26 | 2003-03-18 | Ovonyx, Inc. | Phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and one bipolar base contact |
US6487114B2 (en) | 2001-02-28 | 2002-11-26 | Macronix International Co., Ltd. | Method of reading two-bit memories of NROM cell |
US6514788B2 (en) | 2001-05-29 | 2003-02-04 | Bae Systems Information And Electronic Systems Integration Inc. | Method for manufacturing contacts for a Chalcogenide memory device |
US6613604B2 (en) | 2001-08-02 | 2003-09-02 | Ovonyx, Inc. | Method for making small pore for use in programmable resistance memory element |
US6589714B2 (en) | 2001-06-26 | 2003-07-08 | Ovonyx, Inc. | Method for making programmable resistance memory element using silylated photoresist |
US6673700B2 (en) | 2001-06-30 | 2004-01-06 | Ovonyx, Inc. | Reduced area intersection between electrode and programming element |
US6511867B2 (en) | 2001-06-30 | 2003-01-28 | Ovonyx, Inc. | Utilizing atomic layer deposition for programmable device |
US6605527B2 (en) | 2001-06-30 | 2003-08-12 | Intel Corporation | Reduced area intersection between electrode and programming element |
US6507061B1 (en) | 2001-08-31 | 2003-01-14 | Intel Corporation | Multiple layer phase-change memory |
US6586761B2 (en) | 2001-09-07 | 2003-07-01 | Intel Corporation | Phase change material memory device |
US6566700B2 (en) | 2001-10-11 | 2003-05-20 | Ovonyx, Inc. | Carbon-containing interfacial layer for phase-change memory |
US6545903B1 (en) | 2001-12-17 | 2003-04-08 | Texas Instruments Incorporated | Self-aligned resistive plugs for forming memory cell with phase change material |
US6512241B1 (en) | 2001-12-31 | 2003-01-28 | Intel Corporation | Phase change material memory device |
JP3796457B2 (en) | 2002-02-28 | 2006-07-12 | 富士通株式会社 | Nonvolatile semiconductor memory device |
US6579760B1 (en) | 2002-03-28 | 2003-06-17 | Macronix International Co., Ltd. | Self-aligned, programmable phase change memory |
US6620715B1 (en) | 2002-03-29 | 2003-09-16 | Cypress Semiconductor Corp. | Method for forming sub-critical dimension structures in an integrated circuit |
US6670628B2 (en) | 2002-04-04 | 2003-12-30 | Hewlett-Packard Company, L.P. | Low heat loss and small contact area composite electrode for a phase change media memory device |
US6605821B1 (en) | 2002-05-10 | 2003-08-12 | Hewlett-Packard Development Company, L.P. | Phase change material electronic memory structure and method for forming |
US6744088B1 (en) | 2002-12-13 | 2004-06-01 | Intel Corporation | Phase change memory device on a planar composite layer |
CN1542439A (en) * | 2003-11-06 | 2004-11-03 | 同济大学 | Phase transition behavior measurement system for phase transition energy storage material |
JP2007064834A (en) * | 2005-08-31 | 2007-03-15 | Agilent Technol Inc | Device characteristic measuring system |
CN1905077B (en) * | 2006-06-27 | 2013-10-30 | 中国科学院上海微系统与信息技术研究所 | System and method for testing device unit of phase change storage |
KR100759441B1 (en) * | 2006-09-08 | 2007-09-20 | 삼성전자주식회사 | Phase change memory device generating step set current |
-
2008
- 2008-01-07 US US11/970,348 patent/US7639527B2/en not_active Expired - Fee Related
- 2008-01-28 TW TW097103164A patent/TWI365293B/en active
-
2009
- 2009-01-07 CN CN200910001340.5A patent/CN101562050B/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6584589B1 (en) * | 2000-02-04 | 2003-06-24 | Hewlett-Packard Development Company, L.P. | Self-testing of magneto-resistive memory arrays |
US20080198674A1 (en) * | 2007-02-21 | 2008-08-21 | Jan Keller | Method of testing an integrated circuit, method of determining defect resistivity changing cells, testing device, and computer program adapted to perform a method for testing an integrated circuit |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130094276A1 (en) * | 2011-10-18 | 2013-04-18 | Micron Technology, Inc. | Apparatuses and methods for determining stability of a memory cell |
US8787065B2 (en) * | 2011-10-18 | 2014-07-22 | Micron Technology, Inc. | Apparatuses and methods for determining stability of a memory cell |
US10515696B2 (en) | 2011-10-18 | 2019-12-24 | Micron Technology, Inc. | Apparatuses and methods for determining stability of a memory cell |
Also Published As
Publication number | Publication date |
---|---|
CN101562050B (en) | 2012-08-22 |
US7639527B2 (en) | 2009-12-29 |
TWI365293B (en) | 2012-06-01 |
CN101562050A (en) | 2009-10-21 |
TW200933172A (en) | 2009-08-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7639527B2 (en) | Phase change memory dynamic resistance test and manufacturing methods | |
US8809829B2 (en) | Phase change memory having stabilized microstructure and manufacturing method | |
US8374019B2 (en) | Phase change memory with fast write characteristics | |
US8238149B2 (en) | Methods and apparatus for reducing defect bits in phase change memory | |
US7893418B2 (en) | Phase change memory cell having interface structures with essentially equal thermal impedances and manufacturing methods | |
CN101714609B (en) | Chalcogenide material memory device and manufacturing method thereof | |
Ielmini et al. | Recovery and drift dynamics of resistance and threshold voltages in phase-change memories | |
US8158965B2 (en) | Heating center PCRAM structure and methods for making | |
US7701750B2 (en) | Phase change device having two or more substantial amorphous regions in high resistance state | |
US8233311B2 (en) | Variable resistance nonvolatile storage device having a source line formed of parallel wiring layers connected to each other through vias | |
US7696503B2 (en) | Multi-level memory cell having phase change element and asymmetrical thermal boundary | |
US7423300B2 (en) | Single-mask phase change memory element | |
TWI442562B (en) | Methods for reducing recrystallization time for a phase change material | |
TWI437703B (en) | Bipolar switching of phase change device | |
US7527985B2 (en) | Method for manufacturing a resistor random access memory with reduced active area and reduced contact areas | |
Lee et al. | Switching behavior of indium selenide-based phase-change memory cell | |
US20120181499A1 (en) | QUATERNARY GALLIUM TELLURIUM ANTIMONY (M-GaTeSb) BASED PHASE CHANGE MEMORY DEVICES | |
CN102891252A (en) | Ge-rich GST-212 phase change memory materials | |
TWI489475B (en) | Blocking leakage current in a memory array | |
Burr et al. | The inner workings of phase change memory: Lessons from prototype PCM devices | |
TWI453962B (en) | Cram with current flowing laterally relative to axis defined by electrodes | |
TWI711122B (en) | Switching device and memory device | |
US8467238B2 (en) | Dynamic pulse operation for phase change memory | |
Laguna | The Back-End Selector: From material development to device performances | |
Bez et al. | Phase change memory cell concepts and designs |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, MING-HSIU;LAM, CHUNG-HON;RAJENDRAN, BIPIN;REEL/FRAME:020340/0137 Effective date: 20080107 Owner name: MACRONIX INTERNATIONAL CO., LTD., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, MING-HSIU;LAM, CHUNG-HON;RAJENDRAN, BIPIN;REEL/FRAME:020340/0137 Effective date: 20080107 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FEPP | Fee payment procedure |
Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
LAPS | Lapse for failure to pay maintenance fees |
Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20211229 |