US20090179282A1 - Metal gate device with reduced oxidation of a high-k gate dielectric - Google Patents
Metal gate device with reduced oxidation of a high-k gate dielectric Download PDFInfo
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- US20090179282A1 US20090179282A1 US12/353,766 US35376609A US2009179282A1 US 20090179282 A1 US20090179282 A1 US 20090179282A1 US 35376609 A US35376609 A US 35376609A US 2009179282 A1 US2009179282 A1 US 2009179282A1
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 31
- 239000002184 metal Substances 0.000 title claims abstract description 31
- 230000003647 oxidation Effects 0.000 title abstract description 5
- 238000007254 oxidation reaction Methods 0.000 title abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 125000006850 spacer group Chemical group 0.000 claims abstract description 45
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 29
- 239000001301 oxygen Substances 0.000 claims abstract description 29
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 29
- 239000000463 material Substances 0.000 claims description 32
- 239000004065 semiconductor Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 22
- 230000008569 process Effects 0.000 abstract description 15
- 230000015572 biosynthetic process Effects 0.000 abstract description 14
- 238000000137 annealing Methods 0.000 abstract description 7
- 230000004888 barrier function Effects 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 100
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000010926 purge Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 239000007943 implant Substances 0.000 description 4
- 239000002243 precursor Substances 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 229910000951 Aluminide Inorganic materials 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910052726 zirconium Inorganic materials 0.000 description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 229910026551 ZrC Inorganic materials 0.000 description 1
- OTCHGXYCWNXDOA-UHFFFAOYSA-N [C].[Zr] Chemical compound [C].[Zr] OTCHGXYCWNXDOA-UHFFFAOYSA-N 0.000 description 1
- XWCMFHPRATWWFO-UHFFFAOYSA-N [O-2].[Ta+5].[Sc+3].[O-2].[O-2].[O-2] Chemical compound [O-2].[Ta+5].[Sc+3].[O-2].[O-2].[O-2] XWCMFHPRATWWFO-UHFFFAOYSA-N 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- CAVCGVPGBKGDTG-UHFFFAOYSA-N alumanylidynemethyl(alumanylidynemethylalumanylidenemethylidene)alumane Chemical compound [Al]#C[Al]=C=[Al]C#[Al] CAVCGVPGBKGDTG-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- VKJLWXGJGDEGSO-UHFFFAOYSA-N barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[Ti+4].[Ba+2] VKJLWXGJGDEGSO-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- -1 e.g. Inorganic materials 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- WHJFNYXPKGDKBB-UHFFFAOYSA-N hafnium;methane Chemical compound C.[Hf] WHJFNYXPKGDKBB-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- JQJCSZOEVBFDKO-UHFFFAOYSA-N lead zinc Chemical compound [Zn].[Pb] JQJCSZOEVBFDKO-UHFFFAOYSA-N 0.000 description 1
- 150000001247 metal acetylides Chemical class 0.000 description 1
- 229910001510 metal chloride Inorganic materials 0.000 description 1
- 229910001507 metal halide Inorganic materials 0.000 description 1
- 150000005309 metal halides Chemical class 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- VYIRVGYSUZPNLF-UHFFFAOYSA-N n-(tert-butylamino)silyl-2-methylpropan-2-amine Chemical compound CC(C)(C)N[SiH2]NC(C)(C)C VYIRVGYSUZPNLF-UHFFFAOYSA-N 0.000 description 1
- 230000006855 networking Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 150000002902 organometallic compounds Chemical class 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- KJXBRHIPHIVJCS-UHFFFAOYSA-N oxo(oxoalumanyloxy)lanthanum Chemical compound O=[Al]O[La]=O KJXBRHIPHIVJCS-UHFFFAOYSA-N 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 1
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 1
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000003826 tablet Substances 0.000 description 1
- 229910003468 tantalcarbide Inorganic materials 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- MTPVUVINMAGMJL-UHFFFAOYSA-N trimethyl(1,1,2,2,2-pentafluoroethyl)silane Chemical compound C[Si](C)(C)C(F)(F)C(F)(F)F MTPVUVINMAGMJL-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
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- H—ELECTRICITY
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
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- H—ELECTRICITY
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
- H01L21/2652—Through-implantation
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
Abstract
Description
- This application is a divisional of U.S. patent application Ser. No. 11/158,621, filed Jun. 21, 2005, entitled “METAL GATE DEVICE WITH REDUCED OXIDATION OF A HIGH-K GATE DIELECTRIC” the entire contents of which are hereby incorporated by reference herein.
- 1. Background of the Invention
- MOS field-effect transistors with very thin silicon dioxide based gate dielectrics may experience unacceptable gate leakage currents. Forming the gate dielectric from certain high-k dielectric materials, instead of silicon dioxide, can reduce gate leakage. When conventional processes are used to form such transistors, a silicon dioxide transition layer may form between the high-k dielectric and the substrate. The presence of that transition layer may unfavorably contribute to the overall electrical thickness of the gate dielectric stack.
-
FIG. 1 is a cross sectional side view that illustrates the semiconductor device of one embodiment of the present invention. -
FIG. 2 is a cross sectional side view that illustrates additional regions added to the substrate in some embodiments. -
FIG. 3 is a cross sectional side view that illustrates the capping layer deposited on the top surface of the gate stack, the first set of spacers and the substrate. -
FIG. 4 is a cross sectional side view that illustrates a second set of spacers formed on either side of the gate electrode. -
FIGS. 5 a and 5 b are cross sectional side views that illustrate the formation of source/drain implant regions. -
FIG. 6 is a cross sectional side view that illustrates the device ofFIG. 5 a after annealing of the source/drain implanted regions. -
FIG. 7 is a cross sectional side view that illustrates the device after removal of portions of the capping layer. -
FIG. 8 is a flow chart that summarizes a method according to an embodiment of the present invention. -
FIG. 9 illustrates a system in accordance with one embodiment of the present invention. - In various embodiments, an apparatus and method relating to the formation of a substrate are described. In the following description, various embodiments will be described. However, one skilled in the relevant art will recognize that the various embodiments may be practiced without one or more of the specific details, or with other replacement and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of various embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials, and configurations are set forth in order to provide a thorough understanding of the invention. Nevertheless, the invention may be practiced without specific details. Furthermore, it is understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
- Reference throughout this specification to “one embodiment” or “an Embodiment” means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention, but do not denote that they are present in every embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments. Various additional layers and/or structures may be included and/or described features may be omitted in other embodiments.
- Various operations will be described as multiple discrete operations in turn, in a manner that is most helpful in understanding the invention. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.
-
FIG. 1 is a cross sectional side view that illustrates the semiconductor device of one embodiment of the present invention. In that semiconductor device, a high-k gatedielectric layer 102 may be formed onsubstrate 100, and ametal gate electrode 104 may be formed on the high-k gatedielectric layer 102. In the illustrated embodiment, there is aconductive gate layer 108, which may comprise doped polysilicon, on themetal gate electrode 104, although in other embodiments, themetal gate electrode 104 may extend higher and the device may lack a doped polysilicon or otherconductive gate layer 108 on the metal gate electrode. -
Substrate 100 may comprise any material that may serve as a foundation upon which a semiconductor device may be built. In this embodiment,substrate 100 is a silicon containing substrate. Thesubstrate 100 may be abulk substrate 100, such as a wafer of single crystal silicon, a silicon-on-insulator (SOI)substrate 100, such as a layer of silicon on a layer of insulating material on another layer of silicon, or another type ofsubstrate 100. The device formed on thesubstrate 100 may be a transistor in some embodiments. The device may be a planar transistor on abulk substrate 100, a planar transistor on anSOI substrate 100, a FIN-FET transistor on abulk substrate 100, a FIN-FET transistor on anSOI substrate 100, a tri-gate transistor on abulk substrate 100, a tri-gate transistor on an SOI substrate, or another type of transistor or other device. - The high-k gate
dielectric layer 102 may comprise, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. Although a few examples of materials that may be used to form the high-k gatedielectric layer 102 are described here, the high-k gatedielectric layer 102 may be made from other materials that serve to reduce gate leakage in other embodiments. - In one embodiment of the present invention, high-k gate
dielectric layer 102 may be formed on thesubstrate 100 by an atomic layer chemical vapor deposition (“ALCVD”) process. In an ALCVD process, a growth cycle may be repeated until a high-k gatedielectric layer 102 of a desired thickness is created. Such a growth cycle may comprise the following sequence in an embodiment. Steam is introduced into a CVD reactor for a selected pulse time, followed by a purging gas. A precursor (e.g., an organometallic compound, a metal chloride or other metal halide) is then pulsed into the reactor, followed by a second purge pulse. (A carrier gas that comprises nitrogen or another inert gas may be injected into the reactor at the same time.) - While operating the reactor at a selected pressure and maintaining the substrate at a selected temperature, steam, the purging gas, and the precursor are, in turn, fed at selected flow rates into the reactor. By repeating this growth cycle—steam, purging gas, precursor, and purging gas—multiple times, one may create a high-k gate
dielectric layer 102 of a desired thickness on thesubstrate 100. The pressure at which the reactor is operated, the gases' flow rates, and the temperature at which the substrate is maintained may be varied depending upon the application and the precursor that is used. The CVD reactor may be operated long enough to form the high-k gatedielectric layer 102 with the desired thickness. In some embodiments, the high-k gatedielectric layer 102 may be less than about 40 angstroms thick. In other embodiments, the high-k gatedielectric layer 102 may be between about 5 angstroms and about 20 angstroms thick. - The high-k gate
dielectric layer 102 may have a k-value higher than about 7.5 in some embodiments. In other embodiments, the high-k gatedielectric layer 102 may have a k-value higher than about 10. In other embodiments, the high-k gatedielectric layer 102 may comprise a material such as Al2O3 with a k-value of about 12, or may comprise a material with a higher k-value than that. In other embodiments, the high-k gatedielectric layer 102 may have a k-value between about 15 and about 25, e.g. HfO2. In yet other embodiments, the high-k gatedielectric layer 102 may have a k-value even higher, such as 35, 80 or even higher. - After forming the high-k gate
dielectric layer 102 on thesubstrate 100, themetal gate electrode 104 may be formed on the high-k gatedielectric layer 102.Metal gate electrode 104 may be formed using conventional metal deposition processes, e.g. CVD or PVD processes, by using ALCVD, or another suitable method, and may comprise any conductive material from which metal gate electrodes may be derived. Materials that may be used to form n-type metal gate electrodes include: hafnium, zirconium, titanium, tantalum, aluminum, their alloys (e.g., metal carbides that include these elements, i.e., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and aluminides (e.g., an aluminide that comprises hafnium, zirconium, titanium, tantalum, or tungsten). Materials for forming p-type metal gate electrodes include: ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. Alternatively, a mid-gap metal gate material, e.g. stoichiometric titanium nitride or tantalum nitride, may be used in some embodiments. - In some embodiments, metal NMOS gate electrodes may have a workfunction that is between about 3.9 eV and about 4.2 eV. In some embodiments, metal PMOS gate electrodes may have a workfunction that is between about 4.9 eV and about 5.2 eV. A
metal gate electrode 104 that is formed on a high-kgate dielectric layer 102 may consist essentially of a homogeneous metal layer. Alternatively, relatively thin n-type or p-type metal layers (like those listed above) may generate the lower part of the metal gate electrode, with the remainder of the metal gate electrode comprising another metal or metals, e.g., a metal that may be easily polished like tungsten, aluminum, titanium, or titanium nitride. Although a few examples of materials for forming a metal gate electrode are identified here, such a component may be made from many other materials, as will be apparent to those skilled in the art. - Additionally, while device may be an NMOS or PMOS device, other types of devices may be made within the scope of the present invention as well. For example, a silicon on insulator (SOI) or other type of device may be made with mid-gap gate electrode materials, e.g. stoichiometric titanium nitride or tantalum nitride, among other materials, rather than NMOS or PMOS gate electrode materials. In some embodiments, the material of the
mid-gap gate electrode 104 may have a workfunction between the workfunctions of NMOS and PMOS gate electrode materials - There may be a set of
first spacers 106 formed on either side of thegate electrode 104, high-kgate dielectric layer 102, andconductive gate layer 108. Thespacers 106 may be formed of a material that is substantially free of oxygen in some embodiments. For example, in an embodiment the set offirst spacers 106 may comprise a carbon doped nitride, with 8-12% carbon and silicon nitride. In other embodiments, the set offirst spacers 106 may comprise other materials. - In an embodiment, the device may be a transistor. There may be a
thin oxide layer 110 on thesubstrate 100 beneath thegate stack spacers 106 in some embodiments. Thisthin oxide layer 110 may be as thin as a monolayer of oxide in some embodiments. Thethin oxide layer 110 may provide a potential path for oxygen to travel from an outer edge of the first set ofspacers 106 furthest from thegate stack gate stack substrate 100 to form an unwanted thicker oxide beneath thegate stack -
FIG. 2 is a cross sectional side view that illustratesadditional regions 202 added to thesubstrate 100 in some embodiments. Theadditional regions 202 may be added in some embodiments but omitted in other embodiments. For example, when the device is a Fin-FET transistor or tri-gate transistor, there may be only a small amount of substrate on either side of thegate stack substrate 100 by forming theadditional regions 202. In some embodiments, theadditional regions 202 may be added by epitaxy. In an embodiment, theadditional regions 202 may comprise the same material as theoriginal substrate 100. Theadditional regions 202 may be considered portions of thesubstrate 100 after formation of theadditional regions 202. As shown inFIG. 2 , theadditional regions 202 may have a height above the original substrate 100 a distance away from the first set ofspacers 106, but the thickness of theadditional regions 202 may decrease closer to the first set ofspacers 106. In some embodiments, such as when the device is a planar transistor, theadditional regions 202 may be omitted. -
FIG. 3 is a cross sectional side view that illustrates cappinglayer 302 deposited on the top surface of thegate stack spacers 106 and the substrate, according to one embodiment of the present invention. In an embodiment, thecapping layer 302 may be anoxygen barrier layer 302 that at least partially, if not completely, prevents oxygen from reaching aregion 304 beneath thegate stack capping layer 302 may seal thethin oxide layer 110 from oxygen-containing structures and/or ambient oxygen in further process steps, so may prevent the transport of oxygen by thethin oxide layer 110 into theregion 304 beneath thegate stack gate stack substrate 100, which could result in the formation of undesired oxide, such as silicon oxide, beneath thegate stack capping layer 302 may be less than about 75 angstroms thick. In another embodiment, thecapping layer 302 may be about 50 angstroms thick or less. In an embodiment, the capping oroxygen barrier layer 302 may comprise a nitride material, such as a carbon doped nitride, a stoichiometric silicon nitride deposited in a low O2-push fashion or a silicon carbide, although other materials may be used in other embodiments. Thecapping layer 302 may be substantially free from oxygen, so as not to serve as a source of oxygen that could be transported by the thin oxide layer to theregion 304 beneath thegate stack capping layer 302 may be a conformal layer that covers the exposed surfaces of the device. In an embodiment, the capping oroxygen barrier layer 302 may be deposited by chemical or physical vapor deposition, although atomic layer deposition or other methods may be used as appropriate. The formation of thecapping layer 302 may be performed in an ambient atmosphere with little or no oxygen. -
FIG. 4 is a cross sectional side view that illustrates a second set ofspacers 402 formed on either side of thegate electrode 104, according to one embodiment. In an embodiment, the second set ofspacers 402 may be formed by depositing a thick layer of material over the device, then etching portions of the layer away to form the second set ofspacers 402. In an embodiment, the second set ofspacers 402 may comprise an oxygen-containing material such as a Bis(tert-butylamino)silane-based silicon oxide, a silicon oxynitride, or another material, depending on the need to subsequently recess said second spacers following the self-aligned source/drain implant described below. As thecapping layer 302 may seal the thin layer ofoxide 110 away from the layer of material used to make the second set ofspacers 402, the material used to make the second set ofspacers 402 may contain oxygen; thecapping layer 302 may prevent transport of oxygen from the material of the second set ofspacers 402 to theregion 304 beneath thegate stack thicker oxide layer 110. -
FIG. 5 a is a cross sectional side view that illustrates the formation of source/drain implant regions 504 by implantation ofions 502, as is known in the art. In the illustrated embodiment, theions 502 are implanted into thesubstrate 100 to form the source/drain implantedregions 504 through thecapping layer 302 on thesubstrate 100. -
FIG. 5 b is a cross sectional side view that illustrates another embodiment of the formation of source/drain implant regions 504 by implantation ofions 502, as is known in the art. In the illustrated embodiment, portions of thecapping layer 302 beyond the second set ofspacers 402 have been removed prior to ion implantation. Theions 502 are implanted into thesubstrate 100 to form the source/drain implantedregions 504 without being implanted through thecapping layer 302 on thesubstrate 100. The remaining portions of thecapping layer 302 may be sufficient to seal thethin oxide layer 110 from oxygen present in structures of the device and present in the ambient atmosphere during further processing. Thus, as shown inFIGS. 5 a and 5 b, portions of thecapping layer 302 that do not function to seal the thin oxide layer from sources of oxygen may be removed at various times during formation of the device in various embodiments. -
FIG. 6 is a cross sectional side view that illustrates the device ofFIG. 5 a after annealing of the source/drain implantedregions 504 have been performed to form source and drain regions in thesubstrate 100, as is known in the art. The annealing process may be a high temperature annealing process. During the annealing process, thecapping layer 302 may help prevent formation of an oxide under thegate electrode 104. Absent thecapping layer 302, the high temperature of the annealing process may cause rapid formation of a thick layer of oxide beneath thegate stack -
FIG. 7 is a cross sectional side view that illustrates the device after removal of portions of thecapping layer 302 that are exposed and not covered by the second set ofspacers 402. The removal may be done by a wet etching process in one embodiment, although any suitable process may be used to remove the exposed portions of thecapping layer 302. As stated above, this removal of portions of thecapping layer 302 may be done at other times during processing of the device rather than following anneal. Following anneal and removal of portions of thecapping layer 302, additional steps such as silicidation may be performed to finish fabricating the device. -
FIG. 8 is aflow chart 800 that summarizes a method according to an embodiment of the present invention. A gate stack of a device, such asgate stack FIG. 1 , may be formed 802. A capping layer, such ascapping layer 302 ofFIG. 3 , may be formed 804, sealing a region under the gate stack from oxygen. For example,region 304 ofFIG. 3 is sealed by cappinglayer 302 to prevent oxygen from being transported by thethin oxide layer 110 under thegate stack capping layer 302, oxygen may be mostly or entirely prevented from being transported to the under gate region during these processes. Thus, reaction of oxygen with the substrate beneath the gate and formation of a thick oxide layer beneath the gate may be avoided, which may prevent degradation of the performance of the device. -
FIG. 9 illustrates asystem 900 in accordance with one embodiment of the present invention. One or more devices formed with thecapping layer 302 as described above may be included in thesystem 900 ofFIG. 9 . As illustrated, for the embodiment,system 900 includes acomputing device 902 for processing data.Computing device 902 may include amotherboard 904. Coupled to or part of themotherboard 904 may be in particular aprocessor 906, and anetworking interface 908 coupled to abus 910. A chipset may form part or all of thebus 910. Theprocessor 906, chipset, and/or other parts of thesystem 900 may include one or more devices with thecapping layer 302. - Depending on the applications,
system 900 may include other components, including but are not limited to volatile andnon-volatile memory 912, a graphics processor (integrated with themotherboard 904 or connected to the motherboard as a separate removable component such as an AGP or PCI-E graphics processor), a digital signal processor, a crypto processor, mass storage 914 (such as hard disk, compact disk (CD), digital versatile disk (DVD) and so forth), input and/oroutput devices 916, and so forth. - In various embodiments,
system 900 may be a personal digital assistant (PDA), a mobile phone, a tablet computing device, a laptop computing device, a desktop computing device, a set-top box, an entertainment control unit, a digital camera, a digital video recorder, a CD player, a DVD player, or other digital device of the like. - Any of one or more of the
components FIG. 9 may include one or more devices with thecapping layer 302 as described herein. For example, a transistor formed with thecapping layer 302 may be part of theCPU 906,motherboard 904, graphics processor, digital signal processor, or other devices. - In an embodiment, the device may be a semiconductor device including a substrate, a thin oxide layer on the substrate, a high-k gate dielectric layer on the thin oxide layer, a metal gate electrode on the high-k gate dielectric layer, and a capping layer that is substantially free of oxygen and substantially seals the thin oxide layer from structures that comprise oxygen. The device may also have a first set of spacers on either side of the metal gate electrode and a second set of spacers on either side of the first set of spacers, wherein the capping layer is between the first set of spacers and the second set of spacers. The second set of spacers may have a bottom surface and the capping layer may extend beneath the bottom surface of the second set of spacers. The first set of spacers may have a bottom surface and the thin oxide layer may extend beneath the bottom surface of the first set of spacers. The capping layer may be on the sides of the first set of spacers and may be on the substrate extending away from the sides of the first set of spacers for a distance.
- The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. This description and the claims following include terms, such as left, right, top, bottom, over, under, upper, lower, first, second, etc. that are used for descriptive purposes only and are not to be construed as limiting. For example, terms designating relative vertical position refer to a situation where a device side (or active surface) of a substrate or integrated circuit is the “top” surface of that substrate; the substrate may actually be in any orientation so that a “top” side of a substrate may be lower than the “bottom” side in a standard terrestrial frame of reference and still fall within the meaning of the term “top.” The term “on” as used herein (including in the claims) does not indicate that a first layer “on” a second layer is directly on and in immediate contact with the second layer unless such is specifically stated; there may be a third layer or other structure between the first layer and the second layer on the first layer. The embodiments of a device or article described herein can be manufactured, used, or shipped in a number of positions and orientations. Persons skilled in the relevant art can appreciate that many modifications and variations are possible in light of the above teaching. Persons skilled in the art will recognize various equivalent combinations and substitutions for various components shown in the Figures. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.
Claims (8)
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US12/353,766 US20090179282A1 (en) | 2005-06-21 | 2009-01-14 | Metal gate device with reduced oxidation of a high-k gate dielectric |
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US20150132912A1 (en) * | 2011-11-10 | 2015-05-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for fabricating fin field effect transistors |
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US20060284271A1 (en) | 2006-12-21 |
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