US20090206377A1 - Method and device for reducing crosstalk in back illuminated imagers - Google Patents
Method and device for reducing crosstalk in back illuminated imagers Download PDFInfo
- Publication number
- US20090206377A1 US20090206377A1 US12/132,721 US13272108A US2009206377A1 US 20090206377 A1 US20090206377 A1 US 20090206377A1 US 13272108 A US13272108 A US 13272108A US 2009206377 A1 US2009206377 A1 US 2009206377A1
- Authority
- US
- United States
- Prior art keywords
- layer
- epitaxial layer
- electrical
- seed layer
- interface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 76
- 230000004888 barrier function Effects 0.000 claims abstract description 54
- 239000012212 insulator Substances 0.000 claims abstract description 49
- 230000003287 optical effect Effects 0.000 claims abstract description 39
- 239000002019 doping agent Substances 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 239000002800 charge carrier Substances 0.000 claims abstract description 18
- 230000007423 decrease Effects 0.000 claims abstract description 7
- 238000003384 imaging method Methods 0.000 claims description 25
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 239000010703 silicon Substances 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 17
- 239000012777 electrically insulating material Substances 0.000 claims description 13
- 238000011049 filling Methods 0.000 claims description 9
- 238000000206 photolithography Methods 0.000 claims description 8
- 208000012868 Overgrowth Diseases 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 230000003213 activating effect Effects 0.000 claims 2
- 238000001312 dry etching Methods 0.000 claims 1
- 238000001039 wet etching Methods 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 22
- 238000002955 isolation Methods 0.000 description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 18
- 238000004519 manufacturing process Methods 0.000 description 12
- 239000007943 implant Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 230000005693 optoelectronics Effects 0.000 description 3
- 230000035945 sensitivity Effects 0.000 description 3
- 238000011282 treatment Methods 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000003667 anti-reflective effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005670 electromagnetic radiation Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1464—Back illuminated imager structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14687—Wafer level processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14689—MOS based technologies
Definitions
- the present invention relates generally to imagers, and more particularly, to a method and resulting device for reducing crosstalk in back illuminated imagers.
- CMOS or CCD image sensors are of interest in a wide variety of sensing and imaging applications in a wide range of fields including consumer, commercial, industrial, and space electronics.
- Imagers based on charge coupled devices (CCDs) are currently the most widely utilized.
- CCDs are employed either in front or back illuminated configurations.
- Front illuminated CCD imagers are more cost effective to manufacture than back illuminated CCD imagers such that front illuminated devices dominate the consumer imaging market.
- Front-illuminated imagers have significant performance limitations such as low fill factor/low sensitivity.
- the problem of low fill factor/low sensitivity is typically due to shadowing caused by the presence of opaque metal bus lines, and absorption by an array circuitry structure formed on the front surface in the pixel region of a front-illuminated imager.
- the active region of a pixel is typically relatively small (low fill factor) in large format (high-resolution) front-illuminated imagers.
- Back-illuminated semiconductor (CCD and CMOS) imaging devices are advantageous over front-illuminated imagers for high fill factor, better overall efficiency of charge carrier generation and collection, and are suitable for small pixel arrays.
- Fabrication of thinned back illuminated imagers has several challenges.
- One challenge is the loss of charge carriers near the back surface due to inherent dangling bonds present at the silicon back surface, which reduces Quantum Efficiency (QE) if the backside of the thinned imager is not pinned. Eliminating this problem requires additional treatment at the backside of the device, which adds to the complexity of the fabrication process.
- QE Quantum Efficiency
- a second challenge is absorption of charge carriers within the epitaxial layer, which prevents charge carriers from reaching processing components on the front side, which reduces sensitivity and efficiency of the device.
- photon radiation that enters the backside of the imagers generates charge carriers in the silicon epitaxial layer.
- the location of the charge generation in the epitaxial layer depends on the absorption length of the incident photon, which in turn depends on its wavelength.
- Photons with longer wavelengths, such as red penetrate deeper into the epitaxial layer as compared to shorter wavelengths, such as blue.
- To generate maximum charge carriers from all the incident photons of different wavelengths requires an appropriate thickness for the epitaxial layer.
- charge carriers generated near the back side of the imager should be driven to the front side as quickly as possible in order to avoid horizontal drift of carriers into adjacent pixels, which may smear an image.
- Additional challenges include excessive thinning of wafers, which poses yield issues such as stress in the thinned wafer, and uniformity of thickness, etc. Fabrication cost of back illuminated imagers can be higher than for front illuminated imagers due to thinning and backside treatment.
- the '583 Patent a thin semiconductor seed layer is supported by an ultra-thin substrate and an insulator layer made of an electrically insulating material such as silicon dioxide.
- An epitaxial layer may be grown substantially overlying the seed layer to an appropriate thickness to accommodate devices that are to operate at wavelengths from less than 100 nanometers (deep ultraviolet) to more than 3000 nanometers (far infrared).
- a method and resulting device for reducing crosstalk in a back-illuminated imager comprising providing a substrate comprising an insulator layer and a seed layer substantially overlying the insulator layer, an interface being formed where the seed layer comes in contact with the insulator layer; forming an epitaxial layer substantially overlying the seed layer, the epitaxial layer defining plurality of pixel regions, each pixel region outlining a collection well for collecting charge carriers; and forming one of an electrical, optical, and electrical and optical barrier about the outlined collection well extending into the epitaxial layer to the interface between the seed layer and the insulator layer.
- the seed layer and the epitaxial layer of the device have a net dopant concentration profile which has an initial maximum value at an interface of the seed layer and the insulator layer and which decreases monotonically with increasing distance from the interface within an initial portion of the semiconductor substrate and the epitaxial layer.
- At least one imaging component is formed at least partially overlying and extending into the epitaxial layer.
- a plurality of alignment keys are formed substantially overlying the epitaxial layer.
- the electrical barrier can be formed about the outlined collection well using implanted dopants; an etched trench filled with an electrically insulating material; a combination of implanted dopants and an etched trench filled with an electrically insulating material.
- An electrical/optical barrier can be formed by filling trenches with an electrically insulating material about outlined collection wells, opening trenches about the inner filled trenches, and filling the outer trenches with dopants.
- a method for reducing crosstalk in a back-illuminated imager includes the steps of providing a substrate comprising an insulator layer and a seed layer substantially overlying the insulator layer, an interface being formed where the seed layer comes in contact with the insulator layer; defining pixel regions in the seed layers each pixel region outlining a collection well for collecting charge carriers; depositing an electrically insulating layer substantially overlying the seed layer; patterning the electrically insulating layer such that it forms a ring about location of the outlined collection well; and growing an the epitaxial layer substantially about the seed layer and the ring using an epitaxial lateral overgrowth (ELO) technique.
- ELO epitaxial lateral overgrowth
- the seed layer and the epitaxial layer of the device have a net dopant concentration profile which has an initial maximum value at the interface of the seed layer and the insulator layer and which decreases monotonically with increasing distance from an interface within an initial portion of the semiconductor substrate and the epitaxial layer.
- FIG. 1A is a perspective view of a back-illuminated imager that reduces crosstalk, constructed according to an embodiment of the present invention
- FIG. 1B is a top down view of a portion of FIG. 1 , showing electrical/optical barriers forming rings about pixel collection wells;
- FIG. 2 shows a side view and top down view of the alignment keys formed in the epitaxial layer, according to an embodiment of the present invention
- FIG. 3 shows a cross-section of an imager having a plurality of isolation barriers formed therein by means of implanted dopants, according to an embodiment of the present invention
- FIG. 4 is a flow diagram of a method for forming isolation barriers made from high energy implants according to the embodiment of FIG. 3 ;
- FIG. 5 shows a cross-section of an imager having a plurality of isolation barriers formed therein by means of oxide trenches, according to an embodiment of the present invention
- FIG. 6 is a flow diagram of a method for forming isolation barriers made from oxide trenches according to the embodiment of FIG. 5 ;
- FIG. 7 shows a cross-section of an imager having a plurality of isolation barriers formed therein by means of both oxide trenches and high energy implants, according to an embodiment of the present invention
- FIG. 8 is a flow diagram of a method for forming isolation barriers made from oxide trenches and high energy implants according to the embodiment of FIG. 7 ;
- FIG. 9 shows a cross-sections of an imager having a plurality of isolation barriers formed as rings about collection well regions from oxide “pillars”, according to an embodiment of the present invention.
- FIG. 10 shows a cross section of the imager of FIG. 9 with an epitaxial layer grown substantially about the pillars using an epitaxial lateral overgrowth (ELO) technique;
- ELO epitaxial lateral overgrowth
- FIG. 11 is a flow diagram of a method for forming isolation barriers made from oxide pillars using an ELO technique according to the embodiment of FIGS. 9 and 10 ;
- FIG. 12 shows a cross-section of an imager having a plurality of trenches formed therein that are filled with both an electrical barrier of oxide and an optically opaque material”, according to an embodiment of the present invention.
- FIG. 13 is a flow diagram of a method for forming isolation barriers made from oxide and an optically opaque material according to the embodiment of FIG. 12 .
- the imager 10 may include an initial substrate 12 , sometimes referred to in the art as a semiconductor-on-insulator (SOI) substrate, which is composed of handle wafer 14 to provide mechanical support during processing, an insulator layer 16 (buried oxide layer), and seed layer 18 .
- the handle wafer 14 may be a standard silicon wafer used in fabricating integrated circuits. Alternatively, the handle wafer 14 may be any sufficiently rigid substrate composed of a material which is compatible with the steps of the method disclosed herein. The handle wafer, at later processing steps, can be removed completely.
- Insulator layer 16 may comprise an oxide of silicon with a thickness ranging up to 1 micrometer. Among other embodiments, the thickness of insulator layer 16 may fall in a range from about 10 nm to about 5000 nm. If the handle wafer 14 is completely remove, the insulator layer 16 may also be thinned to produce an anti-reflective layer. Seed layer 18 may be comprised of crystalline silicon having a thickness from about 5 nanometers to about 100 nanometers.
- SOI substrates are available commercially and are manufactured by various known methods.
- thermal silicon oxide is grown on silicon wafers. Two such wafers are joined with oxidized faces in contact and raised to a high temperature.
- an electric potential difference is applied across the two wafers and the oxides. The effect of these treatments is to cause the oxide layers on the two wafers to flow into each other, forming a monolithic bond between the wafers.
- the silicon on one side is lapped and polished to the desired thickness of seed layer 18 , while the silicon on the opposite side of the oxide forms handle wafer 14 .
- the oxide forms insulator layer 16 .
- Another method of fabricating an SOI substrate begins with obtaining a more standard semiconductor-on-insulator (SOI) wafer in which the seed layer 18 has a thickness in the range from about 100 nm to about 1000 nm.
- a thermal oxide is grown on the semiconductor substrate, using known methods. As the oxide layer grows, semiconductor material of the semiconductor substrate is consumed. Then the oxide layer is selectively etched off, leaving a thinned semiconductor substrate having a desired seed layer thickness.
- SOI substrates manufactured by an alternative method known as Smart Cut.TM., are sold by Soitec, S.A.
- Seed layer 18 may comprise silicon (Si), Germanium (Ge), SiGe alloy, a III-V semiconductor, a II-VI semiconductor, or any other semiconductor material suitable for the fabrication of optoelectronic devices.
- An epitaxial layer 20 is formed on the seed layer 18 , using seed layer 18 as the template.
- epitaxial layer 20 may comprise silicon (Si), Germanium (Ge), SiGe alloy, a III-V semiconductor, a II-VI semiconductor, or any other semiconductor material suitable for the fabrication of optoelectronic devices.
- Epitaxial layer 20 may have a thickness from about 1 micrometer to about 50 micrometers. The resistivity of the epitaxial layer 20 can be controlled by controlling the epitaxial growth process.
- alignment keys 22 are printed on and etched into the epitaxial layer 20 .
- the alignment keys 22 can be used to align subsequent layers during the imager fabrication process. The use of alignment keys can result in highly accurate alignment of about 0.1 micrometer or less for subsequently deposited layers.
- key patterns 24 are printed on a top portion 26 of the epitaxial layer 20 .
- a trench plasma etch process can be used to etch the underlying epitaxial layer 20 below the key patterns 24 until the etched away silicon is stopped by the underlying insulator/buried oxide layer 16 .
- the open trenches 28 are then filled with an electrically insulating material such as an oxide of silicon, silicon carbide, silicon nitride, or poly-silicon.
- one or more imaging structures 30 may be fabricated on the epitaxial layer 20 .
- These imaging structures 30 may include charge-coupled device (CCD) components, CMOS imaging components, photodiodes, avalanche photodiodes, phototransistors, or other optoelectronic devices, in any combination. Also included may be other electronic components such as CMOS transistors, bipolar transistors, capacitors, or resistors (not shown).
- the insulator layer 16 can be thinned to a desired thickness such that it acts as an anti-reflective layer to a desired incoming wavelength of light. Alternatively, the insulating layer 16 can also be removed completely, and another suitable material can be deposited on the remaining epitaxial layer 20 which can be of a desired thickness so as to act as an anti-reflective coating/layer.
- Optical components (not shown) can be bonded to the back side of the imager 10 using the alignment keys 22 as precision guides. The one or more optical components can comprise color filters and micro-lenses to produce wavelength dependent signals.
- one of electrical, optical, and electrical and optical barriers 32 are formed in the epitaxial layer 20 about the collection wells 34 of each of the pixels 36 comprising the imager 10 .
- Each of the collection wells 34 and barriers 32 are separated from each other by regions 37 where the transfer/readout circuit elements belonging to the imaging structures 30 are fabricated.
- the barriers 32 preferably extend vertically from about the top surface 35 of the epitaxial layer down to the surface 38 , 39 of one of the seed layer 18 and the insulator layer 16 , respectively.
- the barriers 32 may be formed by one of several techniques and of several types of materials to be described hereinbelow.
- FIG. 3 shows a cross-section of an imager 40 having a plurality of isolation barriers formed therein by means of implanted dopants.
- the high-energy implants 42 are formed from available techniques in the fabrication industry. Today's high-energy (on the order of MeV) implanters are capable of implanting species in the range of 2-10 um deep into silicon. Referring now to FIGS. 1-4 , a method 50 for forming isolation barriers made from high energy implants is described as follows:
- an SOI wafer 12 which has a thin Si seed layer 18 is provided.
- an epitaxial layer 20 with a desired thickness (2-10 um) and resistivity is grown on the seed layer 18 .
- the doping profile of the epitaxial layer 20 is engineered according to the technique described in the '583 Patent.
- alignment keys 22 are formed in the epitaxial layer 20 .
- Sub-steps include printing alignment keys on the epitaxial layer 20 using photolithography; trench etching the epitaxial layer 20 ; and filling the trenches with an electrically insulating material, such as an oxide (preferably of silicon).
- boundary rings are defined about the collecting wells of the pixels using photolithography and with the aid of the alignment keys formed earlier.
- appropriate dopant species are implanted at the locations of the boundary rings around collecting wells such that the dopants reach down to the interface between the insulator layer 16 and the seed layer 18 .
- the high energy implants can be formed by ion implanting p-type impurities into a p-type epitaxial layer (and likewise n-type impurities for an n-type epitaxial layer).
- the dopants can be thermally activated.
- imaging structures 30 are formed overlying the epitaxial layer 20 .
- the dopants can be activated by processes such as rapid thermal annealing so that the diffusion can be minimized.
- the dopants, once activated, provide an electrical isolation barrier such that carriers generated inside a collecting well will not diffuse into adjacent pixels.
- FIG. 5 shows a cross-section of an imager 64 having a plurality of isolation barriers formed therein by means of oxide trenches.
- the oxide trenches 66 being insulators, act as electrical barriers to generated charge carriers and confine them within pixel collecting wells.
- One advantage of this method is that the barrier trenches 66 can be defined along with the alignment keys, eliminating the need for another photo mask. Referring now to FIGS. 1-2 , 5 and 6 , a method 68 for forming isolation barriers made from oxide trenches is described as follows:
- an SOI wafer 12 which has a thin Si seed layer 18 is provided.
- an epitaxial layer 20 with a desired thickness (2-10 um) and resistivity is grown on the seed layer 18 .
- the doping profile of the epitaxial layer 20 is engineered according to the technique described in the '583 Patent.
- trench outlines are formed about collection wells collecting along with alignment keys 22 on the surface of the epitaxial layer 20 using photolithography.
- the epitaxial layer 20 is trench etched down to the buried oxide (insulation) layer 16 .
- the trenches 22 , 66 are filled with an electrically insulating material such as an oxide of silicon.
- the tops of the trenches 22 , 66 are planarized.
- imaging structures 30 are formed overlying the epitaxial layer 20 .
- the trench etch step may result in unnecessary traps at the interfaces between epitaxial layer silicon and trench filled oxide.
- the number traps can be reduced by thermal annealing.
- FIG. 7 shows a cross-sectional of all imager 84 having a plurality of isolation barriers 86 formed therein by means of both oxide trenches 88 and high energy implants 90 , thereby combining methods 1 and 2 by creating oxide trenches and implanting dopants around those trenches.
- a method 92 for forming isolation barriers made from oxide trenches and high energy implants is described as follows:
- the method 92 begins by performing steps 70 to 80 of the method 68 to create oxide trenches and alignment keys.
- steps 94 regions about each of the filled trenches are opened down to the oxide layer 18 , and at step 96 , the regions are implanted with high energy dopants, the dopants being thermally activated thereupon.
- imaging structures 30 are formed overlying the epitaxial layer 20 . Since the oxide trenches are encapsulated by dopants, the electrical barrier due to the dopants can reduce the effect of traps at the interface between the high energy dopants and the epitaxial silicon.
- FIGS. 9 and 10 show cross-sections of an imager 98 having a plurality of isolation barriers comprising oxide “pillars” 102 formed as rings about collection wells with an epitaxial layer 106 grown substantially about the pillars 102 using an epitaxial lateral overgrowth (ELO) technique.
- This technique completely eliminates traps created in a trench process.
- a method 108 for forming isolation barriers made from oxide pillars and using an ELO technique to grow an epitaxial layer is described as follows:
- an SOI wafer 12 which has a thin Si seed layer 18 is provided.
- an electrically insulating layer such as a layer of an oxide of silicon (not shown) is deposited substantially overlying the seed layer 18 , the thickness of the oxide layer (about 2-10 um) being substantially similar to a final desired final epitaxial layer thickness.
- the oxide layer is patterned such that it forms rings about collecting wells (not shown), and also forms alignment keys 104 .
- the oxide rings are partially dry etched anisotropically and the remaining oxide is wet etched, the remaining oxide forming the ringed pillars 102 having a height of about 3 um.
- the epitaxial layer 106 is grown substantially about the seed Si layer 18 , the ringed pillars 102 , and the alignment keys 105 using an ELO technique, such as the ELO technique described in copending U.S. patent application Ser. No. 11/844,775 filed Aug. 24, 2007, which is incorporated herein by reference in its entirety.
- the doping profile is also engineered during the epitaxial growth process to provide forward drift field as described in the '583 patent.
- imaging structures (not shown) are formed overlying the epitaxial layer 106 .
- the ringed pillars 102 will be standing on the Si seed layer 18 . This leaves behind a continuous thin region of Si on the back surface of the imager 98 . Charges generated within the seed layer 18 have a probability of diffusing to the adjacent pixels. This poses a problem when charges are generated by photons having short wavelength, such as ultraviolet (UV), and deep UV radiation. Therefore, the method 108 is preferably employed for imagers that sense visible and longer wavelength light.
- UV ultraviolet
- FIG. 12 shows a cross-section of an imager 124 having a plurality of trenches 126 formed therein that are filled with both an electrical barrier of oxide 128 and an optically opaque material 130 .
- An optical barrier has the advantage that the light incident at an oblique angle will be reflected by the optical barrier so that it is confined within a collecting well of a pixel.
- an SOI wafer 12 which has a thin Si seed layer 18 is provided.
- an epitaxial layer 20 with a desired thickness (2-10 um) and resistivity is grown substantially overlying the seed layer 18 .
- the doping profile of the epitaxial layer 20 is engineered according to the technique described in the '583 Patent.
- trench outlines are formed about pixel collection wells along with alignment keys 22 on the surface of the epitaxial layer 20 using photolithography.
- the epitaxial layer 20 is trench etched down to the buried oxide (BOX) layer.
- BOX buried oxide
- the trenches are partially filled from the top of the epitaxial layer to the top of the underlying BOX oxide layer with an electrically insulating material such as an oxide of silicon.
- the remaining portions of the trenches are filled with an optically opaque material such as refractory metal.
- the tops of the trenches are planarized.
- imaging structures (not shown) are formed overlying the epitaxial layer 20 .
- steps 142 and 144 can be combined into one trench filling step if a material is employed that provides both an electrical barrier to charge carriers and optical barrier to electromagnetic radiation.
Abstract
Description
- This application claims the benefit of U.S. provisional patent application No. 61/029,648 filed Feb. 19, 2008, the disclosure of which is incorporated herein by reference in its entirety.
- The present invention relates generally to imagers, and more particularly, to a method and resulting device for reducing crosstalk in back illuminated imagers.
- CMOS or CCD image sensors are of interest in a wide variety of sensing and imaging applications in a wide range of fields including consumer, commercial, industrial, and space electronics. Imagers based on charge coupled devices (CCDs) are currently the most widely utilized. CCDs are employed either in front or back illuminated configurations. Front illuminated CCD imagers are more cost effective to manufacture than back illuminated CCD imagers such that front illuminated devices dominate the consumer imaging market. Front-illuminated imagers, however, have significant performance limitations such as low fill factor/low sensitivity. The problem of low fill factor/low sensitivity is typically due to shadowing caused by the presence of opaque metal bus lines, and absorption by an array circuitry structure formed on the front surface in the pixel region of a front-illuminated imager. Thus, the active region of a pixel is typically relatively small (low fill factor) in large format (high-resolution) front-illuminated imagers.
- Back-illuminated semiconductor (CCD and CMOS) imaging devices are advantageous over front-illuminated imagers for high fill factor, better overall efficiency of charge carrier generation and collection, and are suitable for small pixel arrays. Fabrication of thinned back illuminated imagers has several challenges. One challenge is the loss of charge carriers near the back surface due to inherent dangling bonds present at the silicon back surface, which reduces Quantum Efficiency (QE) if the backside of the thinned imager is not pinned. Eliminating this problem requires additional treatment at the backside of the device, which adds to the complexity of the fabrication process.
- A second challenge is absorption of charge carriers within the epitaxial layer, which prevents charge carriers from reaching processing components on the front side, which reduces sensitivity and efficiency of the device. In back illuminated imagers, photon radiation that enters the backside of the imagers generates charge carriers in the silicon epitaxial layer. The location of the charge generation in the epitaxial layer depends on the absorption length of the incident photon, which in turn depends on its wavelength. Photons with longer wavelengths, such as red, penetrate deeper into the epitaxial layer as compared to shorter wavelengths, such as blue. To generate maximum charge carriers from all the incident photons of different wavelengths requires an appropriate thickness for the epitaxial layer. Further, charge carriers generated near the back side of the imager should be driven to the front side as quickly as possible in order to avoid horizontal drift of carriers into adjacent pixels, which may smear an image.
- Additional challenges include excessive thinning of wafers, which poses yield issues such as stress in the thinned wafer, and uniformity of thickness, etc. Fabrication cost of back illuminated imagers can be higher than for front illuminated imagers due to thinning and backside treatment.
- To overcome these problems, techniques employing ultra thin silicon-on-insulator (SOI) wafers for the fabrication of back illuminated CCD/CMOS imagers have been developed, an example of which is described in U.S. Pat. No. 7,238,583 (hereinafter “the '583 Patent”), which is incorporated by reference herein in its entirety. In the '583 Patent, a thin semiconductor seed layer is supported by an ultra-thin substrate and an insulator layer made of an electrically insulating material such as silicon dioxide. An epitaxial layer may be grown substantially overlying the seed layer to an appropriate thickness to accommodate devices that are to operate at wavelengths from less than 100 nanometers (deep ultraviolet) to more than 3000 nanometers (far infrared). In order to drive charge carriers to the front side without recombination near the back side, and to prevent horizontal drift, a large electric field needs to be generated within the device. This is accomplished by doping the insulation and seed layers at an initial concentration, growing the epitaxial layer on the seed layer, and then causing the dopant to diffuse into the epitaxial layer such that the final net doping profile has its highest concentration in the insulator layer, with the net doping profile decreasing monotonically within the insulator layer and epitaxial layer.
- This technique solves the aforementioned problems. However, as technology advances in the fabrication of CMOS devices, the current CMOS imaging market demands high pixel density, and hence small pixel size for imagers. The scaling of pixel size also results in a lower bias supply. This limits the drift field that can be produced in a small pixel back illuminated imager array. Charge carriers that are generated near the backside due to short wavelength photons will tend to diffuse to the adjacent pixel, if there is not enough drift field. This phenomenon, which is referred as crosstalk, can be worse for a small pixel back illuminated array. Furthermore, photons that have a non-perpendicular incident angle relative to the back-side surface may generate carriers in adjacent pixels, which is a form of optical crosstalk.
- Accordingly, what would be desirable, but has not yet been provided, are a method and resulting device that reduces crosstalk in back illuminated imagers. Such a method and device would employ the doping profile technique disclosed in the '583 Patent where SOI wafers are used as a starting material.
- The above-described problems are addressed and a technical solution achieved in the art by providing a method and resulting device for reducing crosstalk in a back-illuminated imager, comprising providing a substrate comprising an insulator layer and a seed layer substantially overlying the insulator layer, an interface being formed where the seed layer comes in contact with the insulator layer; forming an epitaxial layer substantially overlying the seed layer, the epitaxial layer defining plurality of pixel regions, each pixel region outlining a collection well for collecting charge carriers; and forming one of an electrical, optical, and electrical and optical barrier about the outlined collection well extending into the epitaxial layer to the interface between the seed layer and the insulator layer. The seed layer and the epitaxial layer of the device have a net dopant concentration profile which has an initial maximum value at an interface of the seed layer and the insulator layer and which decreases monotonically with increasing distance from the interface within an initial portion of the semiconductor substrate and the epitaxial layer. At least one imaging component is formed at least partially overlying and extending into the epitaxial layer. A plurality of alignment keys are formed substantially overlying the epitaxial layer.
- The electrical barrier can be formed about the outlined collection well using implanted dopants; an etched trench filled with an electrically insulating material; a combination of implanted dopants and an etched trench filled with an electrically insulating material. An electrical/optical barrier can be formed by filling trenches with an electrically insulating material about outlined collection wells, opening trenches about the inner filled trenches, and filling the outer trenches with dopants.
- In another embodiment, a method for reducing crosstalk in a back-illuminated imager includes the steps of providing a substrate comprising an insulator layer and a seed layer substantially overlying the insulator layer, an interface being formed where the seed layer comes in contact with the insulator layer; defining pixel regions in the seed layers each pixel region outlining a collection well for collecting charge carriers; depositing an electrically insulating layer substantially overlying the seed layer; patterning the electrically insulating layer such that it forms a ring about location of the outlined collection well; and growing an the epitaxial layer substantially about the seed layer and the ring using an epitaxial lateral overgrowth (ELO) technique. The seed layer and the epitaxial layer of the device have a net dopant concentration profile which has an initial maximum value at the interface of the seed layer and the insulator layer and which decreases monotonically with increasing distance from an interface within an initial portion of the semiconductor substrate and the epitaxial layer.
- The present invention will be more readily understood from the detailed description of an exemplary embodiment presented below considered in conjunction with the attached drawings and in which like reference numerals refer to similar elements and in which:
-
FIG. 1A is a perspective view of a back-illuminated imager that reduces crosstalk, constructed according to an embodiment of the present invention; -
FIG. 1B is a top down view of a portion ofFIG. 1 , showing electrical/optical barriers forming rings about pixel collection wells; -
FIG. 2 shows a side view and top down view of the alignment keys formed in the epitaxial layer, according to an embodiment of the present invention; -
FIG. 3 shows a cross-section of an imager having a plurality of isolation barriers formed therein by means of implanted dopants, according to an embodiment of the present invention; -
FIG. 4 is a flow diagram of a method for forming isolation barriers made from high energy implants according to the embodiment ofFIG. 3 ; -
FIG. 5 shows a cross-section of an imager having a plurality of isolation barriers formed therein by means of oxide trenches, according to an embodiment of the present invention; -
FIG. 6 is a flow diagram of a method for forming isolation barriers made from oxide trenches according to the embodiment ofFIG. 5 ; -
FIG. 7 shows a cross-section of an imager having a plurality of isolation barriers formed therein by means of both oxide trenches and high energy implants, according to an embodiment of the present invention; -
FIG. 8 is a flow diagram of a method for forming isolation barriers made from oxide trenches and high energy implants according to the embodiment ofFIG. 7 ; -
FIG. 9 shows a cross-sections of an imager having a plurality of isolation barriers formed as rings about collection well regions from oxide “pillars”, according to an embodiment of the present invention; -
FIG. 10 shows a cross section of the imager ofFIG. 9 with an epitaxial layer grown substantially about the pillars using an epitaxial lateral overgrowth (ELO) technique; -
FIG. 11 is a flow diagram of a method for forming isolation barriers made from oxide pillars using an ELO technique according to the embodiment ofFIGS. 9 and 10 ; -
FIG. 12 shows a cross-section of an imager having a plurality of trenches formed therein that are filled with both an electrical barrier of oxide and an optically opaque material”, according to an embodiment of the present invention; and -
FIG. 13 is a flow diagram of a method for forming isolation barriers made from oxide and an optically opaque material according to the embodiment ofFIG. 12 . - It is to be understood that the attached drawings are for purposes of illustrating the concepts of the invention and may not be to scale.
- Referring now to
FIGS. 1A and 1B , there is shown a back-illuminatedimager 10, constructed according to an embodiment of the present invention. Theimager 10 may include aninitial substrate 12, sometimes referred to in the art as a semiconductor-on-insulator (SOI) substrate, which is composed ofhandle wafer 14 to provide mechanical support during processing, an insulator layer 16 (buried oxide layer), andseed layer 18. Thehandle wafer 14 may be a standard silicon wafer used in fabricating integrated circuits. Alternatively, thehandle wafer 14 may be any sufficiently rigid substrate composed of a material which is compatible with the steps of the method disclosed herein. The handle wafer, at later processing steps, can be removed completely.Insulator layer 16 may comprise an oxide of silicon with a thickness ranging up to 1 micrometer. Among other embodiments, the thickness ofinsulator layer 16 may fall in a range from about 10 nm to about 5000 nm. If thehandle wafer 14 is completely remove, theinsulator layer 16 may also be thinned to produce an anti-reflective layer.Seed layer 18 may be comprised of crystalline silicon having a thickness from about 5 nanometers to about 100 nanometers. - SOI substrates are available commercially and are manufactured by various known methods. In one method, thermal silicon oxide is grown on silicon wafers. Two such wafers are joined with oxidized faces in contact and raised to a high temperature. In some variations, an electric potential difference is applied across the two wafers and the oxides. The effect of these treatments is to cause the oxide layers on the two wafers to flow into each other, forming a monolithic bond between the wafers. Once the bonding is complete, the silicon on one side is lapped and polished to the desired thickness of
seed layer 18, while the silicon on the opposite side of the oxide forms handlewafer 14. The oxide formsinsulator layer 16. - Another method of fabricating an SOI substrate begins with obtaining a more standard semiconductor-on-insulator (SOI) wafer in which the
seed layer 18 has a thickness in the range from about 100 nm to about 1000 nm. A thermal oxide is grown on the semiconductor substrate, using known methods. As the oxide layer grows, semiconductor material of the semiconductor substrate is consumed. Then the oxide layer is selectively etched off, leaving a thinned semiconductor substrate having a desired seed layer thickness. - SOI substrates manufactured by an alternative method, known as Smart Cut.™., are sold by Soitec, S.A.
-
Seed layer 18 may comprise silicon (Si), Germanium (Ge), SiGe alloy, a III-V semiconductor, a II-VI semiconductor, or any other semiconductor material suitable for the fabrication of optoelectronic devices. - An
epitaxial layer 20 is formed on theseed layer 18, usingseed layer 18 as the template. Depending on the material ofseed layer 18,epitaxial layer 20 may comprise silicon (Si), Germanium (Ge), SiGe alloy, a III-V semiconductor, a II-VI semiconductor, or any other semiconductor material suitable for the fabrication of optoelectronic devices.Epitaxial layer 20 may have a thickness from about 1 micrometer to about 50 micrometers. The resistivity of theepitaxial layer 20 can be controlled by controlling the epitaxial growth process. - Referring now to
FIGS. 1A and 2 ,alignment keys 22 are printed on and etched into theepitaxial layer 20. Thealignment keys 22 can be used to align subsequent layers during the imager fabrication process. The use of alignment keys can result in highly accurate alignment of about 0.1 micrometer or less for subsequently deposited layers. Using photolithography,key patterns 24 are printed on atop portion 26 of theepitaxial layer 20. A trench plasma etch process can be used to etch theunderlying epitaxial layer 20 below thekey patterns 24 until the etched away silicon is stopped by the underlying insulator/buriedoxide layer 16. Theopen trenches 28 are then filled with an electrically insulating material such as an oxide of silicon, silicon carbide, silicon nitride, or poly-silicon. - Referring again to
FIGS. 1A and 1B , one ormore imaging structures 30, such as but not limited to CCD or CMOS imaging structures, may be fabricated on theepitaxial layer 20. Theseimaging structures 30 may include charge-coupled device (CCD) components, CMOS imaging components, photodiodes, avalanche photodiodes, phototransistors, or other optoelectronic devices, in any combination. Also included may be other electronic components such as CMOS transistors, bipolar transistors, capacitors, or resistors (not shown). After fabrication of the one ormore imaging structures 30 is completed, thehandle wafer 14 is removed by etching from the back side of the back-illuminatedimager 10. Theinsulator layer 16 can be thinned to a desired thickness such that it acts as an anti-reflective layer to a desired incoming wavelength of light. Alternatively, the insulatinglayer 16 can also be removed completely, and another suitable material can be deposited on the remainingepitaxial layer 20 which can be of a desired thickness so as to act as an anti-reflective coating/layer. Optical components (not shown) can be bonded to the back side of theimager 10 using thealignment keys 22 as precision guides. The one or more optical components can comprise color filters and micro-lenses to produce wavelength dependent signals. - Before the
imaging structures 30 are formed, one of electrical, optical, and electrical andoptical barriers 32 are formed in theepitaxial layer 20 about thecollection wells 34 of each of thepixels 36 comprising theimager 10. Each of thecollection wells 34 andbarriers 32 are separated from each other byregions 37 where the transfer/readout circuit elements belonging to theimaging structures 30 are fabricated. Thebarriers 32 preferably extend vertically from about thetop surface 35 of the epitaxial layer down to thesurface seed layer 18 and theinsulator layer 16, respectively. Thebarriers 32 may be formed by one of several techniques and of several types of materials to be described hereinbelow. -
FIG. 3 shows a cross-section of animager 40 having a plurality of isolation barriers formed therein by means of implanted dopants. The high-energy implants 42 are formed from available techniques in the fabrication industry. Today's high-energy (on the order of MeV) implanters are capable of implanting species in the range of 2-10 um deep into silicon. Referring now toFIGS. 1-4 , a method 50 for forming isolation barriers made from high energy implants is described as follows: - At
step 52, anSOI wafer 12 which has a thinSi seed layer 18 is provided. Atstep 54, anepitaxial layer 20 with a desired thickness (2-10 um) and resistivity is grown on theseed layer 18. Atstep 55, the doping profile of theepitaxial layer 20 is engineered according to the technique described in the '583 Patent. Atstep 56,alignment keys 22 are formed in theepitaxial layer 20. Sub-steps include printing alignment keys on theepitaxial layer 20 using photolithography; trench etching theepitaxial layer 20; and filling the trenches with an electrically insulating material, such as an oxide (preferably of silicon). Atstep 58, boundary rings are defined about the collecting wells of the pixels using photolithography and with the aid of the alignment keys formed earlier. Atstep 60, using high-energy implanters, appropriate dopant species are implanted at the locations of the boundary rings around collecting wells such that the dopants reach down to the interface between theinsulator layer 16 and theseed layer 18. For a p-type substrate, the high energy implants (dopants) can be formed by ion implanting p-type impurities into a p-type epitaxial layer (and likewise n-type impurities for an n-type epitaxial layer). Atstep 62, the dopants can be thermally activated. Atstep 64,imaging structures 30 are formed overlying theepitaxial layer 20. The dopants can be activated by processes such as rapid thermal annealing so that the diffusion can be minimized. The dopants, once activated, provide an electrical isolation barrier such that carriers generated inside a collecting well will not diffuse into adjacent pixels. -
FIG. 5 shows a cross-section of animager 64 having a plurality of isolation barriers formed therein by means of oxide trenches. Theoxide trenches 66, being insulators, act as electrical barriers to generated charge carriers and confine them within pixel collecting wells. One advantage of this method is that thebarrier trenches 66 can be defined along with the alignment keys, eliminating the need for another photo mask. Referring now toFIGS. 1-2 , 5 and 6, amethod 68 for forming isolation barriers made from oxide trenches is described as follows: - At
step 70, anSOI wafer 12 which has a thinSi seed layer 18 is provided. Atstep 72, anepitaxial layer 20 with a desired thickness (2-10 um) and resistivity is grown on theseed layer 18. Atstep 73, the doping profile of theepitaxial layer 20 is engineered according to the technique described in the '583 Patent. Atstep 74, trench outlines are formed about collection wells collecting along withalignment keys 22 on the surface of theepitaxial layer 20 using photolithography. Atstep 76, theepitaxial layer 20 is trench etched down to the buried oxide (insulation)layer 16. Atstep 78, thetrenches step 80, the tops of thetrenches step 82,imaging structures 30 are formed overlying theepitaxial layer 20. - One concern with employing the
method 68 is that the trench etch step may result in unnecessary traps at the interfaces between epitaxial layer silicon and trench filled oxide. However, the number traps can be reduced by thermal annealing. -
FIG. 7 shows a cross-sectional of all imager 84 having a plurality of isolation barriers 86 formed therein by means of bothoxide trenches 88 andhigh energy implants 90, thereby combiningmethods 1 and 2 by creating oxide trenches and implanting dopants around those trenches. Referring now toFIGS. 1-2 and 7 and 8, amethod 92 for forming isolation barriers made from oxide trenches and high energy implants is described as follows: - The
method 92 begins by performingsteps 70 to 80 of themethod 68 to create oxide trenches and alignment keys. Atstep 94, regions about each of the filled trenches are opened down to theoxide layer 18, and atstep 96, the regions are implanted with high energy dopants, the dopants being thermally activated thereupon. Atstep 97,imaging structures 30 are formed overlying theepitaxial layer 20. Since the oxide trenches are encapsulated by dopants, the electrical barrier due to the dopants can reduce the effect of traps at the interface between the high energy dopants and the epitaxial silicon. -
FIGS. 9 and 10 show cross-sections of animager 98 having a plurality of isolation barriers comprising oxide “pillars” 102 formed as rings about collection wells with anepitaxial layer 106 grown substantially about thepillars 102 using an epitaxial lateral overgrowth (ELO) technique. This technique completely eliminates traps created in a trench process. Referring now toFIGS. 1-2 and 9-11, amethod 108 for forming isolation barriers made from oxide pillars and using an ELO technique to grow an epitaxial layer is described as follows: - At
step 110, anSOI wafer 12 which has a thinSi seed layer 18 is provided. Atstep 112, an electrically insulating layer such as a layer of an oxide of silicon (not shown) is deposited substantially overlying theseed layer 18, the thickness of the oxide layer (about 2-10 um) being substantially similar to a final desired final epitaxial layer thickness. Atstep 114, the oxide layer is patterned such that it forms rings about collecting wells (not shown), and also formsalignment keys 104. Atstep 118, the oxide rings are partially dry etched anisotropically and the remaining oxide is wet etched, the remaining oxide forming the ringedpillars 102 having a height of about 3 um. Atstep 120, theepitaxial layer 106 is grown substantially about theseed Si layer 18, the ringedpillars 102, and the alignment keys 105 using an ELO technique, such as the ELO technique described in copending U.S. patent application Ser. No. 11/844,775 filed Aug. 24, 2007, which is incorporated herein by reference in its entirety. Atstep 121, the doping profile is also engineered during the epitaxial growth process to provide forward drift field as described in the '583 patent. Atstep 122, imaging structures (not shown) are formed overlying theepitaxial layer 106. - Unlike in the previous methods, the ringed
pillars 102 will be standing on theSi seed layer 18. This leaves behind a continuous thin region of Si on the back surface of theimager 98. Charges generated within theseed layer 18 have a probability of diffusing to the adjacent pixels. This poses a problem when charges are generated by photons having short wavelength, such as ultraviolet (UV), and deep UV radiation. Therefore, themethod 108 is preferably employed for imagers that sense visible and longer wavelength light. -
FIG. 12 shows a cross-section of animager 124 having a plurality oftrenches 126 formed therein that are filled with both an electrical barrier ofoxide 128 and an opticallyopaque material 130. An optical barrier has the advantage that the light incident at an oblique angle will be reflected by the optical barrier so that it is confined within a collecting well of a pixel. Referring now toFIGS. 1-2 , 12 and 13, amethod 132 for forming isolation barriers made from oxide and an optically opaque material is described as follows: - At
step 134, anSOI wafer 12 which has a thinSi seed layer 18 is provided. Atstep 136, anepitaxial layer 20 with a desired thickness (2-10 um) and resistivity is grown substantially overlying theseed layer 18. Atstep 137, the doping profile of theepitaxial layer 20 is engineered according to the technique described in the '583 Patent. Atstep 138, trench outlines are formed about pixel collection wells along withalignment keys 22 on the surface of theepitaxial layer 20 using photolithography. Atstep 140, theepitaxial layer 20 is trench etched down to the buried oxide (BOX) layer. Atstep 142, the trenches are partially filled from the top of the epitaxial layer to the top of the underlying BOX oxide layer with an electrically insulating material such as an oxide of silicon. Atstep 144, the remaining portions of the trenches are filled with an optically opaque material such as refractory metal. Atstep 146, the tops of the trenches are planarized. Atstep 148, imaging structures (not shown) are formed overlying theepitaxial layer 20. - Note, in some embodiments,
steps - It is to be understood that the exemplary embodiments are merely illustrative of the invention and that many variations of the above-described embodiments may be devised by one skilled in the art without departing from the scope of the invention. It is therefore intended that all such variations be included within the scope of the following claims and their equivalents.
Claims (27)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/132,721 US7985612B2 (en) | 2008-02-19 | 2008-06-04 | Method and device for reducing crosstalk in back illuminated imagers |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US2964808P | 2008-02-19 | 2008-02-19 | |
US12/132,721 US7985612B2 (en) | 2008-02-19 | 2008-06-04 | Method and device for reducing crosstalk in back illuminated imagers |
Publications (2)
Publication Number | Publication Date |
---|---|
US20090206377A1 true US20090206377A1 (en) | 2009-08-20 |
US7985612B2 US7985612B2 (en) | 2011-07-26 |
Family
ID=40954284
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/132,721 Active 2029-09-08 US7985612B2 (en) | 2008-02-19 | 2008-06-04 | Method and device for reducing crosstalk in back illuminated imagers |
Country Status (3)
Country | Link |
---|---|
US (1) | US7985612B2 (en) |
TW (1) | TW200937628A (en) |
WO (1) | WO2009105120A1 (en) |
Cited By (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100006970A1 (en) * | 2008-07-09 | 2010-01-14 | Brady Frederick T | Backside illuminated image sensor with reduced dark current |
WO2010027395A3 (en) * | 2008-07-09 | 2010-05-14 | Eastman Kodak Company | Backside illuminated image sensor with backside trenches |
US20100164048A1 (en) * | 2008-12-24 | 2010-07-01 | S.O.I.Tec Silicon On Insulator Technologies | Method for fabricating a semiconductor substrate and semiconductor substrate |
US20100232692A1 (en) * | 2009-03-10 | 2010-09-16 | Mrityunjay Kumar | Cfa image with synthetic panchromatic image |
US20100245636A1 (en) * | 2009-03-27 | 2010-09-30 | Mrityunjay Kumar | Producing full-color image using cfa image |
US20100265370A1 (en) * | 2009-04-15 | 2010-10-21 | Mrityunjay Kumar | Producing full-color image with reduced motion blur |
US20100302423A1 (en) * | 2009-05-27 | 2010-12-02 | Adams Jr James E | Four-channel color filter array pattern |
US20100302418A1 (en) * | 2009-05-28 | 2010-12-02 | Adams Jr James E | Four-channel color filter array interpolation |
US20100309347A1 (en) * | 2009-06-09 | 2010-12-09 | Adams Jr James E | Interpolation for four-channel color filter array |
US20100309350A1 (en) * | 2009-06-05 | 2010-12-09 | Adams Jr James E | Color filter array pattern having four-channels |
US20110024868A1 (en) * | 2008-02-26 | 2011-02-03 | Alexis Drouin | Method for fabricating a semiconductor substrate |
US7994463B1 (en) * | 2005-04-25 | 2011-08-09 | Corporation For National Research Initiatives | Fabrication of transducer structures |
US8119435B2 (en) | 2008-07-09 | 2012-02-21 | Omnivision Technologies, Inc. | Wafer level processing for backside illuminated image sensors |
US8139130B2 (en) | 2005-07-28 | 2012-03-20 | Omnivision Technologies, Inc. | Image sensor with improved light sensitivity |
US8194296B2 (en) | 2006-05-22 | 2012-06-05 | Omnivision Technologies, Inc. | Image sensor with improved light sensitivity |
US8274715B2 (en) | 2005-07-28 | 2012-09-25 | Omnivision Technologies, Inc. | Processing color and panchromatic pixels |
US8416339B2 (en) | 2006-10-04 | 2013-04-09 | Omni Vision Technologies, Inc. | Providing multiple video signals from single sensor |
US20150331040A1 (en) * | 2012-07-02 | 2015-11-19 | Freescale Semiconductor, Inc. | Integrated circuit device, safety circuit, safety-critical system and method of manufacturing an integrated circuit device |
US11264423B2 (en) * | 2009-02-10 | 2022-03-01 | Sony Corporation | Solid-state imaging device having improved light-collection, method of manufacturing the same, and electronic apparatus |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101461633B1 (en) * | 2008-12-26 | 2014-11-13 | 삼성전자주식회사 | Image Sensor And Method Of Fabricating The Same |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6008126A (en) * | 1992-04-08 | 1999-12-28 | Elm Technology Corporation | Membrane dielectric isolation IC fabrication |
US20010019361A1 (en) * | 1996-04-15 | 2001-09-06 | Massachusetts Institute Of Technology | Low-light-level imaging and image processing |
US20050139833A1 (en) * | 2003-11-04 | 2005-06-30 | Janesick James R. | Image sensor with deep well region and method of fabricating the image sensor |
US20060038252A1 (en) * | 2004-02-20 | 2006-02-23 | Chandra Mouli | Reduced crosstalk sensor and method of formation |
US7160753B2 (en) * | 2004-03-16 | 2007-01-09 | Voxtel, Inc. | Silicon-on-insulator active pixel sensors |
US7238583B2 (en) * | 2005-02-11 | 2007-07-03 | Sarnoff Corporation | Back-illuminated imaging device and method of fabricating same |
US20070235829A1 (en) * | 2005-02-11 | 2007-10-11 | Levine Peter A | Dark Current Reduction in Back-Illuminated Imaging Sensors and Method of Fabricating Same |
US20080061390A1 (en) * | 2006-09-11 | 2008-03-13 | Pradyumna Kumar Swain | Method and Apparatus for Reducing Smear in Back-Illuminated Imaging Sensors |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100791336B1 (en) | 2006-08-10 | 2008-01-07 | 삼성전자주식회사 | Method for fabricating image sensor |
-
2008
- 2008-06-04 US US12/132,721 patent/US7985612B2/en active Active
- 2008-06-04 WO PCT/US2008/065708 patent/WO2009105120A1/en active Application Filing
- 2008-06-23 TW TW097123387A patent/TW200937628A/en unknown
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6008126A (en) * | 1992-04-08 | 1999-12-28 | Elm Technology Corporation | Membrane dielectric isolation IC fabrication |
US20010019361A1 (en) * | 1996-04-15 | 2001-09-06 | Massachusetts Institute Of Technology | Low-light-level imaging and image processing |
US20050139833A1 (en) * | 2003-11-04 | 2005-06-30 | Janesick James R. | Image sensor with deep well region and method of fabricating the image sensor |
US20060038252A1 (en) * | 2004-02-20 | 2006-02-23 | Chandra Mouli | Reduced crosstalk sensor and method of formation |
US7160753B2 (en) * | 2004-03-16 | 2007-01-09 | Voxtel, Inc. | Silicon-on-insulator active pixel sensors |
US7238583B2 (en) * | 2005-02-11 | 2007-07-03 | Sarnoff Corporation | Back-illuminated imaging device and method of fabricating same |
US20070235829A1 (en) * | 2005-02-11 | 2007-10-11 | Levine Peter A | Dark Current Reduction in Back-Illuminated Imaging Sensors and Method of Fabricating Same |
US20080061390A1 (en) * | 2006-09-11 | 2008-03-13 | Pradyumna Kumar Swain | Method and Apparatus for Reducing Smear in Back-Illuminated Imaging Sensors |
Cited By (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7994463B1 (en) * | 2005-04-25 | 2011-08-09 | Corporation For National Research Initiatives | Fabrication of transducer structures |
US8711452B2 (en) | 2005-07-28 | 2014-04-29 | Omnivision Technologies, Inc. | Processing color and panchromatic pixels |
US8330839B2 (en) | 2005-07-28 | 2012-12-11 | Omnivision Technologies, Inc. | Image sensor with improved light sensitivity |
US8274715B2 (en) | 2005-07-28 | 2012-09-25 | Omnivision Technologies, Inc. | Processing color and panchromatic pixels |
US8139130B2 (en) | 2005-07-28 | 2012-03-20 | Omnivision Technologies, Inc. | Image sensor with improved light sensitivity |
US8194296B2 (en) | 2006-05-22 | 2012-06-05 | Omnivision Technologies, Inc. | Image sensor with improved light sensitivity |
US8416339B2 (en) | 2006-10-04 | 2013-04-09 | Omni Vision Technologies, Inc. | Providing multiple video signals from single sensor |
US20110024868A1 (en) * | 2008-02-26 | 2011-02-03 | Alexis Drouin | Method for fabricating a semiconductor substrate |
US8575010B2 (en) | 2008-02-26 | 2013-11-05 | Soitec | Method for fabricating a semiconductor substrate |
US8119435B2 (en) | 2008-07-09 | 2012-02-21 | Omnivision Technologies, Inc. | Wafer level processing for backside illuminated image sensors |
WO2010027395A3 (en) * | 2008-07-09 | 2010-05-14 | Eastman Kodak Company | Backside illuminated image sensor with backside trenches |
US7915067B2 (en) * | 2008-07-09 | 2011-03-29 | Eastman Kodak Company | Backside illuminated image sensor with reduced dark current |
US20110115957A1 (en) * | 2008-07-09 | 2011-05-19 | Brady Frederick T | Backside illuminated image sensor with reduced dark current |
US20100006970A1 (en) * | 2008-07-09 | 2010-01-14 | Brady Frederick T | Backside illuminated image sensor with reduced dark current |
US20100164048A1 (en) * | 2008-12-24 | 2010-07-01 | S.O.I.Tec Silicon On Insulator Technologies | Method for fabricating a semiconductor substrate and semiconductor substrate |
US11735620B2 (en) * | 2009-02-10 | 2023-08-22 | Sony Group Corporation | Solid-state imaging device having optical black region, method of manufacturing the same, and electronic apparatus |
US20220123041A1 (en) * | 2009-02-10 | 2022-04-21 | Sony Group Corporation | Solid-state imaging device, method of manufacturing the same, and electronic apparatus |
US11264423B2 (en) * | 2009-02-10 | 2022-03-01 | Sony Corporation | Solid-state imaging device having improved light-collection, method of manufacturing the same, and electronic apparatus |
US8224082B2 (en) | 2009-03-10 | 2012-07-17 | Omnivision Technologies, Inc. | CFA image with synthetic panchromatic image |
US20100232692A1 (en) * | 2009-03-10 | 2010-09-16 | Mrityunjay Kumar | Cfa image with synthetic panchromatic image |
US8068153B2 (en) | 2009-03-27 | 2011-11-29 | Omnivision Technologies, Inc. | Producing full-color image using CFA image |
US20100245636A1 (en) * | 2009-03-27 | 2010-09-30 | Mrityunjay Kumar | Producing full-color image using cfa image |
US20100265370A1 (en) * | 2009-04-15 | 2010-10-21 | Mrityunjay Kumar | Producing full-color image with reduced motion blur |
US8045024B2 (en) | 2009-04-15 | 2011-10-25 | Omnivision Technologies, Inc. | Producing full-color image with reduced motion blur |
US20100302423A1 (en) * | 2009-05-27 | 2010-12-02 | Adams Jr James E | Four-channel color filter array pattern |
US8203633B2 (en) | 2009-05-27 | 2012-06-19 | Omnivision Technologies, Inc. | Four-channel color filter array pattern |
US8237831B2 (en) | 2009-05-28 | 2012-08-07 | Omnivision Technologies, Inc. | Four-channel color filter array interpolation |
US20100302418A1 (en) * | 2009-05-28 | 2010-12-02 | Adams Jr James E | Four-channel color filter array interpolation |
US20100309350A1 (en) * | 2009-06-05 | 2010-12-09 | Adams Jr James E | Color filter array pattern having four-channels |
US8125546B2 (en) | 2009-06-05 | 2012-02-28 | Omnivision Technologies, Inc. | Color filter array pattern having four-channels |
US8253832B2 (en) | 2009-06-09 | 2012-08-28 | Omnivision Technologies, Inc. | Interpolation for four-channel color filter array |
US20100309347A1 (en) * | 2009-06-09 | 2010-12-09 | Adams Jr James E | Interpolation for four-channel color filter array |
US20150331040A1 (en) * | 2012-07-02 | 2015-11-19 | Freescale Semiconductor, Inc. | Integrated circuit device, safety circuit, safety-critical system and method of manufacturing an integrated circuit device |
US9638744B2 (en) * | 2012-07-02 | 2017-05-02 | Nxp Usa, Inc. | Integrated circuit device, safety circuit, safety-critical system and method of manufacturing an integrated circuit device |
Also Published As
Publication number | Publication date |
---|---|
US7985612B2 (en) | 2011-07-26 |
TW200937628A (en) | 2009-09-01 |
WO2009105120A1 (en) | 2009-08-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7985612B2 (en) | Method and device for reducing crosstalk in back illuminated imagers | |
US8178914B2 (en) | Method of fabricating back-illuminated imaging sensors | |
US8816443B2 (en) | Method of fabricating heterojunction photodiodes with CMOS | |
CN102856333B (en) | Solid camera head, its manufacture method and electronic equipment | |
US8946818B2 (en) | Dark current reduction in back-illuminated imaging sensors | |
TWI557889B (en) | Nanowire photo-detector grown on a back-side illuminated image sensor | |
JP5569153B2 (en) | Solid-state imaging device and manufacturing method thereof | |
KR101594927B1 (en) | Back-illuminated cmos image sensors | |
CN108886044B (en) | Method for manufacturing improved NIR CMOS sensor | |
US7932575B2 (en) | Method of fabricating back-illuminated imaging sensors using a bump bonding technique | |
US7777229B2 (en) | Method and apparatus for reducing smear in back-illuminated imaging sensors | |
TW200901456A (en) | Methods, structures and sytems for an image sensor device for improving quantum efficiency of red pixels | |
JP2007027730A (en) | Image sensor and its manufacture | |
US7968358B2 (en) | Digital radiographic flat-panel imaging array with dual height semiconductor and method of making same | |
US20120104464A1 (en) | P-pixel cmos imagers using ultra-thin silicon on insulator substrates (utsoi) | |
WO2013097660A1 (en) | Image sensor and manufacturing method thereof | |
US9520441B2 (en) | Method for electronically pinning a back surface of a back-illuminated imager fabricated on a UTSOI wafer | |
US7982277B2 (en) | High-efficiency thinned imager with reduced boron updiffusion | |
JP2012231026A (en) | Solid state image pickup device | |
CN107742629A (en) | A kind of semiconductor devices and forming method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SARNOFF CORPORATION, NEW JERSEY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SWAIN, PRADYUMNA KUMAR;BHASKARAN, MAHALINGAM;REEL/FRAME:021474/0534 Effective date: 20080807 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: SMALL ENTITY |
|
AS | Assignment |
Owner name: SRI INTERNATIONAL, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SARNOFF CORPORATION;REEL/FRAME:026446/0826 Effective date: 20110204 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: SRI INTERNATIONAL, CALIFORNIA Free format text: MERGER;ASSIGNOR:SRANOFF CORPORATION;REEL/FRAME:028564/0791 Effective date: 20110204 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YR, SMALL ENTITY (ORIGINAL EVENT CODE: M2552); ENTITY STATUS OF PATENT OWNER: SMALL ENTITY Year of fee payment: 8 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YR, SMALL ENTITY (ORIGINAL EVENT CODE: M2553); ENTITY STATUS OF PATENT OWNER: SMALL ENTITY Year of fee payment: 12 |