US20090273092A1 - Semiconductor module having an interconnection structure - Google Patents
Semiconductor module having an interconnection structure Download PDFInfo
- Publication number
- US20090273092A1 US20090273092A1 US12/505,011 US50501109A US2009273092A1 US 20090273092 A1 US20090273092 A1 US 20090273092A1 US 50501109 A US50501109 A US 50501109A US 2009273092 A1 US2009273092 A1 US 2009273092A1
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- United States
- Prior art keywords
- conductive posts
- semiconductor chip
- interconnection structure
- semiconductor
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Definitions
- the present invention relates to a method for manufacturing a semiconductor module.
- a semiconductor chip associated with electrodes is faced down and adhered to a printed circuit board associated with external terminals. Then, a sealing resin is supplied so that a gap between the semiconductor chip and the printed circuit board is sealed (see: JP 2001-345418 A).
- a metal layer is formed on a support substrate. Then, first conductive posts and a first insulating layer are formed on the metal layer. The first insulating layer surrounds the sides of the first conductive posts. Then, second conductive posts are formed above the first conductive posts. The second conductive posts are electrically connected to the first conductive posts. Then, a second insulating layer is formed so as to cover the second conductive posts. The second insulating layer is made of adhesive resin. Finally, a semiconductor device is adhered to the second conductive posts by the second insulating layer while a gap between the first semiconductor device and the first insulating layer is sealed by the second insulating layer.
- the support substrate and the metal layer are removed before the semiconductor module is mounted on a printed circuit board or the like.
- the spacing between the electrodes of the semiconductor device is usually expanded by a connection structure including the first conductive posts, the first insulating layer, the second conductive posts and the second insulating layer to the spacing between the external electrodes of the interconnection structure. Therefore, the semiconductor module can easily be mounted on the printed circuit board or the like.
- FIGS. 1A through 1L are cross-sectional views for explaining a first embodiment of the method for manufacturing a semiconductor module according to the present invention
- FIGS. 2A through 2P are cross-sectional views for explaining a second embodiment of the method for manufacturing a semiconductor module according to the present invention.
- FIGS. 3A , 3 B and 3 C are cross-sectional views for explaining a third embodiment of the method for manufacturing a semiconductor module according to the present invention.
- FIGS. 4A , 4 B and 4 C are cross-sectional views for explaining a fourth embodiment of the method for manufacturing a semiconductor module according to the present invention.
- FIGS. 5A , 5 B and 5 C are cross-sectional views for explaining a fifth embodiment of the method for manufacturing a semiconductor module according to the present invention.
- FIGS. 6A , 6 B and 6 C are cross-sectional views for explaining a sixth embodiment of the method for manufacturing a semiconductor module according to the present invention.
- FIGS. 1A through 1L A first embodiment of the method for manufacturing a semiconductor module according to the present invention will now be explained with reference to FIGS. 1A through 1L .
- a support substrate I such as a silicon wafer is prepared.
- a seed metal layer 2 made of Cu or Ni as an electroplating intervening layer is deposited on the entire surface by a sputtering process or the like.
- conductive posts (pads) 3 made of Cu or Ni are formed on the seed metal layer 2 by a photolithography process and an electroplating process using the seed metal layer 2 as a cathode electrode.
- a thin copper diffusion preventing layer (not shown) made of Ni can also be formed by a photolithography process and an electroplating process using the seed metal layer 2 as a cathode electrode before the formation of the conductive posts 3 .
- an insulating resin layer 4 made of polyimide resin or epoxy resin is coated on the entire surface by a spin-coat process, and then, sintered.
- the insulating resin layer 4 can be formed by adhering an insulating resin film made of polyimide resin or epoxy resin on the entire surface.
- the insulating resin layer 4 is flattened by a chemical-mechanical polishing (CMP) process, a grinding process or a cutting process to expose the upper surface of the conductive posts 3 .
- CMP chemical-mechanical polishing
- a conductive pattern layer 5 serving as interconnections made of Cu or Ni is formed by a photolithography process and an electroplating process using the seed metal layer 2 as a cathode electrode.
- the conductive pattern layer 5 is electrically connected to the conductive posts 3 .
- conductive posts (pads) 6 made of Cu or Ni are formed by a photolithography process and an electroplating process using the seed metal layer 2 as a cathode electrode.
- the conductive posts 6 are electrically connected to the conductive pattern layer 5 .
- thermoplastic resin layer 7 made of thermoplastic polyimide as an adhesive layer is coated on the entire surface to cover the conductive pattern layer 5 and the conductive posts 6 .
- thermoplastic resin layer 7 is flattened by a CMP process, a grinding process or a cutting process to expose the upper surface of the conductive posts 6 .
- a copper oxidation preventing layer (not shown) made of Au can also be formed on the surface of the conductive posts 6 by an electroplating process using the seed metal layer 2 as a cathode electrode.
- an interconnection structure CS 1 is formed by the conductive posts 3 , the insulating resin layer 4 , the conductive pattern layer 5 , the conductive posts 6 and the thermoplastic resin layer 7 .
- a semiconductor chip 8 made of silicon associated with electrodes 9 to which solder balls, electroplated balls or stud bumps are applied is faced down to the interconnection structure CS 1 , so that the electrodes 9 of the semiconductor chip 8 correspond to respective ones of the conductive posts 6 of the interconnection structure CS 1 .
- the support substrate 1 and/or the semiconductor chip 8 are heated so as to melt the thermoplastic resin layer 7 .
- the electrical connection of the electrodes 9 of the semiconductor chip 1 to the conductive posts 6 , the adhesion of the semiconductor chip 8 to the interconnection structure CS 1 and the sealing of a gap between the semiconductor chip 8 and the insulating resin layer 4 are simultaneously carried out, which would decrease the number of manufacturing steps.
- the interconnection structure CS 1 since the interconnection structure CS 1 is adhered to the support substrate 1 , the interconnection structure CS 1 thermally expands and shrinks as the support substrate 1 thermally expands and shrinks.
- the support substrate 1 and the semiconductor chip 8 are substantially made of the same material such as silicon so that there is no substantial difference in thermal expansion coefficient therebetween, the semiconductor chip 8 also thermally expands and shrinks as the support substrate 1 thermally expands and shrinks.
- the support substrate 1 and the semiconductor chip 8 can be entirely heated while they are pressed against each other by an XY stage and a suction head (not shown), so that there is no substantial difference in temperature between the support substrate 1 and the semiconductor chip 8 .
- the support substrate 1 along with the interconnection structure CS 1 is mounted on the XY stage and the semiconductor chip 8 is mounted on the suction head. Then. the suction head is pressed against the XY stage, so that the support substrate 1 and the semiconductor chip 8 are pressed against each other.
- the support substrate 1 is heated by a heater incorporated into the XY stage to about 100° C.
- the semiconductor chip 8 is heated by a heater incorporated into the suction head to about 300° C. Therefore, even if the width of the conductive posts 6 becomes narrower and the spacing (pitch) between the conductive posts 6 becomes smaller, the conductive posts 6 can suitably correspond to the electrodes 9 of the semiconductor chip 8 .
- the interconnection structure CS 1 is sealed by a sealing resin layer 10 by a molding process, a printing process or a potting process.
- a sealing resin layer 10 by a molding process, a printing process or a potting process.
- this back surface can be exposed to the air.
- the support substrate 1 is removed from the seed metal layer 2 by a CMP process, a grinding process, a cutting process, a wet etching process a dry etching process, or some combination of the processes.
- a dry etching process as a final process is performed upon the support substrate 1 , the etching ratio of the support substrate 1 to the seed metal layer 2 is so large that the seed metal layer 2 can surely be left.
- the conductive posts 3 and the border portion between the conductive posts 3 and the insulating resin layer 4 are surely covered by the seed metal layer 2 , thus preventing the conductive posts 3 from being damaged and the border portion between the conductive posts 3 and the insulating resin layer 4 from being cracked.
- the seed metal layer 2 is removed from the interconnection structure CS 1 by an etching process to expose the conductive posts 3 .
- external electrodes 11 such as solder balls, electroplated balls or stud bumps are adhered to the conductive posts 3 .
- FIGS. 1A through 1L Note that although a single semiconductor module is illustrated in FIGS. 1A through 1L , a plurality of semiconductor modules are actually manufactured. Therefore, after the process as shown in FIG. 1L , the plurality of semiconductor modules are separated from each other by a dicing process.
- FIGS. 2A through 2 P A second embodiment of the method for manufacturing a semiconductor module according to the present invention will be explained next with reference to FIGS. 2A through 2 P.
- a support substrate 1 such as a silicon wafer is prepared.
- a seed metal layer 2 made of Cu or Ni as an electroplating intervening layer is deposited on the entire surface by a sputtering process or the like.
- conductive posts (pads) 31 made of Cu or Ni are formed on the seed metal layer 2 by a photolithography process and an electroplating process using the seed metal layer 2 as a cathode electrode.
- an insulating resin layer 41 made of polyimide resin or epoxy resin is coated on the entire surface by a spin-coat process, and then sintered.
- the insulating resin layer 41 is flattened by a CMP process, a grinding process or a cutting process to expose the upper surface of the conductive posts 31 .
- a conductive pattern layer 51 serving as interconnections made of Cu or Ni is formed by a photolithography process and an electroplating process using the seed metal layer 2 as a cathode electrode.
- the conductive pattern layer 51 is electrically connected to the conductive posts 31 .
- conductive posts 32 made of Cu or Ni are formed on the conductive pattern layer 51 by a photolithography process and an electroplating process using the seed metal layer 2 as a cathode electrode.
- the conductive posts 32 are electrically connected to the conductive pattern layer 51 .
- an insulating resin layer 42 made of polyimide resin or epoxy resin is coated on the entire surface by a spin-coat process, and then sintered.
- the insulating resin layer 42 is flattened by a CMP process, a grinding process or a cutting process to expose the upper surface of the conductive posts 32 .
- a conductive pattern layer 52 serving as interconnections made of Cu or Ni is formed by a photolithography process and an electroplating process using the seed metal layer 2 as a cathode electrode.
- the conductive pattern layer 52 is electrically connected to the conductive posts 32 .
- conductive posts (pads) 6 made of Cu or Ni are formed by a photolithography process and an electroplating process using the seed metal layer 2 as a cathode electrode.
- the conductive posts 6 are electrically connected to the conductive pattern layer 52 .
- thermoplastic resin layer 7 made of thermoplastic polyimide as an adhesive layer is coated on the entire surface to cover the conductive pattern layer 52 and the conductive posts 6 .
- thermoplastic resin layer 7 is flattened by a CMP process, a grinding process or a cutting process to expose the upper surface of the conductive posts 6 .
- an interconnection structure CS 2 is formed by the conductive posts 31 , the insulating resin layer 41 , the conductive pattern layer 51 , the conductive posts 32 , the insulating resin layer 42 , the conductive pattern layer 52 , the conductive posts 6 and the thermoplastic resin layer 7 .
- a semiconductor chip 8 made of silicon associated with electrodes 9 to which solder balls, electroplated balls or stud bumps are applied is faced down to the interconnection structure CS 2 , so that the electrodes 9 of the semiconductor chip 8 correspond to respective ones of the conductive posts 6 of the interconnection structure CS 2 .
- the support substrate 1 and/or the semiconductor chip 8 are heated so as to melt the thermoplastic resin layer 7 .
- the interconnection structure CS 2 thermally expands and shrinks as the support substrate 1 thermally expands and shrinks.
- the support substrate 1 and the semiconductor chip 8 are substantially made of the same material such as silicon so that there is no substantial difference in thermal expansion coefficient therebetween, the semiconductor chip 8 also thermally expands and shrinks as the support substrate I thermally expands and shrinks. Therefore, even if the width of the conductive posts 6 becomes narrower and the spacing (pitch) between the conductive posts 6 becomes smaller, the conductive posts 6 can suitably correspond to the electrodes 9 of the semiconductor chip 8 .
- the interconnection structure CS 2 is sealed by a sealing resin layer 10 by a molding process, a printing process or a potting process.
- the support substrate 1 is removed from the seed metal layer 2 by a CMP process, a grinding process, a cutting process, a wet etching process, a dry etching process, or some combination of the processes.
- a CMP process a grinding process, a cutting process, a wet etching process, a dry etching process, or some combination of the processes.
- the conductive posts 31 ( 32 ) and the border portion between the conductive posts 31 ( 32 ) and the insulating resin layer 41 ( 42 ) are surely covered by the seed metal layer 2 , thus preventing the conductive posts 31 ( 32 ) from being damaged and the border portion between the conductive posts 31 ( 32 ) and the insulating resin layer 41 ( 42 ) from being cracked.
- the seed metal layer 2 is removed from the interconnection structure CS 2 by an etching process to expose the conductive posts 31 .
- external electrodes 11 such as solder balls, electroplated balls or stud bumps are adhered to the conductive posts 31 .
- FIGS. 2A through 2P Note that although a single semiconductor module is illustrated in FIGS. 2A through 2P , a plurality of semiconductor modules are actually manufactured. Therefore, after the process as shown in FIG. 2P , the plurality of semiconductor modules are separated from each other by a dicing process.
- FIGS. 3A , 3 B and 3 C A third embodiment of the method for manufacturing a semiconductor module according to the present invention will be explained next with reference to FIGS. 3A , 3 B and 3 C.
- an interconnection structure CS 1 adhered by a semiconductor chip 8 associated with electrodes 9 is obtained by the processes as shown in FIGS. 1A through 1K , except that a thermoplastic resin layer 7 ′ is formed instead of the insulating resin layer 4 of the interconnection structure CS 1 .
- the interconnection structure CS 1 is formed by the conductive posts 3 , the thermoplastic resin layer 7 ′, the conductive pattern layer 5 , the conductive posts 6 and the thermoplastic resin layer 7 .
- a semiconductor chip 12 made of silicon associated with electrodes 13 to which solder balls, electroplated balls or stud bumps are applied is faced down to the interconnection structure CS 1 so that the electrodes 13 of the semiconductor chip 12 correspond to respective ones of the conductive posts 3 of the interconnection structure CS 1 .
- the semiconductor chip 8 (the interconnection structure CS 1 ) and/or the semiconductor chip 12 are heated so as to melt the thermoplastic resin layer 7 ′.
- the interconnection structure CS 1 since the interconnection structure CS 1 is adhered to the semiconductor chip 12 , the interconnection structure CS 1 thermally expands and shrinks as the semiconductor chip 8 thermally expands and shrinks.
- the semiconductor chip 8 and the semiconductor chip 12 are substantially made of the same material such as silicon so that there is no substantial difference in thermal expansion coefficient therebetween, the semiconductor chip 12 also thermally expands and shrinks as the semiconductor chip 8 thermally expands and shrinks.
- the semiconductor chip 8 and the semiconductor chip 12 can entirely be heated while they are pushed to each other by pushing members (not shown), so that there is no substantial difference in temperature between the semiconductor chip 8 and the semiconductor chip 12 .
- the semiconductor chip 8 and the semiconductor chip 12 are heated to about 300° C. Therefore, even if the width of the conductive posts 3 becomes narrower and the spacing (pitch) between the conductive posts 3 becomes smaller, the conductive posts 3 can suitably correspond to the electrodes 13 of the semiconductor chip 12 .
- thermoplastic resin layer 7 may be remelted; however, in this case, the semiconductor chip 8 is pressed against the semiconductor chip 12 by an XY stage and a suction head, no problem would occur.
- the semiconductor chip 8 along with the interconnection structure CS 1 is mounted on the XY stage and the semiconductor chip 12 is mounted on the suction head.
- the suction head is pressed against the XY stage, so that the semiconductor chip 8 and the semiconductor chip 12 are pressed against each other.
- only the semiconductor chip 12 is heated by a heater incorporated into the suction head, thus completely preventing the thermoplastic resin layer 7 from remelting.
- external electrodes 11 such as solder balls, electroplated balls or stud bumps are adhered to the conductive posts 3 .
- FIGS. 3A through 3C Note that although a single semiconductor module is illustrated in FIGS. 3A through 3C , a plurality of semiconductor modules are actually manufactured. Therefore, after the process as shown in FIG. 3C , the plurality of semiconductor modules are separated from each other by a dicing process.
- FIGS. 4A , 4 B and 4 C A fourth embodiment of the method for manufacturing a semiconductor module according to the present invention will be explained next with reference to FIGS. 4A , 4 B and 4 C.
- an interconnection structure CS 2 adhered by a semiconductor chip 8 associated with electrodes 9 is obtained by the processes as shown in FIGS. 2A through 2N , except that a thermoplastic resin layer 7 ′ is formed instead of the insulating resin layer 4 of the interconnection structure CS 2 .
- the interconnection structure CS 2 is formed by the conductive posts 31 , the thermoplastic resin layer 7 ′, the conductive pattern layer 51 , the conductive posts 32 , the insulating resin layer 42 , the conductive pattern layer 52 , the conductive posts 6 and the thermoplastic resin layer 7 .
- a semiconductor chip 12 made of silicon associated with electrodes 13 to which solder balls, electroplated balls or stud bumps are applied is faced down to the interconnection structure CS 2 , so that the electrodes 13 of the semiconductor chip 12 correspond to respective ones of the conductive posts 31 of the interconnection structure CS 2 .
- the semiconductor chip 8 (the interconnection structure CS 2 ) and/or the semiconductor chip 12 are heated so as to melt the thermoplastic resin layer 7 ′.
- the interconnection structure CS 2 since the interconnection structure CS 2 is adhered to the semiconductor chip 12 , the interconnection structure CS 2 thermally expands and shrinks as the semiconductor chip 8 thermally expands and shrinks.
- the semiconductor chip 8 and the semiconductor chip 12 are substantially made of the same material such as silicon so that there is no substantial difference in thermal expansion coefficient therebetween, the semiconductor chip 12 also thermally expands and shrinks as the semiconductor chip 8 thermally expands and shrinks. Therefore, even if the width of the conductive posts 31 becomes narrower and the spacing (pitch) between the conductive posts 31 becomes smaller, the conductive posts 31 can suitably correspond to the electrodes 13 of the semiconductor chip 12 .
- external electrodes 11 such as solder balls, electroplated balls or stud bumps are adhered to the conductive posts 31 .
- FIGS. 4A through 4C Note that although a single semiconductor module is illustrated in FIGS. 4A through 4C , a plurality of semiconductor modules are actually manufactured. Therefore, after the process as shown in FIG. 4C , the plurality of semiconductor modules are separated from each other by a dicing process.
- FIGS. 5A , 5 B and 5 C A fifth embodiment of the method for manufacturing a semiconductor module according to the present invention will be explained next with reference to FIGS. 5A , 5 B and 5 C.
- an interconnection structure CS 1 adhered to a semiconductor chip 8 associated with electrodes 9 is obtained by the processes as shown in FIGS. 1A through 1K .
- the interconnection structure CS 1 is formed by the conductive posts 3 , the insulating resin layer 4 , the conductive pattern layer 5 , the conductive posts 6 and the thermoplastic resin layer 7 .
- a build-up interconnection structure BCS is formed by a plurality of photosensitive insulating layers 201 , 202 and 203 made of photosensitive epoxy and conductive structures (including a via and interconnect) 204 and 205 made of Cu alternating with the photosensitive insulating layers 201 , 202 and 203 .
- external electrodes 11 such as solder balls, electroplated balls or stud bumps are adhered to the conductive structure 205 .
- FIGS. 5A through 5C Note that although a single semiconductor module is illustrated in FIGS. 5A through 5C , a plurality of semiconductor modules are actually manufactured. Therefore, after the process as shown in FIG. 5C , the plurality of semiconductor modules are separated from each other by a dicing process.
- FIGS. 6A , 6 B and 6 C A sixth embodiment of the method for manufacturing a semiconductor module according to the present invention will be explained next with reference to FIGS. 6A , 6 B and 6 C.
- connection structure CS 2 adhered to a semiconductor chip 8 associated with electrodes 9 is obtained by the processes as shown in FIGS. 2A through 2N .
- the interconnection structure CS 2 is formed by the conductive posts 31 , the insulating resin layer 41 , the conductive pattern layer 51 , the conductive posts 32 , the insulating resin layer 42 , the conductive pattern layer 52 the conductive posts 6 and the thermoplastic resin layer 7 .
- a build-up interconnection structure BCS is formed by a plurality of photosensitive insulating layers 201 , 202 and 203 made of photosensitive epoxy and conductive structures 204 and 205 made of Cu alternating with the photosensitive insulating layers 201 , 202 and 203 .
- external electrodes 11 such as solder balls, electroplated balls or stud bumps are adhered to the conductive structure 205 .
- FIGS. 6A through 6C Note that although a single semiconductor module is illustrated in FIGS. 6A through 6C , a plurality of semiconductor modules are actually manufactured. Therefore, after the process as shown in FIG. 6C , the plurality of semiconductor modules are separated from each other by a dicing process.
- the conductive posts 3 and 31 can be formed by coating a photosensitive resin layer on the seed metal layer 2 and forming throughholes in the photosensitive resin layer by a photolithography process, thus forming the conductive posts 3 and 31 within the throughholes, which would decrease the number of manufacturing steps.
- thermoplastic resin layer 7 can be replaced by a semi-cured stage (B-stage) thermosetting resin layer such as epoxy.
- B-stage semi-cured stage
- the semiconductor chip 8 is adhered to the B-stage thermosetting resin layer without a heating process, and then, this thermosetting resin layer is completely cured by a heating process.
- resin contact layers made of Ti for being in good contact with resin can be included in the conductive posts and the conductive pattern layers, as occasion demands.
- each of the semiconductor chips 8 and 12 can be replaced by another semiconductor device such as ball grid array (BGA) package, a pin grid array (PGA) package or the like.
- the support substrate 1 is made of a material having substantially the same thermal expansion coefficient as that of such semiconductor devices. Further, a plurality of semiconductor devices can be mounted on each surface of the semiconductor module.
- the semiconductor chips 8 and 12 can be made of materials other than silicon; in this case, the support substrate 1 is also made of such materials so that there is no substantial difference in thermal expansion coefficient therebetween.
Abstract
In a method for manufacturing a semiconductor module, a metal layer is formed on a support substrate. Then, first conductive posts and a first insulating layer are formed on the metal layer. The first insulating layer surrounds the sides of the first conductive posts. Then, second conductive posts are formed above the first conductive posts. The second conductive posts are electrically connected to the first conductive posts. Then, a second insulating layer is formed so as to cover the second conductive posts. The second insulating layer is made of adhesive resin. Finally, a semiconductor device is adhered to the second conductive posts by the second insulating layer while a gap between the first semiconductor device and the first insulating layer is sealed by the second insulating layer.
Description
- 1. Field of the Invention
- The present invention relates to a method for manufacturing a semiconductor module.
- 2. Description of the Related Art
- In a prior art method for manufacturing a semiconductor module, a semiconductor chip associated with electrodes is faced down and adhered to a printed circuit board associated with external terminals. Then, a sealing resin is supplied so that a gap between the semiconductor chip and the printed circuit board is sealed (see: JP 2001-345418 A).
- In the above-described prior art method, however, since there is a large difference in thermal expansion coefficient between the semiconductor chip and the printed circuit board, the position accuracy of the electrodes of the semiconductor chip relative to the external terminals of the printed circuit board would deteriorate. As a result, the adhesion accuracy of the electrodes of the semiconductor chip relative to the external electrodes of the printed circuit board would deteriorate so that the quality of the semiconductor module would also deteriorate.
- According to the present invention, in a method for manufacturing a semiconductor module, a metal layer is formed on a support substrate. Then, first conductive posts and a first insulating layer are formed on the metal layer. The first insulating layer surrounds the sides of the first conductive posts. Then, second conductive posts are formed above the first conductive posts. The second conductive posts are electrically connected to the first conductive posts. Then, a second insulating layer is formed so as to cover the second conductive posts. The second insulating layer is made of adhesive resin. Finally, a semiconductor device is adhered to the second conductive posts by the second insulating layer while a gap between the first semiconductor device and the first insulating layer is sealed by the second insulating layer.
- Since there can be no substantial difference in thermal expansion coefficient between the support substrate and the semiconductor device, the position accuracy of electrodes of the semiconductor device relative to external electrodes of the support substrate would improve.
- Note that the support substrate and the metal layer are removed before the semiconductor module is mounted on a printed circuit board or the like. In this case, the spacing between the electrodes of the semiconductor device is usually expanded by a connection structure including the first conductive posts, the first insulating layer, the second conductive posts and the second insulating layer to the spacing between the external electrodes of the interconnection structure. Therefore, the semiconductor module can easily be mounted on the printed circuit board or the like.
- The present invention will be more clearly understood from the description set forth below, with reference to the accompanying drawings, wherein:
-
FIGS. 1A through 1L are cross-sectional views for explaining a first embodiment of the method for manufacturing a semiconductor module according to the present invention; -
FIGS. 2A through 2P are cross-sectional views for explaining a second embodiment of the method for manufacturing a semiconductor module according to the present invention; -
FIGS. 3A , 3B and 3C are cross-sectional views for explaining a third embodiment of the method for manufacturing a semiconductor module according to the present invention; -
FIGS. 4A , 4B and 4C are cross-sectional views for explaining a fourth embodiment of the method for manufacturing a semiconductor module according to the present invention; -
FIGS. 5A , 5B and 5C are cross-sectional views for explaining a fifth embodiment of the method for manufacturing a semiconductor module according to the present invention; and -
FIGS. 6A , 6B and 6C are cross-sectional views for explaining a sixth embodiment of the method for manufacturing a semiconductor module according to the present invention. - A first embodiment of the method for manufacturing a semiconductor module according to the present invention will now be explained with reference to
FIGS. 1A through 1L . - First, referring to
FIG. 1A , a support substrate I such as a silicon wafer is prepared. Then, aseed metal layer 2 made of Cu or Ni as an electroplating intervening layer is deposited on the entire surface by a sputtering process or the like. Then, conductive posts (pads) 3 made of Cu or Ni are formed on theseed metal layer 2 by a photolithography process and an electroplating process using theseed metal layer 2 as a cathode electrode. Note that, if theconductive posts 3 are made of Cu, a thin copper diffusion preventing layer (not shown) made of Ni can also be formed by a photolithography process and an electroplating process using theseed metal layer 2 as a cathode electrode before the formation of theconductive posts 3. - Next, referring to
FIG. 1B , aninsulating resin layer 4 made of polyimide resin or epoxy resin is coated on the entire surface by a spin-coat process, and then, sintered. Note that the insulatingresin layer 4 can be formed by adhering an insulating resin film made of polyimide resin or epoxy resin on the entire surface. - Next, referring to
FIG. 1C , theinsulating resin layer 4 is flattened by a chemical-mechanical polishing (CMP) process, a grinding process or a cutting process to expose the upper surface of theconductive posts 3. - Next, referring to
FIG. 1D , aconductive pattern layer 5 serving as interconnections made of Cu or Ni is formed by a photolithography process and an electroplating process using theseed metal layer 2 as a cathode electrode. Theconductive pattern layer 5 is electrically connected to theconductive posts 3. - Next, referring to
FIG. 1E , conductive posts (pads) 6 made of Cu or Ni are formed by a photolithography process and an electroplating process using theseed metal layer 2 as a cathode electrode. Theconductive posts 6 are electrically connected to theconductive pattern layer 5. - Next, referring to
FIG. 1F , athermoplastic resin layer 7 made of thermoplastic polyimide as an adhesive layer is coated on the entire surface to cover theconductive pattern layer 5 and theconductive posts 6. - Next, referring to
FIG. 1G , thethermoplastic resin layer 7 is flattened by a CMP process, a grinding process or a cutting process to expose the upper surface of theconductive posts 6. Note that, if theconductive posts 6 are made of Cu, a copper oxidation preventing layer (not shown) made of Au can also be formed on the surface of theconductive posts 6 by an electroplating process using theseed metal layer 2 as a cathode electrode. - Thus, an interconnection structure CS1 is formed by the
conductive posts 3, theinsulating resin layer 4, theconductive pattern layer 5, theconductive posts 6 and thethermoplastic resin layer 7. - Next, referring to
FIG. 1H , asemiconductor chip 8 made of silicon associated withelectrodes 9 to which solder balls, electroplated balls or stud bumps are applied is faced down to the interconnection structure CS1, so that theelectrodes 9 of thesemiconductor chip 8 correspond to respective ones of theconductive posts 6 of the interconnection structure CS1. In this case, thesupport substrate 1 and/or thesemiconductor chip 8 are heated so as to melt thethermoplastic resin layer 7. As a result, the electrical connection of theelectrodes 9 of thesemiconductor chip 1 to theconductive posts 6, the adhesion of thesemiconductor chip 8 to the interconnection structure CS1 and the sealing of a gap between thesemiconductor chip 8 and the insulatingresin layer 4 are simultaneously carried out, which would decrease the number of manufacturing steps. - In
FIG. 1H , since the interconnection structure CS1 is adhered to thesupport substrate 1, the interconnection structure CS1 thermally expands and shrinks as thesupport substrate 1 thermally expands and shrinks. In this case, since thesupport substrate 1 and thesemiconductor chip 8 are substantially made of the same material such as silicon so that there is no substantial difference in thermal expansion coefficient therebetween, thesemiconductor chip 8 also thermally expands and shrinks as thesupport substrate 1 thermally expands and shrinks. - Also, even if only one of the
support substrate 1 and thesemiconductor chip 8 is heated or they are heated to different temperatures, thesupport substrate 1 and thesemiconductor chip 8 can be entirely heated while they are pressed against each other by an XY stage and a suction head (not shown), so that there is no substantial difference in temperature between thesupport substrate 1 and thesemiconductor chip 8. For example, thesupport substrate 1 along with the interconnection structure CS1 is mounted on the XY stage and thesemiconductor chip 8 is mounted on the suction head. Then. the suction head is pressed against the XY stage, so that thesupport substrate 1 and thesemiconductor chip 8 are pressed against each other. Then, thesupport substrate 1 is heated by a heater incorporated into the XY stage to about 100° C., while thesemiconductor chip 8 is heated by a heater incorporated into the suction head to about 300° C. Therefore, even if the width of theconductive posts 6 becomes narrower and the spacing (pitch) between theconductive posts 6 becomes smaller, theconductive posts 6 can suitably correspond to theelectrodes 9 of thesemiconductor chip 8. - Next, referring to
FIG. 1I , the interconnection structure CS1 is sealed by a sealingresin layer 10 by a molding process, a printing process or a potting process. In this case, although the back surface of thesemiconductor chip 8 is sealed by the sealingresin layer 10 as shown inFIG. 1I , this back surface can be exposed to the air. - Next, referring to
FIG. 1J , thesupport substrate 1 is removed from theseed metal layer 2 by a CMP process, a grinding process, a cutting process, a wet etching process a dry etching process, or some combination of the processes. For example, if a dry etching process as a final process is performed upon thesupport substrate 1, the etching ratio of thesupport substrate 1 to theseed metal layer 2 is so large that theseed metal layer 2 can surely be left. As a result, theconductive posts 3 and the border portion between theconductive posts 3 and the insulatingresin layer 4 are surely covered by theseed metal layer 2, thus preventing theconductive posts 3 from being damaged and the border portion between theconductive posts 3 and the insulatingresin layer 4 from being cracked. - Next referring to
FIG. 1K , theseed metal layer 2 is removed from the interconnection structure CS1 by an etching process to expose theconductive posts 3. - Finally, referring to
FIG. 1L ,external electrodes 11 such as solder balls, electroplated balls or stud bumps are adhered to theconductive posts 3. - Note that although a single semiconductor module is illustrated in
FIGS. 1A through 1L , a plurality of semiconductor modules are actually manufactured. Therefore, after the process as shown inFIG. 1L , the plurality of semiconductor modules are separated from each other by a dicing process. - A second embodiment of the method for manufacturing a semiconductor module according to the present invention will be explained next with reference to
FIGS. 2A through 2P. - First, referring to
FIG. 2A , in a similar way to those ofFIG. 1A , asupport substrate 1 such as a silicon wafer is prepared. Then, aseed metal layer 2 made of Cu or Ni as an electroplating intervening layer is deposited on the entire surface by a sputtering process or the like. Then, conductive posts (pads) 31 made of Cu or Ni are formed on theseed metal layer 2 by a photolithography process and an electroplating process using theseed metal layer 2 as a cathode electrode. - Next, referring to
FIG. 2B , in a similar way to those ofFIG. 1B , an insulatingresin layer 41 made of polyimide resin or epoxy resin is coated on the entire surface by a spin-coat process, and then sintered. - Next, referring to
FIG. 2C , in a similar way to those ofFIG. 1C , the insulatingresin layer 41 is flattened by a CMP process, a grinding process or a cutting process to expose the upper surface of the conductive posts 31. - Next, referring to
FIG. 2D , in a similar way to those ofFIG. 1D , aconductive pattern layer 51 serving as interconnections made of Cu or Ni is formed by a photolithography process and an electroplating process using theseed metal layer 2 as a cathode electrode. Theconductive pattern layer 51 is electrically connected to the conductive posts 31. - Next, referring to
FIG. 2E ,conductive posts 32 made of Cu or Ni are formed on theconductive pattern layer 51 by a photolithography process and an electroplating process using theseed metal layer 2 as a cathode electrode. Theconductive posts 32 are electrically connected to theconductive pattern layer 51. - Next, referring to
FIG. 2F , an insulatingresin layer 42 made of polyimide resin or epoxy resin is coated on the entire surface by a spin-coat process, and then sintered. - Next, referring to
FIG. 2G , the insulatingresin layer 42 is flattened by a CMP process, a grinding process or a cutting process to expose the upper surface of the conductive posts 32. - Next, referring to
FIG. 2H , aconductive pattern layer 52 serving as interconnections made of Cu or Ni is formed by a photolithography process and an electroplating process using theseed metal layer 2 as a cathode electrode. Theconductive pattern layer 52 is electrically connected to the conductive posts 32. - Next, referring to
FIG. 2I , in a similar way to those ofFIG. 1E , conductive posts (pads) 6 made of Cu or Ni are formed by a photolithography process and an electroplating process using theseed metal layer 2 as a cathode electrode. Theconductive posts 6 are electrically connected to theconductive pattern layer 52. - Next, referring to
FIG. 2J , in a similar way to those ofFIG. 1F , athermoplastic resin layer 7 made of thermoplastic polyimide as an adhesive layer is coated on the entire surface to cover theconductive pattern layer 52 and theconductive posts 6. - Next, referring to
FIG. 2K , in a similar way to those ofFIG. 1G , thethermoplastic resin layer 7 is flattened by a CMP process, a grinding process or a cutting process to expose the upper surface of theconductive posts 6. - Thus, an interconnection structure CS2 is formed by the
conductive posts 31, the insulatingresin layer 41, theconductive pattern layer 51, theconductive posts 32, the insulatingresin layer 42, theconductive pattern layer 52, theconductive posts 6 and thethermoplastic resin layer 7. - Next, referring to
FIG. 2L , in a similar way to those ofFIG. 1H , asemiconductor chip 8 made of silicon associated withelectrodes 9 to which solder balls, electroplated balls or stud bumps are applied is faced down to the interconnection structure CS2, so that theelectrodes 9 of thesemiconductor chip 8 correspond to respective ones of theconductive posts 6 of the interconnection structure CS2. In this case, thesupport substrate 1 and/or thesemiconductor chip 8 are heated so as to melt thethermoplastic resin layer 7. As a result, the electrical connection of theelectrodes 9 of thesemiconductor chip 1 to theconductive posts 6, the adhesion of thesemiconductor chip 8 to the interconnection structure CS and the sealing of a gap between thesemiconductor chip 8 and the insulatingresin layer 42 are simultaneously carried out, which would decrease the number of manufacturing steps. - Even in
FIG. 2L , in a similar way to those ofFIG. 1H , since the interconnection structure CS2 is adhered to thesupport substrate 1, the interconnection structure CS2 thermally expands and shrinks as thesupport substrate 1 thermally expands and shrinks. In this case, since thesupport substrate 1 and thesemiconductor chip 8 are substantially made of the same material such as silicon so that there is no substantial difference in thermal expansion coefficient therebetween, thesemiconductor chip 8 also thermally expands and shrinks as the support substrate I thermally expands and shrinks. Therefore, even if the width of theconductive posts 6 becomes narrower and the spacing (pitch) between theconductive posts 6 becomes smaller, theconductive posts 6 can suitably correspond to theelectrodes 9 of thesemiconductor chip 8. - Next, referring to
FIG. 2M , in a similar way to those ofFIG. 1I , the interconnection structure CS2 is sealed by a sealingresin layer 10 by a molding process, a printing process or a potting process. - Next, referring to
FIG. 2N , in a similar way to those ofFIG. 1J , thesupport substrate 1 is removed from theseed metal layer 2 by a CMP process, a grinding process, a cutting process, a wet etching process, a dry etching process, or some combination of the processes. As a result, the conductive posts 31 (32) and the border portion between the conductive posts 31 (32) and the insulating resin layer 41 (42) are surely covered by theseed metal layer 2, thus preventing the conductive posts 31 (32) from being damaged and the border portion between the conductive posts 31 (32) and the insulating resin layer 41 (42) from being cracked. - Next, referring to
FIG. 2O , in a similar way to those ofFIG. 1K , theseed metal layer 2 is removed from the interconnection structure CS2 by an etching process to expose the conductive posts 31. - Finally, referring to
FIG. 2P , in a similar way to those ofFIG. 1L ,external electrodes 11 such as solder balls, electroplated balls or stud bumps are adhered to the conductive posts 31. - Note that although a single semiconductor module is illustrated in
FIGS. 2A through 2P , a plurality of semiconductor modules are actually manufactured. Therefore, after the process as shown inFIG. 2P , the plurality of semiconductor modules are separated from each other by a dicing process. - A third embodiment of the method for manufacturing a semiconductor module according to the present invention will be explained next with reference to
FIGS. 3A , 3B and 3C. - First, referring to
FIG. 3A , an interconnection structure CS1 adhered by asemiconductor chip 8 associated withelectrodes 9 is obtained by the processes as shown inFIGS. 1A through 1K , except that athermoplastic resin layer 7′ is formed instead of the insulatingresin layer 4 of the interconnection structure CS1. - Thus, the interconnection structure CS1 is formed by the
conductive posts 3, thethermoplastic resin layer 7′, theconductive pattern layer 5, theconductive posts 6 and thethermoplastic resin layer 7. - Next, referring to
FIG. 3B , asemiconductor chip 12 made of silicon associated withelectrodes 13 to which solder balls, electroplated balls or stud bumps are applied is faced down to the interconnection structure CS1 so that theelectrodes 13 of thesemiconductor chip 12 correspond to respective ones of theconductive posts 3 of the interconnection structure CS1. In this case, the semiconductor chip 8 (the interconnection structure CS1) and/or thesemiconductor chip 12 are heated so as to melt thethermoplastic resin layer 7′. As a result, the electrical connection of theelectrodes 13 of thesemiconductor chip 12 to theconductive posts 3, the adhesion of thesemiconductor chip 12 to the interconnection structure CS1 and the sealing of a gap between thesemiconductor chip 12 and thethermoplastic resin layer 7′ are simultaneously carried out, which would decrease the number of manufacturing steps. - In
FIG. 3B , since the interconnection structure CS1 is adhered to thesemiconductor chip 12, the interconnection structure CS1 thermally expands and shrinks as thesemiconductor chip 8 thermally expands and shrinks. In this case, since thesemiconductor chip 8 and thesemiconductor chip 12 are substantially made of the same material such as silicon so that there is no substantial difference in thermal expansion coefficient therebetween, thesemiconductor chip 12 also thermally expands and shrinks as thesemiconductor chip 8 thermally expands and shrinks. - Also, even if only one of the
semiconductor chip 8 and thesemiconductor chip 12 is heated or they are heated to different temperatures, thesemiconductor chip 8 and thesemiconductor chip 12 can entirely be heated while they are pushed to each other by pushing members (not shown), so that there is no substantial difference in temperature between thesemiconductor chip 8 and thesemiconductor chip 12. For example, thesemiconductor chip 8 and thesemiconductor chip 12 are heated to about 300° C. Therefore, even if the width of theconductive posts 3 becomes narrower and the spacing (pitch) between theconductive posts 3 becomes smaller, theconductive posts 3 can suitably correspond to theelectrodes 13 of thesemiconductor chip 12. - Further, in
FIG. 3B , when thesemiconductor chip 8 and/or thesemiconductor chip 12 are heated, thethermoplastic resin layer 7 may be remelted; however, in this case, thesemiconductor chip 8 is pressed against thesemiconductor chip 12 by an XY stage and a suction head, no problem would occur. In this case, actually, thesemiconductor chip 8 along with the interconnection structure CS1 is mounted on the XY stage and thesemiconductor chip 12 is mounted on the suction head. Then, the suction head is pressed against the XY stage, so that thesemiconductor chip 8 and thesemiconductor chip 12 are pressed against each other. Then, only thesemiconductor chip 12 is heated by a heater incorporated into the suction head, thus completely preventing thethermoplastic resin layer 7 from remelting. - Finally, referring to
FIG. 3C ,external electrodes 11 such as solder balls, electroplated balls or stud bumps are adhered to theconductive posts 3. - Note that although a single semiconductor module is illustrated in
FIGS. 3A through 3C , a plurality of semiconductor modules are actually manufactured. Therefore, after the process as shown inFIG. 3C , the plurality of semiconductor modules are separated from each other by a dicing process. - A fourth embodiment of the method for manufacturing a semiconductor module according to the present invention will be explained next with reference to
FIGS. 4A , 4B and 4C. - First, referring to
FIG. 4A , an interconnection structure CS2 adhered by asemiconductor chip 8 associated withelectrodes 9 is obtained by the processes as shown inFIGS. 2A through 2N , except that athermoplastic resin layer 7′ is formed instead of the insulatingresin layer 4 of the interconnection structure CS2. - Thus, the interconnection structure CS2 is formed by the
conductive posts 31, thethermoplastic resin layer 7′, theconductive pattern layer 51, theconductive posts 32, the insulatingresin layer 42, theconductive pattern layer 52, theconductive posts 6 and thethermoplastic resin layer 7. - Next, referring to
FIG. 4B , asemiconductor chip 12 made of silicon associated withelectrodes 13 to which solder balls, electroplated balls or stud bumps are applied is faced down to the interconnection structure CS2, so that theelectrodes 13 of thesemiconductor chip 12 correspond to respective ones of theconductive posts 31 of the interconnection structure CS2. In this case, the semiconductor chip 8 (the interconnection structure CS2) and/or thesemiconductor chip 12 are heated so as to melt thethermoplastic resin layer 7′. As a result, the electrical connection of theelectrodes 13 of thesemiconductor chip 12 to theconductive posts 31, the adhesion of thesemiconductor chip 12 to the interconnection structure CS2 and the sealing of a gap between thesemiconductor chip 12 and thethermoplastic resin layer 7′ are simultaneously carried out, which would decrease the number of manufacturing steps. - In
FIG. 4B , since the interconnection structure CS2 is adhered to thesemiconductor chip 12, the interconnection structure CS2 thermally expands and shrinks as thesemiconductor chip 8 thermally expands and shrinks. In this case, since thesemiconductor chip 8 and thesemiconductor chip 12 are substantially made of the same material such as silicon so that there is no substantial difference in thermal expansion coefficient therebetween, thesemiconductor chip 12 also thermally expands and shrinks as thesemiconductor chip 8 thermally expands and shrinks. Therefore, even if the width of theconductive posts 31 becomes narrower and the spacing (pitch) between theconductive posts 31 becomes smaller, theconductive posts 31 can suitably correspond to theelectrodes 13 of thesemiconductor chip 12. - Finally, referring to
FIG. 4C ,external electrodes 11 such as solder balls, electroplated balls or stud bumps are adhered to the conductive posts 31. - Note that although a single semiconductor module is illustrated in
FIGS. 4A through 4C , a plurality of semiconductor modules are actually manufactured. Therefore, after the process as shown inFIG. 4C , the plurality of semiconductor modules are separated from each other by a dicing process. - A fifth embodiment of the method for manufacturing a semiconductor module according to the present invention will be explained next with reference to
FIGS. 5A , 5B and 5C. - First, referring to
FIG. 5A , an interconnection structure CS1 adhered to asemiconductor chip 8 associated withelectrodes 9 is obtained by the processes as shown inFIGS. 1A through 1K . - Thus, the interconnection structure CS1 is formed by the
conductive posts 3, the insulatingresin layer 4, theconductive pattern layer 5, theconductive posts 6 and thethermoplastic resin layer 7. - Next, referring to
FIG. 5B , a build-up interconnection structure BCS is formed by a plurality of photosensitive insulatinglayers layers - Finally, referring to
FIG. 5C ,external electrodes 11 such as solder balls, electroplated balls or stud bumps are adhered to theconductive structure 205. - Note that although a single semiconductor module is illustrated in
FIGS. 5A through 5C , a plurality of semiconductor modules are actually manufactured. Therefore, after the process as shown inFIG. 5C , the plurality of semiconductor modules are separated from each other by a dicing process. - A sixth embodiment of the method for manufacturing a semiconductor module according to the present invention will be explained next with reference to
FIGS. 6A , 6B and 6C. - First, referring to
FIG. 6A , a connection structure CS2 adhered to asemiconductor chip 8 associated withelectrodes 9 is obtained by the processes as shown inFIGS. 2A through 2N . - Thus, the interconnection structure CS2 is formed by the
conductive posts 31, the insulatingresin layer 41, theconductive pattern layer 51, theconductive posts 32, the insulatingresin layer 42, theconductive pattern layer 52 theconductive posts 6 and thethermoplastic resin layer 7. - Next, referring to
FIG. 6B , a build-up interconnection structure BCS is formed by a plurality of photosensitive insulatinglayers conductive structures layers - Finally, referring to
FIG. 6C ,external electrodes 11 such as solder balls, electroplated balls or stud bumps are adhered to theconductive structure 205. - Note that although a single semiconductor module is illustrated in
FIGS. 6A through 6C , a plurality of semiconductor modules are actually manufactured. Therefore, after the process as shown inFIG. 6C , the plurality of semiconductor modules are separated from each other by a dicing process. - In the above-described first, second, fifth and sixth embodiments, the
conductive posts seed metal layer 2 and forming throughholes in the photosensitive resin layer by a photolithography process, thus forming theconductive posts - Also, in the above-described embodiments, the
thermoplastic resin layer 7 can be replaced by a semi-cured stage (B-stage) thermosetting resin layer such as epoxy. In this case, thesemiconductor chip 8 is adhered to the B-stage thermosetting resin layer without a heating process, and then, this thermosetting resin layer is completely cured by a heating process. - Further, in the above-described embodiments, resin contact layers made of Ti for being in good contact with resin can be included in the conductive posts and the conductive pattern layers, as occasion demands.
- Additionally, each of the
semiconductor chips support substrate 1 is made of a material having substantially the same thermal expansion coefficient as that of such semiconductor devices. Further, a plurality of semiconductor devices can be mounted on each surface of the semiconductor module. - Still further, in the above-described embodiments, the
semiconductor chips support substrate 1 is also made of such materials so that there is no substantial difference in thermal expansion coefficient therebetween.
Claims (6)
1. A semiconductor module comprising:
an interconnection structure including first and second conductive posts electrically connected to each other on front and back surfaces, respectively, of said connection structure, and first and second insulating layers surrounding sides of said first and second conductive poles, respectively, said second insulating layer being made of adhesive resin;
a first semiconductor device adhered to said second conductive posts by said second insulating layer so that a gap between said first semiconductor device and said interconnection structure is sealed by said second insulating layer.
2. The semiconductor module as set forth in claim 1 , further comprising:
a metal layer formed on the back surface of said interconnection structure; and
a support substrate formed on said metal layer.
3. The semiconductor module as set forth in claim 1 , further comprising external electrodes on at least a part of said first conductive posts.
4. The semiconductor module as set forth in claim 1 , wherein said first insulating layer is made of adhesive resin, and said semiconductor module further comprises a second semiconductor device adhered to a part of said first conductive posts by said first insulating layer so that a gap between said second semiconductor device and said interconnection structure is sealed by said first insulating layer.
5. The semiconductor module as set forth in claim 1 further comprising a build-up interconnection structure on said first conductive posts and said first insulating layer.
6. The semiconductor module as set forth in claim 5 , further comprising external electrodes on said build-up interconnection structure.
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Also Published As
Publication number | Publication date |
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CN1953152A (en) | 2007-04-25 |
US20070086166A1 (en) | 2007-04-19 |
JP5065586B2 (en) | 2012-11-07 |
CN101504937A (en) | 2009-08-12 |
JP2007115774A (en) | 2007-05-10 |
CN100530581C (en) | 2009-08-19 |
US7598117B2 (en) | 2009-10-06 |
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