US20090296501A1 - Method and Apparatus for Implementing Write Levelization in Memory Subsystems - Google Patents
Method and Apparatus for Implementing Write Levelization in Memory Subsystems Download PDFInfo
- Publication number
- US20090296501A1 US20090296501A1 US12/127,059 US12705908A US2009296501A1 US 20090296501 A1 US20090296501 A1 US 20090296501A1 US 12705908 A US12705908 A US 12705908A US 2009296501 A1 US2009296501 A1 US 2009296501A1
- Authority
- US
- United States
- Prior art keywords
- signal
- strobe signal
- value
- error
- recited
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 26
- 238000009825 accumulation Methods 0.000 claims abstract description 69
- 238000011084 recovery Methods 0.000 claims abstract description 33
- 238000005070 sampling Methods 0.000 claims description 15
- 230000004044 response Effects 0.000 claims description 10
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 5
- 230000001419 dependent effect Effects 0.000 claims description 4
- 240000007320 Pinus strobus Species 0.000 description 44
- 238000010586 diagram Methods 0.000 description 23
- 230000000630 rising effect Effects 0.000 description 10
- 230000003111 delayed effect Effects 0.000 description 6
- 230000007423 decrease Effects 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- 230000006870 function Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012935 Averaging Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 230000001934 delay Effects 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000009249 intrinsic sympathomimetic activity Effects 0.000 description 1
- 230000006855 networking Effects 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000012549 training Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1689—Synchronisation and timing concerns
Definitions
- This invention relates to memory subsystems and, more particularly, to write levelization mechanisms for memory subsystems.
- DDR SDRAM Double Data Rate Synchronous Dynamic Random Access Memory
- DDR2 SDRAM Double Data Rate Synchronous Dynamic Random Access Memory
- the signals are phase aligned due, at least in part, to the fact that the trace lengths associated with the signals are matched. Since DDR3 SDRAM systems do not have matched trace lengths for these signals, DDR3 SDRAM memory architectures may include mechanisms for performing write levelization to phase align the memory clock signal and the DQS signals at the memory devices.
- a memory controller includes a clock generator configured to generate the clock signal, and a respective strobe signal generator configured to generate each strobe signal.
- the memory controller further includes a phase recovery engine associated with each strobe signal generator that is configured to receive an error signal from a corresponding memory device.
- the error signal conveys an error indication indicative of an alignment of the strobe signal relative to the clock signal for each of a plurality of cycles of the strobe signal.
- the phase recovery engine includes an accumulator configured to maintain an accumulation value that depends upon the error indications for the plurality of cycles of the strobe signal.
- the strobe signal generator is configured to control a delay associated with generation of the strobe signal depending upon the accumulation value.
- FIG. 1 is a block diagram of one embodiment of a memory subsystem including a memory controller and one or more memory modules;
- FIGS. 2A-C are timing diagrams illustrating the alignment of a data strobe (DQS) signal relative to a memory clock (MemClk) signal, according to one embodiment
- FIG. 3 is a block diagram of one embodiment of a memory clock generator, a strobe signal generator, and a phase recovery engine;
- FIG. 4 is a block diagram of one embodiment of a memory device of a memory module
- FIG. 5 is a flow diagram illustrating a method for performing write levelization in a memory subsystem, according to various embodiments
- FIGS. 6A and 6B are timing diagrams illustrating a generation of an error signal indicative of alignment between a DQS signal and the MemClk signal;
- FIG. 7 is a block diagram of one particular implementation of a memory clock generator, a strobe signal generator and a phase recovery engine;
- FIG. 8 illustrates fields of an accumulation value maintained by an accumulator
- FIG. 9 is a flow diagram illustrating operations associated with the embodiment of FIG. 7 ;
- FIGS. 10 and 11 are timing diagrams illustrating signals associated with the embodiment of FIG. 7 ;
- FIG. 12 is a block diagram illustrating a further particular implementation of a strobe signal generator and a phase recovery engine
- FIG. 13 is a timing diagram illustrating a repeating sequence of DQS cycles followed by a delay period, according to one embodiment
- FIG. 14 is a block diagram illustrating a particular implementation of an accumulator.
- FIG. 15 is a block diagram of one embodiment of a computer system including a processor and a system memory.
- memory controller 100 may include a clock generator 102 , a memory clock generator 105 , a plurality of data strobe signal generators 110 A-X, and a plurality of phase recovery engines 120 A-X.
- Memory modules 180 may each include a plurality of memory devices 150 A-X.
- memory controller 100 may support a write levelization algorithm to phase align a memory clock (MemClk) signal and corresponding data strobe (DQS) signals at the memory devices 150 to effectively perform memory read and write operations.
- MemClk memory clock
- DQS data strobe
- clock generator 102 may be coupled to memory clock generator 105 , strobe signal generators 110 A-X, and phase recovery engines 120 A-X.
- Memory clock generator 105 may be coupled to the memory devices 150 A-X.
- Each of the memory devices 150 A-X of memory modules 180 may be coupled to a corresponding strobe signal generator 110 via a DQS signal line, and to a corresponding phase recovery engine 120 via an Error signal line.
- memory device 150 X may be coupled to strobe signal generator 110 X and phase recovery engine 120 X.
- Each of the phase recovery engines 120 A-X may also be coupled to a corresponding strobe signal generator 110 .
- Memory controller 100 and memory modules 180 may be included in any of various types of computing or processing systems, e.g., a personal computer (PC), a workstation, a server blade, a portable computing device, a game console, a system-on-a-chip (SoC), a television system, an audio system, among others.
- Memory controller 100 and memory modules 180 may be connected to a circuit board or motherboard of a computing system.
- memory controller 100 may be integrated within a processor of the computer system.
- memory controller 100 may be implemented externally to the processor via a separate chipset.
- Memory modules 180 may form the main system memory of the computer system (e.g., system memory 640 of FIG. 14 ).
- Memory modules 180 may be Dual In-line Memory Modules (DIMMs), and memory devices 150 may be RAM devices, such as DDR3 SDRAM devices. It is noted, however, that in other embodiments the write levelization algorithm may be implemented in memory subsystems that include other types of memory to phase align a MemClk signal and the corresponding DQS signals at the memory devices.
- DIMMs Dual In-line Memory Modules
- RAM devices such as DDR3 SDRAM devices.
- the write levelization algorithm may be implemented in memory subsystems that include other types of memory to phase align a MemClk signal and the corresponding DQS signals at the memory devices.
- clock generator 102 may generate a clock signal (PClk) that serves as the internal clock of memory controller 100 .
- the internal clock may run at 1600 Mhz.
- the internal clock signal may be provided to various components of memory controller 100 , such as strobe signal generators 110 and memory clock generator 105 .
- the internal clock signal may serve as the timing reference used by memory clock generator 105 to generate the memory clock (MemClk) signal.
- the MemClk signal is provided to each of the memory devices 150 .
- the MemClk signal may be generated at half the frequency of the internal clock signal PClk (e.g., at 800 MHz).
- the internal clock signal (PClk) may also serve as a timing reference used by each of the strobe signal generators 110 to generate a respective data strobe (DQS) signal that is provided to a corresponding memory device 150 .
- DQS data strobe
- strobe signal generator 110 A provides a corresponding DQS signal to memory device 150 A.
- the DQS signals are used to control data read and write operations associated with memory devices 150 during normal modes of operation of the memory subsystem, as will be appreciated by one of skill in the art.
- the DQS signals may be provided as test signals to sample the MemClk signal at the memory devices 150 to thereby determine the phase alignment of each DQS signal relative to the MemClk signal.
- each strobe signal generator 110 may generate its corresponding DQS signal in the form of cycles (or strobes) having the same frequency as the MemClk signal.
- the DQS signals and the MemClk signal may start out aligned at memory controller 100 ; however, when the signals arrive at the memory devices 150 , an individual DQS signal may be ahead of the MemClk, as illustrated in FIG. 2A , or behind the MemClk, as illustrated in FIG. 2B .
- Write levelization may be implemented in the memory subsystem to either delay or speed up an individual DQS signal to phase align the DQS signal and the MemClk, as will be further described below. After write levelization, each DQS signal may be aligned relative to the MemClk when received at the corresponding memory device 150 , as illustrated in FIG. 2C . Subsequent to this initialization procedure, the memory subsystem may enter a mode of operation that allows normal data read and write operations to be performed.
- Phase recovery engines 120 may be used to interpret and process Error signals received from the corresponding memory devices 150 to implement the write levelization algorithm. Each phase recovery engine 120 may receive an indication of an error in response to each cycle of the DQS signal sent to the corresponding memory device 150 . The phase recovery engine may then process the error indications to generate alignment information that determines whether to increase or decrease a delay associated with the corresponding DQS signal to achieve phase alignment relative to the MemClk signal. It is noted that in various embodiments the feedback path for receiving the Error signals during the write levelization procedure may be the same lines used for data transfers during normal memory read and write operations, e.g., the bidirectional data (DQ) lines in memory subsystems. Further details regarding specific implementations of the write levelization procedure are described below in conjunction with FIGS. 3-14 .
- FIG. 1 the components described with reference to FIG. 1 are meant to be exemplary only, and are not intended to limit the invention to any specific set of components or configurations.
- one or more of the components described may be omitted, combined, modified, or additional components may be included, as desired.
- FIG. 3 is a generalized block diagram of one embodiment of a memory clock generator 105 , a strobe signal generator 110 (e.g., representative of any of strobe signal generators 110 A- 110 X of FIG. 1 ), and a phase recovery engine 120 (e.g., representative of the corresponding phase recovery engine 120 A- 120 X).
- FIG. 4 is a block diagram of one embodiment of a memory device 150 (e.g., representative of the corresponding memory device 150 A- 150 X).
- memory clock generator 105 may include a delay-locked loop (DLL) device 206 , a divide-by-two divider circuit 207 , and a flip-flop 208 .
- DLL delay-locked loop
- strobe signal generator 110 may include a DLL device 215 , a divide-by-two divider circuit 216 , and a flip-flop 217 .
- Phase recovery engine 120 is shown with an error value generator 222 and an accumulator 225 .
- memory device 150 is shown with a flip-flop 255 . It is noted that various circuitry that may be used in association with specific implementations of the illustrated circuit components such as signal drivers, bias circuitry, multiplexers, etc. may be omitted from the diagram for simplicity and clarity.
- memory clock generator 105 of memory controller 100 provides the MemClk signal (at half the frequency of PClk, in this embodiment) to each memory device 150 of memory modules 180 , and each strobe signal generator 110 provides to the corresponding memory device 150 a respective DQS signal that cycles at the frequency of the MemClk signal (block 402 ).
- the DQS signals and the MemClk signal are provided to generate error indications to determine the phase alignment of each DQS signal relative to the MemClk signal at the corresponding memory device 150 .
- each rising edge of a cycle of the DQS signal provided to memory device 150 results in the sampling of the MemClk signal, e.g., using flip-flop 255 .
- phase recovery engine 120 may receive error indications from the memory device 150 (block 404 ).
- the rising edge of each cycle of the DQS signal causes flip flop 255 to sample the MemClk signal, and thus the corresponding Error signal is driven either low or high depending upon the alignment of the DQS signal relative to the MemClk signal at the memory device 150 . For example, as illustrated in FIG.
- MemClk may be sampled low, and thus the Error signal provided from the corresponding memory device 150 is driven low.
- the MemClk signal is sampled high, and thus the Error signal is driven high.
- FIG. 6B illustrates a similar example where the MemClk signal is first sampled high, resulting in a high Error signal, and subsequently sampled low, resulting in a low Error signal.
- the corresponding phase recovery engine 120 may update an associated accumulation value (block 406 ). For example, in the embodiment of FIG. 3 , an accumulation value (which may be initialized with a particular starting value, as described below) may be maintained by accumulator 225 .
- error value generator 222 of phase recovery engine 120 associates the state of the Error signal with either a first value (such as ⁇ 1 if the Error signal is high) or a second value (such as +1 if the Error signal is low), and provides the first or second value to accumulator 225 .
- Accumulator 225 may add the value provided from error value generator 222 (or a value dependent thereon) with the then-current accumulation value to derive an updated accumulation value (e.g., upon each cycle of the DQS signal). It is thus noted that the accumulation value maintained by accumulator 225 either increases or decreases depending on the phase alignment of the DQS signal relative to the MemClk signal. The accumulation value, or a signal dependent thereon, is correspondingly provided to DLL 215 to control a delay associated with the generation of the corresponding DQS signal. In this manner, the alignment of the DQS signal relative to the MemClk signal may be adjusted and controlled in a feedback fashion to achieve phase alignment.
- FIG. 7 is a block diagram of one particular implementation of memory clock generator 105 , strobe signal generator 110 , and phase recovery engine 120 . Circuit portions that correspond to those of FIG. 3 are numbered identically for simplicity and clarity.
- memory clock generator 206 is shown with a divide-by-two clock divider 701 coupled to an output of DLL 206 .
- Strobe signal generator 110 is shown with DLL 215 , a flip-flop 702 , a 2:1 multiplexer 704 , and an inverter 706 .
- Phase recovery engine 120 is shown with a gain unit 710 coupled between error value generator 222 and accumulator 225 .
- accumulator 225 is configured to maintain an accumulation value including three fields.
- the accumulation value maintained by accumulator 225 is a 10-bit value formed by bits [9:0].
- Bits [2:0] referred to herein as the sub-fine delay bits (or field), provide averaging for noise and provide delay between the update of DLL 215 and a corresponding return in the error signal, thereby providing stability.
- Bits [7:3] control the delay associated with DLL 215 .
- Bits [9:8] are provided to control the coarse delay, as discussed further below.
- sub-fine delay bits are formed by bits [2:0]
- sub-fine delay bits [n:0] may be formed by a different number of one or more bits.
- DLL control bits [c:n+1] and the coarse delay bits [M:c+1] may also each be formed by a different number of one or more bits.
- error value generator 222 may receive an error indication conveyed in the Error signal upon each rising edge of the corresponding DQS signal (block 432 ). When the received Error signal is in a low state, it may indicate that the DQS signal received at the corresponding memory device 150 is ahead of the MemClk signal (as illustrated in FIG. 2A ). When the received Error signal is in a high state, it may indicate that the DQS signal is behind the MemClk signal (as illustrated in FIG. 2B ).
- Error value generator 222 may associate the error indication with a first value, such as ⁇ 1, when the error signal is high (blocks 434 and 436 ), or a second value, such as +1, when the error signal is low (blocks 434 and 438 ).
- the first or second value from error value generator 222 is provided to gain unit 710 , which amplifies (or attenuates) the provided value (block 439 ).
- gain unit 710 may increase the value +1 to +8, or the value ⁇ 1 to ⁇ 8, and provide the resulting amplified value to accumulator 225 .
- accumulator 225 sums the amplified value from gain unit 710 with its then-current accumulation value to derive an updated accumulation value (block 440 ). It is noted that the particular amount of gain as provided by gain unit 710 may control the extent to which the accumulation value increases or decreases upon each sampling of the DQS signal.
- the amount of gain provided by gain block 710 may be programmable.
- the sub-fine delay field of the accumulation value as maintained by accumulator 225 may include one or more additional bits (e.g., denoted as bits [ ⁇ 1] and [ ⁇ 2] in FIG. 8 ) to allow accumulation of such sub-unity values).
- bits [7:3] of the accumulation value are provided to control the delay associated with an output signal (DllClk) of DLL 215 .
- the DllClk signal may be controllably delayed in fractional increments of 1/32 of a unit interval (UI), where a unit interval equals the period of the internal clock PClk.
- FIG. 10 illustrates several versions of the DilClk signal, delayed from between 0/32 to 31/32 of a unit interval with respect to the PClk signal.
- DLL 215 generates the DllClk signal according to one of these selected delays, and provides such signal to control the clocking of flip flop 702 .
- FIG. 10 also illustrates the MemClk signal as output from divide-by-two circuit 701 . As shown, in this particular embodiment, the MemClk signal has a frequency that is half that of the internal clock PClk.
- bit [8] of the accumulation value is provided to a select input of multiplexer 704 .
- Multiplexer 704 receives the MemClk signal at one of its inputs, and an inverted version of the MemClk signal at its other input.
- multiplexer 704 causes either the MemClk signal or the inverted version of the MemClk signal to be provided as an input to flip flop 702 .
- strobe signal generator may separately generate a duplicate version of the MemClk signal using a separate divide-by-two circuit that receives the internal clock PClk and divides its frequency by two.
- flip flop 702 samples either the MemClk signal or the inverted version of the MemClk signal, depending upon bit [8] of the accumulation value.
- the DQS signal as represented by the output of flip flop 702 thus cycles at a frequency of the MemClk signal, with a controlled delay of between 0/32 UI to 63/32 UI in 1/32 UI increments, based upon the accumulation value.
- the delay may be conceptually controlled from 0/32 UI to 127/32 UI (and so on for further bits that may be provided in the coarse delay field, as desired).
- the DllClk signal generated by DLL 215 is associated with a delay of 1/32 UI and bit [8] of the accumulation value is low, the MemClk signal is sampled high upon the first illustrated rising edge of the DllClk signal (having a delay corresponding to 1/32 UI), thus causing the DQS signal to be driven high.
- the MemClk signal is sampled low, thus causing the DQS signal to transition low, and so on.
- a DQS signal as represented by the output of flip flop 702 with a delay corresponding to 1/32 UI may be generated.
- bit [8] of the accumulation value is high, the first rising edge of the DllClk signal results in the sampling of the low state of the inverted version of the MemClk signal (i.e., MemClk ), thus causing the DQS signal to be driven low.
- the MemClk MemClk signal is sampled high, thus causing the DQS signal to transition high, and so on.
- a DQS signal with a delay corresponding to 33/32 UI may be generated.
- Other delayed versions of the DQS signal may be generated similarly.
- the accumulation value maintained by accumulator 225 will converge to a value that achieves and maintains alignment of the DQS signal and the MemClk signal at the corresponding memory device 150 . If, for example, the DQS signal is significantly ahead of the MemClk signal, the accumulation value will gradually increase, which will cause strobe signal generator 110 to output increasingly delayed versions of the DQS signal (i.e., to retard or delay the DQS signal).
- the accumulation value will gradually decrease, which will cause strobe signal generator 110 to decrease the delay associated with (i.e., advance or speed up) the DQS signal.
- the accumulation value will converge to a value that maintains alignment between the DQS signal and the MemClk signal as received at the corresponding memory device 150 .
- the sub-fine delay bits [n: 0 ] of the accumulation value maintained by accumulator 225 provide averaging for noise and further provide stability.
- the sub-fine delay bits are formed by a total of three bits (e.g., [2:0]).
- the bits are initially all logic 0 (i.e., “000”), it will take eight consecutive “+1” error values from error value generator 222 /gain unit 710 to cause bit 3 of the accumulation value to increment (which causes a corresponding change to the delay associated with the DQS signal).
- the sub-fine delay bits are initially all logic 1 (i.e., “111”), it will take eight “ ⁇ 1” error values from error value generator 222 /gain unit 710 to cause bit 3 to decrement.
- the accumulation value converges to a value that maintains alignment between the DQS signal and the MemClk signal, noise in the system that may cause random incrementing and decrementing of the accumulation value may not result in any change to the selected delay of the DQS signal (e.g., since bits [8:3] of the accumulation value may not be affected).
- This averaging also acts to stabilize any external delay in the loop.
- DLL 215 is controllable to generate the DllClk signal with a delay of from 0/32 UI to 31/32 UI.
- the coarse delay bit [c+1] of the accumulation value e.g., bit [8] is used to control whether a high phase of the MemClk signal (i.e., MemClk) or a low phase of the MemClk signal (i.e., MemClk ) is provided as an input for sampling by flip flop 702 .
- the DQS signal may be generated with an associated delay that may be selected in a range that spans the entire period of the MemClk signal (i.e., 2 UI), even though DLL device 215 may only configured to provide a selectable delay that can span a range of 1 UI.
- one or more higher order bits forming the coarse delay field (e.g., bit [9]) of the accumulation value may be provided to simplify the tracking of accumulator wrapping (i.e., overflow or underflow).
- the write levelization procedure may be terminated.
- the total number of iterations of the operations as depicted in FIG. 9 that may be performed may be selected to ensure convergence of the accumulation value.
- the length of time during which the write levelization procedure is performed may be set, as desired, to ensure convergence of the accumulation value. It is noted that the gain provided by gain unit 710 may dictate the number of iterations or time that may be required until suitable convergence of the accumulation value is achieved.
- the strobe signal generator 110 may utilize the determined delay value to set a delay associated with the generation of the corresponding strobe signal to perform normal memory read and write operations.
- the gain provided by gain unit 710 may be adjusted automatically during the write-levelization procedure to speed convergence.
- the gain may be initially set to a relatively high value (e.g., +8).
- the gain may be lowered (e.g., to a value of +1), thereby allowing refined adjustments to be made to the accumulation value as convergence is achieved.
- the lowering of the gain in such embodiments may be performed in a single gain-change step, or may be performed by iteratively lowering the gain across several discrete values over time.
- changes in the gain of gain unit 710 may be made in response to particular conditions, such as a detection of a phase reversal in the DQS signal relative to the MemClk signal.
- the accumulation value maintained by accumulator 225 may initially be set with a predetermined value (e.g., a seed value).
- a predetermined value e.g., a seed value
- an initial value may be programmed within accumulator 225 upon initialization through the execution of BIOS (Basic Input/Output System) code of a computer system in which memory controller 100 may be deployed.
- BIOS Basic Input/Output System
- bit [n] of the sub-fine delay field may be initialized with a value of “1”
- the lower order bits of the sub-fine delay field may be initialized with a value of “0”.
- the DLL control field [i.e., bits c:n+1] and the coarse delay field [i.e., bits M:c+1] may similarly be initialized with particular starting values, as desired.
- FIG. 12 illustrates an embodiment wherein a sequencer 1102 is provided within strobe signal generator 110 .
- sequencer 1102 operates to control strobe signal generator 110 such that a sequence 1202 of a predetermined number of cycles of the DQS signal are generated followed by a delay period 1204 , in a repeating fashion.
- an error indication associated with each cycle of the sequence 1202 may be provided to phase recovery engine 120 and, in a manner as described above, cause the accumulation value associated with accumulator 225 to be updated accordingly.
- sequencer 1102 may only allow the delay associated with generation of the DQS signal to be changed following an entire sequence 1202 of cycles of the DQS signal (e.g., during delay period 1204 ), rather than upon every cycle of the DQS signal.
- phase recovery engine 120 may still accumulate the value associated with the error indication received in response to each cycle of the DQS signal.
- FIG. 13 also variously illustrates the subsequent generation of a second sequence 1206 of the predetermined number of cycles of the DQS signal that may be generated if the delay remains unchanged, if the delay is increased, or if the delay is decreased.
- the predetermined number of cycles generated in each sequence ( 1202 , 1206 ) as controlled by sequencer 1102 may be programmable, as well as the length of delay period 1204 .
- one or more decimators 1104 may be provided within phase recovery engine 120 to prevent the accumulation of values output from error value generator 222 /gain unit 710 during the delay period 1204 .
- accumulator 225 may be implemented using a multi-stage integrate-and-dump configuration. Such an implementation is illustrated in FIG. 14 in which accumulator 225 is implemented using a first accumulator 1402 (e.g., a four-bit wide accumulator in this example) that is clocked by the internal clock signal PClk.
- a first accumulator 1402 e.g., a four-bit wide accumulator in this example
- a second accumulator 1404 which is coupled to receive an output of accumulator 1402 (appropriately sign-extended by sign extension unit 1404 ), maintains the entire accumulation value (e.g., bits [9:0]), but may be clocked by a slower clock signal (e.g., having a frequency of PClk/4 in this instance).
- the implementation of accumulator 225 as illustrated in FIG. 14 may consume less power and may be simpler to make function at higher data rates in comparison to implementations that utilize a single stage accumulator.
- strobe signal generator 110 may employ other specific circuitry and/or circuit configurations to control the delay associated with the generation of the associated DQS signal depending upon the accumulation value provided from phase recovery engine 120 .
- flip-flop 702 may be replaced with a different specific implementation of a sampling circuit.
- DLL device 215 may be configured to generate an output signal that can be selectively delayed across a range of delays that spans the entire period of the MemClk signal (i.e., 2 UI).
- flip flop 702 as well as multiplexer 702 may be omitted entirely, and the DQS signal may be derived directly from the output of the DLL device 215 .
- the choice of the specific number of bits forming each field of the accumulation value i.e., the sub-fine delay bits, the DLL control bits, and the coarse delay bits
- the gain provided by gain unit 710 may be selected as desired to optimize performance for a given implementation.
- FIG. 15 is a block diagram of one embodiment of a computer system 650 including a processor 600 and a system memory 640 .
- Processor 600 may include one or more processor cores, e.g., processor cores 601 A-D, fabricated as part of a single integrated circuit along with other structures.
- processor core 601 may be configured to execute instructions that may be stored in a system memory 640 .
- Such instructions may be defined according to a particular instruction set architecture (ISA).
- ISA instruction set architecture
- processor cores 601 may be configured to implement a version of the x86 ISA, although in other embodiments cores 601 may implement a different ISA or a combination of ISAs.
- each of the cores 100 may couple to an L3 cache 620 and a memory controller/peripheral interface unit (MCU) 630 via a system interface unit (SIU) 610 .
- L3 cache 620 may be configured as a unified cache, implemented using any suitable organization, that operates as an intermediate cache between L2 caches of cores 100 and system memory 640 .
- MCU 630 may be configured to interface processor 600 directly with system memory 640 .
- MCU 630 may be configured to generate the signals necessary to support one or more different types of random access memory (RAM) such as DDR-3 SDRAM.
- MCU 630 may include the functionality of memory controller 100 described above with reference to FIGS. 1-14 to support a write levelization algorithm to phase align each of a set of data strobe (DQS) signals relative to a memory clock (MemClk) signal at system memory 640 .
- System memory 640 may be configured to store instructions and data that may be operated on by the various cores 100 of processor 600 , and the contents of system memory 640 may be cached by various ones of the caches described above.
- MCU 630 may support other types of interfaces to processor 600 .
- MCU 630 may implement a dedicated graphics processor interface such as a version of the Accelerated/Advanced Graphics Port (AGP) interface, which may be used to interface processor 600 to a graphics-processing subsystem, which may include a separate graphics processor, graphics memory and/or other components.
- AGP Accelerated/Advanced Graphics Port
- MCU 630 may also be configured to implement one or more types of peripheral interfaces, e.g., a version of the PCI-Express bus standard, through which processor 600 may interface with peripherals such as storage devices, graphics devices, networking devices, etc.
- a secondary bus bridge external to processor 600 may be used to couple processor 600 to other peripheral devices via other types of buses or interconnects.
- memory controller and peripheral interface functions are shown integrated within processor 600 via MCU 630 , in other embodiments these functions may be implemented externally to processor 600 via a conventional “north bridge” arrangement.
- various functions of MCU 630 may be implemented via a separate chipset rather than being integrated within processor 600 .
Abstract
Description
- This application is related to the following co-pending applications which are incorporated herein by reference in their entirety:
-
- a. application Ser. No. 12/059,653, filed Mar. 31, 2008, entitled “METHOD FOR TRAINING DYNAMIC RANDOM ACCESS MEMORY CONTROLLER TIMING DELAYS” invented by Shawn Searles, Tahsin Askar, Thomas H. Hamilton, and Oswin Housty.
- b. application Ser. No. 12/059,613, filed Mar. 31, 2008, entitled “CIRCUIT USING A SHARED DELAY LOCKED LOOP (DLL) AND METHOD THEREFOR” invented by Shawn Searles, Nicholas T. Humphries, and Faisal A. Syed.
- c. application Ser. No. 12/059,593, filed Mar. 31, 2008, entitled “CIRCUIT FOR LOCKING A DELAY LOCKED LOOP (DLL) AND METHOD THEREFOR” invented by Shawn Searles, Nicholas T. Humphries, and Faisal A. Syed.
- d. application Ser. No. 12/059,641, filed Mar. 31, 2008, entitled “DATA DRIVER CIRCUIT FOR A DYNAMIC RANDOM ACCESS MEMORY (DRAM) CONTROLLER OR THE LIKE AND METHOD THEREFOR” invented by Shawn Searles, Nicholas T. Humphries, and Faisal A. Syed.
- 1. Field of the Invention
- This invention relates to memory subsystems and, more particularly, to write levelization mechanisms for memory subsystems.
- 2. Description of the Related Art
- Various memory subsystem architectures are designed such that a memory clock signal and data strobe (DQS) signals generated by a memory controller arrive phase aligned at the corresponding memory devices to effectively perform read and write operations. In Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) and DDR2 SDRAM systems, the signals are phase aligned due, at least in part, to the fact that the trace lengths associated with the signals are matched. Since DDR3 SDRAM systems do not have matched trace lengths for these signals, DDR3 SDRAM memory architectures may include mechanisms for performing write levelization to phase align the memory clock signal and the DQS signals at the memory devices.
- Various embodiments are disclosed of a method and apparatus for aligning a clock signal and a set of strobe signals at one or more memory devices of a computing system. In one embodiment, a memory controller includes a clock generator configured to generate the clock signal, and a respective strobe signal generator configured to generate each strobe signal. The memory controller further includes a phase recovery engine associated with each strobe signal generator that is configured to receive an error signal from a corresponding memory device. The error signal conveys an error indication indicative of an alignment of the strobe signal relative to the clock signal for each of a plurality of cycles of the strobe signal. The phase recovery engine includes an accumulator configured to maintain an accumulation value that depends upon the error indications for the plurality of cycles of the strobe signal. The strobe signal generator is configured to control a delay associated with generation of the strobe signal depending upon the accumulation value.
-
FIG. 1 is a block diagram of one embodiment of a memory subsystem including a memory controller and one or more memory modules; -
FIGS. 2A-C are timing diagrams illustrating the alignment of a data strobe (DQS) signal relative to a memory clock (MemClk) signal, according to one embodiment; -
FIG. 3 is a block diagram of one embodiment of a memory clock generator, a strobe signal generator, and a phase recovery engine; -
FIG. 4 is a block diagram of one embodiment of a memory device of a memory module; -
FIG. 5 is a flow diagram illustrating a method for performing write levelization in a memory subsystem, according to various embodiments; -
FIGS. 6A and 6B are timing diagrams illustrating a generation of an error signal indicative of alignment between a DQS signal and the MemClk signal; -
FIG. 7 is a block diagram of one particular implementation of a memory clock generator, a strobe signal generator and a phase recovery engine; -
FIG. 8 illustrates fields of an accumulation value maintained by an accumulator; -
FIG. 9 is a flow diagram illustrating operations associated with the embodiment ofFIG. 7 ; -
FIGS. 10 and 11 are timing diagrams illustrating signals associated with the embodiment ofFIG. 7 ; -
FIG. 12 is a block diagram illustrating a further particular implementation of a strobe signal generator and a phase recovery engine; -
FIG. 13 is a timing diagram illustrating a repeating sequence of DQS cycles followed by a delay period, according to one embodiment; -
FIG. 14 is a block diagram illustrating a particular implementation of an accumulator; and -
FIG. 15 is a block diagram of one embodiment of a computer system including a processor and a system memory. - While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.
- Turning now to
FIG. 1 , a block diagram is shown of a memory subsystem comprising amemory controller 100 and one ormore memory modules 180, according to one embodiment. As illustrated,memory controller 100 may include aclock generator 102, amemory clock generator 105, a plurality of data strobe signal generators 110A-X, and a plurality ofphase recovery engines 120A-X.Memory modules 180 may each include a plurality ofmemory devices 150A-X. As will be further described below,memory controller 100 may support a write levelization algorithm to phase align a memory clock (MemClk) signal and corresponding data strobe (DQS) signals at thememory devices 150 to effectively perform memory read and write operations. - In one specific implementation,
clock generator 102 may be coupled tomemory clock generator 105, strobe signal generators 110A-X, andphase recovery engines 120A-X.Memory clock generator 105 may be coupled to thememory devices 150A-X. Each of thememory devices 150A-X ofmemory modules 180 may be coupled to a correspondingstrobe signal generator 110 via a DQS signal line, and to a correspondingphase recovery engine 120 via an Error signal line. For example,memory device 150X may be coupled tostrobe signal generator 110X andphase recovery engine 120X. Each of thephase recovery engines 120A-X may also be coupled to a correspondingstrobe signal generator 110. -
Memory controller 100 andmemory modules 180 may be included in any of various types of computing or processing systems, e.g., a personal computer (PC), a workstation, a server blade, a portable computing device, a game console, a system-on-a-chip (SoC), a television system, an audio system, among others.Memory controller 100 andmemory modules 180 may be connected to a circuit board or motherboard of a computing system. In various embodiments,memory controller 100 may be integrated within a processor of the computer system. In other embodiments,memory controller 100 may be implemented externally to the processor via a separate chipset.Memory modules 180 may form the main system memory of the computer system (e.g.,system memory 640 ofFIG. 14 ).Memory modules 180 may be Dual In-line Memory Modules (DIMMs), andmemory devices 150 may be RAM devices, such as DDR3 SDRAM devices. It is noted, however, that in other embodiments the write levelization algorithm may be implemented in memory subsystems that include other types of memory to phase align a MemClk signal and the corresponding DQS signals at the memory devices. - During operation,
clock generator 102 may generate a clock signal (PClk) that serves as the internal clock ofmemory controller 100. In one specific implementation, for DDR3 SDRAM systems, the internal clock may run at 1600 Mhz. The internal clock signal may be provided to various components ofmemory controller 100, such asstrobe signal generators 110 andmemory clock generator 105. In one embodiment, the internal clock signal may serve as the timing reference used bymemory clock generator 105 to generate the memory clock (MemClk) signal. As shown, the MemClk signal is provided to each of thememory devices 150. In one specific implementation, the MemClk signal may be generated at half the frequency of the internal clock signal PClk (e.g., at 800 MHz). - The internal clock signal (PClk) may also serve as a timing reference used by each of the
strobe signal generators 110 to generate a respective data strobe (DQS) signal that is provided to acorresponding memory device 150. For example, strobe signal generator 110A provides a corresponding DQS signal tomemory device 150A. The DQS signals are used to control data read and write operations associated withmemory devices 150 during normal modes of operation of the memory subsystem, as will be appreciated by one of skill in the art. - During the write levelization procedure, the DQS signals may be provided as test signals to sample the MemClk signal at the
memory devices 150 to thereby determine the phase alignment of each DQS signal relative to the MemClk signal. In particular, eachstrobe signal generator 110 may generate its corresponding DQS signal in the form of cycles (or strobes) having the same frequency as the MemClk signal. The DQS signals and the MemClk signal may start out aligned atmemory controller 100; however, when the signals arrive at thememory devices 150, an individual DQS signal may be ahead of the MemClk, as illustrated inFIG. 2A , or behind the MemClk, as illustrated inFIG. 2B . Since the signals take completely disparate paths to thememory devices 150, and the trace lengths may not be matched, different delays may be introduced that may cause the signals to arrive unaligned at thememory devices 150. Write levelization may be implemented in the memory subsystem to either delay or speed up an individual DQS signal to phase align the DQS signal and the MemClk, as will be further described below. After write levelization, each DQS signal may be aligned relative to the MemClk when received at thecorresponding memory device 150, as illustrated inFIG. 2C . Subsequent to this initialization procedure, the memory subsystem may enter a mode of operation that allows normal data read and write operations to be performed. -
Phase recovery engines 120 may be used to interpret and process Error signals received from thecorresponding memory devices 150 to implement the write levelization algorithm. Eachphase recovery engine 120 may receive an indication of an error in response to each cycle of the DQS signal sent to thecorresponding memory device 150. The phase recovery engine may then process the error indications to generate alignment information that determines whether to increase or decrease a delay associated with the corresponding DQS signal to achieve phase alignment relative to the MemClk signal. It is noted that in various embodiments the feedback path for receiving the Error signals during the write levelization procedure may be the same lines used for data transfers during normal memory read and write operations, e.g., the bidirectional data (DQ) lines in memory subsystems. Further details regarding specific implementations of the write levelization procedure are described below in conjunction withFIGS. 3-14 . - It should be noted that the components described with reference to
FIG. 1 are meant to be exemplary only, and are not intended to limit the invention to any specific set of components or configurations. For example, in various embodiments, one or more of the components described may be omitted, combined, modified, or additional components may be included, as desired. -
FIG. 3 is a generalized block diagram of one embodiment of amemory clock generator 105, a strobe signal generator 110 (e.g., representative of any of strobe signal generators 110A-110X ofFIG. 1 ), and a phase recovery engine 120 (e.g., representative of the correspondingphase recovery engine 120A-120X).FIG. 4 is a block diagram of one embodiment of a memory device 150 (e.g., representative of thecorresponding memory device 150A-150X). As shown,memory clock generator 105 may include a delay-locked loop (DLL)device 206, a divide-by-twodivider circuit 207, and a flip-flop 208. Similarly,strobe signal generator 110 may include aDLL device 215, a divide-by-twodivider circuit 216, and a flip-flop 217.Phase recovery engine 120 is shown with anerror value generator 222 and anaccumulator 225. Finally,memory device 150 is shown with a flip-flop 255. It is noted that various circuitry that may be used in association with specific implementations of the illustrated circuit components such as signal drivers, bias circuitry, multiplexers, etc. may be omitted from the diagram for simplicity and clarity. - Referring collectively to
FIGS. 1-4 and the associated flow diagram ofFIG. 5 , during the write levelization procedure,memory clock generator 105 ofmemory controller 100 provides the MemClk signal (at half the frequency of PClk, in this embodiment) to eachmemory device 150 ofmemory modules 180, and eachstrobe signal generator 110 provides to the corresponding memory device 150 a respective DQS signal that cycles at the frequency of the MemClk signal (block 402). As described previously, the DQS signals and the MemClk signal are provided to generate error indications to determine the phase alignment of each DQS signal relative to the MemClk signal at thecorresponding memory device 150. - In the depicted embodiment, each rising edge of a cycle of the DQS signal provided to
memory device 150 results in the sampling of the MemClk signal, e.g., using flip-flop 255. In response to the sampling operations,phase recovery engine 120 may receive error indications from the memory device 150 (block 404). Specifically, in the depicted embodiment, the rising edge of each cycle of the DQS signal causesflip flop 255 to sample the MemClk signal, and thus the corresponding Error signal is driven either low or high depending upon the alignment of the DQS signal relative to the MemClk signal at thememory device 150. For example, as illustrated inFIG. 6A , upon a first rising edge of the DQS signal, MemClk may be sampled low, and thus the Error signal provided from thecorresponding memory device 150 is driven low. Upon a subsequent rising edge of the DQS signal (illustratively shown with a slight phase shift relative to the MemClk signal), the MemClk signal is sampled high, and thus the Error signal is driven high.FIG. 6B illustrates a similar example where the MemClk signal is first sampled high, resulting in a high Error signal, and subsequently sampled low, resulting in a low Error signal. - In response to receiving the error indications conveyed in the Error signal, the corresponding
phase recovery engine 120 may update an associated accumulation value (block 406). For example, in the embodiment ofFIG. 3 , an accumulation value (which may be initialized with a particular starting value, as described below) may be maintained byaccumulator 225. Upon each cycle of the DQS signal,error value generator 222 ofphase recovery engine 120 associates the state of the Error signal with either a first value (such as −1 if the Error signal is high) or a second value (such as +1 if the Error signal is low), and provides the first or second value toaccumulator 225.Accumulator 225 may add the value provided from error value generator 222 (or a value dependent thereon) with the then-current accumulation value to derive an updated accumulation value (e.g., upon each cycle of the DQS signal). It is thus noted that the accumulation value maintained byaccumulator 225 either increases or decreases depending on the phase alignment of the DQS signal relative to the MemClk signal. The accumulation value, or a signal dependent thereon, is correspondingly provided toDLL 215 to control a delay associated with the generation of the corresponding DQS signal. In this manner, the alignment of the DQS signal relative to the MemClk signal may be adjusted and controlled in a feedback fashion to achieve phase alignment. It is noted that the general operations described above with reference to blocks 402-408 ofFIG. 5 may be implemented using a variety of specific mechanisms and methods, such as those discussed below with reference toFIGS. 7-14 . In addition, it is noted that the delay-locked loop devices described herein (e.g., DLL 215) may be replaced with other phase-controllable signal generation devices such as phase interpolators in other embodiments. -
FIG. 7 is a block diagram of one particular implementation ofmemory clock generator 105,strobe signal generator 110, andphase recovery engine 120. Circuit portions that correspond to those ofFIG. 3 are numbered identically for simplicity and clarity. In the depicted embodiment,memory clock generator 206 is shown with a divide-by-two clock divider 701 coupled to an output ofDLL 206.Strobe signal generator 110 is shown withDLL 215, a flip-flop 702, a 2:1multiplexer 704, and aninverter 706.Phase recovery engine 120 is shown with again unit 710 coupled betweenerror value generator 222 andaccumulator 225. - In the embodiment of
FIG. 7 ,accumulator 225 is configured to maintain an accumulation value including three fields. In particular, as illustrated inFIG. 8 , in one embodiment the accumulation value maintained byaccumulator 225 is a 10-bit value formed by bits [9:0]. Bits [2:0], referred to herein as the sub-fine delay bits (or field), provide averaging for noise and provide delay between the update ofDLL 215 and a corresponding return in the error signal, thereby providing stability. Bits [7:3] control the delay associated withDLL 215. Bits [9:8] are provided to control the coarse delay, as discussed further below. It is noted that while in the depicted embodiment the sub-fine delay bits are formed by bits [2:0], in other embodiments, the sub-fine delay bits [n:0] may be formed by a different number of one or more bits. Likewise, the DLL control bits [c:n+1] and the coarse delay bits [M:c+1] may also each be formed by a different number of one or more bits. - The operation of the embodiment of
FIG. 7 is discussed in conjunction with the flow diagram ofFIG. 9 and timing diagrams ofFIGS. 10 and 11 . As discussed previously, during the write levelization procedure,error value generator 222 may receive an error indication conveyed in the Error signal upon each rising edge of the corresponding DQS signal (block 432). When the received Error signal is in a low state, it may indicate that the DQS signal received at thecorresponding memory device 150 is ahead of the MemClk signal (as illustrated inFIG. 2A ). When the received Error signal is in a high state, it may indicate that the DQS signal is behind the MemClk signal (as illustrated inFIG. 2B ).Error value generator 222 may associate the error indication with a first value, such as −1, when the error signal is high (blocks 434 and 436), or a second value, such as +1, when the error signal is low (blocks 434 and 438). - In the embodiment of
FIG. 7 , the first or second value fromerror value generator 222 is provided to gainunit 710, which amplifies (or attenuates) the provided value (block 439). For example, gainunit 710 may increase the value +1 to +8, or the value −1 to −8, and provide the resulting amplified value toaccumulator 225. For each cycle of the DQS signal,accumulator 225 sums the amplified value fromgain unit 710 with its then-current accumulation value to derive an updated accumulation value (block 440). It is noted that the particular amount of gain as provided bygain unit 710 may control the extent to which the accumulation value increases or decreases upon each sampling of the DQS signal. It is further noted that the amount of gain provided bygain block 710 may be programmable. In addition, in embodiments wheregain unit 710 may provide less than unity gain, it is noted that the sub-fine delay field of the accumulation value as maintained byaccumulator 225 may include one or more additional bits (e.g., denoted as bits [−1] and [−2] inFIG. 8 ) to allow accumulation of such sub-unity values). - As shown, bits [7:3] of the accumulation value are provided to control the delay associated with an output signal (DllClk) of
DLL 215. In one embodiment, the DllClk signal may be controllably delayed in fractional increments of 1/32 of a unit interval (UI), where a unit interval equals the period of the internal clock PClk.FIG. 10 illustrates several versions of the DilClk signal, delayed from between 0/32 to 31/32 of a unit interval with respect to the PClk signal. Depending upon bits [7:3] of the accumulation value,DLL 215 generates the DllClk signal according to one of these selected delays, and provides such signal to control the clocking offlip flop 702. It is noted thatFIG. 10 also illustrates the MemClk signal as output from divide-by-two circuit 701. As shown, in this particular embodiment, the MemClk signal has a frequency that is half that of the internal clock PClk. - As is also shown in
FIG. 7 , bit [8] of the accumulation value is provided to a select input ofmultiplexer 704.Multiplexer 704 receives the MemClk signal at one of its inputs, and an inverted version of the MemClk signal at its other input. Depending upon bit [8] of the accumulation value,multiplexer 704 causes either the MemClk signal or the inverted version of the MemClk signal to be provided as an input to flipflop 702. It is noted that in some embodiments, rather than receiving the MemClk signal frommemory clock generator 110, strobe signal generator may separately generate a duplicate version of the MemClk signal using a separate divide-by-two circuit that receives the internal clock PClk and divides its frequency by two. - As a result of the circuit configuration of
FIG. 7 , upon each rising edge of the DllClk signal as generated by DLL 215 (and delayed in accordance with bits [7:3] of the accumulation value),flip flop 702 samples either the MemClk signal or the inverted version of the MemClk signal, depending upon bit [8] of the accumulation value. As illustrated inFIG. 11 , the DQS signal as represented by the output offlip flop 702 thus cycles at a frequency of the MemClk signal, with a controlled delay of between 0/32 UI to 63/32 UI in 1/32 UI increments, based upon the accumulation value. It is noted that if bit [9] is included, the delay may be conceptually controlled from 0/32 UI to 127/32 UI (and so on for further bits that may be provided in the coarse delay field, as desired). Thus, if the DllClk signal generated byDLL 215 is associated with a delay of 1/32 UI and bit [8] of the accumulation value is low, the MemClk signal is sampled high upon the first illustrated rising edge of the DllClk signal (having a delay corresponding to 1/32 UI), thus causing the DQS signal to be driven high. Upon the next rising edge of the illustrated DllClk signal, the MemClk signal is sampled low, thus causing the DQS signal to transition low, and so on. In this manner, a DQS signal as represented by the output offlip flop 702 with a delay corresponding to 1/32 UI may be generated. On the other hand, if bit [8] of the accumulation value is high, the first rising edge of the DllClk signal results in the sampling of the low state of the inverted version of the MemClk signal (i.e.,MemClk ), thus causing the DQS signal to be driven low. Upon the next rising edge of the illustrated DllClk signal, theMemClk MemClk signal is sampled high, thus causing the DQS signal to transition high, and so on. In this manner, a DQS signal with a delay corresponding to 33/32 UI may be generated. Other delayed versions of the DQS signal may be generated similarly. - As error indications resulting from successive cycles of the DQS signal are received by
error value generator 222, the accumulation value maintained byaccumulator 225 will converge to a value that achieves and maintains alignment of the DQS signal and the MemClk signal at thecorresponding memory device 150. If, for example, the DQS signal is significantly ahead of the MemClk signal, the accumulation value will gradually increase, which will causestrobe signal generator 110 to output increasingly delayed versions of the DQS signal (i.e., to retard or delay the DQS signal). Likewise, if the DQS signal is significantly behind the MemClk signal, the accumulation value will gradually decrease, which will causestrobe signal generator 110 to decrease the delay associated with (i.e., advance or speed up) the DQS signal. Eventually, due to the looped feedback configuration of the circuitry, the accumulation value will converge to a value that maintains alignment between the DQS signal and the MemClk signal as received at thecorresponding memory device 150. - It is noted that the sub-fine delay bits [n:0] of the accumulation value maintained by
accumulator 225 provide averaging for noise and further provide stability. In particular, consider an embodiment (as illustrated inFIG. 7 ) wherein the sub-fine delay bits are formed by a total of three bits (e.g., [2:0]). In such an embodiment, if the bits are initially all logic 0 (i.e., “000”), it will take eight consecutive “+1” error values fromerror value generator 222/gain unit 710 to causebit 3 of the accumulation value to increment (which causes a corresponding change to the delay associated with the DQS signal). Likewise, if the sub-fine delay bits are initially all logic 1 (i.e., “111”), it will take eight “−1” error values fromerror value generator 222/gain unit 710 to causebit 3 to decrement. Thus, as the accumulation value converges to a value that maintains alignment between the DQS signal and the MemClk signal, noise in the system that may cause random incrementing and decrementing of the accumulation value may not result in any change to the selected delay of the DQS signal (e.g., since bits [8:3] of the accumulation value may not be affected). This averaging also acts to stabilize any external delay in the loop. - It is also noted that in the embodiment of
FIG. 7 ,DLL 215 is controllable to generate the DllClk signal with a delay of from 0/32 UI to 31/32 UI. However, since the frequency of the MemClk signal is half that of the DllClk signal, the coarse delay bit [c+1] of the accumulation value (e.g., bit [8]) is used to control whether a high phase of the MemClk signal (i.e., MemClk) or a low phase of the MemClk signal (i.e.,MemClk ) is provided as an input for sampling byflip flop 702. In this manner, the DQS signal may be generated with an associated delay that may be selected in a range that spans the entire period of the MemClk signal (i.e., 2 UI), even thoughDLL device 215 may only configured to provide a selectable delay that can span a range of 1 UI. It is noted that in various embodiments, one or more higher order bits forming the coarse delay field (e.g., bit [9]) of the accumulation value may be provided to simplify the tracking of accumulator wrapping (i.e., overflow or underflow). - Once the accumulation value converges to a value that achieves alignment between the DQS signal and the MemClk signal, the write levelization procedure may be terminated. In various embodiments, the total number of iterations of the operations as depicted in
FIG. 9 that may be performed may be selected to ensure convergence of the accumulation value. In other embodiments, the length of time during which the write levelization procedure is performed may be set, as desired, to ensure convergence of the accumulation value. It is noted that the gain provided bygain unit 710 may dictate the number of iterations or time that may be required until suitable convergence of the accumulation value is achieved. Following the write levelization procedure, thestrobe signal generator 110 may utilize the determined delay value to set a delay associated with the generation of the corresponding strobe signal to perform normal memory read and write operations. - In some embodiments, the gain provided by
gain unit 710 may be adjusted automatically during the write-levelization procedure to speed convergence. For example, the gain may be initially set to a relatively high value (e.g., +8). After a predetermined number of accumulation cycles, the gain may be lowered (e.g., to a value of +1), thereby allowing refined adjustments to be made to the accumulation value as convergence is achieved. The lowering of the gain in such embodiments may be performed in a single gain-change step, or may be performed by iteratively lowering the gain across several discrete values over time. In still further embodiments, changes in the gain ofgain unit 710 may be made in response to particular conditions, such as a detection of a phase reversal in the DQS signal relative to the MemClk signal. - It is further noted that in various embodiments, the accumulation value maintained by
accumulator 225 may initially be set with a predetermined value (e.g., a seed value). For example, an initial value may be programmed withinaccumulator 225 upon initialization through the execution of BIOS (Basic Input/Output System) code of a computer system in whichmemory controller 100 may be deployed. For example, bit [n] of the sub-fine delay field may be initialized with a value of “1”, while the lower order bits of the sub-fine delay field may be initialized with a value of “0”. The DLL control field [i.e., bits c:n+1] and the coarse delay field [i.e., bits M:c+1] may similarly be initialized with particular starting values, as desired. - Although in the above description of
FIG. 7 , the DQS signal as generated bystrobe signal generator 110 cycles continuously at the frequency of the MemClk signal during the write levelization procedure, and the accumulation value is updated according to an error indication received in response to each DQS cycle, other embodiments are also possible. For example,FIG. 12 illustrates an embodiment wherein asequencer 1102 is provided withinstrobe signal generator 110. During operation, as illustrated inFIG. 13 ,sequencer 1102 operates to controlstrobe signal generator 110 such that asequence 1202 of a predetermined number of cycles of the DQS signal are generated followed by adelay period 1204, in a repeating fashion. In such an embodiment, an error indication associated with each cycle of thesequence 1202 may be provided to phaserecovery engine 120 and, in a manner as described above, cause the accumulation value associated withaccumulator 225 to be updated accordingly. However,sequencer 1102 may only allow the delay associated with generation of the DQS signal to be changed following anentire sequence 1202 of cycles of the DQS signal (e.g., during delay period 1204), rather than upon every cycle of the DQS signal. In other words,phase recovery engine 120 may still accumulate the value associated with the error indication received in response to each cycle of the DQS signal. However, instead of allowing the accumulation value to potentially change the delay associated withstrobe signal generator 110 as a result of every cycle, the delay associated with the DQS signal generated bystrobe signal generator 110 may only be changed (e.g., during the delay period 1204) following theentire sequence 1202 of cycles of the DQS signal.FIG. 13 also variously illustrates the subsequent generation of asecond sequence 1206 of the predetermined number of cycles of the DQS signal that may be generated if the delay remains unchanged, if the delay is increased, or if the delay is decreased. It is noted that the predetermined number of cycles generated in each sequence (1202, 1206) as controlled bysequencer 1102 may be programmable, as well as the length ofdelay period 1204. It is also noted that in such embodiments, one or more decimators 1104 may be provided withinphase recovery engine 120 to prevent the accumulation of values output fromerror value generator 222/gain unit 710 during thedelay period 1204. - It is also noted that various components generally depicted by the block diagrams of
FIGS. 3 , 7 and 12 may be implemented using various specific circuit configurations and techniques. For example, in one particular implementation,accumulator 225 may be implemented using a multi-stage integrate-and-dump configuration. Such an implementation is illustrated inFIG. 14 in which accumulator 225 is implemented using a first accumulator 1402 (e.g., a four-bit wide accumulator in this example) that is clocked by the internal clock signal PClk. Asecond accumulator 1404, which is coupled to receive an output of accumulator 1402 (appropriately sign-extended by sign extension unit 1404), maintains the entire accumulation value (e.g., bits [9:0]), but may be clocked by a slower clock signal (e.g., having a frequency of PClk/4 in this instance). The implementation ofaccumulator 225 as illustrated inFIG. 14 may consume less power and may be simpler to make function at higher data rates in comparison to implementations that utilize a single stage accumulator. - In addition, it is finally noted that
strobe signal generator 110 may employ other specific circuitry and/or circuit configurations to control the delay associated with the generation of the associated DQS signal depending upon the accumulation value provided fromphase recovery engine 120. For example, in some embodiments, flip-flop 702 may be replaced with a different specific implementation of a sampling circuit. In addition, in some embodiments,DLL device 215 may be configured to generate an output signal that can be selectively delayed across a range of delays that spans the entire period of the MemClk signal (i.e., 2 UI). In such embodiments,flip flop 702 as well asmultiplexer 702 may be omitted entirely, and the DQS signal may be derived directly from the output of theDLL device 215. Furthermore, it is noted that the choice of the specific number of bits forming each field of the accumulation value (i.e., the sub-fine delay bits, the DLL control bits, and the coarse delay bits) as well as the gain provided bygain unit 710 may be selected as desired to optimize performance for a given implementation. -
FIG. 15 is a block diagram of one embodiment of acomputer system 650 including aprocessor 600 and asystem memory 640.Processor 600 may include one or more processor cores, e.g., processor cores 601A-D, fabricated as part of a single integrated circuit along with other structures. Each processor core 601 may be configured to execute instructions that may be stored in asystem memory 640. Such instructions may be defined according to a particular instruction set architecture (ISA). For example, processor cores 601 may be configured to implement a version of the x86 ISA, although in other embodiments cores 601 may implement a different ISA or a combination of ISAs. - In the illustrated embodiment, each of the
cores 100 may couple to anL3 cache 620 and a memory controller/peripheral interface unit (MCU) 630 via a system interface unit (SIU) 610. In one embodiment,L3 cache 620 may be configured as a unified cache, implemented using any suitable organization, that operates as an intermediate cache between L2 caches ofcores 100 andsystem memory 640. -
MCU 630 may be configured to interfaceprocessor 600 directly withsystem memory 640. For example,MCU 630 may be configured to generate the signals necessary to support one or more different types of random access memory (RAM) such as DDR-3 SDRAM.MCU 630 may include the functionality ofmemory controller 100 described above with reference toFIGS. 1-14 to support a write levelization algorithm to phase align each of a set of data strobe (DQS) signals relative to a memory clock (MemClk) signal atsystem memory 640.System memory 640 may be configured to store instructions and data that may be operated on by thevarious cores 100 ofprocessor 600, and the contents ofsystem memory 640 may be cached by various ones of the caches described above. - Additionally,
MCU 630 may support other types of interfaces toprocessor 600. For example,MCU 630 may implement a dedicated graphics processor interface such as a version of the Accelerated/Advanced Graphics Port (AGP) interface, which may be used tointerface processor 600 to a graphics-processing subsystem, which may include a separate graphics processor, graphics memory and/or other components.MCU 630 may also be configured to implement one or more types of peripheral interfaces, e.g., a version of the PCI-Express bus standard, through whichprocessor 600 may interface with peripherals such as storage devices, graphics devices, networking devices, etc. In some embodiments, a secondary bus bridge (e.g., a “south bridge”) external toprocessor 600 may be used tocouple processor 600 to other peripheral devices via other types of buses or interconnects. It is noted that while memory controller and peripheral interface functions are shown integrated withinprocessor 600 viaMCU 630, in other embodiments these functions may be implemented externally toprocessor 600 via a conventional “north bridge” arrangement. For example, various functions ofMCU 630 may be implemented via a separate chipset rather than being integrated withinprocessor 600. - Although the embodiments above have been described in considerable detail, numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.
Claims (20)
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/127,059 US7961533B2 (en) | 2008-05-27 | 2008-05-27 | Method and apparatus for implementing write levelization in memory subsystems |
TW098116834A TWI494925B (en) | 2008-05-27 | 2009-05-21 | Method and apparatus for implementing write levelization in memory subsystems |
KR1020107029336A KR101443891B1 (en) | 2008-05-27 | 2009-05-27 | Method and apparatus for implementing write levelization in memory subsystems |
EP09755253.3A EP2304574B1 (en) | 2008-05-27 | 2009-05-27 | Method and apparatus for implementing write levelization in memory subsystems |
JP2011511628A JP5520938B2 (en) | 2008-05-27 | 2009-05-27 | Method and apparatus for implementing write levelization in a memory subsystem |
PCT/US2009/003220 WO2009145890A1 (en) | 2008-05-27 | 2009-05-27 | Method and apparatus for implementing write levelization in memory subsystems |
CN200980128912.4A CN102099796B (en) | 2008-05-27 | 2009-05-27 | Method and apparatus for implementing write levelization in memory subsystems |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/127,059 US7961533B2 (en) | 2008-05-27 | 2008-05-27 | Method and apparatus for implementing write levelization in memory subsystems |
Publications (2)
Publication Number | Publication Date |
---|---|
US20090296501A1 true US20090296501A1 (en) | 2009-12-03 |
US7961533B2 US7961533B2 (en) | 2011-06-14 |
Family
ID=40847834
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/127,059 Active 2029-07-01 US7961533B2 (en) | 2008-05-27 | 2008-05-27 | Method and apparatus for implementing write levelization in memory subsystems |
Country Status (7)
Country | Link |
---|---|
US (1) | US7961533B2 (en) |
EP (1) | EP2304574B1 (en) |
JP (1) | JP5520938B2 (en) |
KR (1) | KR101443891B1 (en) |
CN (1) | CN102099796B (en) |
TW (1) | TWI494925B (en) |
WO (1) | WO2009145890A1 (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090244995A1 (en) * | 2008-03-31 | 2009-10-01 | Advanced Micro Devices, Inc. | Circuit for Locking a Delay Locked Loop (DLL) and Method Therefor |
US20090244996A1 (en) * | 2008-03-31 | 2009-10-01 | Advanced Micro Devices, Inc. | Circuit Using a Shared Delay Locked Loop (DLL) and Method Therefor |
US20090245010A1 (en) * | 2008-03-31 | 2009-10-01 | Advanced Micro Devices, Inc. | Data Driver Circuit for a Dynamic Random Access Memory (DRAM) Controller or the Like and Method Therefor |
US7924637B2 (en) | 2008-03-31 | 2011-04-12 | Advanced Micro Devices, Inc. | Method for training dynamic random access memory (DRAM) controller timing delays |
US20160162426A1 (en) * | 2014-12-05 | 2016-06-09 | Marvell Israel (M.I.S.L) Ltd. | Optimal sampling of data-bus signals using configurable individual time delays |
KR20170107764A (en) * | 2016-03-16 | 2017-09-26 | 에스케이하이닉스 주식회사 | Semiconductor system and operating method thereof |
US11152044B1 (en) * | 2020-04-17 | 2021-10-19 | SK Hynix Inc. | System for performing phase matching operation |
CN114627918A (en) * | 2020-12-09 | 2022-06-14 | 美光科技公司 | Write leveling of memory devices using write DLL circuitry |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101079209B1 (en) * | 2010-04-28 | 2011-11-03 | 주식회사 하이닉스반도체 | Data input/output apparatus and method of semiconductor system |
JP6007676B2 (en) * | 2012-08-29 | 2016-10-12 | 富士通株式会社 | Determination support apparatus, determination apparatus, memory controller, system, and determination method |
US8937846B2 (en) | 2013-05-09 | 2015-01-20 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Write level training using dual frequencies in a double data-rate memory device interface |
KR102147228B1 (en) | 2014-01-23 | 2020-08-24 | 삼성전자주식회사 | write leveling control circuit for target module and thereof Method |
US9330749B1 (en) * | 2014-10-21 | 2016-05-03 | Xilinx, Inc. | Dynamic selection of output delay in a memory control device |
CN107918443B (en) * | 2016-10-11 | 2020-04-24 | 深圳市中兴微电子技术有限公司 | Signal generation method and device |
KR20180089239A (en) * | 2017-01-31 | 2018-08-08 | 에스케이하이닉스 주식회사 | Integrated circuit |
US10230370B2 (en) | 2017-04-25 | 2019-03-12 | Ati Technologies Ulc | Data transmission with power supply noise compensation |
TWI713042B (en) * | 2019-07-22 | 2020-12-11 | 群聯電子股份有限公司 | Memory interface circuit, memory storage device and configuration status checking method |
Citations (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5373255A (en) * | 1993-07-28 | 1994-12-13 | Motorola, Inc. | Low-power, jitter-compensated phase locked loop and method therefor |
US5440515A (en) * | 1994-03-08 | 1995-08-08 | Motorola Inc. | Delay locked loop for detecting the phase difference of two signals having different frequencies |
US5857095A (en) * | 1995-09-12 | 1999-01-05 | Micron Electronics, Inc. | Method for aligning a control signal and a clock signal |
US20020147896A1 (en) * | 2001-04-07 | 2002-10-10 | Rentschler Eric M. | Memory controller with 1X/MX write capability |
US20030021164A1 (en) * | 2001-03-09 | 2003-01-30 | Samsung Electronics Co., Ltd. | Semiconductor memory device having different data rates in read operation and write operation |
US6691214B1 (en) * | 2000-08-29 | 2004-02-10 | Micron Technology, Inc. | DDR II write data capture calibration |
US6873564B2 (en) * | 2000-06-30 | 2005-03-29 | Micron Technology, Inc. | Zero latency-zero bus turnaround synchronous flash memory |
US6930932B2 (en) * | 2003-08-27 | 2005-08-16 | Hewlett-Packard Development Company, L.P. | Data signal reception latch control using clock aligned relative to strobe signal |
US20050197082A1 (en) * | 2004-03-04 | 2005-09-08 | Ati Technologies, Inc. | Method and apparatus for fine tuning a memory interface |
US20050204245A1 (en) * | 2000-11-09 | 2005-09-15 | Lee Terry R. | Method of timing calibration using slower data rate pattern |
US20050243608A1 (en) * | 2004-04-28 | 2005-11-03 | Lee Chang H | Input circuit for a memory device |
US7038971B2 (en) * | 2002-04-23 | 2006-05-02 | Samsung Electronics Co., Ltd. | Multi-clock domain data input-processing device having clock-receiving locked loop and clock signal input method thereof |
US20060114742A1 (en) * | 2004-11-30 | 2006-06-01 | Joe Salmon | Method and apparatus for optimizing strobe to clock relationship |
US20060133158A1 (en) * | 2004-12-22 | 2006-06-22 | Shin Beom J | Pipe latch circuit of multi-bit prefetch-type semiconductor memory device with improved structure |
US7117381B2 (en) * | 2003-01-06 | 2006-10-03 | Samsung Electronics Co., Ltd. | Control signal generation circuit and data transmission circuit having the same |
US20060262613A1 (en) * | 2005-04-23 | 2006-11-23 | Georg Braun | Semiconductor memory and method for adapting the phase relationship between a clock signal and strobe signal during the acceptance of write data to be transmitted |
US20070036020A1 (en) * | 2005-08-01 | 2007-02-15 | Edward Lee | Bit-deskewing IO method and system |
US7184323B2 (en) * | 2003-11-27 | 2007-02-27 | Elpida Memory, Inc. | 4N pre-fetch memory data transfer system |
US20070217559A1 (en) * | 2006-03-16 | 2007-09-20 | Rambus Inc. | Signaling system with adaptive timing calibration |
US7304910B1 (en) * | 2005-12-28 | 2007-12-04 | Hitachi, Ltd. | Semiconductor memory device with sub-amplifiers having a variable current source |
US7321525B2 (en) * | 2005-09-13 | 2008-01-22 | Renesas Technology Corp. | Semiconductor integrated circuit device |
US7487378B2 (en) * | 2005-09-19 | 2009-02-03 | Ati Technologies, Inc. | Asymmetrical IO method and system |
US20090086562A1 (en) * | 2007-09-27 | 2009-04-02 | Micron Technology, Inc. | Devices, systems, and methods for independent output drive strengths |
US7518946B2 (en) * | 2006-09-15 | 2009-04-14 | Ricoh Company, Ltd. | Memory control device |
US20090245010A1 (en) * | 2008-03-31 | 2009-10-01 | Advanced Micro Devices, Inc. | Data Driver Circuit for a Dynamic Random Access Memory (DRAM) Controller or the Like and Method Therefor |
US20090244995A1 (en) * | 2008-03-31 | 2009-10-01 | Advanced Micro Devices, Inc. | Circuit for Locking a Delay Locked Loop (DLL) and Method Therefor |
US20090244996A1 (en) * | 2008-03-31 | 2009-10-01 | Advanced Micro Devices, Inc. | Circuit Using a Shared Delay Locked Loop (DLL) and Method Therefor |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4345604B3 (en) * | 1992-03-06 | 2012-07-12 | Rambus Inc. | Device for communication with a DRAM |
JP4707204B2 (en) * | 1999-10-08 | 2011-06-22 | 富士通セミコンダクター株式会社 | Semiconductor memory device |
JP4002378B2 (en) * | 1999-12-27 | 2007-10-31 | エルピーダメモリ株式会社 | Electronic circuit |
JP3565837B2 (en) * | 2001-06-07 | 2004-09-15 | 株式会社アドバンテスト | Calibration method for semiconductor test equipment |
KR100427723B1 (en) | 2001-11-21 | 2004-04-28 | 주식회사 하이닉스반도체 | Memory Subsystem |
JP4181847B2 (en) * | 2002-10-25 | 2008-11-19 | エルピーダメモリ株式会社 | Timing adjustment circuit, semiconductor device and timing adjustment method |
JP4450586B2 (en) * | 2003-09-03 | 2010-04-14 | 株式会社ルネサステクノロジ | Semiconductor integrated circuit |
JP4843334B2 (en) * | 2006-02-23 | 2011-12-21 | 株式会社リコー | Memory control device |
JP5023539B2 (en) * | 2006-04-11 | 2012-09-12 | 富士通セミコンダクター株式会社 | Semiconductor device and signal processing method |
US8122275B2 (en) * | 2006-08-24 | 2012-02-21 | Altera Corporation | Write-leveling implementation in programmable logic devices |
JP2008071018A (en) * | 2006-09-13 | 2008-03-27 | Matsushita Electric Ind Co Ltd | Memory interface circuit |
JP5072317B2 (en) * | 2006-10-25 | 2012-11-14 | キヤノン株式会社 | Memory controller |
WO2008063199A1 (en) | 2006-11-20 | 2008-05-29 | Rambus Inc. | Memory systems and methods for dynamically phase adjusting a write strobe and data to account for receive-clock drift |
-
2008
- 2008-05-27 US US12/127,059 patent/US7961533B2/en active Active
-
2009
- 2009-05-21 TW TW098116834A patent/TWI494925B/en active
- 2009-05-27 WO PCT/US2009/003220 patent/WO2009145890A1/en active Application Filing
- 2009-05-27 JP JP2011511628A patent/JP5520938B2/en active Active
- 2009-05-27 EP EP09755253.3A patent/EP2304574B1/en active Active
- 2009-05-27 CN CN200980128912.4A patent/CN102099796B/en active Active
- 2009-05-27 KR KR1020107029336A patent/KR101443891B1/en active IP Right Grant
Patent Citations (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5373255A (en) * | 1993-07-28 | 1994-12-13 | Motorola, Inc. | Low-power, jitter-compensated phase locked loop and method therefor |
US5440515A (en) * | 1994-03-08 | 1995-08-08 | Motorola Inc. | Delay locked loop for detecting the phase difference of two signals having different frequencies |
US5857095A (en) * | 1995-09-12 | 1999-01-05 | Micron Electronics, Inc. | Method for aligning a control signal and a clock signal |
US6873564B2 (en) * | 2000-06-30 | 2005-03-29 | Micron Technology, Inc. | Zero latency-zero bus turnaround synchronous flash memory |
US6691214B1 (en) * | 2000-08-29 | 2004-02-10 | Micron Technology, Inc. | DDR II write data capture calibration |
US20040143775A1 (en) * | 2000-08-29 | 2004-07-22 | Wen Li | DDR II write data capture calibration |
US20050204245A1 (en) * | 2000-11-09 | 2005-09-15 | Lee Terry R. | Method of timing calibration using slower data rate pattern |
US20030021164A1 (en) * | 2001-03-09 | 2003-01-30 | Samsung Electronics Co., Ltd. | Semiconductor memory device having different data rates in read operation and write operation |
US20020147896A1 (en) * | 2001-04-07 | 2002-10-10 | Rentschler Eric M. | Memory controller with 1X/MX write capability |
US7038971B2 (en) * | 2002-04-23 | 2006-05-02 | Samsung Electronics Co., Ltd. | Multi-clock domain data input-processing device having clock-receiving locked loop and clock signal input method thereof |
US7117381B2 (en) * | 2003-01-06 | 2006-10-03 | Samsung Electronics Co., Ltd. | Control signal generation circuit and data transmission circuit having the same |
US6930932B2 (en) * | 2003-08-27 | 2005-08-16 | Hewlett-Packard Development Company, L.P. | Data signal reception latch control using clock aligned relative to strobe signal |
US7184323B2 (en) * | 2003-11-27 | 2007-02-27 | Elpida Memory, Inc. | 4N pre-fetch memory data transfer system |
US20050197082A1 (en) * | 2004-03-04 | 2005-09-08 | Ati Technologies, Inc. | Method and apparatus for fine tuning a memory interface |
US20050243608A1 (en) * | 2004-04-28 | 2005-11-03 | Lee Chang H | Input circuit for a memory device |
US20060114742A1 (en) * | 2004-11-30 | 2006-06-01 | Joe Salmon | Method and apparatus for optimizing strobe to clock relationship |
US20060133158A1 (en) * | 2004-12-22 | 2006-06-22 | Shin Beom J | Pipe latch circuit of multi-bit prefetch-type semiconductor memory device with improved structure |
US20060262613A1 (en) * | 2005-04-23 | 2006-11-23 | Georg Braun | Semiconductor memory and method for adapting the phase relationship between a clock signal and strobe signal during the acceptance of write data to be transmitted |
US7457174B2 (en) * | 2005-04-23 | 2008-11-25 | Infineon Technologies Ag | Semiconductor memory and method for adapting the phase relationship between a clock signal and strobe signal during the acceptance of write data to be transmitted |
US20070036020A1 (en) * | 2005-08-01 | 2007-02-15 | Edward Lee | Bit-deskewing IO method and system |
US7321525B2 (en) * | 2005-09-13 | 2008-01-22 | Renesas Technology Corp. | Semiconductor integrated circuit device |
US7487378B2 (en) * | 2005-09-19 | 2009-02-03 | Ati Technologies, Inc. | Asymmetrical IO method and system |
US7304910B1 (en) * | 2005-12-28 | 2007-12-04 | Hitachi, Ltd. | Semiconductor memory device with sub-amplifiers having a variable current source |
US20070217559A1 (en) * | 2006-03-16 | 2007-09-20 | Rambus Inc. | Signaling system with adaptive timing calibration |
US7518946B2 (en) * | 2006-09-15 | 2009-04-14 | Ricoh Company, Ltd. | Memory control device |
US20090086562A1 (en) * | 2007-09-27 | 2009-04-02 | Micron Technology, Inc. | Devices, systems, and methods for independent output drive strengths |
US20090245010A1 (en) * | 2008-03-31 | 2009-10-01 | Advanced Micro Devices, Inc. | Data Driver Circuit for a Dynamic Random Access Memory (DRAM) Controller or the Like and Method Therefor |
US20090244995A1 (en) * | 2008-03-31 | 2009-10-01 | Advanced Micro Devices, Inc. | Circuit for Locking a Delay Locked Loop (DLL) and Method Therefor |
US20090244996A1 (en) * | 2008-03-31 | 2009-10-01 | Advanced Micro Devices, Inc. | Circuit Using a Shared Delay Locked Loop (DLL) and Method Therefor |
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7929361B2 (en) | 2008-03-31 | 2011-04-19 | Advanced Micro Devices, Inc. | Circuit using a shared delay locked loop (DLL) and method therefor |
US20090244995A1 (en) * | 2008-03-31 | 2009-10-01 | Advanced Micro Devices, Inc. | Circuit for Locking a Delay Locked Loop (DLL) and Method Therefor |
US20090245010A1 (en) * | 2008-03-31 | 2009-10-01 | Advanced Micro Devices, Inc. | Data Driver Circuit for a Dynamic Random Access Memory (DRAM) Controller or the Like and Method Therefor |
US7869287B2 (en) | 2008-03-31 | 2011-01-11 | Advanced Micro Devices, Inc. | Circuit for locking a delay locked loop (DLL) and method therefor |
US7872937B2 (en) | 2008-03-31 | 2011-01-18 | Globalfoundries Inc. | Data driver circuit for a dynamic random access memory (DRAM) controller or the like and method therefor |
US7924637B2 (en) | 2008-03-31 | 2011-04-12 | Advanced Micro Devices, Inc. | Method for training dynamic random access memory (DRAM) controller timing delays |
US20090244996A1 (en) * | 2008-03-31 | 2009-10-01 | Advanced Micro Devices, Inc. | Circuit Using a Shared Delay Locked Loop (DLL) and Method Therefor |
US20160162426A1 (en) * | 2014-12-05 | 2016-06-09 | Marvell Israel (M.I.S.L) Ltd. | Optimal sampling of data-bus signals using configurable individual time delays |
US9864713B2 (en) * | 2014-12-05 | 2018-01-09 | Marvell Israel (M.I.S.L.) Ltd. | Optimal sampling of data-bus signals using configurable individual time delays |
US9892772B2 (en) * | 2016-03-16 | 2018-02-13 | SK Hynix Inc. | Semiconductor system and method of performing write leveling operation thereof |
KR20170107764A (en) * | 2016-03-16 | 2017-09-26 | 에스케이하이닉스 주식회사 | Semiconductor system and operating method thereof |
KR102472123B1 (en) | 2016-03-16 | 2022-11-30 | 에스케이하이닉스 주식회사 | Semiconductor system and operating method thereof |
US11152044B1 (en) * | 2020-04-17 | 2021-10-19 | SK Hynix Inc. | System for performing phase matching operation |
CN114627918A (en) * | 2020-12-09 | 2022-06-14 | 美光科技公司 | Write leveling of memory devices using write DLL circuitry |
Also Published As
Publication number | Publication date |
---|---|
TW201001418A (en) | 2010-01-01 |
TWI494925B (en) | 2015-08-01 |
KR20110021982A (en) | 2011-03-04 |
KR101443891B1 (en) | 2014-09-24 |
CN102099796A (en) | 2011-06-15 |
CN102099796B (en) | 2015-04-08 |
EP2304574A1 (en) | 2011-04-06 |
WO2009145890A1 (en) | 2009-12-03 |
EP2304574B1 (en) | 2013-07-03 |
US7961533B2 (en) | 2011-06-14 |
JP2011522323A (en) | 2011-07-28 |
JP5520938B2 (en) | 2014-06-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7961533B2 (en) | Method and apparatus for implementing write levelization in memory subsystems | |
CN1794580B (en) | Delay locked loop for use in semiconductor memory device and method thereof | |
US6611905B1 (en) | Memory interface with programable clock to output time based on wide range of receiver loads | |
US7227809B2 (en) | Clock generator having a delay locked loop and duty cycle correction circuit in a parallel configuration | |
US8144529B2 (en) | System and method for delay locked loop relock mode | |
US7158443B2 (en) | Delay-lock loop and method adapting itself to operate over a wide frequency range | |
JP3960583B2 (en) | Semiconductor memory device and system having memory module including the same | |
US6865135B2 (en) | Multi-frequency synchronizing clock signal generator | |
US8164368B2 (en) | Power savings mode for memory systems | |
US20120293221A1 (en) | Delay lock loop and delay lock method | |
US6493285B1 (en) | Method and apparatus for sampling double data rate memory read data | |
US20240021229A1 (en) | Low power memory with on-demand bandwidth boost | |
US7733129B2 (en) | Method and circuit for generating memory clock signal | |
US20110051531A1 (en) | Data output control circuit of a double data rate (ddr) synchronous semiconductor memory device responsive to a delay locked loop (dll) clock | |
KR102148806B1 (en) | Semiconductor device and semiconductor system with the same | |
US7616037B2 (en) | Method and apparatus for controlling power-down mode of delay locked loop | |
US7173878B2 (en) | Apparatus for driving output signals from DLL circuit | |
US10698846B2 (en) | DDR SDRAM physical layer interface circuit and DDR SDRAM control device | |
US20040008069A1 (en) | Method and apparatus for skewing data with respect to command on a DDR interface | |
US8482326B2 (en) | DLL circuit, semiconductor device including the same, and data processing system | |
US9570135B2 (en) | Apparatuses and methods to delay memory commands and clock signals | |
CN115576386B (en) | Signal delay adjustment chip, method, equipment and storage medium | |
JP2008210307A (en) | Ddr-sdram interface circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: ADVANCED MICRO DEVICES, INC.,CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SEARLES, SHAWN;REEL/FRAME:020999/0743 Effective date: 20080523 Owner name: ADVANCED MICRO DEVICES, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SEARLES, SHAWN;REEL/FRAME:020999/0743 Effective date: 20080523 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 12 |