US20100005439A1 - Designing method of semiconductor integrated circuit - Google Patents
Designing method of semiconductor integrated circuit Download PDFInfo
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- US20100005439A1 US20100005439A1 US12/556,649 US55664909A US2010005439A1 US 20100005439 A1 US20100005439 A1 US 20100005439A1 US 55664909 A US55664909 A US 55664909A US 2010005439 A1 US2010005439 A1 US 2010005439A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F2119/06—Power analysis or power optimisation
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Abstract
Description
- This application is a Continuation of International Application No. PCT/JP2007/056381, with an international filing date of Mar. 27, 2007, which designating the United States of America, the entire contents of which are incorporated herein by reference.
- The present invention relates to a designing method of a semiconductor integrated circuit and, more specifically, to a designing method of generating design data for verifying power supply control of an LSI divided into a plurality of power supply blocks using a hardware emulator or FPGA.
- In recent years, an LSI (semiconductor integrated circuit) divided into a plurality of power supply blocks has been developed. By performing ON/OFF control of power supply or DVFS (Dynamic Voltage and Frequency Scaling) control of a specific power supply block, the power consumption of the LSI can be reduced. The DVFS control dynamically controls the power supply voltage and the operating frequency.
- However, poor conditions of products associated with a change in the power supply voltage or the ON/OFF control of the power supply voltage frequently happen, and therefore enhancement of a verification technique is desired. It has been known that most of failures in the LSI are often caused by the operation composed of complicated operations of both software and hardware.
- At present, however, the verification about the power supply management control is usually performed by a software simulator, in which case there is a problem that debugging of software such as an actual power supply management application or the like cannot be appropriately performed in terms of simulation execution time.
- Therefore, a technique becomes necessary which verifies the power supply management control by a hardware emulator or FPGA (Field Programmable Gate Array) capable of verification at a higher speed than simulation. An existing hardware emulator is composed of an FPGA and a dedicated processor and cannot perform ON/OFF of the power supply voltage and dynamic change of the power supply voltage of a specific logic block, in which there is a problem that a high-speed verification technique for the power supply management control by the hardware emulator or FPGA has not been established.
- Japanese Laid-open Patent Publication No. 2006-31408 discloses a verification technique by an emulator to solve such problems. However, this is based on the assumption that there is an emulator which can monitor the power supply voltage and is not considered to be a direct solution unless such emulator and FPGA exist at present.
- According to an aspect of the embodiment, a designing method of a semiconductor integrated circuit includes: a preparation step of preparing first design data having a power gating circuit for supplying a power supply voltage to a logic circuit according to a power gating control signal and a first clamp circuit for clamping an output signal from the logic circuit according to a clamp control signal; and a generation step of generating, in order to verify the first design data, second design data in which a first mask circuit for masking the output signal from the logic circuit according to the power gating control signal is added in place of the power gating circuit to the first design data.
- According to an another aspect of the embodiment, a designing method of a semiconductor integrated circuit includes: a preparation step of preparing first design data having a power gating circuit for supplying a power supply voltage to a logic circuit according to a power gating control signal and a first clamp circuit for clamping an output signal from the logic circuit according to a clamp control signal; and a generation step of generating, in order to verify the first design data, second design data in which an error detection circuit for detecting an error based on the power gating control signal and the clamp control signal is added to the first design data.
- According to an other aspect of the embodiment, a designing method of a semiconductor integrated circuit includes: a preparation step of preparing first design data having a power gating circuit for controlling a value of a power supply voltage to be supplied to a logic circuit according to a power gating control signal and a first level shift circuit outputting a signal at a level different from a level of an output signal from the logic circuit by shifting the level of the output signal from the logic circuit; and a generation step of generating, in order to verify the first design data, second design data in which a comparison circuit for comparing whether or not the power supply voltage value according to the power gating control signal is an operable voltage and a first mask circuit for masking the output signal from the logic circuit according to a comparison result of the comparison circuit are added in place of the power gating circuit to the first design data.
- The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims.
- It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed.
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FIG. 1 is a block diagram illustrating a configuration example of an LSI designed by a designing method of a semiconductor integrated circuit of a first embodiment; -
FIG. 2 is a circuit diagram illustrating a configuration example of each of the circuit blocks inFIG. 1 ; -
FIG. 3 is a timing chart for explaining a normal operation of the circuit block inFIG. 2 ; -
FIG. 4 is a timing chart for explaining a malfunction of the circuit block inFIG. 2 ; -
FIG. 5 is a circuit diagram illustrating a configuration example of a circuit block made by modifying the circuit block inFIG. 2 in order to enable verification by a hardware emulator or FPGA; -
FIG. 6 is a timing chart for explaining a normal operation of the circuit block inFIG. 5 ; -
FIG. 7 is a timing chart for explaining a malfunction of the circuit block inFIG. 5 ; -
FIG. 8 is a circuit diagram illustrating a configuration example of a circuit block according to a second embodiment; -
FIG. 9 is a timing chart for explaining a malfunction of the circuit block inFIG. 8 ; -
FIG. 10 is a circuit diagram illustrating a configuration example of each of circuit blocks according to a third embodiment; -
FIG. 11 is a timing chart for explaining a malfunction of the circuit block inFIG. 10 ; -
FIG. 12 is a circuit diagram illustrating a configuration example of a circuit block made by modifying the circuit block inFIG. 10 in order to enable verification by the hardware emulator or FPGA; -
FIG. 13 is a timing chart for explaining a malfunction of the circuit block inFIG. 12 ; -
FIG. 14 is a circuit diagram illustrating a configuration example of a circuit block according to a fourth embodiment; -
FIG. 15 is a block diagram illustrating a configuration example of hardware in a computer for realizing a designing method according to a fifth embodiment; -
FIG. 16 is a flowchart illustrating a processing example of a program to be executed by the computer inFIG. 15 ; and -
FIG. 17 is a flowchart illustrating another processing example of a program to be executed by the computer inFIG. 15 . -
FIG. 1 is a block diagram illustrating a configuration example of an LSI (Large Scale Integrated Circuit) 100 designed by a designing method of a semiconductor integrated circuit of a first embodiment. The LSI 100 includes a first CPU (Central Processing Unit) 101, asecond CPU 102, a bus component orperipheral module 103, anaudio circuit 104, avideo circuit 105, acard interface 106, avoice codec circuit 107 and a power supply management (power management)unit 110. The bus component orperipheral module 103 is an On-Chip Bus (OCB), a memory controller, a clock generator or the like. Thecircuit blocks 101 to 107 each have a logic circuit. The powersupply management unit 110 can control ON/OFF of the power supply voltage for each of thecircuit blocks 101 to 107 and conduct DVFS (Dynamic Voltage and Frequency Scaling) control for each of theCPUs LSI 100. The DVFS control dynamically controls the power supply voltage and the operating frequency. -
FIG. 2 is a circuit diagram illustrating a configuration example of each of thecircuit blocks 101 to 107 inFIG. 1 . The powersupply management unit 110 outputs a power gating control signal PGC and a clamp control signal CCS to each of thecircuit blocks 101 to 107. A power gating circuit (cell) 201 is an n-channel field effect transistor having a gate connected to the power gating control signal PGC, a drain connected to a power supply voltage Vdd, and a source connected to a logic circuit (logic block) 202. Thepower gating circuit 201 supplies the power supply voltage to thelogic circuit 202 according to the power gating control signal PGC. Note that thepower gating circuit 201 may be composed of a p-channel field effect transistor. - A clamp circuit (cell) 203 clamps a logic signal SA according to the clamp control signal CCS and outputs a logic signal SB to the
logic circuit 202. Specifically, theclamp circuit 203 includes a logical product (AND) circuit which outputs a logical product signal SB of the logic signal SA and the clamp control signal CCS to thelogic circuit 202. - A clamp circuit (cell) 204 clamps an output logic signal SC from the
logic circuit 202 according to the clamp control signal CCS and outputs a logic signal SD. Specifically, theclamp circuit 204 outputs a logical product signal SD of the output logic signal SC from thelogic circuit 202 and the clamp control signal CCS. -
FIG. 3 is a timing chart for explaining the normal operation of the circuit block inFIG. 2 . When the power gating control signal PGC becomes high level, thepower gating circuit 201 is turned on so that the power supply voltage Vdd is supplied to thelogic circuit 202 to make thelogic circuit 202 operable. In contrast, when the power gating control signal PGC becomes low level, thepower gating circuit 201 is turned off so that the power supply voltage Vdd is not supplied to thelogic circuit 202 to bring thelogic circuit 202 into an operation stop state, whereby the power consumption can be reduced. - The clamp control signal CCS is controlled according to the power gating control signal PGC. Initially, the clamp control signal CCS and the power gating control signal PGC are at high level.
- First, a case of controlling the power supply voltage from ON to OFF will be described. The clamp control signal CCS is first changed from high level to low level, and the power gating control signal PGC is then changed from high level to low level.
- Next, a case of controlling the power supply voltage from OFF to ON will be described. The power gating control signal PGC is first changed from low level to high level, and the clamp control signal CCS is then changed from low level to high level.
- The logic signal SB becomes low level when the clamp control signal CCS is at low level, and becomes the same signal as the logic signal SA when the clamp control signal CCS is at high level.
- Since the power supply voltage Vdd is not supplied to the
logic circuit 202 when the power gating control signal PGC is at low level, the logic signal SC becomes a high impedance state HZ. - The logic signal SD becomes low level when the clamp control signal CCS is at low level, and becomes the same signal as the logic signal SC when the clamp control signal CCS is at high level. When the logic signal SC is in the high impedance state HZ, the clamp control signal CCS is at low level, so that the logic signal SD does not become the high impedance state HZ but is clamped at low level. In other words, the logic signal SC is clamped according to the clamp control signal CCS, whereby the high impedance state HZ of the logic signal SC is not propagated to the logic signal SD at the subsequent stage.
- As described above, in turning off the power supply to the circuit block, the
clamp circuits clamp circuits logic circuit 202 is off, a malfunction and an unintended flow of leak current due to propagation of an unknown value of the high impedance state (an intermediate potential or 0 V) HZ outputted from the circuit block can be prevented. Note that in the case where thelogic circuit 202 is composed of a CMOS and all of input signals are received by an ordinary buffer, inverter or the like, there is no problem if theclamp circuit 203 clamping the logic signal SA is omitted. Further, theclamp circuits -
FIG. 4 is a timing chart for explaining a malfunction of the circuit block inFIG. 2 , illustrating a failure case occurring when there is an incorrect relation between the clamp control signal CCS and the power gating control signal PGC in ON/OFF controlling the power supply to the circuit block. Essentially, it is necessary that, as illustrated inFIG. 3 , after the power gating control signal PGC is changed from low level to high level, the clamp control signal CCS is changed from low level to high level. A case will be described in which, however, the clamp control signal CCS is accidentally changed from low level to high level before the power gating control signal PGC is changed from low level to high level as illustrated inFIG. 4 . The logic signal SC becomes the high impedance state HZ when the power gating control signal PGC is at low level. Here, at atiming 401 of the logic signal SD, the logic signal SC is in the high impedance state HZ and the clamp control signal CCS is at high level, so that the logic signal SD becomes the high impedance state HZ. Propagation of the high impedance state HZ to the logic signal SD causes the circuit at the subsequent stage using the logic signal SD to malfunction. - As described above, in bringing the power OFF state to the power ON state, if the clamping by the
clamp circuits - However, such a high impedance state HZ cannot be expressed by the hardware emulator and FPGA, leading to a problem that the malfunction by such a signal cannot be detected by the hardware emulator or FPGA.
-
FIG. 5 is a circuit diagram illustrating a configuration example of a circuit block made by modifying the circuit block inFIG. 2 in order to enable verification by the hardware emulator or FPGA.FIG. 5 is made by omitting thepower gating circuit 201 and addingmask logic circuits selectors power gating circuit 201 with respect to the circuit block inFIG. 2 . Hereinafter, points thatFIG. 5 is different fromFIG. 2 will be described. Themask logic circuits - The
selector 502 selects the mask data outputted from themask logic circuit 501 or the logic signal SB outputted from theclamp circuit 203 according to the power gating control signal PGC and outputs it to thelogic circuit 202. In short, theselector 502 is a mask circuit for masking the input signal to thelogic circuit 202 according to the power gating control signal PGC. - The
selector 504 selects the mask data outputted from themask logic circuit 503 or the logic signal outputted from thelogic circuit 202 according to the power gating control signal PGC and outputs it as the logic signal SC to theclamp circuit 204. In short, theselector 504 is a mask circuit for masking the output signal from thelogic circuit 202 according to the power gating control signal PGC. -
FIG. 6 is a timing chart for explaining the normal operation of the circuit block inFIG. 5 . Theselector 502 selects the output logic signal SB from theclamp circuit 203 when the power gating control signal PGC is at high level or selects the output mask data (for example, high level) from themask logic circuit 501 when the power gating control signal PGC is at low level, and outputs it to thelogic circuit 202. Theselector 504 selects the output logic signal from thelogic circuit 202 when the power gating control signal PGC is at high level or selects the output mask data (for example, high level) from themask logic circuit 503 when the power gating control signal PGC is at low level, and outputs it to theclamp circuit 204. - The clamp control signal CCS, the power gating control signal PGC and the logic signal SB are the same as those in
FIG. 3 . - The logic signal SC is the same signal as the output logic signal from the
logic circuit 202 when the power gating control signal PGC is at high level and is the same signal as the mask data (for example, high level) when the power gating control signal PGC is at low level. In other words, the high impedance state HZ inFIG. 3 is expressed as the mask data (for example, high level) inFIG. 6 . - The logic signal SD becomes low level when the clamp control signal CCS is at low level and is the same signal as the logic signal SC when the clamp control signal CCS is at high level. When the logic signal SC is the mask data (for example, high level), the clamp control signal CCS is at low level, so that the logic signal SD does not become the mask data (for example, high level) but is clamped at low level. In other words, the logic signal SC is clamped according to the clamp control signal CCS, whereby the mask data (for example, high level) of the logic signal SC is not propagated to the logic signal SD at the subsequent stage.
-
FIG. 7 is a timing chart for explaining a malfunction of the circuit block inFIG. 5 , illustrating a failure case occurring when there is an incorrect relation between the clamp control signal CCS and the power gating control signal PGC in ON/OFF controlling the power supply to the circuit block. The clamp control signal CCS, the power gating control signal PGC and the logic signal SB are the same as those inFIG. 4 . - The logic signal SC becomes the mask data (for example, high level) when the power gating control signal PGC is at low level, and becomes the same signal as the output logic signal from the
logic circuit 202 when the power gating control signal PGC is at high level. - At a
timing 701 of the logic signal SD, since the logic signal SC is the mask data (for example, high level) and the clamp control signal CCS is at high level, the logic signal SD becomes the same signal as the mask data (for example, high level). By detecting this state by the hardware emulator or FPGA, a malfunction (design error) of the circuit block can be detected. - As described above, since the
power gating circuit 201 inFIG. 2 cannot be actually realized by the hardware emulator and FPGA, the power cut-off (OFF) state of thelogic circuit 202 is simulated by masking the output signal (or input/output signal) from thelogic circuit 202 by the mask data with a specific value. Theselectors logic circuit 202 to pass as it is or to take the value masked by the mask data according to the power gating control signal PGC. At the power cut-off, the value masked by the mask data is selected. As a matter of course, it is also possible that the power gating control signal PGC is used not as a select signal but directly as the mask data. Thus, if there is a control error in the clamp control signal CCS as illustrated inFIG. 7 , not the output signal from thelogic circuit 202 but the mask data is outputted as the logic signal SC, so that the malfunction can be detected also by the hardware emulator or FPGA. - Note that the mask circuit (including the
mask logic circuit 501 and the selector 502) on the side of the input signal to thelogic circuit 202 can be omitted. Besides, the mask data outputted from themask logic circuits - According to this embodiment, by generating the design data of the circuit block for verification, the operation in ON/OFF control of the power supply voltage can be verified. Further, the verification can be performed by the hardware emulator or FPGA, so that high-speed verification is possible.
-
FIG. 8 is a circuit diagram illustrating a configuration example of a circuit block according to a second embodiment, and illustrating a configuration example of a circuit block made by modifying the circuit block inFIG. 2 in order to enable verification by the hardware emulator or FPGA.FIG. 8 is made by omitting thepower gating circuit 201 and adding errorcondition detection circuits 801 to 803, a logical sum (OR)circuit 811 and anerror storage unit 812 in place of thepower gating circuit 201 with respect to the circuit block inFIG. 2 . Hereinafter, points thatFIG. 8 is different fromFIG. 2 will be described. - The first error
condition detection circuit 801 detects and outputs an error when a first error condition is satisfied, based on the power gating control signal PGC and the clamp control signal CCS. The second errorcondition detection circuit 802 detects and outputs an error when a second error condition is satisfied. The third errorcondition detection circuit 803 detects and outputs an error when a third error condition is satisfied. The ORcircuit 811 outputs a logical sum signal of the output signals from the errorcondition detection circuits 801 to 803 to theerror storage unit 812 as an error detection signal ER1. When the error detection signal ER1 becomes high level representing an error, theerror storage unit 812 holds the error state as high level and outputs an error detection signal ER2. -
FIG. 9 is a timing chart for explaining a malfunction of the circuit block inFIG. 8 , illustrating a failure case occurring when there is an incorrect relation between the clamp control signal CCS and the power gating control signal PGC in ON/OFF controlling the power supply to the circuit block. The clamp control signal CCS, the power gating control signal PGC and the logic signals SB, SC and SD are the same as those inFIG. 4 . - The first error
condition detection circuit 801 detects an error based on the power gating control signal PGC and the clamp control signal CCS. Specifically, the first errorcondition detection circuit 801 detects an error when the clamp control signal CCS is at high level and the power gating control signal PGC is at low level as at thetiming 401, and outputs high level, but otherwise outputs low level. The output signal from the first errorcondition detection circuit 801 becomes the error detection signal ER1. The error detection signal ER2 has an initial state at low level and becomes and keeps high level representing the error state once the error detection signal ER1 becomes high level. - As described above, this embodiment is made by leaving the logic configurations of the
clamp circuits logic circuit 202 inFIG. 2 as they are and adding the errorcondition detection circuits 801 to 803 using specific control signals such as the power gating control signal PGC, the clamp control signal CCS and so on. The errorcondition detection circuits 801 to 803 can be circuits detecting a condition under which the circuit block potentially causes a malfunction. For example, the errorcondition detection circuit 801 detects, as an error, a condition that the clamp control signal CCS is at high level and the power gating control signal PGC is at low level. Then, in the case where there are a plurality of errorcondition detection circuits 801 to 803, they are configured such that their detection results can be individually held or the error detection signal ER1 summarized by theOR circuit 811 can be held in theerror storage unit 812 so that occurrence of an error can be verified afterward. - The error
condition detection circuits 801 to 803 and theerror storage unit 812 may be provided in advance in circuitry as a redundant test circuit or may be transplanted into the hardware emulator or FPGA and added in verification. Further, a method of reading the result of theerror storage unit 812 may be configured such that the result can be read out by the CPU or the like via the bus in the semiconductor chip or an interface signal for reading out the error result is added when the result is compiled for the hardware emulator or FPGA. - According to this embodiment, by generating the design data of the circuit block for verification, the operation in ON/OFF control of the power supply voltage can be verified. Further, the verification can be performed by the hardware emulator or FPGA, so that high-speed verification is possible.
-
FIG. 10 is a circuit diagram illustrating a configuration example of each of the circuit blocks 101 to 107 (FIG. 1 ) according to a third embodiment, andFIG. 11 is a timing chart for explaining a malfunction of the circuit block inFIG. 10 .FIG. 10 is made by providingclamp circuits clamp circuits FIG. 2 . Hereinafter, points thatFIG. 10 is different fromFIG. 2 will be described. - The
power gating circuit 201 controls the value of the power supply voltage to be supplied to thelogic circuit 202 according to the power gating control signal PGC. For example, thepower gating circuit 201 supplies a power supply voltage of 1.2 V to thelogic circuit 202 when the power gating control signal PGC is brought to a voltage V1, and supplies a power supply voltage of 0.8 V to thelogic circuit 202 when the power gating control signal PGC is brought to a voltage V2. Here, the voltage V2 is a voltage lower than the voltage V1. The voltages V1 and V2 are voltages higher than 0 V. - The
clamp circuit 1003 with level shift function includes a clamp circuit and a level shift circuit. Theclamp circuit 1003 clamps the logic signal SA according to the clamp control signal CCS and outputs the logic signal SB to thelogic circuit 202. Specifically, theclamp circuit 1003 has an AND circuit which outputs the logical product signal SB of the logic signal SA and the clamp control signal CCS to thelogic circuit 202. Further, the clamp circuit (level shift circuit) 1003 outputs to thelogic circuit 202 the logic signal SB at a level different from that of the logic signal SA by shifting the level of the logic signal SA. For example, when thepower gating circuit 201 supplies the power supply voltage of 0.8 V to thelogic circuit 202, the logic signal SA has a high level of 1.2 V and a low level of 0 V, and the logic signal SB has a high level of 0.8 V and a low level of 0 V. In this case, theclamp circuit 1003 shifts the level from 1.2 V to 0.8 V. - The
clamp circuit 1004 with level shift function includes a clamp circuit and a level shift circuit. Theclamp circuit 1004 clamps the output logic signal SC from thelogic circuit 202 according to the clamp control signal CCS and outputs the logic signal SD. Specifically, theclamp circuit 1004 has an AND circuit which outputs the logical product signal SD of the output logic signal SC from thelogic circuit 202 and the clamp control signal CCS. Further, the clamp circuit (level shift circuit) 1004 outputs the logic signal SD at a level different from that of the output logic signal SC from thelogic circuit 202 by shifting the level of the output logic signal SC from thelogic circuit 202. For example, when thepower gating circuit 201 supplies the power supply voltage of 0.8 V to thelogic circuit 202, the logic signal SC has a high level of 0.8 V and a low level of 0 V, and the logic signal SD has a high level of 1.2 V and a low level of 0 V. In this case, theclamp circuit 1004 shifts the level from 0.8 V to 1.2 V. - A malfunction in
FIG. 11 will be described. Thepower gating circuit 201 supplies the power supply voltage of 1.2 V to thelogic circuit 202 when the power gating control signal PGC is at the voltage V1. Further, it is assumed that thepower gating circuit 201 supplies a power supply voltage of, for example, 0.6 V to thelogic circuit 202 when the power gating control signal PGC is at the voltage V2. Here, it is assumed that thelogic circuit 202 has an operable voltage of, for example, 0.8 V or higher and its normal operation is not ensured at the power supply voltage of 0.6 V. - The voltages V1 and V2 are voltages higher than 0 V, and when the
power gating circuit 201 is supplying the power supply voltage to thelogic circuit 202, the clamp control signal CCS becomes high level. The logic signal SB becomes the same signal as the logic signal SA when the clamp control signal CCS is at high level. - When the power gating control signal PGC is at the voltage V1, the power supply voltage of 1.2 V is supplied to the
logic circuit 202, so that thelogic circuit 202 outputs a normal logic signal SC. In contrast, when the power gating control signal PGC is at the voltage V2, the power supply voltage of 0.6 V is supplied to thelogic circuit 202, so that thelogic circuit 202 does not perform the normal operation but outputs a logic signal SC having an unknown value at atiming 1101. The logic signal SD becomes the same signal as the logic signal SC when the clamp control signal CCS is at high level. - The unknown value of the logic signal SC propagates to the logic signal SD to cause a problem of occurrence of a malfunction in the circuit at the subsequent stage using the logic signal SD. The hardware emulator and FPGA cannot express such an unknown value, thus causing a problem of failure to detect the above-described malfunction.
- As described above, in the case where the value of the power supply voltage to the circuit block is changed, a malfunction occurs if the power supply voltage is set to a voltage value outside the voltage range within which the
logic circuit 202 is operable. In this case, in the case where the value of the power supply voltage to be supplied to thelogic circuit 202 can be changed by an instruction from the powersupply management unit 110, for example, if the value of the supplied power supply voltage is decreased to be lower than the power supply voltage at which circuit elements constituting the logic circuit 202 (a combinational circuit, a sequential circuit such as a flip-flop or the like, a memory circuit such as SRAM or the like, other analog circuits and so on) can operate, the logic signal SC outputted from thelogic circuit 202 takes an unknown value to cause a malfunction in an actual circuit. - However, the hardware emulator and FPGA keep applying a fixed power supply voltage at all times to the circuits realizing the
logic circuit 202 and therefore have a problem of failure to recognize the unknown value due to the decrease in the power supply voltage and detect a malfunction. -
FIG. 12 is a circuit diagram illustrating a configuration example of a circuit block made by modifying the circuit block inFIG. 10 in order to enable verification by the hardware emulator or FPGA.FIG. 12 is made by omitting thepower gating circuit 201 and adding a power supplyvoltage storage unit 1201, an operablevoltage storage unit 1202, acomparison circuit 1203,mask logic circuits selectors power gating circuit 201 with respect to the circuit block inFIG. 10 . Hereinafter, points thatFIG. 12 is different fromFIG. 10 will be described. - The power supply
voltage storage unit 1201 stores the power supply voltage value according to the power gating control signal PGC. For example, the power supply voltage is 1.2 V when the power gating control signal PGC is at the voltage V1, and the power supply voltage is 0.6 V when the power gating control signal PGC is at the voltage V2. The operablevoltage storage unit 1202 stores the operable voltage of thelogic circuit 202. For example, the operable voltage of thelogic circuit 202 ranges from 0.8 V to 1.2 V. Thecomparison circuit 1203 compares whether or not the power supply voltage value stored in the power supplyvoltage storage unit 1201 is the operable voltage stored in the operablevoltage storage unit 1202, and outputs a comparison result. - The
mask logic circuits - The
selector 1205 selects the mask data outputted from themask logic circuit 1204 or the logic signal SB outputted from theclamp circuit 1003 according to the comparison result of thecomparison circuit 1203, and outputs it to thelogic circuit 202. In short, theselector 1205 is a mask circuit for masking the input signal to thelogic circuit 202 according to the comparison result of thecomparison circuit 1203. - The
selector 1207 selects the mask data outputted from themask logic circuit 1206 or the logic signal outputted from thelogic circuit 202 according to the comparison result of thecomparison circuit 1203, and outputs it as the logic signal SC to theclamp circuit 1004. In short, theselector 1207 is a mask circuit for masking the output signal from thelogic circuit 202 according to the comparison result of thecomparison circuit 1203. -
FIG. 13 is a timing chart for explaining a malfunction of the circuit block inFIG. 12 . Theselector 1205 selects the output logic signal SB from theclamp circuit 1003 when the power supply voltage value is the operable voltage or selects the output mask data (for example, high level) from themask logic circuit 1204 when the power supply voltage value is not the operable voltage, and outputs it to thelogic circuit 202. Theselector 1207 selects the output logic signal from thelogic circuit 202 when the power supply voltage value is the operable voltage or selects the output mask data (for example, high level) from themask logic circuit 1206 when the power supply voltage value is not the operable value, and outputs it to theclamp circuit 1004. - The clamp control signal CCS, the power gating control signal PGC and the logic signals SA and SB are the same as those in
FIG. 11 . - The logic signal SC becomes the same signal as the output logic signal from the
logic circuit 202 when the power supply voltage value is the operable voltage or becomes the same signal as the mask data (for example, high level) when the power supply voltage value is not the operable voltage. In other words, the unknown value at thetiming 1101 inFIG. 11 is expressed as the mask data (for example, high level) at atiming 1301 inFIG. 13 . - The logic signal SD becomes the same signal as the logic signal SC when the clamp control signal CCS is at high level. The unknown value generated because the power supply voltage value is not the operable voltage is expressed as mask data, and the mask data is propagated from the logic signal SC to the logic signal SD, whereby a malfunction can be detected by the hardware emulator or FPGA.
- As described above, the supplied power voltage value instructed from the power
supply management unit 110 is stored in the power supply voltage storage unit (a flip-flop, a memory or the like) 1201, and the voltage (the minimum voltage value and/or the maximum voltage value) at which thelogic circuit 202 is operable is stored in the operable voltage storage unit (a flip-flop, a memory or the like) 1202. Thecomparison circuit 1203 compares the supplied power supply voltage value and the operable voltage. As a result of the comparison, if the supplied power supply voltage is not the operable voltage, theselector 1205 outputs the mask data to thelogic circuit 202, and theselector 1206 outputs the mask data to theclamp circuit 1004. As a matter of course, it is also possible that the comparison result output signal from thecomparison circuit 1203 is used not as a select signal but directly as the mask data. - Thus, if the value of the supplied power supply voltage to the circuit block in the semiconductor chip is brought to an inappropriate value (an inoperable voltage value), the malfunction in such a case can be detected by the hardware emulator or FPGA by masking the output signal (or the input/output signal) from the
logic circuit 202 by the mask data. - Note that the
clamp circuits - According to this embodiment, by generating the design data of the circuit block for verification, the operation in dynamic change of the power supply voltage can be verified. Further, the verification can be performed by the hardware emulator or FPGA, so that high-speed verification is possible.
-
FIG. 14 is a circuit diagram illustrating a configuration example of a circuit block according to a fourth embodiment, and illustrating a configuration example of a circuit block made by modifying the circuit block inFIG. 10 in order to enable verification by the hardware emulator or FPGA. This embodiment is made by combining the first to third embodiments. Hereinafter, points thatFIG. 14 is different fromFIG. 12 will be described. - An AND
circuit 1403 outputs a logical product signal of a logic inverted signal of a comparison result signal from thecomparison circuit 1203 and the power gating control signal PGC. Theselectors circuit 1403. Thus, the control by the first and third embodiments is possible. - Further, the configurations of the error
condition detection circuits 801 to 803, theOR circuit 811 and theerror storage unit 812 are the same as those in the second embodiment (FIG. 8 ). Thus, the control by the second embodiment is possible. - As described above, this embodiment is the one made by combining the first to third embodiments. In this case, the output signal (or the input/output signal) from the
logic circuit 202 is masked when the power gating control signal PGC becomes low level to turn off the power supply or when the supplied power supply voltage falls outside the operable voltage range to bring the comparison result signal from thecomparison circuit 1203 to high level. - Thus, when the power supply to the
logic circuit 202 is turned off or when the supplied power supply voltage value is set to an inoperable voltage value, the mask data can be propagated to the logic signal SD, and the occurrence of a malfunction can be recognized by the errorcondition detection circuits 801 to 803, so that the verification of the power supply management control can be performed by the hardware emulator or FPGA. - Note that the
clamp circuits - According to this embodiment, by generating the design data of the circuit block for verification, the operation in ON/OFF control and dynamic change of the power supply voltage can be verified. Further, the verification can be performed by the hardware emulator or FPGA, so that high-speed verification is possible.
-
FIG. 15 is a block diagram illustrating a configuration example of hardware in a computer (designing apparatus) 1510 for realizing a designing method according to a fifth embodiment. Thecomputer 1510 can be used to generate the design data of the circuit blocks for verification in the first to fourth embodiments. - To a
bus 1501, aCPU 1502, aROM 1503, aRAM 1504, anetwork interface 1505, aninput device 1506, anoutput device 1507 and anexternal storage 1508 are connected. - The
CPU 1502 performs processing or computation of data and controls various components connected thereto via thebus 1501. A control procedure (computer program) for theCPU 1502 is stored in theROM 1503 in advance and started by executing the computer program by theCPU 1502. A computer program is stored in theexternal storage 1508, and the computer program is copied into theRAM 1504 and executed by theCPU 1502. TheRAM 1504 is used as a work memory for inputting/outputting and transmitting/receiving data and a temporary storage for controlling the components. Theexternal storage 1508 is, for example, a hard disk storage, a CD-ROM or the like, and its stored contents are not erased even if the power is turned off. TheCPU 1502 executes the computer program in theRAM 1504 to thereby perform processing inFIG. 16 orFIG. 17 which will be described later so as to generate the design data of the circuit blocks in the first to fourth embodiments. - The
network interface 1505 is an interface for connecting to a network and is connected to a hardware emulator orFPGA 1520. Thecomputer 1510 can transmit the design data to the hardware emulator orFPGA 1520 via thenetwork interface 1505. Theinput device 1506 is, for example, a keyboard, a mouse and the like and can perform various kinds of designation, input and so on. Theoutput device 1507 is a display, a printer and so on. -
FIG. 16 is a flowchart illustrating a processing example of the program executed by thecomputer 1510 inFIG. 15 . Thecomputer 1510 performs the following processing by executing the program. - First, at a
step 1601, thecomputer 1510 prepares RTL (Register Transfer Level) design data of the circuit block including theclamp circuits clamp circuits external storage 1508. In the first and second embodiments, the design data having the circuit block inFIG. 2 is prepared. In the third and fourth embodiments, the design data having the circuit block inFIG. 10 is prepared. - Then, at a
step 1602, thecomputer 1510 generates, in order to verify the above-described RTL design data, RTL design data of the circuit block for verification based on the above-described RTL design data using a CAD (Computer-Aided Design) tool, alibrary 1603 andmask circuit information 1604. Thelibrary 1603 and themask circuit information 1604 are stored in theexternal storage 1508. In the first embodiment, in order to verify the above-described RTL design data, RTL design data in which the mask circuit (including themask logic circuits selectors 502 and 504) is added in place of thepower gating circuit 201 to the above-described RTL design data is generated. In the second embodiment, in order to verify the above-described RTL design data, RTL design data in which the error detection circuit (including the errorcondition detection circuits 801 to 803, theOR circuit 811 and the error storage unit 812) is added to the above-described RTL design data is generated. In the third embodiment, in order to verify the above-described RTL design data, RTL design data in which the power supplyvoltage storage unit 1201, the operablevoltage storage unit 1202, thecomparison circuit 1203 and the mask circuit (including themask logic circuits selectors 1205 and 1207) are added in place of thepower gating circuit 201 to the above-described RTL design data is generated. - Then, at a
step 1605, thecomputer 1510 writes the RTL design data generated at thestep 1602 into theexternal storage 1508. - Then, at a
step 1606, thecomputer 1510 generates netlist design data for the hardware emulator orFPGA 1520 based on the RTL design data generated at thestep 1602 using a netlist synthesizing tool for the hardware emulator orFPGA 1520 and alibrary 1607. Thelibrary 1607 is stored in theexternal storage 1508. - Then, at a
step 1608, thecomputer 1510 writes the netlist design data generated at thestep 1606 into theexternal storage 1508, and transmits the netlist design data to the hardware emulator orFPGA 1520 via thenetwork interface 1505. - Then, at a
step 1609, the hardware emulator orFPGA 1520 receives the netlist design data from thecomputer 1510 and performs the operation verification. Since the netlist design data is generated such that a malfunction can be verified as described in the first to fourth embodiments, the hardware emulator orFPGA 1520 can verify the malfunction due to the design errors as illustrated in the first to fourth embodiments. -
FIG. 17 is a flowchart illustrating a processing example of the program executed by thecomputer 1510 inFIG. 15 . Thecomputer 1510 performs the following processing by executing the program. InFIG. 16 , an example has been illustrated in which the design data of the circuit block for verification is generated at the stage of the RTL design data. InFIG. 17 , an example will be described in which the design data of the circuit block for verification is generated at the stage of the netlist design data. - First, at a
step 1701, thecomputer 1510 prepares RTL design data of the circuit block before theclamp circuits clamp circuits external storage 1508. The RTL design data of the circuit block is the same as that at thestep 1601 except that there are noclamp circuits clamp circuits - Then, at a
step 1702, thecomputer 1510 generates netlist design data in which theclamp circuits clamp circuits library 1703 and clamp circuit or levelshift circuit information 1704. Thelibrary 1703 and the clamp circuit or levelshift circuit information 1704 are stored in theexternal storage 1508. - Then, at a
step 1705, thecomputer 1510 writes the netlist design data generated at thestep 1702 into theexternal storage 1508. - Then, at a
step 1706, thecomputer 1510 generates, in order to verify the above-described netlist design data, netlist design data of the circuit block for verification based on the above-described netlist design data using a CAD tool, alibrary 1707 andmask circuit information 1708. Thelibrary 1707 and themask circuit information 1708 are stored in theexternal storage 1508. Thestep 1706 is the same as thestep 1602 except that the netlist design data is generated in place of the RTL design data. - Then, at a
step 1709, thecomputer 1510 writes the netlist design data generated at thestep 1706 into theexternal storage 1508. - Then, at a
step 1710, thecomputer 1510 generates netlist design data for the hardware emulator orFPGA 1520 based on the netlist design data generated at thestep 1706 using the netlist synthesizing tool for the hardware emulator orFPGA 1520 and alibrary 1711. Thelibrary 1711 is stored in theexternal storage 1508. - Then, at a step 1712, the
computer 1510 writes the netlist design data generated at thestep 1710 into theexternal storage 1508, and transmits the netlist design data to the hardware emulator orFPGA 1520 via thenetwork interface 1505. - Then, at a
step 1713, the hardware emulator orFPGA 1520 receives the netlist design data from thecomputer 1510 and performs the operation verification. Since the netlist design data is generated such that a malfunction can be verified as described in the first to fourth embodiments, the hardware emulator orFPGA 1520 can verify the malfunction due to the design error as illustrated in the first to fourth embodiments. - This embodiment can be realized by the
computer 1510 executing the program. Further, means for supplying the program to the computer, for example, a computer-readable recording medium such as a CD-ROM or the like recording the program thereon or a transmission medium such as the Internet or the like transmitting the program is also applicable as an embodiment. Further, a computer program product such as the above-described computer-readable recording medium or the like recording the program thereon is also applicable as an embodiment. The above-described program, recording medium, transmission medium and computer program product are included in the scope of the present invention. As the recording medium, for example, a flexible disk, a hard disk, an optical disk, a magneto-optic disk, a CD-ROM, a magnetic tape, a non-volatile memory card, a ROM and so on can be used. - As described above, in this embodiment, CAD processing is performed which automatically changes circuits from the
clamp circuits clamp circuits circuits FIG. 14 . This ensures that the power supply management verification is performed more simply and surely by the hardware emulator orFPGA 1520. Further, by automatically inserting the mask circuit or the like at thestep 1602 or thestep 1706, the verification by the hardware emulator or FPGA becomes possible with ease. - The malfunction when the power supply management control is performed (the control error of the control signal, the malfunction when the logic circuit accidentally decreases the power supply voltage to be lower than the operable voltage, or the like) can be verified by the hardware emulator or FPGA at a high speed.
- It should be noted that the above embodiments merely illustrate concrete examples of implementing the present invention, and the technical scope of the present invention is not to be construed in a restrictive manner by these embodiments. That is, the present invention may be implemented in various forms without departing from the technical spirit or main features thereof.
Claims (20)
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PCT/JP2007/056381 WO2008126207A1 (en) | 2007-03-27 | 2007-03-27 | Semiconductor integrated circuit designing method |
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PCT/JP2007/056381 Continuation WO2008126207A1 (en) | 2007-03-27 | 2007-03-27 | Semiconductor integrated circuit designing method |
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US20140025879A1 (en) * | 2012-07-17 | 2014-01-23 | Etron Technology, Inc. | Dynamic random access memory applied to an embedded display port |
WO2018200243A1 (en) * | 2017-04-27 | 2018-11-01 | Qualcomm Incorporated | Methods for detecting an imminent power failure in time to protect local design state |
US10535394B2 (en) | 2017-07-20 | 2020-01-14 | Samsung Electronics Co., Ltd. | Memory device including dynamic voltage and frequency scaling switch and method of operating the same |
US11002790B2 (en) * | 2018-11-07 | 2021-05-11 | SK Hynix Inc. | Power gating system |
US11280509B2 (en) | 2017-07-17 | 2022-03-22 | Johnson Controls Technology Company | Systems and methods for agent based building simulation for optimal control |
Families Citing this family (1)
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JP5591621B2 (en) * | 2010-08-04 | 2014-09-17 | ピーエスフォー ルクスコ エスエイアールエル | Semiconductor device and control method thereof |
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US5051572A (en) * | 1990-04-06 | 1991-09-24 | Mcdonnell Douglas Corporation | Photomultiplier gating circuit |
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US20140025879A1 (en) * | 2012-07-17 | 2014-01-23 | Etron Technology, Inc. | Dynamic random access memory applied to an embedded display port |
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US11183830B2 (en) | 2017-04-27 | 2021-11-23 | Qualcomm Incorporated | Methods for detecting an imminent power failure in time to protect local design state |
US11280509B2 (en) | 2017-07-17 | 2022-03-22 | Johnson Controls Technology Company | Systems and methods for agent based building simulation for optimal control |
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Also Published As
Publication number | Publication date |
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WO2008126207A1 (en) | 2008-10-23 |
JP5012890B2 (en) | 2012-08-29 |
JPWO2008126207A1 (en) | 2010-07-22 |
US8250504B2 (en) | 2012-08-21 |
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