US20100012175A1

US20100012175A1 - Ohmic n-contact formed at low temperature in inverted metamorphic multijunction solar cells

Info

Publication number: US20100012175A1
Application number: US12/218,582
Authority: US
Inventors: Tansen Varghese; Arthur Cornfeld
Original assignee: Emcore Solar Power Inc
Current assignee: Solaero Solar Power Inc
Priority date: 2008-07-16
Filing date: 2008-07-16
Publication date: 2010-01-21
Also published as: US20150162485A1; US8753918B2; US8987042B2; US9601652B2; US20130034931A1; US20140342494A1

Abstract

A method of forming a multifunction solar cell including an upper subcell, a middle subcell, and a lower subcell by providing a substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on the substrate having a first band gap; forming a second solar subcell over the first solar subcell having a second band gap smaller than the first band gap; forming a graded interlayer over the second subcell, the graded interlayer having a third band gap greater than the second band gap; forming a third solar subcell over the graded interlayer having a fourth band gap smaller than the second band gap such that the third subcell is lattice mismatched with respect to the second subcell; and forming a contact composed of a sequence of layers over the first subcell at a temperature of 280° C. or less and having a contact resistance of less than 5×10⁻⁴ohms-cm².

Description

REFERENCE TO RELATED APPLICATIONS

This application is related to co-pending U.S. patent application Ser. No. 12/218,558 filed Jul. 16, 2008.
This application is related to co-pending U.S. patent application Ser. No. 12/123,864 filed May 20, 2008.
This application is related to co-pending U.S. patent application Ser. No. 12/102,550 filed Apr. 14, 2008.
This application is related to co-pending U.S. patent application Ser. No. 12/047,842, and U.S. Ser. No. 12/047,944, filed Mar. 13, 2008.
This application is related to co-pending U.S. patent application Ser. No. 12/023,772, filed Jan. 31, 2008.
This application is related to co-pending U.S. patent application Ser. No. 11/956,069, filed Dec. 13, 2007.
This application is also related to co-pending U.S. patent application Ser. Nos. 11/860,142 and 11/860,183 filed Sep. 24, 2007.
This application is also related to co-pending U.S. patent application Ser. No. 11/836,402 filed Aug. 8, 2007.
This application is also related to co-pending U.S. patent application Ser. No. 11/616,596 filed Dec. 27, 2006.
This application is also related to co-pending U.S. patent application Ser. No. 11/614,332 filed Dec. 21, 2006.
This application is also related to co-pending U.S. patent application Ser. No. 11/445,793 filed Jun. 2, 2006.
This application is also related to co-pending U.S. patent application Ser. No. 11/500,053 filed Aug. 7, 2006.

GOVERNMENT RIGHTS STATEMENT

This invention was made with government support under Contract No. FA9453-06-C-0345 awarded by the U.S. Air Force. The Government has certain rights in the invention.

BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to the field of semiconductor devices, and to processes requiring the formation of ohmic contacts at relatively low temperatures. More particularly, the invention relates to fabrication processes and devices such as multifunction solar cells based on III-V semiconductor compounds including a metamorphic layer. Such devices are also known as inverted metamorphic multifunction solar cells.
2. Description of the Related Art
Photovoltaic cells, also called solar cells, are one of the most important new energy sources that have become available in the past several years. Considerable effort has gone into solar cell development. As a result, solar cells are currently being used in a number of commercial and consumer-oriented applications. While significant progress has been made in this area, the requirement for solar cells to meet the needs of more sophisticated applications has not kept pace with demand. Applications such as concentrator terrestrial power systems and satellites used in data communications have dramatically increased the demand for solar cells with improved power and energy conversion characteristics.
In satellite and other space related applications, the size, mass and cost of a satellite power system are dependent on the power and energy conversion efficiency of the solar cells used. Putting it another way, the size of the payload and the availability of on-board services are proportional to the amount of power provided. Thus, as the payloads become more sophisticated, solar cells, which act as the power conversion devices for the on-board power systems, become increasingly more important.
Solar cells are often fabricated in vertical, multifunction structures, and disposed in horizontal arrays, with the individual solar cells connected together in a series. The shape and structure of an array, as well as the number of cells it contains, are determined in part by the desired output voltage and current.
Inverted metamorphic solar cell structures such as described in M. W. Wanlass et al., Lattice Mismatched Approaches for High Performance, III-V Photovoltaic Energy Converters (Conference Proceedings of the 31^stIEEE Photovoltaic Specialists Conference, Jan. 3-7, 2005, IEEE Press, 2005) present an important conceptual starting point for the development of future commercial high efficiency solar cells. The structures described in such reference present a number of practical difficulties relating to the appropriate choice of materials and fabrication steps, for a number of different layers of the cell.
Prior to the present invention, the materials and fabrication steps disclosed in the prior art have not been adequate to produce a commercially viable and energy efficient solar cell using commercially established fabrication processes for producing an inverted metamorphic multifunction cell structure.

SUMMARY OF THE INVENTION

Briefly, and in general terms, the present invention provides a method of forming a multifunction solar cell comprising an upper subcell, a middle subcell, and a lower subcell, the method comprising; providing a first substrate for the epitaxial growth of semiconductor material; forming an upper first solar subcell on said first substrate having a first band gap; forming a middle second solar subcell over said first solar subcell having a second band gap smaller than said first band gap; forming a graded interlayer over said second solar cell; forming a lower third solar subcell over said graded interlayer having a fourth band gap smaller than said second band gap such that said third subcell is lattice mismatched with respect to said second subcell; and forming a contact having a contact resistance of less than 2×10⁻⁴ohms-cm²over said first subcell at a temperature of 210° or less.
In another aspect, the present invention provides a method of manufacturing a solar cell including; providing a first semiconductor substrate for the epitaxial growth of semiconductor material; forming a first subcell on said substrate comprising a first semiconductor material with a first band gap and a first lattice constant; forming a second subcell comprising a second semiconductor material with a second band gap and a second lattice constant, wherein the second band gap is less than the first band gap and the second lattice constant is greater than the first lattice constant; and forming a lattice constant transition material positioned between the first subcell and the second subcell, said lattice constant transition material having a lattice constant that changes gradually from the first lattice constant to the second lattice constant; and forming a contact at a temperature of 280° C. or less, and having a contact resistance of less than 5×10⁻⁴ohms-cm².
In still another aspect, the present invention provides a method of manufacturing a solar cell including; providing a first semiconductor substrate; depositing on a first substrate a sequence of layers of semiconductor material forming a solar cell forming a contact having a resistance of less than 5×10⁻⁴ohms-cm²; mounting a surrogate second substrate on top of the sequence of layers; and removing the first substrate.
In still another aspect, the present invention provides, more generally, a method of forming a semiconductor device including providing a substrate for the epitaxial growth of semiconductor material; forming first active layer on said substrate; forming a second active layer over said first active layer; and forming an electrical contact having a contact resistance of less than 2×10⁻⁴ohms-cm²over at least one of said active layers at a temperature of 210° C. or less.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be better and more fully appreciated by reference to the following detailed description when considered in conjunction with the accompanying drawings, wherein:

FIG. 1 is a graph representing the bandgap of certain binary materials and their lattice constants;

FIG. 2 is a cross-sectional view of the solar cell of the invention after the deposition of semiconductor layers on the growth substrate;

FIG. 3 is a cross-sectional view of the solar cell of FIG. 2 after the next process step;

FIG. 4 is a cross-sectional view of the solar cell of FIG. 3 after next process step;

FIG. 5A is a cross-sectional view of the solar cell of FIG. 4 after the next process step in which a surrogate substrate is attached;

FIG. 5B is a cross-sectional view of the solar cell of FIG. 5A after the next process step in which the original substrate is removed;

FIG. 5C is another cross-sectional view of the solar cell of FIG. 5B with the surrogate substrate on the bottom of the Figure;

FIG. 6 is a simplified cross-sectional view of the solar cell of FIG. 5C after the next process step;

FIG. 7 is a cross-sectional view of the solar cell of FIG. 6 after the next process step;

FIG. 8 is a cross-sectional view of the solar cell of FIG. 7 after the next process step;

FIG. 9 is a cross-sectional view of the solar cell of FIG. 8 after the next process step;

FIG. 10A is a top plan view of a wafer in which the solar cells are fabricated;

FIG. 10B is a bottom plan view of a wafer in which the solar cells are fabricated;

FIG. 11 is a cross-sectional view of the solar cell of FIG. 9 after the next process step;

FIG. 12 is a cross-sectional view of the solar cell of FIG. 11 after the next process step;

FIG. 13 is a top plan view of the wafer of FIG. 12 depicting the surface view of the trench etched around the cell;

FIG. 14A is a cross-sectional view of the solar cell of FIG. 12 after the next process step in a first embodiment of the present invention;

FIG. 14B is a cross-sectional view of the solar cell of FIG. 14A after the next process step in a second embodiment of the present invention;

FIG. 15 is a cross-sectional view of the solar cell of FIG. 14B after the next process step in a third embodiment of the present invention;

FIG. 16 is a graph of the doping profile in a base layer in the metamorphic solar cell according to the present invention; and

FIG. 17 is a graph that depicts the specific contact resistance of contact structures according to the present invention using the transmission line method.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Details of the present invention will now be described including exemplary aspects and embodiments thereof. Referring to the drawings and the following description, like reference numbers are used to identify like or functionally similar elements, and are intended to illustrate major features of exemplary embodiments in a highly simplified diagrammatic manner. Moreover, the drawings are not intended to depict every feature of the actual embodiment nor the relative dimensions of the depicted elements, and are not drawn to scale.
The basic concept of fabricating an inverted metamorphic multijunction (IMM) solar cell is to grow the subcells of the solar cell on a substrate in a “reverse” sequence. That is, the high band gap subcells (i.e. subcells with band gaps in the range of 1.8 to 2.1 eV), which would normally be the “top” subcells facing the solar radiation, are grown epitaxially on a semiconductor growth substrate, such as for example GaAs or Ge, and such subcells are therefore lattice-matched to such substrate. One or more lower band gap middle subcells (i.e. with band gaps in the range of 1.2 to 1.8 eV) can then be grown on the high band gap subcells.
At least one lower subcell is formed over the middle subcell such that the at least one lower subcell is substantially lattice-mismatched with respect to the growth substrate and such that the at least one lower subcell has a third lower band gap (i.e. a band gap in the range of 0.7 to 1.2 eV). A surrogate substrate or support structure is provided over the “bottom” or substantially lattice-mismatched lower subcell, and the growth semiconductor substrate is subsequently removed. (The growth substrate may then subsequently be re-used for the growth of a second and subsequent solar cells).
The present invention is directed to the composition of the metal contact used for the grid lines and bus bar on the top (sunward facing) side of the solar cell. As noted above, one aspect of fabrication of an IMM solar cell is the requirement for attachment to a surrogate substrate of support (also called a “handler”) during fabrication. Such attachment is typically done by a temporary adhesive.
The commercially available temporary adhesives have a relatively low melting point of around 100° C., and maintain adhesion to somewhat greater than 200° C. These relatively low operating temperatures place critical restrictions on the alloy temperature needed for forming an ohmic metal contact to the semiconductor layers of the cell, especially to an n-type GaAs layer with a Au—Ge eutectic based alloy with eutectic temperature of 361° C. Normal alloying temperature is typically greater than 360° C. The current commercial production triple junction solar cells use a 365° C. temperature to alloy simultaneously a Ti/Au/Ag to both the n and p-contact. From an electric standpoint, these contacts are rather poor, with specific contact resistivity of greater than 1×10⁻³Ω-cm².
FIG. 1 is a graph representing the band gap of certain binary materials and their lattice constants. The band gap and lattice constants of ternary materials are located on the lines drawn between typical associated binary materials (such as the ternary material GaAlAs being located between the GaAs and AlAs points on the graph, with the band gap of the ternary material lying between 1.42 eV for GaAs and 2.16 eV for AlAs depending upon the relative amount of the individual constituents). Thus, depending upon the desired band gap, the material constituents of ternary materials can be appropriately selected for growth.
The lattice constants and electrical properties of the layers in the semiconductor structure are preferably controlled by specification of appropriate reactor growth temperatures and times, and by use of appropriate chemical composition and dopants. The use of a vapor deposition method, such as Organo Metallic Vapor Phase Epitaxy (OMVPE), Metal Organic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE), or other vapor deposition methods for the reverse growth may enable the layers in the monolithic semiconductor structure forming the cell to be grown with the required thickness, elemental composition, dopant concentration and grading and conductivity type.
FIG. 2 depicts the multijunction solar cell according to the present invention after the sequential formation of the three subcells A, B and C on a GaAs growth substrate. More particularly, there is shown a substrate 101, which is preferably gallium arsenide (GaAs), but may also be germanium (Ge) or other suitable material. For GaAs, the substrate is preferably a 15° off-cut substrate, that is to say, its surface is orientated 15° off the (100) plane towards the (111)A plane, as more fully described in U.S. patent application Ser. No. 12/047,944, filed Mar. 13, 2008.
In the case of a Ge substrate, a nucleation layer (not shown) is deposited directly on the substrate 101. On the substrate, or over the nucleation layer (in the case of a Ge substrate), a buffer layer 102 and an etch stop layer 103 are further deposited. In the case of GaAs substrate, the buffer layer 102 is preferably GaAs. In the case of Ge substrate, the buffer layer 102 is preferably InGaAs. A contact layer 104 of GaAs is then deposited on layer 103, and a window layer 105 of AlInP is deposited on the contact layer. The subcell A, consisting of an n+emitter layer 106 and a p-type base layer 107, is then epitaxially deposited on the window layer 105. The subcell A is generally latticed matched to the growth substrate 101.
It should be noted that the multijunction solar cell structure could be formed by any suitable combination of group III to V elements listed in the periodic table subject to lattice constant and bandgap requirements, wherein the group III includes boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (T). The group IV includes carbon (C), silicon (Si), germanium (Ge), and tin (Sn). The group V includes nitrogen (N), phosphorous (P), arsenic (As), antimony (Sb), and bismuth (Bi).
In the preferred embodiment, the emitter layer 106 is composed of InGa(Al)P and the base layer 107 is composed of InGa(Al)P. The aluminum or Al term in parenthesis in the preceding formula means that Al is an optional constituent, and in this instance may be used in an amount ranging from 0% to 30%. The doping profile of the emitter and base layers 106 and 107 according to the present invention will be discussed in conjunction with FIG. 16.
Subcell A will ultimately become the “top” subcell of the inverted metamorphic structure after completion of the process steps according to the present invention to be described hereinafter.
On top of the base layer 107 a back surface field (“BSF”) layer 108 is deposited and used to reduce recombination loss, preferably p+ AlGaInP.
The BSF layer 108 drives minority carriers from the region near the base/BSF interface surface to minimize the effect of recombination loss. In other words, a BSF layer 18 reduces recombination loss at the backside of the solar subcell A and thereby reduces the recombination in the base.
On top of the BSF layer 108 is deposited a sequence of heavily doped p-type and n-type layers 109 which forms a tunnel diode which is an ohmic circuit element to connect subcell A to subcell B. These layers are preferably composed of p++AlGaAs, and n++InGaP.
On top of the tunnel diode layers 109 a window layer 110 is deposited, preferably n+InAlP. The window layer 110 used in the subcell B operates to reduce the interface recombination loss. It should be apparent to one skilled in the art, that additional layer(s) may be added or deleted in the cell structure without departing from the scope of the present invention.
On top of the window layer 110 the layers of subcell B are deposited: the n-type emitter layer 111 and the p-type base layer 112. These layers are preferably composed of InGaP and In_0.015GaAs respectively (for a Ge substrate or growth template), or InGaP and GaAs respectively (for a GaAs substrate), although any other suitable materials consistent with lattice constant and bandgap requirements may be used as well. Thus, subcell B may be composed of a GaAs, GaInP, GaInAs, GaAsSb, or GaInAsN emitter region and a GaAs, GaInAs, GaAsSb, or GaInAsN base region. The doping profile of layers 111 and 112 according to the present invention will be discussed in conjunction with FIG. 16.
In the preferred embodiment of the present invention, the middle subcell emitter has a band gap equal to the top subcell emitter, and the bottom subcell emitter has a band gap greater than the band gap of the base of the middle subcell. Therefore, after fabrication of the solar cell, and implementation and operation, neither the middle subcell B nor the bottom subcell C emitters will be exposed to absorbable radiation. Substantially radiation will be absorbed in the bases of cells B and C, which have narrower band gaps than the emitters. Therefore, the advantages of using heterojunction subcells are: 1) the short wavelength response for both subcells will improve, and 2) the bulk of the radiation is more effectively absorbed and collected in the narrower band gap base. The effect will be to increase J_sc.
On top of the cell B is deposited a BSF layer 113 which performs the same function as the BSF layer 109. A p++/n++ tunnel diode 114 is deposited over the BSF layer 113 similar to the layers 109, again forming an ohmic circuit element to connect subcell B to subcell C. These layers 114 are preferably compound of p++ AlGaAs and n++ InGaP.
A barrier layer 115, preferably composed of n-type InGa(Al)P, is deposited over the tunnel diode 114, to a thickness of about 1.0 micron. Such barrier layer is intended to prevent threading dislocations from propagating, either opposite to the direction of growth into the middle and top subcells B and C, or in the direction of growth into the bottom subcell A, and is more particularly described in copending U.S. patent application Ser. No. 11/860,183, filed Sep. 24, 2007.
A metamorphic layer (or graded interlayer) 116 is deposited over the barrier layer 115 using a surfactant. Layer 116 is preferably a compositionally step-graded series of InGaAlAs layers, preferably with monotonically changing lattice constant, so as to achieve a gradual transition in lattice constant in the semiconductor structure from subcell B to subcell C while minimizing threading dislocations from occurring. The bandgap of layer 116 is constant throughout its thickness preferably approximately 1.5 eV or otherwise consistent with a value slightly greater than the bandgap of the middle subcell B. The preferred embodiment of the graded interlayer may also be expressed as being composed of (In_xGa_1-x)_yAl_1-yAs, with x and y selected such that the band gap of the interlayer remains constant at approximately 1.50 eV.
In the surfactant assisted growth of the metamorphic layer 116, a suitable chemical element is introduced into the reactor during the growth of layer 116 to improve the surface characteristics of the layer. In the preferred embodiment, such element may be a dopant or donor atom such as selenium (Se) or tellurium (Te). Small amounts of Se or Te are therefore incorporated in the metamorphic layer 116, and remain in the finished solar cell. Although Se or Te are the preferred n-type dopant atoms, other non-isoelectronic surfactants may be used as well.
Surfactant assisted growth results in a much smoother or planarized surface. Since the surface topography affects the bulk properties of the semiconductor material as it grows and the layer becomes thicker, the use of the surfactants minimizes threading dislocations in the active regions, and therefore improves overall solar cell efficiency.
As an alternative to the use of non-isoelectronic surfactants one may use an isoelectronic surfactant. The term “isoelectronic” refers to surfactants such as antimony (Sb) or Bismuch (Bi), since such elements have the same number of valence electrons as the P of InGaP, or as in InGaAlAs, in the metamorphic buffer layer. Such Sb or Bi surfactants will not typically be incorporated into the metamorphic layer 116.
In an alternative embodiment where the solar cell has only two subcells, and the “middle” cell B is the uppermost or top subcell in the final solar cell, wherein the “top” subcell B would typically have a bandgap of 1.8 to 1.9 eV, then the band gap of the interlayer would remain constant at 1.9 eV.
In the inverted metamorphic structure described in the Wanlass et al. paper cited above, the metamorphic layer consists of nine compositionally graded InGaP steps, with each step layer having a thickness of 0.25 micron. As a result, each layer of Wanlass et al. has a different bandgap. In the preferred embodiment of the present invention, the layer 116 is composed of a plurality of layers of InGaAlAs, with monotonically changing lattice constant, each layer having the same bandgap, approximately 1.5 eV.
The advantage of utilizing a constant bandgap material such as InGaAlAs is that arsenide-based semiconductor material is much easier to process in standard commercial MOCVD reactors, while the small amount of aluminum assures radiation transparency of the metamorphic layers.
Although the preferred embodiment of the present invention utilizes a plurality of layers of InGaAlAs for the metamorphic layer 116 for reasons of manufacturability and radiation transparency, other embodiments of the present invention may utilize different material systems to achieve a change in lattice constant from subcell B to subcell C. Thus, the system of Wanlass using compositionally graded InGaP is a second embodiment of the present invention. Other embodiments of the present invention may utilize continuously graded, as opposed to step graded, materials. More generally, the graded interlayer may be composed of any of the As, P, N, Sb based III-V compound semiconductors subject to the constraints of having the in-plane lattice parameter greater or equal to that of the second solar cell and less than or equal to that of the third solar cell, and having a bandgap energy greater than that of the second solar cell.
In another embodiment of the present invention, an optional second barrier layer 117 may be deposited over the InGaAlAs metamorphic layer 116. The second barrier layer 117 will typically have a different composition than that of barrier layer 115, and performs essentially the same function of preventing threading dislocations from propagating. In the preferred embodiment, barrier layer 117 is n+ type GaInP.
A window layer 118 preferably composed of n+ type GaInP is then deposited over the barrier layer 117 (or directly over layer 116, in the absence of a second barrier layer). This window layer operates to reduce the recombination loss in subcell “C”. It should be apparent to one skilled in the art that additional layers may be added or deleted in the cell structure without departing from the scope of the present invention.
On top of the window layer 118, the layers of cell C are deposited: the n+emitter layer 119, and the p-type base layer 120. These layers are preferably composed of n type InGaAs and p type InGaAs respectively, or n type InGaP and p type InGaAs for a heterojunction subcell, although other suitable materials consistent with lattice constant and bandgap requirements may be used as well. The doping profile of layers 119 and 120 will be discussed in connection with FIG. 16.
A BSF layer 121, preferably composed of InGaAlAs, is then deposited on top of the cell C, the BSF layer performing the same function as the BSF layers 108 and 113.
Finally a high band gap contact layer 122, preferably composed of InGaAlAs, is deposited on the BSF layer 121.
This contact layer added to the bottom (non-illuminated) side of a lower band gap photovoltaic cell, in a single or a multifunction photovoltaic cell, can be formulated to reduce absorption of the light that passes through the cell, so that (1) an ohmic metal contact layer below (non-illuminated side) it will also act as a mirror layer, and (2) the contact layer doesn't have to be selectively etched off, to prevent absorption.
It should be apparent to one skilled in the art, that additional layer(s) may be added or deleted in the cell structure without departing from the scope of the present invention.
FIG. 3 is a cross-sectional view of the solar cell of FIG. 2 after the next process step in which a metal contact layer 123 is deposited over the p+semiconductor contact layer 122. The metal is preferably the sequence of metal layers Ti/Au/Ag/Au.
Also, the metal contact scheme chosen is one that has a planar interface with the semiconductor, after heat treatment to activate the ohmic contact. This is done so that (1) a dielectric layer separating the metal from the semiconductor doesn't have to be deposited and selectively etched in the metal contact areas; and (2) the contact layer is specularly reflective over the wavelength range of interest.
FIG. 4 is a cross-sectional view of the solar cell of FIG. 3 after the next process step in which an adhesive layer 124 is deposited over the metal layer 123. The adhesive is preferably Wafer Bond (manufactured by Brewer Science, Inc. of Rolla, Mo.).
FIG. 5A is a cross-sectional view of the solar cell of FIG. 4 after the next process step in which a surrogate substrate 125, preferably sapphire, is attached. Alternatively, the surrogate substrate may be GaAs, Ge or Si, or other suitable material. The surrogate substrate is about 40 mils in thickness, and is perforated with holes about 1 mm in diameter, spaced 4 mm apart, to aid in subsequent removal of the adhesive and the substrate. As an alternative to using an adhesive layer 124, a suitable substrate (e.g., GaAs) may be eutectically bonded to the metal layer 123.
FIG. 5B is a cross-sectional view of the solar cell of FIG. 5A after the next process step in which the original substrate is removed by a sequence of lapping and/or etching steps in which the substrate 101, and the buffer layer 103 are removed. The choice of a particular etchant is growth substrate dependent.
FIG. 5C is a cross-sectional view of the solar cell of FIG. 5B with the orientation with the surrogate substrate 125 being at the bottom of the Figure. Subsequent Figures in this application will assume such orientation.
FIG. 6 is a simplified cross-sectional view of the solar cell of FIG. 5B depicting just a few of the top layers and lower layers over the surrogate substrate 125.
FIG. 7 is a cross-sectional view of the solar cell of FIG. 6 after the next process step in which the etch stop layer 103 is removed by a HCl/H₂O solution.
FIG. 8 is a cross-sectional view of the solar cell of FIG. 7 after the next sequence of process steps in which a photoresist mask (not shown) is placed over the contact layer 104 to form the grid lines 501. As will be described in greater detail below, the grid lines 501 are deposited via evaporation and lithographically patterned and deposited over the contact layer 104. The mask is subsequently lifted off to form the finished metal grid lines 501 as depicted in the Figures.
As noted above, the present invention is directed to the composition of the metal contact. One composition considered was the sequence of layers Au/Ge/Pd/Au, and another was Pd/Ge/Ti/Pd/Au.
Initial investigation of both compositions was done at 280° C. The Au/Ge based contact required a 60 minute anneal (45 minute anneal resulted in a rectifying contact) to give a specific contact resistance of 3×10⁻⁶Ω-cm².
The Pd/Ge based contact sintered for 5 min at 280° C. yielded an acceptable specific contact resistance of nominally 1×10⁻⁴Ω-cm². The more reasonable sintering time for the required specific contact resistance (>1×10⁻³Ω-cm²) led to the identification of the Pd/Ge based metallization as optimum for the fabrication process of the solar cell described herein. Moreover, the adhesive thermal property permitted lowering the sinter temperature to 205° C. At this low sinter temperature, a time of 35 minutes was required to achieve a specific contact resistance of 1×10⁻⁴Ω-cm².
A more detailed description of the preferred embodiment is as follows. Prior to the metal deposition of the n-contact, residual oxide is removed from the wafer by soaking the wafer in a solution of 15H₂0) 1NH₄OH for one minute, and spin dried in N₂. The wafer is then loaded in the deposition chamber within 30 minutes to preclude excessive oxide growth. The metallization in the preferred embodiment, the sequence of layers of 50 nm Pd/100 nm Ge/30 nm Ti/30 nm Pd/5 μm Ag/100 nm Au, is e-beam evaporated during one vacuum cycle. The background chamber pressure at the beginning of deposition is 5×10⁻⁷torr. Following deposition, the grid lines 501 and bus bar are defined by liftoff. The contact sintering is then performed in the lab oratory ambient atmosphere on a hot plate. The wafer is placed grid side down on a clean silicon wafer on a hot plate, set at a temperature of 120° C. The wafer and silicon carrier are allowed to equilibrate for 5 min. The hot plate is then set at the sintering temperature (e.g. a set point of 215). Ten minutes are allowed for the wafer to attain the sintering temperature. The metal contact then sinters for 40 min. The hot plate temperature is then dropped in ten minutes to 120° C. The Si carrier and wafer are removed from the hot plate. Transmission line method (TLM) patterns formed on the solar cell wafer permit specific contact resistance measurements, as will be subsequently described in connection with FIG. 17.
A variety of different Pd/Ge based contacts are suitable for application in the present invention, including, but not limited to Pd/Ge/Au, Pd/Ge/Ag, Pd/Ge/Pt/Au, Pd/Ge/Pt/Ag, dried Pd/Ge/Pt/Ag/Au. Those skilled in the art would be able to select the most suitable combination for the semiconductor layers and fabrication processes being utilized.
Two embodiments of the contact composition according to the present invention, viz. Au/Ge/Pd/Au or Pd/Ge/Ti/Pd/Au, are illustrated in FIG. 8. The preferred embodiment is Pd/Ge/Ti/Pd/Au, while other Pd/Ge based layer sequences provide substantially similar results and are within the scope of the present invention.
FIG. 9 is a cross-sectional view of the solar cell of FIG. 8 after the next process step in which the grid lines are used as a mask to etch down the surface to the window layer 105 using a citric acid/peroxide etching mixture.
FIG. 10A is a top plan view of a wafer in which four solar cells are implemented. The depiction of four cells is for illustration purposes only, and the present invention is not limited to any specific number of cells per wafer.
In each cell there are grid lines 501 (more particularly shown in cross-section in FIG. 9), an interconnecting bus line 502, and a contact pad 503. The geometry and number of grid and bus lines is illustrative and the present invention is not limited to the illustrated embodiment.
FIG. 10B is a bottom plan view of the wafer with four solar cells shown in FIG. 10A.
FIG. 11 is a cross-sectional view of the solar cell of FIG. 11 after the next process step in which an antireflective (ARC) dielectric coating layer 130 is applied over the entire surface of the “bottom” side of the wafer with the grid lines 501.
FIG. 12 is a cross-sectional view of the solar cell of FIG. 1I after the next process step according to the present invention in which a channel 510 or portion of the semiconductor structure is etched down to the metal layer 123 using phosphide and arsenide etchants defining a peripheral boundary and leaving a mesa structure which constitutes the solar cell. The cross-section depicted in FIG. 12 is that as seen from the A-A plane shown in FIG. 13.
FIG. 13 is a top plan view of the wafer of FIG. 12 depicting the channel 510 etched around the periphery of each cell using phosphide and arsenide etchants.
FIG. 14A is a cross-sectional view of the solar cell of FIG. 12 after the next process step in a first embodiment of the present invention in which the surrogate substrate 125 is appropriately thinned to a relatively thin layer 125 a, by grinding, lapping, or etching.
FIG. 14B is a cross-sectional view of the solar cell of FIG. 14A after the next process step in a second embodiment of the present invention in which a cover glass is secured to the top of the cell by an adhesive.
FIG. 15 is a cross-sectional view of the solar cell of FIG. 14B after the next process step in a third embodiment of the present invention in which a cover glass is secured to the top of the cell and the surrogate substrate 125 is entirely removed, leaving only the metal contact layer 123 which forms the backside contact of the solar cell. The surrogate substrate may be reused in subsequent wafer processing operations.
FIG. 16 is a graph of a doping profile in the emitter and base layers in one or more subcells of the inverted metamorphic multijunction solar cell of the present invention. The various doping profiles within the scope of the present invention, and the advantages of such doping profiles are more particularly described in copending U.S. patent application Ser. No. 11/956,069 filed Dec. 13, 2007, herein incorporated by reference. The doping profiles depicted herein are merely illustrative, and other more complex profiles may be utilized as would be apparent to those skilled in the art without departing from the scope of the present invention.
FIG. 17 is a graph depicting the results of a TLM pattern measurement on wafers with contacts 501 formed with Pd/Ge/Ti/Pd/Au according to the present invention, with the resistance between electrodes (measured in ohms) shown as a function of the electrode separation, depicted along the x-axis.
It will be understood that each of the elements described above, or two or more together, also may find a useful application in other types of constructions differing from the types of constructions described above.
Although the preferred embodiment of the present invention utilizes a vertical stack of three subcells, the present invention can apply to stacks with fewer or greater number of subcells, i.e. two junction cells, four junction cells, five junction cells, etc. In the case of four or more junction cells, the use of more than one metamorphic grading interlayer may also be utilized.
In addition, although the present embodiment is configured with top and bottom electrical contacts, the subcells may alternatively be contacted by means of metal contacts to laterally conductive semiconductor layers between the subcells. Such arrangements may be used to form 3-terminal, 4-terminal, and in general, n-terminal devices. The subcells can be interconnected in circuits using these additional terminals such that most of the available photogenerated current density in each subcell can be used effectively, leading to high efficiency for the multijunction cell, notwithstanding that the photogenerated current densities are typically different in the various subcells.
As noted above, the present invention may utilize an arrangement of one or more, or all, homojunction cells or subcells, i.e., a cell or subcell in which the p-n junction is formed between a p-type semiconductor and an n-type semiconductor both of which have the same chemical composition and the same band gap, differing only in the dopant species and types, and one or more heterojunction cells or subcells. Subcell A, with p-type and n-type InGaP is one example of a homojunction subcell. Alternatively, as more particularly described in U.S. patent application Ser. No. 12/023,772 filed Jan. 31, 2008, the present invention may utilize one or more, or all, heterojunction cells or subcells, i.e., a cell or subcell in which the p-n junction is formed between a p-type semiconductor and an n-type semiconductor having different chemical compositions of the semiconductor material in the n-type regions, and/or different band gap energies in the p-type regions, in addition to utilizing different dopant species and type in the p-type and n-type regions that form the p-n junction.
The composition of the window or BSF layers may utilize other semiconductor compounds, subject to lattice constant and band gap requirements, and may include AlInP, AlAs, AlP, AlGaInP, AlGaAsP, AlGaInAs, AlGaInPAs, GaInP, GaInAs, GaInPAs, AlGaAs, AlInAs, AlInPAs, GaAsSb, AlAsSb, GaAlAsSb, AlInSb, GaInSb, AlGaInSb, AIN, GaN, InN, GaInN, AlGaInN, GaInNAs, AlGaInNAs, ZnSSe, CdSSe, and similar materials, and still fall within the spirit of the present invention.
While the invention has been illustrated and described as embodied in an inverted metamorphic multifunction solar cell, it is not intended to be limited to the details shown, since various modifications and structural changes may be made without departing in any way from the spirit of the present invention.
Thus, while the description of this invention has focused primarily on solar cells or photovoltaic devices, persons skilled in the art know that other electronic and optoelectronic devices, such as, transistors, thermophotovoltaic (TPV) cells, photodetectors and light-emitting diodes (LEDS) are very similar in structure, physics, and materials to photovoltaic devices with some minor variations in doping and the minority carrier lifetime. For example, photodetectors can be the same materials and structures as the photovoltaic devices described above, but perhaps more lightly-doped for sensitivity rather than power production. On the other hand LEDs can also be made with similar structures and materials, but perhaps more heavily-doped to shorten recombination time, thus radiative lifetime to produce light instead of power. Therefore, this invention also applies to photodetectors and LEDs with structures, compositions of matter, articles of manufacture, and improvements as described above for photovoltaic cells.
Without further analysis, the foregoing will so fully reveal the gist of the present invention that others can, by applying current knowledge, readily adapt it for various applications without omitting features that, from the standpoint of prior art, fairly constitute essential characteristics of the generic or specific aspects of this invention and, therefore, such adaptations should and are intended to be comprehended within the meaning and range of equivalence of the following claims.

Claims

1. A method of forming a multifunction solar cell comprising an upper subcell, a middle subcell, and a lower subcell, the method comprising:

providing a first substrate for the epitaxial growth of semiconductor material;

forming an upper first solar subcell on said first substrate having a first band gap;

forming a middle second solar subcell over said first solar subcell having a second band gap smaller than said first band gap;

forming a graded interlayer over said second solar cell;

forming a lower third solar subcell over said graded interlayer having a fourth band gap smaller than said second band gap such that said third subcell is lattice mismatched with respect to said second subcell; and

forming a contact having a contact resistance of less than 2×10⁻⁴ohms-cm²over said first subcell at a temperature of 210° C. or less.

2. The method as defined in claim 1, wherein the graded interlayer has a third band gap greater than said second band gap.

3. The method as defined in claim 1, wherein the contact includes germanium and palladium.

4. The method as defined in claim 1, wherein the contact is sintered at 205° C.

5. The method as defined in claim 4, wherein the sintering time is approximately 35 minutes or less.

6. The method as defined in claim 1, wherein the contact is a sequence of layers including Pd/Ge/Ti/Pd.

7. The method as defined claim 6, wherein the contact is sintered for approximately 5 minutes at 280° C.

8. The method as defined in claim 7, wherein the contact resistance is less than 5×10⁻⁶ohms-cm².

9. The method as defined in claim 1, wherein the contact is composed of a Pd/Ge/Ti/Pd/Ag/Au sequence of layers.

10. A method as defined in claim 9, wherein the contact layers are deposited by e-beam evaporation.

11. A method as defined in claim 4, wherein the sintering is performed in ambient atmosphere on a hot plate.

12. The method as defined in claim 1, wherein the upper subcell is composed of InGa(Al)P.

13. The method as defined in claim 1, wherein the middle subcell is composed of an GaAs, GaInP, GaInAs, GaAsSb, or GaInAsN emitter region and a GaAs, GaInAs, GaAsSb, or GaInAsN base region.

14. The method as defined in claim 1, wherein the lower solar subcell is composed of an InGaAs base and emitter layer, or a InGaAs base layer and a InGaP emitter layer.

15. The method as defined in claim 1, wherein the graded interlayer is compositionally graded to lattice match the middle subcell on one side and the lower subcell on the other side.

16. The method as defined in claim 1, wherein the graded interlayer is composed of InGaAlAs.

17. The method as defined in claim 1, wherein the graded interlayer has approximately a 1.5 eV band gap throughout its thickness.

18. The method as defined in claim 1, wherein the graded interlayer is composed of any of the As, P, N, Sb based III-V compound semiconductors subject to the constraints of having the in-plane lattice parameter greater or equal to that of the second solar cell and less than or equal to that of the second solar cell and less than or equal to that of the third solar cell, and having a band gap energy greater than that of the second solar cell.

19. The method as defined in claim 1, wherein said graded interlayer is composed of nine or more steps of layers of semiconductor material with monotonically changing lattice constant and constant band gap.

20. The method as defined in claim 1, further comprising attaching a surrogate second substrate over said contact and removing said first substrate.

21. The method as defined in claim 20, further comprising:

patterning said contact layer into a grid; and

etching a trough around the periphery of said solar cell so as to form a mesa structure on said surrogate second substrate.

22. A method as defined in claim 20, further comprising thinning the surrogate substrate and mounting the solar cell on a support.

23. A method as defined in claim 20, further comprising removing the surrogate substrate and mounting the solar cell on a support.

24. A method as defined in claim 20, wherein the support is a rigid coverglass.

25. A method of manufacturing a solar cell comprising:

providing a first semiconductor substrate for the epitaxial growth of semiconductor material;

forming a first subcell on said substrate comprising a first semiconductor material with a first band gap and a first lattice constant;

forming a second subcell comprising a second semiconductor material with a second band gap and a second lattice constant, wherein the second band gap is less than the first band gap and the second lattice constant is greater than the first lattice constant; and

forming a lattice constant transition material positioned between the first subcell and the second subcell, said lattice constant transition material having a lattice constant that changes gradually from the first lattice constant to the second lattice constant; and

forming a contact to said solar cell at a temperature of 280° C. or less, and having a contact resistance of less than 5×10⁻⁴ohms-cm².

26. The method as defined in claim 25, wherein the contact includes germanium and palladium.

27. The method as defined in claim 25, wherein the contact is sintered at 205° C.

28. The method as defined in claim 27, wherein the sintering time is approximately 35 minutes or less.

29. The method as defined in claim 25, wherein the contact includes a Pd/Ge/Ti/Pd sequence of layers.

30. The method as defined in claim 29, wherein the contact is Pd/Ge/Ti/Pd/Au or Pd/Ge/Ti/Pd/Ag/Au.

31. The method as defined in claim 30, wherein the contact resistance is less than 5×10⁻⁶ohms-cm².

32. The method as defined in claim 25 wherein the contact layer is composed of GaAs.

33. A method as defined in claim 30, wherein said contact resistance is approximately 1×10⁻⁴ohms-cm².

34. A method as defined in claim 25, wherein said first subcell is composed of an GaInP, GaSa, GaInAs, GaAsSb, or GaInAsN emitter region and an GaAs, GaInAs, GaAsSb, or GaInAsN base region.

35. A method as defined in claim 25, wherein the second subcell is composed of an InGaAs base and emitter regions.

36. A method as defined in claim 25, wherein said transition material is composed of any of the As, P, N, Sb based III-V compound semiconductors subject to the constraints of having the in-plane lattice parameter greater or equal to that of the first subcell and less than or equal to that of the second subcell, and having a band gap energy greater than that of the first subcell.

37. A method as defined in claim 25, wherein the transition material is composed of (In_xGa_1-x)_yAl_1-yAs, with x and y selected such that the band gap of the transition material remains constant at a band gap energy greater than that of said first subcell.

38. A method as defined in claim 25, wherein the band gap of the transition material remains constant at approximately 1.50 eV.

39. A method of manufacturing a solar cell comprising:

providing a first semiconductor substrate;

depositing on a first substrate a sequence of layers of semiconductor material forming a solar cell;

forming a contact on said solar cell having a resistance of less than 5×10⁻⁴ohms-cm²;

mounting a surrogate second substrate on top of the sequence of layers; and

removing the first substrate.

40. The method as defined in claim 39, wherein the contact includes germanium and palladium.

41. The method as defined in claim 39, wherein the contact is sintered at 205° C.

42. The method as defined in claim 41, wherein the sintering time is approximately 35 minutes or less.

43. The method as defined in claim 39, wherein the contact is a Pd/Ge/Ti/Pd/Au sequence of layers.

44. The method as defined in claim 43, wherein the contact is sintered for approximately 35 minutes.

45. The method as defined in claim 44, wherein the contact resistance is approximately 1×10⁻⁴ohms-cm².

46. The method as defined in claim 39, wherein the sequence of layers of semiconductor material forms a triple junction solar cell, including top, middle and bottom solar subcells.

47. The method as defined in claim 39, wherein the mounting step includes adhering the solar cell to the surrogate substrate.

48. The method as defined in claim 39, wherein the surrogate substrate is selected from the group of sapphire, Ge, GaAs, or silicon.

49. The method as defined in claim 39, wherein the solar cell is bonded to said surrogate substrate by an adhesive.

50. The method as defined in claim 39, wherein the solar cell is eutectically bonded to the surrogate substrate.

51. The method as defined in claim 39, further comprising thinning the surrogate substrate to a predetermined thickness.

52. The method as defined in claim 39, further mounting the solar cell on a rigid coverglass; and removing the surrogate substrate.

53. The method as defined in claim 52, wherein the support is a rigid coverglass.

54. A method as defined in claim 39, wherein said middle and bottom subcells are lattice mismatched.

55. A method as defined in claim 39, further comprising a graded interlayer disposed between said middle and bottom subcells, and has a band gap greater than the band gap of said middle subcell.

56. A method as defined in claim 55, wherein said graded interlayer is composed of any of the As, P, N, Sb based III-V compound semiconductors subject to the constraints of having the in-plane lattice parameter greater or equal to that of the middle subcell and less than or equal to that of the bottom subcell.

57. A method as defined in claim 56, wherein the graded interlayer is composed of (In_xGa_1-x)_yAl_1-yAs, with x and y selected such that the band gap of the interlayer remains constant at approximately 1.50 eV.

58. A multifunction solar cell comprising:

a first solar subcell having a first band gap;

a second solar subcell disposed over the first solar subcell having a second band gap smaller than the first band gap;

a graded interlayer disposed over the second-subcell having a third band gap greater than the second band gap;

a third solar subcell disposed over the graded interlayer having a fourth band gap smaller than the second band gap such that the third subcell is lattice mismatched with respect to the second subcell; and

a contact disposed over the first subcell having a contact resistance of less than 5×10⁻⁴ohms-cm².

59. A method of forming a semiconductor device comprising:

providing a substrate for the epitaxial growth of semiconductor material;

forming first active layer on said substrate;

forming a second active layer over said first active layer; and

forming an electrical contact having a contact resistance of less than 2×10⁻⁴ohms-cm²over said second active layer at a temperature of 210° C. or less.