US20100091927A1 - Clock and Data Recovery (CDR) Using Phase Interpolation - Google Patents
Clock and Data Recovery (CDR) Using Phase Interpolation Download PDFInfo
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- US20100091927A1 US20100091927A1 US12/511,365 US51136509A US2010091927A1 US 20100091927 A1 US20100091927 A1 US 20100091927A1 US 51136509 A US51136509 A US 51136509A US 2010091927 A1 US2010091927 A1 US 2010091927A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
- H03L7/0998—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator using phase interpolation
Definitions
- the present disclosure relates generally to signal communication.
- a phase-locked loop (PLL)-based CDR circuit is a conventional type of CDR circuit.
- a phase detector compares the phase between input data bits from a serial input data stream and a clock signal from a voltage-controlled oscillator (VCO). In response to the phase difference between the input data and the clock, the phase detector generates signals UP and DN.
- a charge pump drives a current to or from a loop filter according to the UP and DN signals.
- the loop filter generates a control voltage V CTRL for the VCO based on the UP and DN signals.
- the loop acts as a feedback control system that tracks the phase of input data stream with the phase of the clock that the loop generates.
- the dynamics of the loop are generally determined by the open loop gain and the location of open loop zeroes and poles (predominantly in the loop filter).
- DLL delay-locked loops
- PI phase interpolators
- phase detectors such as a phase and frequency detector (PFD) or an Alexander Detector
- PFD phase and frequency detector
- Alexander Detector an Alexander Detector
- these conventional phase detectors are designed to output zero for nominal zero input phase offset, and are typically asymmetric in that the output of such phase detectors has a built-in phase offset between its inputs. The phase offset output from the phase detector typically cannot be compensated.
- FIG. 1 illustrates an example CDR circuit.
- FIG. 2 illustrates another example CDR circuit.
- FIG. 3 illustrates an example half-rate CDR circuit.
- FIG. 4 illustrates another example CDR circuit.
- FIG. 5 illustrates an example quarter-rate CDR circuit.
- FIG. 6 illustrate an example phase interpolator block.
- FIG. 7 illustrates an example phase interpolator.
- FIG. 8A illustrates an example phase detector
- FIG. 8B illustrates another example phase detector.
- FIG. 9A illustrates a circuit schematic of an example Gilbert cell.
- FIG. 9B illustrates a symbol of an example Gilbert cell equivalent to that of FIG. 7A .
- FIG. 9C illustrates a phase characteristic of the example Gilbert cell of FIG. 7A .
- FIG. 10A illustrates an example circuit arrangement of Gilbert cells.
- FIG. 10B illustrates a phase characteristic of the example arrangement of FIG. 8A .
- FIG. 11 illustrates an example phase detector circuit.
- FIG. 12 illustrates an example phase detector circuit.
- Particular embodiments relate to a clock and data recovery (CDR) circuit.
- CDR clock and data recovery
- Particular embodiments relate to a CDR circuit that includes a phase interpolator integrated with a phase detector.
- Particular embodiments relate to the generation of an 8-phase clock signal from a 4-phase clock signal for use as a sampling clock signal in a 40 Gb/s quarter-rate CDR circuit.
- Particular embodiments relate to a 10 GHz phase interpolator for a 40 Gb/s CDR circuit.
- Particular embodiments relate to a phase detector that is symmetric with respect to the inputs to the phase detector.
- Particular embodiments relate to a high-speed phase detector for periodic input signals (e.g., clock signals).
- Particular embodiments relate to a phase detector having an output that is zero for a 90° or other non-zero phase offset between the inputs to the phase detector. Particular embodiments further relate to the use of parallel cross-coupled Gilbert cells for use in a phase detector.
- the signals described below are differential signals where appropriate.
- various signals described below are periodic signals, where appropriate.
- FIG. 1 illustrates an example CDR circuit that includes a phase detector (PD) 102 , a charge pump 104 , a loop filter 106 , and a voltage-controlled oscillator (VCO) 108 , each of which may include one or more sub-circuits or sub-blocks.
- PD 102 receives as input one or more input data streams D in as well as a multi-phase clock signal, VCO.Clk, from VCO 108 .
- an m-phase clock signal actually includes m clock signals, each having different relative phase and each transmitted over, for example, a corresponding wire to PD 102 .
- VCO PD 102 is used to sample the data in the one or more input data streams D in multiple times within each VCO.Clk clock cycle, whereas VCO 108 is used to generate the appropriate clock phases for the multi-phase signal VCO.Clk that control the timing of the sampling.
- the data is sampled twice per cycle: at the data transition point (edge sample) and at the middle of the cycle (center sample).
- the operating frequency of the CDR may be 1/n of the data rate of D in , which requires that PD 102 receive multiple clock phases.
- half-rate CDR architectures require four clock phases (e.g., 0°, 90° ( ⁇ /2), 180° ( ⁇ ), and 270° (3 ⁇ /2)) and quarter-rate CDR architectures require eight clock phases (e.g., 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°).
- other CDR architectures may require more than two samples per clock cycle.
- PI block 210 receives as inputs an m-phase clock signal, VCO.Clk, generated from VCO 108 as well as a control input, phAdj, and produces an m-phase clock signal PI.Clk that is then fed to PD 102 for use in sampling the input data stream D in .
- the input phAdj determines the sign and magnitude of the phase adjustment.
- FIG. 3 illustrates an example of a half-rate CDR circuit.
- the circuit of FIG. 3 is a special case of the circuit of FIG. 2 in which VCO 108 generates a 4-phase clock signal VCO.Clk.
- VCO.Clk includes clock signals ⁇ 0 , ⁇ 90 , ⁇ 180 , and ⁇ 270 , having phases of approximately 0°, 90°, 180°, and 270°, respectively (note that there is a 90° phase difference between the individual signals).
- PI block 210 receives the clock signals ⁇ 0 , ⁇ 90 , ⁇ 180 , and ⁇ 270 and outputs four phase-interpolated clock signals ⁇ 0 , ⁇ 90 , ⁇ 180 , and ⁇ 270 , which have phases of approximately 0°, 90°, 180°, and 270°, respectively.
- the four phase-interpolated clock signals may have phase differences with respect to each other that are not 90°.
- PI block 210 may skew phases (such as, for example, ⁇ 90 and ⁇ 270 with respect to ⁇ 0 and ⁇ 180 ) to support phase adjustment capability, as described above.
- VCO.Clk represents differential signals
- ⁇ 0 and ⁇ 180 may represent one differential pair
- ⁇ 90 and ⁇ 270 may represent one differential pair
- ⁇ 0 and ⁇ 180 may represent one differential pair
- ⁇ 90 and ⁇ 270 may represent one differential pair.
- VCO.Clk may actually include two differential signals in practice.
- High data rate CDRs are often implemented as quarter-rate architectures with inductor-capacitor (LC)-based VCOs.
- high data rates may refer to data rates equal or greater than 10 Gb/s, equal or greater than 20 Gb/s, or equal or greater than 40 Gb/s.
- Quarter-rate CDRs generally require eight or more clock phases, the generation and delivery of which present numerous difficulties using LC-based VCOs, partly due to the number of inductors required.
- LC-based VCOs can relatively easily produce two or four clock phases, but become difficult to deal with when more phases (e.g., 8, 12 or more) are required.
- the generation of the extra intermediate phases needed for, by way of example, quarter-rate CDRs is combined with the phase adjustment requirement using a single PI block 410 as illustrated in FIG. 4 .
- a low noise oscillator such as an LC-based VCO 102 as a k-phase clock generator to generate a k-phase clock signal (where k ⁇ 2) input to PI block 410 .
- PI block 410 receives the k-phase clock signal from VCO 108 and produces an m-phase clock signal for use by phase detector 402 , where m ⁇ k (unlike previous conventional CDR architectures that produce the same number of phases as are received).
- FIG. 5 illustrates an example embodiment of a quarter-rate CDR circuit.
- VCO 508 produces a 4-phase clock signal including clock signals ⁇ 0 , ⁇ 90 , ⁇ 180 , and ⁇ 270 , having phases of approximately 0°, 90°, 180°, and 270°, respectively.
- clock signals ⁇ 0 , ⁇ 90 , ⁇ 180 , and ⁇ 270 are input to PI block 510 , which, in the illustrated embodiment, outputs an 8-phase clock signal that includes clock signals ⁇ 0 , ⁇ 90 , ⁇ 180 , and ⁇ 270 , having phases of approximately 0°, 90°, 180°, and 270°, respectively, along with four additional intermediately-phased clock signals ⁇ 45 , ⁇ 135 , ⁇ 225 , and ⁇ 315 , having phases of approximately 45°, 135°, 225°, and 315°, respectively.
- PI block 510 may also be used to adjust the decision clocks based on the phAdj control input by introducing a static phase offset.
- VCO.Clk represents differential signals
- ⁇ 0 and ⁇ 180 may represent one differential pair
- ⁇ 90 and ⁇ 270 may represent one differential pair
- ⁇ 0 and ⁇ 180 may represent one differential pair
- ⁇ 90 and ⁇ 270 may represent one differential pair
- ⁇ 45 and ⁇ 225 may represent one differential pair
- ⁇ 135 and ⁇ 315 may represent one differential pair.
- VCO.Clk may actually include two differential signals in practice while PI.Clk may actually include four differential signals in practice.
- the output of PI 612 is the current summation of the differential pair, which is converted to voltage through a resistor.
- an approximate desired phase is achieved as a weighted sum of the two input signals.
- the ratio of the tail current will determine the phase and the sum of the tail currents will determine the amplitude of the output signal.
- the inputs to differential pairs 740 and 742 are the gates of the transistors in the differential pairs 740 and 742 and the outputs are the wires tapping the outputs of the transistors.
- input signal ⁇ 0 may go the gate of the illustrated left transistor in differential pair 740 ;
- input signal ⁇ 180 may go the gate of the illustrated right transistor in differential pair 740 ;
- input signal ⁇ 90 may go the gate of the illustrated left transistor in differential pair 742 ;
- input signal ⁇ 270 may go the gate of the illustrated right transistor in differential pair 742 .
- Output signal ⁇ 225 may come from the illustrated vertical wire at the illustrated bottom of differential pair 740
- output signal ⁇ 45 may come from the illustrated vertical wire at the illustrated bottom of differential pair 742 .
- PI 612 takes as input the 4-phase clock signal including clock signals ⁇ 0 , ⁇ 90 , ⁇ 180 , and ⁇ 270 , having phases of approximately 0°, 90°, 180°, and 270°, respectively, from VCO 508 .
- PI 612 uses these signals to generate an 8-phase clock signal that includes clock signals ⁇ 0 , ⁇ 90 , ⁇ 180 , and ⁇ 270 , having phases of approximately 0°, 90°, 180°, and 270°, respectively, along with four additional intermediately-phased clock signals ⁇ 45 , ⁇ 135 , ⁇ 225 , and ⁇ 315 , having phases of approximately 45°, 135°, 225°, and 315°, respectively.
- PD 614 provides feedback to PI 612 in the form of error (or control) signals that are used by PI 612 to adjust the 8-phase clock signal output.
- a first PI 612 may use the input signals ⁇ 0 and ⁇ 90 to generate the output signal ⁇ 45 , while other PIs 612 in parallel with the first PI 612 generate the other intermediately-phase clock signals, respectively.
- FIG. 8A illustrates an example phase detector 802 suitable for use as PD 614 and/or PDs 402 or 502 .
- PD 802 includes a first PD input that receives (during operation) a first input signal V in1 , a second PD input that receives (during operation) a second input signal V in2 , and a third PD input that receives (during operation) a third input signal V in3 .
- each of the described inputs, and those described below, may actually include two inputs: one for the described signal and one for the corresponding complement (since the signals are generally differential).
- input signal V in1 is a first clock signal output by PI 612
- V in2 is a second clock signal output by PI 612
- V in3 is a third clock signal output by PI 612
- the third clock signal V in3 may be referred to as the target phase signal.
- PD 802 includes a first mixer cell (or circuit/block) 820 and a second mixer cell (or circuit/block) 822 .
- first mixer cell 820 includes a first MC input, a second MC input, and a first MC output while second mixer cell 822 includes a third MC input, a fourth MC input, and a second MC output.
- the first PD input is connected to the first MC input
- the second PD input is connected to the third MC input
- the third PD input is connected to the second MC input and the fourth MC input.
- PD 802 further includes an adder 824 that receives the first and second MC output signals and adds the first and second MC output signals to produce a summed output signal.
- PD 802 additionally includes an integrator 826 that filters the summed output signal to produce an integrated (e.g., DC) output signal that represents the PD output signal V out output over the PD output.
- the PD output signal V out represents an error signal that is then input to PI 612 and used to adjust the phase of the input signal V in3 .
- first mixer cell 820 is a multiplying mixer cell and second mixer cell 822 is a multiplying mixer cell.
- first mixer cell 820 is a Gilbert cell and second mixer cell 822 is a Gilbert cell.
- a Gilbert cell is an electronic multiplying mixer.
- the output current of a Gilbert cell is an accurate multiplication of the (differential) base currents of both inputs.
- FIG. 9A illustrates a circuit schematic of an example Gilbert cell having inputs for receiving two differential signals in 1 (the complement of in 1 is denoted as in 1 ) and in 2 (the complement of in 2 is denoted as in 2 ).
- FIG. 9B illustrates an accepted equivalent symbol for a Gilbert cell
- FIG. 9C illustrates the value of the output differential signal I out ⁇ I out as a function of the phase offset ⁇ (in 1 ⁇ in 2 ) between the differential input signals in 1 and in 2 .
- first mixer cell 820 includes a first Gilbert cell 830 and a second Gilbert cell 832 cross-coupled in parallel, while second mixer cell 822 includes a third Gilbert cell 834 and a fourth Gilbert cell 836 cross-coupled in parallel, as illustrated in FIG. 8B .
- a first input of first Gilbert cell 830 receives input signal V in1 while a second input of first Gilbert cell 830 receives input signal V in2 .
- a first input of second Gilbert cell 832 receives input signal V in2 while a second input of second Gilbert cell 832 receives input signal V in1 .
- the outputs of first and second Gilbert cells 830 and 832 may be connected to provide the first MC output signal, as shown in the illustrate embodiment.
- a first input of third Gilbert cell 834 receives input signal V in3 while a second input of third Gilbert cell 834 receives input signal V in2 .
- a first input of fourth Gilbert cell 836 receives input signal V in2 while a second input of fourth Gilbert cell 836 receives input signal V in3 .
- the outputs of third and fourth Gilbert cells 834 and 836 may be connected to provide the second MC output signal, as shown in the illustrate embodiment.
- the first MC output signal output from first mixer cell 820 is symmetric with respect to the inputs V in1 and V in2 and the second MC output signal output from second mixer cell 822 is symmetric with respect to the inputs V in2 and V in3 .
- the delay between the first input of any Gilbert cell and the output of the Gilbert cell is generally different than the delay between the second input of the Gilbert cell and the output of the Gilbert cell. This results in a static phase offset in the output signal output from the Gilbert cell.
- the static phase offset is cancelled to at least a first approximation.
- FIG. 10A and 10B illustrates a circuit that includes two Gilbert cells cross-coupled in parallel (as in each mixer cell 820 and 822 ) as well as the circuit's phase characteristic, respectively.
- the circuit shown in FIG. 10A may itself be used as a phase detector.
- the inputs to the two Gilbert cells 1002 and 1004 are interchanged: input in 1 is connected to the input A of Gilbert cell 1002 and to input B of Gilbert cell 1004 ; input in 2 is connected to the input B of Gilbert cell 1002 and to input A of Gilbert cell 1004 .
- the interchanging of the inputs effectively interpolates the outputs of the Gilbert cells and results in zero input offset to a first degree of approximation. Such an arrangement minimizes the phase offset (the phase delay between the inputs for which the output of the arrangement is still equal to zero).
- the output, V out , of PD 802 represents an error signal that is proportional to the difference in phase between the phase of V in3 and the average of the phases of V in1 and V in2 .
- V in1 represents ⁇ 0
- V in2 represents ⁇ 90
- V in3 represents ⁇ 45 .
- V out represent an error signal that is proportional to the difference between the phase of ⁇ 45 , which is approximately 45° (as noted above, VCOs have difficulty generating intermediately-phased signals such as 45°, and as such the phase of ⁇ 45 is only roughly equal to 45°), and the average of the phases of ⁇ 0 and ⁇ 90 , which is approximately 45° since the phase of ⁇ 0 and ⁇ 90 are approximately 0° and 90°, respectively.
- the error signal, V out is then fed to PI 612 , which then adjusts the phase of ⁇ 45 to eliminate the phase difference (which would then result in a zero-valued error signal), which results in a ⁇ 45 having a phase truer to 45°.
- PD 614 provides a feedback loop to PI 612 to compensate for the inaccuracy of PI 612 .
- PD 614 also utilizes this circuit and process to adjust or verify the other intermediately-phased signals ⁇ 135 , ⁇ 225 , and ⁇ 315 generated by PIs 612 .
- PD 614 generates four error signals V out in parallel to adjust or verify signals ⁇ 45 , ⁇ 135 , ⁇ 225 , and ⁇ 315 .
- PD 614 may receive ⁇ 90 as V in1 , ⁇ 135 as V in2 , and ⁇ 180 as V in3 .
- PD 614 may receive ⁇ 180 as V in1 , ⁇ 225 as V in2 , and ⁇ 270 as V in3 .
- PD 614 may receive ⁇ 270 as V in1 , ⁇ 315 as V in2 and ⁇ 0 as V in3 . Note that since the clock signals are differential signals, the signals may be inverted to obtain signals having 180° phase offsets.
- this circuit and method may be used to adjust any of the signals ⁇ 0 , ⁇ 45 , ⁇ 90 , ⁇ 135 , ⁇ 180 , ⁇ 225 , ⁇ 270 , and ⁇ 315 , as well as any other signal have any desired intermediate phase in between any of these signals.
- PD 614 may receive ⁇ 0 as V in1 , an additional signal ⁇ having phase in the range between ⁇ 0 and ⁇ 45 as V in2 , and ⁇ 45 as V in3 . After a number of iterations, ⁇ will have a phase of approximately 22.5°.
- phase offset may either be introduced as a weighted difference of the tail currents of the multipliers (Gilbert cells) as illustrated in FIG. 8A or by injecting a current on the output of the Gilbert cell.
- the current output, I out , of the double Gilbert cell phase detector illustrated in FIG. 10A can be sensed by resistors to transform the output current to an output voltage and subsequently filtered.
- FIG. 11 shows an implementation of the double Gilbert cell phase detector in a negative feedback configuration.
- the current outputs of the first and second Gilbert cells 1102 and 1104 can be mirrored and summed in a single node used to modulate the phase between the inputs in 1 and in 2 .
- Such a configuration forces the phase difference between the inputs to 90°, so that the net current in the V out node is zero.
- a large capacitor or another form of a loop filter may be needed in such a configuration to filter the transient response of the phase detector and to govern the dynamic behavior of the loop.
- a VCO, delay line, phase interpolator, or other suitable device can be used to control the phase difference between the two input signals in 1 and in 2 , as represented by box 1110 .
- FIG. 12 illustrates another embodiment that involves a circuit for adjusting the phase characteristic externally.
- additional offset current sources 1212 and 1214 that sink or source current to or from the phase detector may be used to offset its phase characteristic.
- the offset current sources 1212 and 1214 may be externally controlled and can be connected either at the output of the Gilbert cells 1102 and 1104 , or at the voltage summing node V out , as illustrated in FIG. 12 .
Abstract
Description
- This application claims the benefit, under 35 U.S.C. §119(e), of U.S. Provisional Patent Application No. 61/084,483, entitled Clock and Data Recovery System Using Phase Interpolation, filed 29 Jul. 2008.
- The present disclosure relates generally to signal communication.
- CDR circuits (or systems) are generally used to sample an incoming data signal, extract the clock from the incoming data signal, and retime the sampled data. A phase-locked loop (PLL)-based CDR circuit is a conventional type of CDR circuit. By way of example, in a conventional PLL based CDR, a phase detector compares the phase between input data bits from a serial input data stream and a clock signal from a voltage-controlled oscillator (VCO). In response to the phase difference between the input data and the clock, the phase detector generates signals UP and DN. A charge pump drives a current to or from a loop filter according to the UP and DN signals. The loop filter generates a control voltage VCTRL for the VCO based on the UP and DN signals. The loop acts as a feedback control system that tracks the phase of input data stream with the phase of the clock that the loop generates. The dynamics of the loop are generally determined by the open loop gain and the location of open loop zeroes and poles (predominantly in the loop filter).
- When multiple phases of a periodic signal are needed, such as with a clock signal used for clock and data recovery (CDR), a challenge is to accurately generate these multiple phases. Conventionally, delay-locked loops (DLL) and phase interpolators (PI) have been used to generate the needed phases in conjunction with conventional voltage-controlled oscillators. One problem with these devices is the accuracy obtained when generating phases having intermediate degree increments.
- Various applications such as DLLs, 90 degree shifters, phase interpolators, and generators of adjustable clock phases require a high-speed phase detector whose output is zero for a 90 degree or other non-zero phase offset between inputs. The speed of conventional phase detectors, such as a phase and frequency detector (PFD) or an Alexander Detector, are limited by the speed of the flip-flops which are their integral parts. In addition, these conventional phase detectors are designed to output zero for nominal zero input phase offset, and are typically asymmetric in that the output of such phase detectors has a built-in phase offset between its inputs. The phase offset output from the phase detector typically cannot be compensated.
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FIG. 1 illustrates an example CDR circuit. -
FIG. 2 illustrates another example CDR circuit. -
FIG. 3 illustrates an example half-rate CDR circuit. -
FIG. 4 illustrates another example CDR circuit. -
FIG. 5 illustrates an example quarter-rate CDR circuit. -
FIG. 6 illustrate an example phase interpolator block. -
FIG. 7 illustrates an example phase interpolator. -
FIG. 8A illustrates an example phase detector. -
FIG. 8B illustrates another example phase detector. -
FIG. 9A illustrates a circuit schematic of an example Gilbert cell. -
FIG. 9B illustrates a symbol of an example Gilbert cell equivalent to that ofFIG. 7A . -
FIG. 9C illustrates a phase characteristic of the example Gilbert cell ofFIG. 7A . -
FIG. 10A illustrates an example circuit arrangement of Gilbert cells. -
FIG. 10B illustrates a phase characteristic of the example arrangement ofFIG. 8A . -
FIG. 11 illustrates an example phase detector circuit. -
FIG. 12 illustrates an example phase detector circuit. - Particular embodiments relate to a clock and data recovery (CDR) circuit. Particular embodiments relate to a CDR circuit that includes a phase interpolator integrated with a phase detector. Particular embodiments relate to the generation of an 8-phase clock signal from a 4-phase clock signal for use as a sampling clock signal in a 40 Gb/s quarter-rate CDR circuit. Particular embodiments relate to a 10 GHz phase interpolator for a 40 Gb/s CDR circuit. Particular embodiments relate to a phase detector that is symmetric with respect to the inputs to the phase detector. Particular embodiments relate to a high-speed phase detector for periodic input signals (e.g., clock signals). Particular embodiments relate to a phase detector having an output that is zero for a 90° or other non-zero phase offset between the inputs to the phase detector. Particular embodiments further relate to the use of parallel cross-coupled Gilbert cells for use in a phase detector. In particular embodiments, the signals described below are differential signals where appropriate. In particular embodiments, various signals described below are periodic signals, where appropriate.
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FIG. 1 illustrates an example CDR circuit that includes a phase detector (PD) 102, acharge pump 104, aloop filter 106, and a voltage-controlled oscillator (VCO) 108, each of which may include one or more sub-circuits or sub-blocks. In particular embodiments, PD 102 receives as input one or more input data streams Din as well as a multi-phase clock signal, VCO.Clk, from VCO 108. Here it should be noted that, in general, an m-phase clock signal actually includes m clock signals, each having different relative phase and each transmitted over, for example, a corresponding wire toPD 102.PD 102 is used to sample the data in the one or more input data streams Din multiple times within each VCO.Clk clock cycle, whereas VCO 108 is used to generate the appropriate clock phases for the multi-phase signal VCO.Clk that control the timing of the sampling. In typical CDRs, the data is sampled twice per cycle: at the data transition point (edge sample) and at the middle of the cycle (center sample). - In particular embodiments, to relax the bandwidth requirements in
PD 102 and VCO 108, the operating frequency of the CDR may be 1/n of the data rate of Din, which requires thatPD 102 receive multiple clock phases. By way of example, half-rate CDR architectures require four clock phases (e.g., 0°, 90° (π/2), 180° (π), and 270° (3π/2)) and quarter-rate CDR architectures require eight clock phases (e.g., 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°). In general, 1/n-rate CDR architectures require m=2×n clock phases. Furthermore, other CDR architectures may require more than two samples per clock cycle. By way of example, if j samples per clock cycle are required, then the corresponding 1/n-rate CDR would require m=j×n clock phases. For purposes of simplified illustration of example embodiments, the following disclosure focuses on embodiments utilizing conventional CDRs with one edge and one center sample per cycle (m=2×n). - Generally, one requirement of a CDR is the capability to adjust the decision phase (i.e., the center sample time relative to the edge sample). In particular embodiments, this phase adjustment functionality may be implemented with the use of a phase interpolator (PI) block 210 connected between
PD 102 andVCO 108, as illustrated inFIG. 2 . A phase interpolator generally receives two input signals separated by a phase offset (e.g., 90°) and generates an output signal having a phase in between the phases of the two input signals depending on a control signal. In particular embodiments, PI block 210 receives as inputs an m-phase clock signal, VCO.Clk, generated fromVCO 108 as well as a control input, phAdj, and produces an m-phase clock signal PI.Clk that is then fed toPD 102 for use in sampling the input data stream Din. The input phAdj determines the sign and magnitude of the phase adjustment. -
FIG. 3 illustrates an example of a half-rate CDR circuit. The circuit ofFIG. 3 is a special case of the circuit ofFIG. 2 in whichVCO 108 generates a 4-phase clock signal VCO.Clk. VCO.Clk includes clock signals φ0, φ90, φ180, and φ270, having phases of approximately 0°, 90°, 180°, and 270°, respectively (note that there is a 90° phase difference between the individual signals).PI block 210 receives the clock signals φ0, φ90, φ180, and φ270 and outputs four phase-interpolated clock signals Φ0, Φ90, Φ180, and Φ270, which have phases of approximately 0°, 90°, 180°, and 270°, respectively. In particular embodiments, the four phase-interpolated clock signals may have phase differences with respect to each other that are not 90°. PI block 210 may skew phases (such as, for example, Φ90 and Φ270 with respect to Φ0 and Φ180) to support phase adjustment capability, as described above. Note that since VCO.Clk represents differential signals, φ0 and φ180 may represent one differential pair, φ90 and φ270 may represent one differential pair, Φ0 and Φ180 may represent one differential pair, and Φ90 and Φ270 may represent one differential pair. Thus, VCO.Clk may actually include two differential signals in practice. - High data rate CDRs are often implemented as quarter-rate architectures with inductor-capacitor (LC)-based VCOs. By way of example, high data rates may refer to data rates equal or greater than 10 Gb/s, equal or greater than 20 Gb/s, or equal or greater than 40 Gb/s. Quarter-rate CDRs generally require eight or more clock phases, the generation and delivery of which present numerous difficulties using LC-based VCOs, partly due to the number of inductors required. LC-based VCOs can relatively easily produce two or four clock phases, but become difficult to deal with when more phases (e.g., 8, 12 or more) are required.
- In particular embodiments, the generation of the extra intermediate phases needed for, by way of example, quarter-rate CDRs, is combined with the phase adjustment requirement using a
single PI block 410 as illustrated inFIG. 4 . Particular embodiments use a low noise oscillator such as an LC-basedVCO 102 as a k-phase clock generator to generate a k-phase clock signal (where k≧2) input to PI block 410. In particular embodiments, PI block 410 receives the k-phase clock signal fromVCO 108 and produces an m-phase clock signal for use byphase detector 402, where m≠k (unlike previous conventional CDR architectures that produce the same number of phases as are received). -
FIG. 5 illustrates an example embodiment of a quarter-rate CDR circuit. In the illustrated embodiment,VCO 508 produces a 4-phase clock signal including clock signals φ0, φ90, φ180, and φ270, having phases of approximately 0°, 90°, 180°, and 270°, respectively. These four clock signals φ0, φ90, φ180, and φ270 are input to PI block 510, which, in the illustrated embodiment, outputs an 8-phase clock signal that includes clock signals Φ0, Φ90, Φ180, and Φ270, having phases of approximately 0°, 90°, 180°, and 270°, respectively, along with four additional intermediately-phased clock signals Φ45, Φ135, Φ225, and Φ315, having phases of approximately 45°, 135°, 225°, and 315°, respectively. Although this example describes 4-to-8 phase generation, the present disclosure is intended to cover the generation of m=k+l phases from a k-phase clock signal. Using PI block 510 to generate the additional intermediately-phases clock signals reduces/relaxes the requirements ofVCO 508 in terms of the number of clock phases output fromVCO 508. In particular embodiments, PI block 510 may also be used to adjust the decision clocks based on the phAdj control input by introducing a static phase offset. Again, it should be noted that, in particular embodiments, since VCO.Clk represents differential signals, φ0 and φ180 may represent one differential pair, φ90 and φ270 may represent one differential pair, Φ0 and Φ180 may represent one differential pair, and Φ90 and Φ270 may represent one differential pair, Φ45 and Φ225 may represent one differential pair, and Φ135 and Φ315 may represent one differential pair. Thus, VCO.Clk may actually include two differential signals in practice while PI.Clk may actually include four differential signals in practice. -
FIG. 6 illustrates anexample PI block 610 suitable for use as PI block 410 or 510. In particular embodiments, PI block 610 includes one or more phase interpolators (PIs) 612 that receive as input a k-phase clock signal and output an m-phase clock signal. In the illustrated embodiment, PI block 610 additionally includes one or more phase detectors 614 (hereinafter PD 614) in a feedback loop with PI or PIs 612 (hereinafter PI 612). As illustrated inFIG. 7 ,PI 612 may include twodifferential pairs PI 612 is the current summation of the differential pair, which is converted to voltage through a resistor. Thus, an approximate desired phase is achieved as a weighted sum of the two input signals. The ratio of the tail current will determine the phase and the sum of the tail currents will determine the amplitude of the output signal. In particular embodiments, the inputs todifferential pairs differential pair 740; input signal Φ180 may go the gate of the illustrated right transistor indifferential pair 740; input signal Φ90 may go the gate of the illustrated left transistor indifferential pair 742; and input signal Φ270 may go the gate of the illustrated right transistor indifferential pair 742. Output signal Φ225 may come from the illustrated vertical wire at the illustrated bottom ofdifferential pair 740, and output signal Φ45 may come from the illustrated vertical wire at the illustrated bottom ofdifferential pair 742. - In particular embodiments,
PI 612 takes as input the 4-phase clock signal including clock signals φ0, φ90, φ180, and φ270, having phases of approximately 0°, 90°, 180°, and 270°, respectively, fromVCO 508. Using these signals,PI 612 outputs an 8-phase clock signal that includes clock signals Φ0, Φ90, Φ180, and Φ270, having phases of approximately 0°, 90°, 180°, and 270°, respectively, along with four additional intermediately-phased clock signals Φ45, Φ135, Φ225, and Φ315, having phases of approximately 45°, 135°, 225°, and 315°, respectively. As described above,PD 614 provides feedback toPI 612 in the form of error (or control) signals that are used byPI 612 to adjust the 8-phase clock signal output. By way of example, afirst PI 612 may use the input signals Φ0 and Φ90 to generate the output signal Φ45, whileother PIs 612 in parallel with thefirst PI 612 generate the other intermediately-phase clock signals, respectively. -
FIG. 8A illustrates anexample phase detector 802 suitable for use asPD 614 and/orPDs PD 802 includes a first PD input that receives (during operation) a first input signal Vin1, a second PD input that receives (during operation) a second input signal Vin2, and a third PD input that receives (during operation) a third input signal Vin3. Note that each of the described inputs, and those described below, may actually include two inputs: one for the described signal and one for the corresponding complement (since the signals are generally differential). In particular embodiments, input signal Vin1 is a first clock signal output byPI 612, Vin2 is a second clock signal output byPI 612, and Vin3 is a third clock signal output byPI 612. In particular embodiments, the third clock signal Vin3 may be referred to as the target phase signal. In particular embodiments,PD 802 includes a first mixer cell (or circuit/block) 820 and a second mixer cell (or circuit/block) 822. In the illustrated embodiment,first mixer cell 820 includes a first MC input, a second MC input, and a first MC output whilesecond mixer cell 822 includes a third MC input, a fourth MC input, and a second MC output. In the illustrated embodiment, the first PD input is connected to the first MC input, the second PD input is connected to the third MC input, and the third PD input is connected to the second MC input and the fourth MC input. - In particular embodiments,
PD 802 further includes anadder 824 that receives the first and second MC output signals and adds the first and second MC output signals to produce a summed output signal. In particular embodiments,PD 802 additionally includes anintegrator 826 that filters the summed output signal to produce an integrated (e.g., DC) output signal that represents the PD output signal Vout output over the PD output. In the embodiment illustrated inFIG. 6 , the PD output signal Vout represents an error signal that is then input toPI 612 and used to adjust the phase of the input signal Vin3. - In particular embodiments,
first mixer cell 820 is a multiplying mixer cell andsecond mixer cell 822 is a multiplying mixer cell. In more particular embodiments,first mixer cell 820 is a Gilbert cell andsecond mixer cell 822 is a Gilbert cell. As those of skill in the art may appreciate, a Gilbert cell is an electronic multiplying mixer. By way of reference, the output current of a Gilbert cell is an accurate multiplication of the (differential) base currents of both inputs.FIG. 9A illustrates a circuit schematic of an example Gilbert cell having inputs for receiving two differential signals in1 (the complement of in1 is denoted asin1 ) and in2 (the complement of in2 is denoted asin2 ).FIG. 9B illustrates an accepted equivalent symbol for a Gilbert cell, whileFIG. 9C illustrates the value of the output differential signal Iout−Iout as a function of the phase offset Δφ(in1−in2) between the differential input signals in1 and in2. - In even more particular embodiments,
first mixer cell 820 includes afirst Gilbert cell 830 and asecond Gilbert cell 832 cross-coupled in parallel, whilesecond mixer cell 822 includes athird Gilbert cell 834 and afourth Gilbert cell 836 cross-coupled in parallel, as illustrated inFIG. 8B . In the illustrated embodiment, a first input offirst Gilbert cell 830 receives input signal Vin1 while a second input offirst Gilbert cell 830 receives input signal Vin2. A first input ofsecond Gilbert cell 832 receives input signal Vin2 while a second input ofsecond Gilbert cell 832 receives input signal Vin1. The outputs of first andsecond Gilbert cells third Gilbert cell 834 receives input signal Vin3 while a second input ofthird Gilbert cell 834 receives input signal Vin2. A first input offourth Gilbert cell 836 receives input signal Vin2 while a second input offourth Gilbert cell 836 receives input signal Vin3. The outputs of third andfourth Gilbert cells - In this way, the first MC output signal output from
first mixer cell 820 is symmetric with respect to the inputs Vin1 and Vin2 and the second MC output signal output fromsecond mixer cell 822 is symmetric with respect to the inputs Vin2 and Vin3. More specifically, the delay between the first input of any Gilbert cell and the output of the Gilbert cell is generally different than the delay between the second input of the Gilbert cell and the output of the Gilbert cell. This results in a static phase offset in the output signal output from the Gilbert cell. However, by cross-coupling two Gilbert cells in parallel as illustrated in each of themixer cells FIG. 8B , the static phase offset is cancelled to at least a first approximation.FIGS. 10A and 10B illustrates a circuit that includes two Gilbert cells cross-coupled in parallel (as in eachmixer cell 820 and 822) as well as the circuit's phase characteristic, respectively. The circuit shown inFIG. 10A may itself be used as a phase detector. As illustrated inFIG. 10A , the inputs to the twoGilbert cells Gilbert cell 1002 and to input B ofGilbert cell 1004; input in2 is connected to the input B ofGilbert cell 1002 and to input A ofGilbert cell 1004. The interchanging of the inputs effectively interpolates the outputs of the Gilbert cells and results in zero input offset to a first degree of approximation. Such an arrangement minimizes the phase offset (the phase delay between the inputs for which the output of the arrangement is still equal to zero). - The output, Vout, of
PD 802 represents an error signal that is proportional to the difference in phase between the phase of Vin3 and the average of the phases of Vin1 and Vin2. By way of example, assume Vin1 represents Φ0, Vin2 represents Φ90, and Vin3 represents Φ45. In this example, Vout represent an error signal that is proportional to the difference between the phase of Φ45, which is approximately 45° (as noted above, VCOs have difficulty generating intermediately-phased signals such as 45°, and as such the phase of Φ45 is only roughly equal to 45°), and the average of the phases of Φ0 and Φ90, which is approximately 45° since the phase of Φ0 and Φ90 are approximately 0° and 90°, respectively. The error signal, Vout, is then fed toPI 612, which then adjusts the phase of Φ45 to eliminate the phase difference (which would then result in a zero-valued error signal), which results in a Φ45 having a phase truer to 45°. In this manner,PD 614 provides a feedback loop toPI 612 to compensate for the inaccuracy ofPI 612. - In particular embodiments,
PD 614 also utilizes this circuit and process to adjust or verify the other intermediately-phased signals Φ135, Φ225, and Φ315 generated byPIs 612. In particular embodiments,PD 614 generates four error signals Vout in parallel to adjust or verify signals Φ45, Φ135, Φ225, and Φ315. By way of example, to adjust or verify Φ135,PD 614 may receive Φ90 as Vin1, Φ135 as Vin2, and Φ180 as Vin3. To adjust or verify Φ225,PD 614 may receive Φ180 as Vin1, Φ225 as Vin2, and Φ270 as Vin3. To adjust or verify Φ315,PD 614 may receive Φ270 as Vin1, Φ315 as Vin2 and Φ0 as Vin3. Note that since the clock signals are differential signals, the signals may be inverted to obtain signals having 180° phase offsets. - It should also be appreciated that this circuit and method may be used to adjust any of the signals Φ0, Φ45, Φ90, Φ135, Φ180, Φ225, Φ270, and Φ315, as well as any other signal have any desired intermediate phase in between any of these signals. By way of example,
PD 614 may receive Φ0 as Vin1, an additional signal δ having phase in the range between Φ0 and Φ45 as Vin2, and Φ45 as Vin3. After a number of iterations, δ will have a phase of approximately 22.5°. Additionally, by adding deliberate offsets in the feedback path an arbitrary phase (other than, for example, 45° and 135°) may be created. By way of example, the phases offset may either be introduced as a weighted difference of the tail currents of the multipliers (Gilbert cells) as illustrated inFIG. 8A or by injecting a current on the output of the Gilbert cell. - Referring back to
FIG. 10A , in alternate embodiments (potentially unrelated to those described above), the current output, Iout, of the double Gilbert cell phase detector illustrated inFIG. 10A can be sensed by resistors to transform the output current to an output voltage and subsequently filtered. Alternatively,FIG. 11 shows an implementation of the double Gilbert cell phase detector in a negative feedback configuration. In such a configuration, the current outputs of the first andsecond Gilbert cells FIG. 11 , a VCO, delay line, phase interpolator, or other suitable device can be used to control the phase difference between the two input signals in1 and in2, as represented bybox 1110. -
FIG. 12 illustrates another embodiment that involves a circuit for adjusting the phase characteristic externally. By way of example, in cases where a phase difference between the inputs in1 and in2 other than 90° is desired, such as for generating boundary and data clock phases in a CDR with a phase adjustment requirement, additional offsetcurrent sources 1212 and 1214 that sink or source current to or from the phase detector may be used to offset its phase characteristic. The offsetcurrent sources 1212 and 1214 may be externally controlled and can be connected either at the output of theGilbert cells FIG. 12 . - The present disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Similarly, where appropriate, the appended claims encompass all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend.
Claims (33)
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100085086A1 (en) * | 2008-07-29 | 2010-04-08 | Fujitsu Limited | Digital Frequency Detector |
US20100086075A1 (en) * | 2008-07-29 | 2010-04-08 | Fujitsu Limited | Parallel Generation and Matching of a Deskew Channel |
US20100090733A1 (en) * | 2008-07-29 | 2010-04-15 | Fujitsu Limited | Generating Multiple Clock Phases |
US20100090723A1 (en) * | 2008-07-29 | 2010-04-15 | Fujitsu Limited | Symmetric Phase Detector |
US20100091925A1 (en) * | 2008-07-29 | 2010-04-15 | Fujitsu Limited | Triple Loop Clock and Data Recovery (CDR) |
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Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
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US9094028B2 (en) | 2012-04-11 | 2015-07-28 | Rambus Inc. | Wide range frequency synthesizer with quadrature generation and spur cancellation |
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US9337848B2 (en) | 2014-02-27 | 2016-05-10 | Industry-Academic Cooperation Foundation, Yonsei University | Clock and data recovery device |
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US20230291409A1 (en) * | 2022-03-09 | 2023-09-14 | Mellanox Technologies, Ltd. | High Performance Feedback Loop with Delay Compensation |
US11949423B2 (en) | 2022-06-22 | 2024-04-02 | Faraday Technology Corp. | Clock and data recovery device with pulse filter and operation method thereof |
Citations (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4920278A (en) * | 1987-05-26 | 1990-04-24 | Nec Corporation | Phase comparator |
US5039889A (en) * | 1989-08-19 | 1991-08-13 | U.S. Philips Corp. | Phase comparison circuit |
US5343097A (en) * | 1991-09-13 | 1994-08-30 | Nec Corporation | Phase comparator circuit and phase locked loop (PLL) circuit using the same |
US6381291B1 (en) * | 1998-09-28 | 2002-04-30 | Harris Corporation | Phase detector and method |
US6426662B1 (en) * | 2001-11-12 | 2002-07-30 | Pericom Semiconductor Corp. | Twisted-ring oscillator and delay line generating multiple phases using differential dividers and comparators to match delays |
US20020131539A1 (en) * | 2000-10-27 | 2002-09-19 | Li Hung Sung | Clock and data recovery method and apparatus |
US6496077B2 (en) * | 2000-11-23 | 2002-12-17 | Samsung Electronics Co., Ltd. | Phase detector for automatically controlling offset current and phase locked loop including the same |
US20030189464A1 (en) * | 2002-04-04 | 2003-10-09 | Oleg Drapkin | Spurious-free fractional-n frequency synthesizer with multi-phase network circuit |
US20030198105A1 (en) * | 2002-04-15 | 2003-10-23 | Fujitsu Limited | Clock recovery circuit and data receiving circuit |
US20030198311A1 (en) * | 2002-04-19 | 2003-10-23 | Wireless Interface Technologies, Inc. | Fractional-N frequency synthesizer and method |
US20040022339A1 (en) * | 2002-03-27 | 2004-02-05 | Takehiko Nakao | Clock recovery circuit |
US20040210790A1 (en) * | 2001-11-26 | 2004-10-21 | Yongsam Moon | 0.6-2.5 GBaud CMOS tracked 3X oversampling transceiver with dead zone phase detection for robust clock/data recovery |
US7012474B2 (en) * | 2003-08-07 | 2006-03-14 | Broadcom Corporation | System and method generating a delayed clock output |
US20060208811A1 (en) * | 2005-03-21 | 2006-09-21 | An-Ming Lee | Multi-phase clock generator and method thereof |
US20060255866A1 (en) * | 2005-05-10 | 2006-11-16 | Nec Electronics Corporation | Pulse width modulation circuit and multiphase clock generation circuit |
US20070006053A1 (en) * | 2005-07-01 | 2007-01-04 | Lucent Technologies Inc. | Method and apparatus for synchronizing data channels using an alternating parity deskew channel |
US20070041486A1 (en) * | 2005-08-18 | 2007-02-22 | Samsung Electronics Co., Ltd. | Semiconductor device, spread spectrum clock generator and method thereof |
US20070047972A1 (en) * | 2005-08-25 | 2007-03-01 | Fujitsu Limited | DQPSK optical receiver circuit |
US7286625B2 (en) * | 2003-02-07 | 2007-10-23 | The Regents Of The University Of California | High-speed clock and data recovery circuit |
US20080100364A1 (en) * | 2006-10-30 | 2008-05-01 | Nec Electronics Corporation | Multiphase clock generation circuit |
US20080111634A1 (en) * | 2006-11-15 | 2008-05-15 | Shaw-N Min | Phase-locked loop capable of dynamically adjusting phase of output signal according to detection result of phase/frequency detector, and method thereof |
US20080192873A1 (en) * | 2007-02-09 | 2008-08-14 | Fujitsu Limited | Single Loop Frequency and Phase Detection |
US7420870B2 (en) * | 2005-06-21 | 2008-09-02 | Samsung Electronics Co., Ltd. | Phase locked loop circuit and method of locking a phase |
US20080260071A1 (en) * | 2005-12-07 | 2008-10-23 | Stefanos Sidiropoulos | Methods and Apparatus for Frequency Synthesis with Feedback Interpolation |
US20080309319A1 (en) * | 2007-06-12 | 2008-12-18 | Texas Instruments Deutschland G.M.B.H. | Electronic Device and Method for on Chip Jitter Measurement |
US20090009228A1 (en) * | 2007-07-02 | 2009-01-08 | Samsung Electronics Co., Ltd. | Clock generating apparatus |
US7489743B2 (en) * | 2004-07-14 | 2009-02-10 | Samsung Electronics Co., Ltd. | Recovery circuits and methods for the same |
US20090066423A1 (en) * | 2007-09-05 | 2009-03-12 | Texas Instruments Deutschland Gmbh | Spread spectrum clocking in fractional-n pll |
US7532038B2 (en) * | 2005-07-01 | 2009-05-12 | Via Technologies, Inc. | Phase detecting circuit having adjustable gain curve and method thereof |
US20090125652A1 (en) * | 2002-07-26 | 2009-05-14 | Broadcom Corporation | Physical layer device having a serdes pass through mode |
US7535271B2 (en) * | 2002-03-22 | 2009-05-19 | Rambus Inc. | Locked loop circuit with clock hold function |
US20090149149A1 (en) * | 2006-08-10 | 2009-06-11 | Ruijs Leonardus C H | Dual Gilbert Cell Mixer with Offset Cancellation |
US20090237128A1 (en) * | 2008-03-19 | 2009-09-24 | Integrated Device Technology, Inc. | High frequency fractional-N divider |
US20100085086A1 (en) * | 2008-07-29 | 2010-04-08 | Fujitsu Limited | Digital Frequency Detector |
US20100086075A1 (en) * | 2008-07-29 | 2010-04-08 | Fujitsu Limited | Parallel Generation and Matching of a Deskew Channel |
US20100090723A1 (en) * | 2008-07-29 | 2010-04-15 | Fujitsu Limited | Symmetric Phase Detector |
US20100091925A1 (en) * | 2008-07-29 | 2010-04-15 | Fujitsu Limited | Triple Loop Clock and Data Recovery (CDR) |
US20100090733A1 (en) * | 2008-07-29 | 2010-04-15 | Fujitsu Limited | Generating Multiple Clock Phases |
US20100104057A1 (en) * | 2008-07-29 | 2010-04-29 | Fujitsu Limited | Clock and Data Recovery with a Data Aligner |
US20100119024A1 (en) * | 2005-01-21 | 2010-05-13 | Shumarayev Sergey Y | Method and apparatus for multi-mode clock data recovery |
US20100241918A1 (en) * | 2009-03-20 | 2010-09-23 | Fujitsu Limited | Clock and data recovery for differential quadrature phase shift keying |
US7924071B2 (en) * | 2008-09-16 | 2011-04-12 | Renesas Electronics Corporation | Synchronization detection circuit, pulse width modulation circuit using the same, and synchronization detection method |
-
2009
- 2009-07-29 US US12/511,365 patent/US8718217B2/en not_active Expired - Fee Related
Patent Citations (49)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4920278A (en) * | 1987-05-26 | 1990-04-24 | Nec Corporation | Phase comparator |
US5039889A (en) * | 1989-08-19 | 1991-08-13 | U.S. Philips Corp. | Phase comparison circuit |
US5343097A (en) * | 1991-09-13 | 1994-08-30 | Nec Corporation | Phase comparator circuit and phase locked loop (PLL) circuit using the same |
US6381291B1 (en) * | 1998-09-28 | 2002-04-30 | Harris Corporation | Phase detector and method |
US20020131539A1 (en) * | 2000-10-27 | 2002-09-19 | Li Hung Sung | Clock and data recovery method and apparatus |
US6496077B2 (en) * | 2000-11-23 | 2002-12-17 | Samsung Electronics Co., Ltd. | Phase detector for automatically controlling offset current and phase locked loop including the same |
US6426662B1 (en) * | 2001-11-12 | 2002-07-30 | Pericom Semiconductor Corp. | Twisted-ring oscillator and delay line generating multiple phases using differential dividers and comparators to match delays |
US20040210790A1 (en) * | 2001-11-26 | 2004-10-21 | Yongsam Moon | 0.6-2.5 GBaud CMOS tracked 3X oversampling transceiver with dead zone phase detection for robust clock/data recovery |
US7535271B2 (en) * | 2002-03-22 | 2009-05-19 | Rambus Inc. | Locked loop circuit with clock hold function |
US20040022339A1 (en) * | 2002-03-27 | 2004-02-05 | Takehiko Nakao | Clock recovery circuit |
US20030189464A1 (en) * | 2002-04-04 | 2003-10-09 | Oleg Drapkin | Spurious-free fractional-n frequency synthesizer with multi-phase network circuit |
US20030198105A1 (en) * | 2002-04-15 | 2003-10-23 | Fujitsu Limited | Clock recovery circuit and data receiving circuit |
US20030198311A1 (en) * | 2002-04-19 | 2003-10-23 | Wireless Interface Technologies, Inc. | Fractional-N frequency synthesizer and method |
US20090125652A1 (en) * | 2002-07-26 | 2009-05-14 | Broadcom Corporation | Physical layer device having a serdes pass through mode |
US7286625B2 (en) * | 2003-02-07 | 2007-10-23 | The Regents Of The University Of California | High-speed clock and data recovery circuit |
US7012474B2 (en) * | 2003-08-07 | 2006-03-14 | Broadcom Corporation | System and method generating a delayed clock output |
US7489743B2 (en) * | 2004-07-14 | 2009-02-10 | Samsung Electronics Co., Ltd. | Recovery circuits and methods for the same |
US20100119024A1 (en) * | 2005-01-21 | 2010-05-13 | Shumarayev Sergey Y | Method and apparatus for multi-mode clock data recovery |
US20060208811A1 (en) * | 2005-03-21 | 2006-09-21 | An-Ming Lee | Multi-phase clock generator and method thereof |
US7446616B2 (en) * | 2005-03-21 | 2008-11-04 | Realtek Semiconductor Corp. | Multi-phase clock generator and method thereof |
US20060255866A1 (en) * | 2005-05-10 | 2006-11-16 | Nec Electronics Corporation | Pulse width modulation circuit and multiphase clock generation circuit |
US7420870B2 (en) * | 2005-06-21 | 2008-09-02 | Samsung Electronics Co., Ltd. | Phase locked loop circuit and method of locking a phase |
US20070006053A1 (en) * | 2005-07-01 | 2007-01-04 | Lucent Technologies Inc. | Method and apparatus for synchronizing data channels using an alternating parity deskew channel |
US7532038B2 (en) * | 2005-07-01 | 2009-05-12 | Via Technologies, Inc. | Phase detecting circuit having adjustable gain curve and method thereof |
US20070041486A1 (en) * | 2005-08-18 | 2007-02-22 | Samsung Electronics Co., Ltd. | Semiconductor device, spread spectrum clock generator and method thereof |
US7881419B2 (en) * | 2005-08-18 | 2011-02-01 | Samsung Electronics Co., Ltd. | Semiconductor device, spread spectrum clock generator and method thereof |
US7444085B2 (en) * | 2005-08-25 | 2008-10-28 | Fujitsu Limited | DQPSK optical receiver circuit |
US20070047972A1 (en) * | 2005-08-25 | 2007-03-01 | Fujitsu Limited | DQPSK optical receiver circuit |
US20080260071A1 (en) * | 2005-12-07 | 2008-10-23 | Stefanos Sidiropoulos | Methods and Apparatus for Frequency Synthesis with Feedback Interpolation |
US20090149149A1 (en) * | 2006-08-10 | 2009-06-11 | Ruijs Leonardus C H | Dual Gilbert Cell Mixer with Offset Cancellation |
US20080100364A1 (en) * | 2006-10-30 | 2008-05-01 | Nec Electronics Corporation | Multiphase clock generation circuit |
US20080111634A1 (en) * | 2006-11-15 | 2008-05-15 | Shaw-N Min | Phase-locked loop capable of dynamically adjusting phase of output signal according to detection result of phase/frequency detector, and method thereof |
US7679453B2 (en) * | 2006-11-15 | 2010-03-16 | Realtek Semiconductor Corp. | Phase-locked loop capable of dynamically adjusting phase of output signal according to detection result of phase/frequency detector, and method thereof |
US20080192873A1 (en) * | 2007-02-09 | 2008-08-14 | Fujitsu Limited | Single Loop Frequency and Phase Detection |
US20080309319A1 (en) * | 2007-06-12 | 2008-12-18 | Texas Instruments Deutschland G.M.B.H. | Electronic Device and Method for on Chip Jitter Measurement |
US20090009228A1 (en) * | 2007-07-02 | 2009-01-08 | Samsung Electronics Co., Ltd. | Clock generating apparatus |
US7737791B2 (en) * | 2007-09-05 | 2010-06-15 | Texas Instruments Deutschland Gmbh | Spread spectrum clocking in fractional-N PLL |
US20090066423A1 (en) * | 2007-09-05 | 2009-03-12 | Texas Instruments Deutschland Gmbh | Spread spectrum clocking in fractional-n pll |
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