US20100116676A1 - Method of fabricating probe pin for probe card - Google Patents

Method of fabricating probe pin for probe card Download PDF

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Publication number
US20100116676A1
US20100116676A1 US12/502,652 US50265209A US2010116676A1 US 20100116676 A1 US20100116676 A1 US 20100116676A1 US 50265209 A US50265209 A US 50265209A US 2010116676 A1 US2010116676 A1 US 2010116676A1
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Prior art keywords
probe pin
probe
concave region
substrate
mold substrate
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US12/502,652
Inventor
Sang Jin Kim
Byeung Gyu Chang
Hee Ju Son
Ho Joon PARK
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Samsung Electro Mechanics Co Ltd
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Samsung Electro Mechanics Co Ltd
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Assigned to SAMSUNG ELECTRO-MECHANICS CO., LTD. reassignment SAMSUNG ELECTRO-MECHANICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHANG, BYEUNG GYU, KIM, SANG JIN, PARK, HO JOON, SON, HEE JU
Publication of US20100116676A1 publication Critical patent/US20100116676A1/en
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26Testing of individual semiconductor devices
    • G01R31/2601Apparatus or methods therefor
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D1/00Electroforming
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D1/00Electroforming
    • C25D1/0033D structures, e.g. superposed patterned layers
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D1/00Electroforming
    • C25D1/10Moulds; Masks; Masterforms
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0017Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor for the production of embossing, cutting or similar devices; for the production of casting means

Definitions

  • the present invention relates to a probe pin for a probe card, and more particularly, to a method of fabricating a probe pin for a probe card, which makes it possible to simplify a fabrication process of the probe pin and reuse a mold used for fabrication of the probe pin.
  • a probe card is a test device for determining the defects or the electrical characteristics of a semiconductor chip on a wafer by using the electrical contact with a probe pin.
  • the probe card may include a circuit substrate such as a ceramic substrate with a circuit, and a plurality of fine probe pins that are electrically connected to the circuit.
  • a probe pin for a probe card mechanically contacts a wafer. Therefore, the body of the probe pin requires an excellent mechanical elasticity because it must have a high yield strength and an excellent restoring force. Also, the probe pin body must have a low electrical resistance because it electrically tests a chip.
  • a recent probe test device requires the improvement of the integration level of a probe pin in order to test a highly-integrated semiconductor memory chip on a wafer level in a batch fashion.
  • the general trend is that a MEMS processing technology is used to form fine probe fines in a batch fashion, thereby improving the integration level of the probe pins.
  • an electrode is formed at one side of a ceramic substrate; a MEMS process is performed to form a probe pin on a semiconductor wafer such as a silicon wafer; and the ceramic substrate and the silicon wafer are bonded together.
  • the silicon wafer used as a mold is removed to form the probe pin on the ceramic substrate, thereby providing a desired probe card.
  • the first method uses a polymer material to fabricate a probe pin mold on a ceramic substrate, fills the probe pin mold through a plating process to form a probe pin, and removes only the mold material so that the probe pin remains on the ceramic substrate.
  • the second method processes a selectively-removable substrate into a desired mold structure by means of a mold material, forms a probe pin in the processed space through a plating process, bonds the probe pin with the ceramic substrate, and selectively removes the mold substrate.
  • the mold forming process for fabrication of the probe pin is complex. Also, because the structure used as the mold is finally removed, the mold must be formed in every probe pin fabrication process. For example, if the mold is fabricated using a polymer material, an exposing process, a developing process, a layer growing process, and a plating process are used to form a probe pin body (or a probe beam); the above processes are repeated to form a probe tip portion; and a bonding process and a mold removing process are performed to fabricate a probe pin.
  • preprocessing processes such as a cleaning process, a surface treating process, a polymer coating process, and a drying process are required, when considering only the exposing process, which increases the fabrication process time and the fault repair time of the probe card and reduces the chip production due to the test efficiency reduction in the actual field.
  • An aspect of the present invention provides a method of fabricating a probe pin for a probe card, which makes it possible to simplify a fabrication process of the probe pin and reuse a mold structure for fabrication of the probe pin by facilitating the separation of the mold structure from the probe pin.
  • a method of fabricating a probe pin including: forming a concave region corresponding to a probe pin on a mold substrate; reducing the surface roughness of the concave region to smooth the surface of the concave region; forming a release layer on the surface of the concave region of the mold substrate; and performing a plating process to form a probe pin corresponding to the concave region.
  • the mold substrate may be a silicon substrate.
  • the probe pin may have a probe beam and a probe tip provided at one end of the probe beam.
  • the reducing of the surface roughness of the concave region may include: forming an oxide layer on the surface of the concave region; and removing the oxide layer.
  • the oxide layer formed on the surface of the concave region may be a thermal oxide layer.
  • the release layer may be formed of a copper or a copper alloy.
  • the method may further include forming a mask layer on the surface of the mold substrate other than the surface of the concave region before the forming of the release layer. In this case, the method may further include removing the mask layer after the performing of the plating process.
  • the probe pin may be formed of one selected from the group consisting of Ti, Ni, Co and a combination thereof.
  • the method may further include, after the performing of the plating process, disposing the mold substrate having the probe pin on a circuit substrate and connecting the probe pin to a desired portion of the circuit substrate; and separating the mold substrate from the probe pin in such away that the mold substrate remains unchanged.
  • the separating of the mold substrate from the probe pin may be performed using the thermal expansion coefficient difference between the probe pin and the mold substrate.
  • the separated mold substrate may be reused. That is, the mold substrate separated from the probe pin may be reused in the surface smoothing process for reduction of the surface roughness, the release layer forming process, and the plating process for formation of the probe pin.
  • FIGS. 1A to 1F are cross-sectional views illustrating a process of forming a probe pin in a probe pin fabrication method according to an exemplary embodiment of the present invention.
  • FIGS. 2A to 2C are cross-sectional views illustrating a transfer process in the probe pin fabrication method according to an exemplary embodiment of the present invention.
  • FIGS. 1A to 1F are cross-sectional views illustrating a process of forming a probe pin in a probe pin fabrication method according to an exemplary embodiment of the present invention.
  • a substrate 11 for a mold (hereinafter referred to as a mold substrate) is prepared for fabrication of a probe pin.
  • the mold substrate 11 may preferably be a silicon wafer, to which the present invention is not limited.
  • the mold substrate 11 may also be other well-known semiconductor substrates that are easy to process.
  • the mold substrate 11 may be any substrate that can have a desired concave structure formed through an anisotropic etching process such as a Reactive Ion Etching (RIE) process.
  • RIE Reactive Ion Etching
  • a concave region P for a desired probe pin is formed at the mold substrate 11 .
  • the concave region P may be formed to have a region 11 b for a probe beam (hereinafter referred to as a probe beam region) and a region 11 a for a probe tip (hereinafter referred to as a probe tip region), so that it corresponds to a desired probe pin structure.
  • a probe beam region a region 11 b for a probe beam
  • a probe tip region a region 11 a for a probe tip
  • One concave region P for one probe pin is illustrated in this embodiment. However, in an actual process, a plurality of concave regions for a plurality of probe pins may be formed at a large-area silicon wafer.
  • the present process may be implemented using a well-known anisotropic etching process such as an RIE process, as described above.
  • a well-known anisotropic etching process such as an RIE process, as described above.
  • each of the etched surfaces of the silicon mold substrate may have an inclined surface (e.g., 11 a ) with respect to a horizontal plane according to a desired probe shape.
  • the etched surfaces with different crystal surfaces can improve the releasability of the mold.
  • the present invention includes an improvement process for the surface of the concave region P. That is, the present invention uses at least a process of reducing the surface roughness (Ra) of the concave region P in order to smooth the surface of the concave region P.
  • a simple wet etching process may be performed in order to reduce the surface roughness of the concave region P.
  • a process of reducing the surface roughness of the concave region P according to a preferred embodiment of the present invention may be performed through processes illustrated in FIGS. 1C and 1D .
  • a thin oxide layer 12 is formed on the surface of the concave region P.
  • the oxide layer 12 may be a silicon oxide layer if a silicon substrate is used as the mold substrate 11 .
  • the oxide layer 12 formed on the surface of the concave region P may be a thermal oxide layer.
  • the oxide layer 12 formed on the surface of the concave region P is removed to achieve the smoother surface thereof.
  • the removing process may be performed using a well-known wet etching process.
  • the smoothed surface of the concave region P achieved through the oxide layer forming/removing processes can guarantee the high releasability of the mold.
  • a release layer 15 is formed on the surface of the concave region P.
  • the release layer 15 of the present invention may be formed of any material that is electrically conductive and also provides the high releasability between the material of the mold substrate 11 and a metal used in the subsequent plating process.
  • the related art grows a Ti or Cr layer in order to increase the adhesion to the silicon.
  • the present method may not use Ti or Cr in order to secure the releasability of a probe pin.
  • the release layer 15 of the present invention may be formed of a copper or a copper alloy.
  • the release layer 15 formed of a copper increases the current density, thus making it possible to increase the efficiency of the subsequent plating process and provide the high releasability.
  • the adhesion (or the releasability) between the release layer 15 and the mold substrate 11 formed of a silicon may be adjusted to a desired level by controlling the thickness of the release layer 15 .
  • the present process may be easily implemented by forming a mask layer 16 such as a photoresist pattern on the surface of the mold substrate 11 other than the surface of the concave region P before forming the release layer 15 .
  • the mask layer 16 may remain until the start of the plating layer, and may be removed after the completion of the plating process.
  • the plating process is performed to form a probe pin 17 corresponding to the concave region P.
  • the probe pin 17 may be formed of one selected from the group consisting of Ti, Ni, Co and a combination thereof.
  • the probe pin 17 formed by the plating process may have a prove beam 17 b corresponding to the concave region P and a probe tip 17 a formed at one end portion of the probe beam 17 b.
  • the release layer 15 formed of a copper of the present invention can guarantee the high current density, thus making it possible to easily perform an electrolytic plating process.
  • FIGS. 2A to 2C are cross-sectional views illustrating a transfer process in the probe pin fabrication method according to an exemplary embodiment of the present invention.
  • a probe card substrate 21 a having a circuit formed thereon is prepared.
  • the probe card substrate 21 may be a multilayer ceramic substrate.
  • a metal bonding unit 27 is formed on a circuit region 22 of the probe card substrate 21 .
  • the metal bonding unit 27 may have a predetermined height and may be formed of a portion of the probe pin.
  • the mold substrate 11 having the probe pin 17 formed therein is disposed on the probe card substrate 21 , and then a portion of the probe pin 17 is connected to a desired portion of the probe card substrate 21 .
  • one end portion of the probe beam 17 b formed on the opposite side of the end portion of the probe beam 17 b having the probe tip 17 a formed thereat, is connected to the metal bonding unit 27 , thereby transferring the probe pin 17 to the probe card substrate 21 .
  • the mold substrate 11 is separated from the probe pin 17 in such a way that the mold substrate 11 remains unchanged.
  • the present invention separates the mold substrate 11 from the probe pin 17 on the basis of the high releasability, while maintaining the shape of the mold substrate 11 , without removing the mold structure.
  • the high releasability can be implemented by removing the surface roughness and using the release layer 15 that is formed of a conductive material such as a copper.
  • the separated mold substrate 11 can be reused.
  • the mold substrate 11 separated from the probe pin 17 can be repeatedly used several times, due to the surface smoothing process for reduction of the surface roughness, the release layer forming process, and the plating process for formation of the probe pin 17 .
  • the separating process can be easily implemented by using the thermal expansion coefficient difference between the material of the mold substrate 11 and the material of the probe pin 17 (including the release layer 15 ).
  • the bonding process is performed at high temperature. Thereafter, only the probe pin 17 and the mold substrate 11 are locally cooled at low temperature, thereby increasing the interfacial stress due to the thermal expansion coefficient difference between the silicon and the metal and releasing the probe pin 17 along the metal layer introduced in the plating process.
  • the silicon and the general metal have a thermal expansion coefficient difference of about 4.4 times therebetween, the separating process using the thermal expansion coefficient difference, such as the local low-temperature cooling process, can be easily implemented.
  • the probe pin fabrication method according to the present invention can simplify the mold forming process for fabrication of the probe pin and can continuously reuse the mold in the probe pin fabrication process. Consequently, the present invention can greatly reduce the fabrication time of the probe pin and can greatly increase the mass production through the reuse of the mold. Particularly, the present invention can reduce the fault repair time of the probe pin like a MEMS probe card, thus making it possible to increase the chip test efficiency.

Abstract

Provided is a method of fabricating a probe pin. In the method, a concave region for a probe pin is formed on a mold substrate. The surface roughness of the concave region is reduced to smooth the surface of the concave region. A release layer is formed on the surface of the concave region of the mold substrate. A plating process is performed to form a probe pin corresponding to the concave region. After the performing of the plating process, the mold substrate having the probe pin is disposed on a circuit substrate and the probe pin is connected to a desired portion of the circuit substrate. Thereafter, the mold substrate is separated from the probe pin in such a way that the mold substrate remains unchanged. Also, the separated mold substrate may be reused.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application claims the priority of Korean Patent Application No. 2008-0112201 filed on Nov. 12, 2008, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a probe pin for a probe card, and more particularly, to a method of fabricating a probe pin for a probe card, which makes it possible to simplify a fabrication process of the probe pin and reuse a mold used for fabrication of the probe pin.
  • 2. Description of the Related Art
  • A probe card is a test device for determining the defects or the electrical characteristics of a semiconductor chip on a wafer by using the electrical contact with a probe pin. The probe card may include a circuit substrate such as a ceramic substrate with a circuit, and a plurality of fine probe pins that are electrically connected to the circuit.
  • In general, a probe pin for a probe card mechanically contacts a wafer. Therefore, the body of the probe pin requires an excellent mechanical elasticity because it must have a high yield strength and an excellent restoring force. Also, the probe pin body must have a low electrical resistance because it electrically tests a chip.
  • Also, a tip portion of the probe pin mechanically contacting the chip requires an anti-abrasion and a low contact resistance. A recent probe test device requires the improvement of the integration level of a probe pin in order to test a highly-integrated semiconductor memory chip on a wafer level in a batch fashion. Thus, the general trend is that a MEMS processing technology is used to form fine probe fines in a batch fashion, thereby improving the integration level of the probe pins.
  • In general, an electrode is formed at one side of a ceramic substrate; a MEMS process is performed to form a probe pin on a semiconductor wafer such as a silicon wafer; and the ceramic substrate and the silicon wafer are bonded together. Herein, the silicon wafer used as a mold is removed to form the probe pin on the ceramic substrate, thereby providing a desired probe card.
  • Herein, a probe pin fabrication method according to the related art can be summarized into the following two methods.
  • The first method uses a polymer material to fabricate a probe pin mold on a ceramic substrate, fills the probe pin mold through a plating process to form a probe pin, and removes only the mold material so that the probe pin remains on the ceramic substrate.
  • The second method processes a selectively-removable substrate into a desired mold structure by means of a mold material, forms a probe pin in the processed space through a plating process, bonds the probe pin with the ceramic substrate, and selectively removes the mold substrate.
  • In the probe pin fabrication method according to the related art, the mold forming process for fabrication of the probe pin is complex. Also, because the structure used as the mold is finally removed, the mold must be formed in every probe pin fabrication process. For example, if the mold is fabricated using a polymer material, an exposing process, a developing process, a layer growing process, and a plating process are used to form a probe pin body (or a probe beam); the above processes are repeated to form a probe tip portion; and a bonding process and a mold removing process are performed to fabricate a probe pin. However, preprocessing processes such as a cleaning process, a surface treating process, a polymer coating process, and a drying process are required, when considering only the exposing process, which increases the fabrication process time and the fault repair time of the probe card and reduces the chip production due to the test efficiency reduction in the actual field.
  • SUMMARY OF THE INVENTION
  • An aspect of the present invention provides a method of fabricating a probe pin for a probe card, which makes it possible to simplify a fabrication process of the probe pin and reuse a mold structure for fabrication of the probe pin by facilitating the separation of the mold structure from the probe pin.
  • According to an aspect of the present invention, there is provided a method of fabricating a probe pin, the method including: forming a concave region corresponding to a probe pin on a mold substrate; reducing the surface roughness of the concave region to smooth the surface of the concave region; forming a release layer on the surface of the concave region of the mold substrate; and performing a plating process to form a probe pin corresponding to the concave region.
  • The mold substrate may be a silicon substrate. The probe pin may have a probe beam and a probe tip provided at one end of the probe beam.
  • The reducing of the surface roughness of the concave region may include: forming an oxide layer on the surface of the concave region; and removing the oxide layer.
  • In this case, the oxide layer formed on the surface of the concave region may be a thermal oxide layer.
  • The release layer may be formed of a copper or a copper alloy.
  • The method may further include forming a mask layer on the surface of the mold substrate other than the surface of the concave region before the forming of the release layer. In this case, the method may further include removing the mask layer after the performing of the plating process.
  • The probe pin may be formed of one selected from the group consisting of Ti, Ni, Co and a combination thereof.
  • The method may further include, after the performing of the plating process, disposing the mold substrate having the probe pin on a circuit substrate and connecting the probe pin to a desired portion of the circuit substrate; and separating the mold substrate from the probe pin in such away that the mold substrate remains unchanged.
  • The separating of the mold substrate from the probe pin may be performed using the thermal expansion coefficient difference between the probe pin and the mold substrate.
  • Particularly, the separated mold substrate may be reused. That is, the mold substrate separated from the probe pin may be reused in the surface smoothing process for reduction of the surface roughness, the release layer forming process, and the plating process for formation of the probe pin.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The above and other aspects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
  • FIGS. 1A to 1F are cross-sectional views illustrating a process of forming a probe pin in a probe pin fabrication method according to an exemplary embodiment of the present invention; and
  • FIGS. 2A to 2C are cross-sectional views illustrating a transfer process in the probe pin fabrication method according to an exemplary embodiment of the present invention.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • Exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
  • FIGS. 1A to 1F are cross-sectional views illustrating a process of forming a probe pin in a probe pin fabrication method according to an exemplary embodiment of the present invention.
  • As illustrated in FIG. 1A, a substrate 11 for a mold (hereinafter referred to as a mold substrate) is prepared for fabrication of a probe pin.
  • The mold substrate 11 may preferably be a silicon wafer, to which the present invention is not limited. For example, the mold substrate 11 may also be other well-known semiconductor substrates that are easy to process. Specifically, the mold substrate 11 may be any substrate that can have a desired concave structure formed through an anisotropic etching process such as a Reactive Ion Etching (RIE) process.
  • Thereafter, as illustrated in FIG. 1B, a concave region P for a desired probe pin is formed at the mold substrate 11.
  • The concave region P may be formed to have a region 11 b for a probe beam (hereinafter referred to as a probe beam region) and a region 11 a for a probe tip (hereinafter referred to as a probe tip region), so that it corresponds to a desired probe pin structure. One concave region P for one probe pin is illustrated in this embodiment. However, in an actual process, a plurality of concave regions for a plurality of probe pins may be formed at a large-area silicon wafer.
  • The present process may be implemented using a well-known anisotropic etching process such as an RIE process, as described above. Particularly, if the concave region P is formed through an anisotropic etching process, each of the etched surfaces of the silicon mold substrate may have an inclined surface (e.g., 11 a) with respect to a horizontal plane according to a desired probe shape. The etched surfaces with different crystal surfaces can improve the releasability of the mold.
  • Meanwhile, the surface of the concave region P, that is, the surface resulting from the anisotropic etching process may be damaged during the etching process and thus may have a high surface roughness. Because the high surface roughness of the concave region P hinders the achievement of the releasability of the mold, the present invention includes an improvement process for the surface of the concave region P. That is, the present invention uses at least a process of reducing the surface roughness (Ra) of the concave region P in order to smooth the surface of the concave region P.
  • For example, after the anisotropic etching process such as an RIE process is performed, a simple wet etching process may be performed in order to reduce the surface roughness of the concave region P. However, a process of reducing the surface roughness of the concave region P according to a preferred embodiment of the present invention may be performed through processes illustrated in FIGS. 1C and 1D.
  • That is, as illustrated in FIG. 1C, a thin oxide layer 12 is formed on the surface of the concave region P. The oxide layer 12 may be a silicon oxide layer if a silicon substrate is used as the mold substrate 11. The oxide layer 12 formed on the surface of the concave region P may be a thermal oxide layer.
  • Thereafter, as illustrated in FIG. 1D, the oxide layer 12 formed on the surface of the concave region P is removed to achieve the smoother surface thereof. The removing process may be performed using a well-known wet etching process.
  • The smoothed surface of the concave region P achieved through the oxide layer forming/removing processes can guarantee the high releasability of the mold.
  • In addition, as illustrated in FIG. 1E, a release layer 15 is formed on the surface of the concave region P.
  • The release layer 15 of the present invention may be formed of any material that is electrically conductive and also provides the high releasability between the material of the mold substrate 11 and a metal used in the subsequent plating process.
  • For example, before forming a seed layer, the related art grows a Ti or Cr layer in order to increase the adhesion to the silicon. However, the present method may not use Ti or Cr in order to secure the releasability of a probe pin.
  • The release layer 15 of the present invention may be formed of a copper or a copper alloy. The release layer 15 formed of a copper increases the current density, thus making it possible to increase the efficiency of the subsequent plating process and provide the high releasability. The adhesion (or the releasability) between the release layer 15 and the mold substrate 11 formed of a silicon may be adjusted to a desired level by controlling the thickness of the release layer 15.
  • The present process may be easily implemented by forming a mask layer 16 such as a photoresist pattern on the surface of the mold substrate 11 other than the surface of the concave region P before forming the release layer 15. In this case, the mask layer 16 may remain until the start of the plating layer, and may be removed after the completion of the plating process.
  • Thereafter, as illustrated in FIG. 1F, the plating process is performed to form a probe pin 17 corresponding to the concave region P.
  • In a specific embodiment of the present invention, the probe pin 17 may be formed of one selected from the group consisting of Ti, Ni, Co and a combination thereof. The probe pin 17 formed by the plating process may have a prove beam 17 b corresponding to the concave region P and a probe tip 17 a formed at one end portion of the probe beam 17 b. As described above, the release layer 15 formed of a copper of the present invention can guarantee the high current density, thus making it possible to easily perform an electrolytic plating process.
  • The advantages and effects of the present invention can be clearly understood through a process of transferring to a probe card substrate such as a ceramic substrate.
  • FIGS. 2A to 2C are cross-sectional views illustrating a transfer process in the probe pin fabrication method according to an exemplary embodiment of the present invention.
  • As illustrated in FIG. 2A, a probe card substrate 21 a having a circuit formed thereon is prepared. The probe card substrate 21 may be a multilayer ceramic substrate.
  • As illustrated in the drawings, a metal bonding unit 27 is formed on a circuit region 22 of the probe card substrate 21. The metal bonding unit 27 may have a predetermined height and may be formed of a portion of the probe pin.
  • Thereafter, as illustrated in FIG. 2B, the mold substrate 11 having the probe pin 17 formed therein is disposed on the probe card substrate 21, and then a portion of the probe pin 17 is connected to a desired portion of the probe card substrate 21.
  • Specifically, as illustrated in the drawings, one end portion of the probe beam 17 b, formed on the opposite side of the end portion of the probe beam 17 b having the probe tip 17 a formed thereat, is connected to the metal bonding unit 27, thereby transferring the probe pin 17 to the probe card substrate 21.
  • Thereafter, as illustrated in FIG. 2C, the mold substrate 11 is separated from the probe pin 17 in such a way that the mold substrate 11 remains unchanged.
  • The advantages of the present invention well appear in the present process. That is, unlike the related art, the present invention separates the mold substrate 11 from the probe pin 17 on the basis of the high releasability, while maintaining the shape of the mold substrate 11, without removing the mold structure. As described above, the high releasability can be implemented by removing the surface roughness and using the release layer 15 that is formed of a conductive material such as a copper.
  • Particularly, the separated mold substrate 11 can be reused. The mold substrate 11 separated from the probe pin 17 can be repeatedly used several times, due to the surface smoothing process for reduction of the surface roughness, the release layer forming process, and the plating process for formation of the probe pin 17.
  • The separating process can be easily implemented by using the thermal expansion coefficient difference between the material of the mold substrate 11 and the material of the probe pin 17 (including the release layer 15). In general, the bonding process is performed at high temperature. Thereafter, only the probe pin 17 and the mold substrate 11 are locally cooled at low temperature, thereby increasing the interfacial stress due to the thermal expansion coefficient difference between the silicon and the metal and releasing the probe pin 17 along the metal layer introduced in the plating process. Actually, because the silicon and the general metal have a thermal expansion coefficient difference of about 4.4 times therebetween, the separating process using the thermal expansion coefficient difference, such as the local low-temperature cooling process, can be easily implemented.
  • As described above, the probe pin fabrication method according to the present invention can simplify the mold forming process for fabrication of the probe pin and can continuously reuse the mold in the probe pin fabrication process. Consequently, the present invention can greatly reduce the fabrication time of the probe pin and can greatly increase the mass production through the reuse of the mold. Particularly, the present invention can reduce the fault repair time of the probe pin like a MEMS probe card, thus making it possible to increase the chip test efficiency.
  • While the present invention has been shown and described in connection with the exemplary embodiments, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (12)

1. A method of fabricating a probe pin, the method comprising:
forming a concave region corresponding to a probe pin on a mold substrate;
reducing the surface roughness of the concave region to smooth the surface of the concave region;
forming a release layer on the surface of the concave region of the mold substrate; and
performing a plating process to form a probe pin corresponding to the concave region.
2. The method of claim 1, wherein the mold substrate is a silicon substrate.
3. The method of claim 1, wherein the probe pin has a probe beam and a probe tip provided at one end of the probe beam.
4. The method of claim 1, wherein the reducing of the surface roughness of the concave region comprises:
forming an oxide layer on the surface of the concave region; and
removing the oxide layer.
5. The method of claim 4, wherein the oxide layer formed on the surface of the concave region is a thermal oxide layer.
6. The method of claim 1, wherein the release layer is formed of a copper or a copper alloy.
7. The method of claim 1, further comprising:
forming a mask layer on the surface of the mold substrate other than the surface of the concave region before the forming of the release layer.
8. The method of claim 7, further comprising:
removing the mask layer after the performing of the plating process.
9. The method of claim 1, wherein the probe pin is formed of one selected from the group consisting of Ti, Ni, Co and a combination thereof.
10. The method of claim 1, further comprising, after the performing of the plating process:
disposing the mold substrate having the probe pin on a circuit substrate and connecting the probe pin to a desired portion of the circuit substrate; and
separating the mold substrate from the probe pin in such a way that the mold substrate remains unchanged.
11. The method of claim 10, wherein the separating of the mold substrate from the probe pin is performed using the thermal expansion coefficient difference between the probe pin and the mold substrate.
12. The method of claim 10, further comprising:
performing the process of claim 1 by using the separated mold substrate.
US12/502,652 2008-11-12 2009-07-14 Method of fabricating probe pin for probe card Abandoned US20100116676A1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10115690B2 (en) * 2015-02-26 2018-10-30 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing micro pins and isolated conductive micro pin
EP4151776A1 (en) * 2021-09-17 2023-03-22 FUJIFILM Corporation Electroforming master, method for producing electroforming master, and method for producing electroforming material

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101996521B1 (en) * 2018-03-05 2019-07-04 임근환 Method for Manufacturing Probe for Testing Electronic Components

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5645684A (en) * 1994-03-07 1997-07-08 The Regents Of The University Of California Multilayer high vertical aspect ratio thin film structures
US5953622A (en) * 1996-11-23 1999-09-14 Hyundai Electronics Industries Co., Ltd. Method for fabricating semiconductor wafers
US6482013B2 (en) * 1993-11-16 2002-11-19 Formfactor, Inc. Microelectronic spring contact element and electronic component having a plurality of spring contact elements
US6576301B1 (en) * 1999-04-30 2003-06-10 Advantest, Corp. Method of producing contact structure
US20050045481A1 (en) * 2003-09-01 2005-03-03 Yuuko Kawaguchi Method for manufacturing stamper, stamper and optical recording medium
US7326327B2 (en) * 2003-06-06 2008-02-05 Formfactor, Inc. Rhodium electroplated structures and methods of making same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6656369B2 (en) 2002-01-17 2003-12-02 International Business Machines Corporation Method for fabricating a scanning probe microscope probe
KR100736679B1 (en) 2006-08-09 2007-07-06 주식회사 유니테스트 Device and method of generating pattern for testing semiconductor
KR100796207B1 (en) 2007-02-12 2008-01-24 주식회사 유니테스트 Method for forming probe structure of probe card

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6482013B2 (en) * 1993-11-16 2002-11-19 Formfactor, Inc. Microelectronic spring contact element and electronic component having a plurality of spring contact elements
US5645684A (en) * 1994-03-07 1997-07-08 The Regents Of The University Of California Multilayer high vertical aspect ratio thin film structures
US5953622A (en) * 1996-11-23 1999-09-14 Hyundai Electronics Industries Co., Ltd. Method for fabricating semiconductor wafers
US6576301B1 (en) * 1999-04-30 2003-06-10 Advantest, Corp. Method of producing contact structure
US7326327B2 (en) * 2003-06-06 2008-02-05 Formfactor, Inc. Rhodium electroplated structures and methods of making same
US20050045481A1 (en) * 2003-09-01 2005-03-03 Yuuko Kawaguchi Method for manufacturing stamper, stamper and optical recording medium

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10115690B2 (en) * 2015-02-26 2018-10-30 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing micro pins and isolated conductive micro pin
US11101232B2 (en) 2015-02-26 2021-08-24 Taiwan Semiconductor Manufacturing Co., Ltd. Conductive micro pin
EP4151776A1 (en) * 2021-09-17 2023-03-22 FUJIFILM Corporation Electroforming master, method for producing electroforming master, and method for producing electroforming material

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