US20100193952A1 - Integrated circuit die containing particale-filled through-silicon metal vias with reduced thermal expansion - Google Patents
Integrated circuit die containing particale-filled through-silicon metal vias with reduced thermal expansion Download PDFInfo
- Publication number
- US20100193952A1 US20100193952A1 US12/386,238 US38623809A US2010193952A1 US 20100193952 A1 US20100193952 A1 US 20100193952A1 US 38623809 A US38623809 A US 38623809A US 2010193952 A1 US2010193952 A1 US 2010193952A1
- Authority
- US
- United States
- Prior art keywords
- matrix
- die
- semiconductor package
- forming
- bulk
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000000463 material Substances 0.000 claims abstract description 100
- 239000002245 particle Substances 0.000 claims abstract description 42
- 239000011159 matrix material Substances 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 31
- 239000002131 composite material Substances 0.000 claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims description 65
- 239000002184 metal Substances 0.000 claims description 65
- 239000000945 filler Substances 0.000 claims description 34
- 229910000679 solder Inorganic materials 0.000 claims description 20
- 238000009713 electroplating Methods 0.000 claims description 16
- 239000013590 bulk material Substances 0.000 claims description 15
- 239000010949 copper Substances 0.000 claims description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 10
- 230000005496 eutectics Effects 0.000 claims description 9
- 239000010931 gold Substances 0.000 claims description 9
- 229910001374 Invar Inorganic materials 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 229910000833 kovar Inorganic materials 0.000 claims description 4
- 238000005240 physical vapour deposition Methods 0.000 claims description 4
- 238000003860 storage Methods 0.000 claims description 4
- 229910052582 BN Inorganic materials 0.000 claims description 3
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- 239000003302 ferromagnetic material Substances 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 claims description 3
- 230000005484 gravity Effects 0.000 claims description 3
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 230000008020 evaporation Effects 0.000 claims description 2
- 238000001704 evaporation Methods 0.000 claims description 2
- 238000001912 gas jet deposition Methods 0.000 claims description 2
- 238000004544 sputter deposition Methods 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims 11
- 230000005291 magnetic effect Effects 0.000 claims 1
- 230000006855 networking Effects 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 101
- 229910052710 silicon Inorganic materials 0.000 description 101
- 239000010703 silicon Substances 0.000 description 101
- 239000010410 layer Substances 0.000 description 88
- 238000002161 passivation Methods 0.000 description 17
- 239000011229 interlayer Substances 0.000 description 14
- 239000000758 substrate Substances 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000005336 cracking Methods 0.000 description 4
- 230000032798 delamination Effects 0.000 description 4
- 239000011800 void material Substances 0.000 description 4
- 238000005459 micromachining Methods 0.000 description 3
- 239000000725 suspension Substances 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 238000005868 electrolysis reaction Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 239000012798 spherical particle Substances 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000005422 blasting Methods 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- WCCJDBZJUYKDBF-UHFFFAOYSA-N copper silicon Chemical compound [Si].[Cu] WCCJDBZJUYKDBF-UHFFFAOYSA-N 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000012772 electrical insulation material Substances 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/1141—Manufacturing methods by blanket deposition of the material of the bump connector in liquid form
- H01L2224/11424—Immersion coating, e.g. in a solder bath
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/1146—Plating
- H01L2224/11462—Electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H01L2224/13009—Bump connector integrally formed with a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13199—Material of the matrix
- H01L2224/132—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13201—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13216—Lead [Pb] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13199—Material of the matrix
- H01L2224/132—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13217—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/13224—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13199—Material of the matrix
- H01L2224/132—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13238—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13239—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13199—Material of the matrix
- H01L2224/132—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13238—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13244—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13199—Material of the matrix
- H01L2224/132—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13238—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13247—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13199—Material of the matrix
- H01L2224/132—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13263—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/13284—Tungsten [W] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13298—Fillers
- H01L2224/13299—Base material
- H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13363—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/13384—Tungsten [W] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13298—Fillers
- H01L2224/13299—Base material
- H01L2224/13386—Base material with a principal constituent of the material being a non metallic, non metalloid inorganic material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12033—Gunn diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Definitions
- the invention relates to the field of microelectronics and more particularly, but not exclusively, to stacked packages and electrically conductive through silicon vias.
- a typical through silicon via may simply be a void within a bulk silicon portion of a die filled with a bulk material of approximately uniform composition, for example an alloy of copper.
- a coefficient of thermal expansion may represent a change in unit volume of a bulk material for a unit change in temperature. If a volume of a first bulk material encloses a second volume of a second bulk material with different coefficient of thermal expansion from the first bulk material with zero stress at a given temperature, a change in temperature may cause a non-zero stress to develop at an interface of the different bulk materials. In some cases, under a sufficient change in temperature, or a sufficient number of temperature excursion cycles, a stress at an interface of the different bulk materials may exceed a certain critical stress and cause a permanent deformation or dislocation in one or the other or both bulk materials. Alternatively, performance of the integrated circuit device may degrade from an increased stress at an interface of different bulk materials, without either material undergoing a permanent deformation or dislocation.
- packages containing integrated circuits may undergo various processes, some of which may occur at an elevated temperature.
- a package containing integrated circuits may undergo, for example, a solder reflow process, after perhaps being at room temperature.
- various components within the package, including the integrated circuits and accompanying bulk silicon to which the integrated circuits may be coupled may approach, or even exceed a temperature at which a solder reflows, e.g., perhaps 230° C. for a representative Pb-free solder, contrasting with a normal storage temperature, for example, perhaps 25° C.
- a package and its components may undergo a significant temperature change, e.g. based on the present example, as much or greater than 205° C.
- integrated circuits such as processors generate heat that may cause various components within a package, including the integrated circuits and accompanying bulk silicon to which the integrated circuits may be coupled, to undergo temperature variations. While temperature excursions under normal operation may not be as extreme as those experienced in a manufacturing process, throughout a product's design life, a package and its components including the integrated circuits and accompanying bulk silicon to which the integrated circuits may be coupled may undergo a high number of temperature excursions resulting from normal operation.
- Copper has a bulk linear CTE of approximately 16.5 ppm/° C. in contrast to silicon, which has a bulk linear CTE of approximately 2.6 ppm/° C.
- a unit volume of copper expands considerably more than a unit volume of silicon. Because a typical through silicon via may simply be a void in a bulk silicon portion of an integrated circuit die filled with an alloy of copper and the CTE of each material is almost an order of magnitude different, a mechanical stress may be induced at a copper-silicon interface when the package undergoes a temperature excursion.
- FIG. 1( a ) represents a group of prior art through silicon vias, showing a portion of a bulk silicon die with integrated circuits 100 .
- Prior art through silicon vias 112 may be electrically coupled to metal pads 108 through an electrically conductive seed layer 114 .
- Between an electrically conductive seed layer 114 and a portion of the bulk silicon die 102 may be a passivation or electrical insulation layer 116 .
- Metal pads 108 and a portion of the bulk silicon die 102 may be separated by an interlayer dielectric (ILD) material 104 .
- ILD interlayer dielectric
- FIG. 1( b ) and FIG. 1( c ) represent a prior art through silicon via suffering stress induced, mechanical failures of delamination 120 and die cracking 118 , respectively.
- a prior art through silicon via may have a bulk CTE substantially similar in magnitude to the bulk CTE of the continuous metal phase and substantially different from the bulk CTE of silicon, leading to significant principal stresses under temperature excursions. The significant principal stresses in turn may cause mechanical failures of the integrated circuit such as delamination 120 or die cracking 118 . Further, significant principal stresses, without causing delamination 120 or die cracking 118 may cause degraded performance within an integrated circuit.
- via size may be reduced, spacing between adjacent vias may be increased, or vias may be positioned far from active circuitry.
- Each of these solution options may lead to increased die size, lower density circuits than may otherwise be realized or increased cost per die.
- FIG. 1 illustrates a representation of prior art through silicon vias made of a single phase bulk material ( FIG. 1( a )) leading to delamination ( FIG. 1( b )) and die cracking ( FIG. 1( c )).
- FIG. 2 illustrates one embodiment of a system including an electronic package assembly having particle-filled through silicon vias with reduced thermal expansion.
- FIG. 3 illustrates a graph of normalized material stress variation with normalized coefficient of thermal expansion for a given array of through silicon vias.
- FIG. 4 illustrates a graph of normalized material stress variation with via array pitch for vias filled with pure copper and for vias filled with a bulk material with 25% of the CTE of pure copper.
- FIG. 5 illustrates variation of CTE and variation of Electrical Resistivity with volume fraction of embedded particles for two different filler materials.
- FIG. 6 illustrates an embodiment of electrically conductive through silicon vias made of a bulk material, the bulk material consisting of a matrix metal forming a continuous phase and embedded particles forming a dispersed phase.
- FIG. 7 illustrates a portion of a silicon die prior to applying.
- FIG. 8 illustrates the portion of a silicon die of FIG. 7 with several areas of bulk silicon removed.
- FIG. 9 illustrates the portion of a silicon die of FIG. 8 with a first layer of material deposited on a surface of the bulk silicon and an underside of a metal pad.
- FIG. 10 illustrates the portion of a silicon die of FIG. 9 after exposing the metal pads through partial removal of the first layer of material deposited.
- FIG. 11 illustrates the portion of a silicon die of FIG. 10 with a second layer of material deposited over the exposed metal pads and first layer of material.
- FIG. 12 illustrates the portion of a silicon die of FIG. 11 with photoresist applied.
- FIG. 13 illustrates the portion of a silicon die of FIG. 12 immersed in an electrolysis bath with dispersed particles.
- FIG. 14 illustrates the portion of a silicon die of FIG. 13 with partially deposited through silicon vias with dispersed particles.
- FIG. 15 illustrates the portion of a silicon die of FIG. 14 with fully deposited through silicon vias with dispersed particles.
- FIG. 16 illustrates the portion of a silicon die of FIG. 15 with the electrolysis bath removed.
- FIG. 17 illustrates the portion of a silicon die of FIG. 16 with the photoresist removed.
- FIG. 18 illustrates the portion of a silicon die of FIG. 17 with the first and second layers of material removed in regions between the through silicon vias.
- FIG. 19 illustrates a method of manufacture of reduced CTE through silicon vias.
- FIG. 20 illustrates a table of possible materials used to form a composite via.
- the integrated circuit package 200 may contain a portion of a silicon die similar to the portion of a silicon die 600 , 700 , 800 , 900 , 1000 , 1100 , 1200 , 1300 , 1400 , 1500 , 1600 , 1700 , and 1800 depicted in FIG. 6-FIG . 18 , respectively.
- the integrated circuit package 200 may include a microprocessor.
- the integrated circuit package 200 may include an application specific IC (ASIC).
- ASIC application specific IC
- Integrated circuits found in chipsets (e.g., graphics, sound, and control chipsets) or memory may also be packaged in alternate embodiments.
- the system 90 may also include a main memory 202 , a graphics processor 204 , a mass storage device 206 , and an input/output module 208 coupled to each other by way of a bus 210 , as shown.
- the memory 202 include but are not limited to static random access memory (SRAM) and dynamic random access memory (DRAM).
- Examples of the mass storage device 206 include but are not limited to a hard disk drive, a flash drive, a compact disk drive (CD), a digital versatile disk drive (DVD), and so forth.
- Examples of the input/output modules 208 include but are not limited to a keyboard, cursor control devices, a display, a network interface, and so forth.
- bus 210 examples include but are not limited to a peripheral control interface (PCI) bus, and Industry Standard Architecture (ISA) bus, and so forth.
- the system 90 may be a wireless mobile phone, a personal digital assistant, a pocket PC, a tablet PC, a notebook PC, a desktop computer, a set-top box, an audio/video controller, a DVD player, a network router, a network switching device, or a server.
- PCI peripheral control interface
- ISA Industry Standard Architecture
- the system 90 may be a wireless mobile phone, a personal digital assistant, a pocket PC, a tablet PC, a notebook PC, a desktop computer, a set-top box, an audio/video controller, a DVD player, a network router, a network switching device, or a server.
- FIG. 3 illustrates a graph of results from a finite element simulation of a first principal stress with a normalized bulk CTE (reference CTE is that of copper) of a material used to fill a 20 micron via in an array of vias with a 500 micron pitch.
- a normalized CTE of 0.16 represents silicon.
- the data of FIG. 3 shows the first principal stress may reduce as the via material's bulk CTE approaches that of silicon.
- FIG. 4 illustrates a graph of further finite element simulation showing a variation of a first principal stress with via pitch for a 20 micron pure copper via and a 20-micron via made of a material with a CTE 25% that of copper.
- the data of FIG. 4 shows the first principal stress may decrease significantly at small pitch if a bulk material with reduced CTE forms a via. Further, a reduced CTE via may result in a lower first principal stress, at smaller pitch, than a conventional CTE via at large pitch.
- a dispersed phase of filler particles may alter one or more bulk material properties of a through silicon via.
- a resulting electrical resistivity of a composite of a metal matrix forming a continuous phase and an embedded spherical filler forming a dispersed phase may be approximated by the expression
- k composite 2 ⁇ k 1 + k 2 + p ⁇ ( k 1 - k 2 ) 2 ⁇ k 1 + k 2 - 2 ⁇ p ⁇ ( k 1 - k 2 ) ⁇ k 2 ,
- k composite represents the resulting bulk electrical resistivity
- k 1 represents the bulk electrical resistivity of the spherical filler
- k 2 represents the bulk electrical resistivity of the matrix metal
- p represents the volume fraction of spherical filler to bulk composite volume.
- FIG. 5 illustrates a graph showing an increased volume fraction of a spherical filler with CTE less than a matrix metal may monotonically decrease the bulk CTE of a resulting composite of matrix metal and embedded spherical filler. Further, FIG. 5 illustrates that increased volume fraction of a spherical filler with electrical resistivity greater than a matrix metal may monotonically increase the bulk resistivity of a resulting composite of matrix metal and embedded spherical filler. Still further, the data of FIG. 5 implies a choice of filler material may comprehend a tradeoff of reduced CTE with increased electrical resistivity. However, filler particle volume fractions may range up to more than 80%.
- filler particles comprising the dispersed phase may be any one, or combination, of silica, alumina, boron nitride, tungsten, Invar, Super Invar, Kovar or other material with CTE less than the surrounding bulk die material through which the via passes, e.g., silicon.
- filler particles made of a ferromagnetic material e.g., Invar, Super Invar and Kovar, may be used in a magnetic-field assisted electroplating process.
- An embodiment may use one of many metals for the matrix.
- Exemplary matrix materials include copper (Cu), gold (Au), aluminum (Al), tungsten (W), silver (Ag) and both eutectic and non-eutectic solders.
- Exemplary eutectic solders include tin-lead (Pb/Sn) and gold-tin (Au/Sn) solders.
- FIG. 6 illustrates one embodiment of a portion of a die with integrated circuits 600 .
- through silicon vias 612 may be electrically coupled to metal pads 608 through an electrically conductive seed layer 614 .
- the through silicon vias 612 may be a composite wherein the bulk CTE of the vias 612 is less than the bulk CTE of the matrix metal.
- a reduced CTE through silicon via 612 may comprise a matrix metal forming a continuous phase and embedded particles with a CTE less than the matrix metal, the embedded particles forming a dispersed phase and the reduced CTE through silicon via 612 having a bulk CTE less than the bulk CTE of the matrix metal.
- ILD interlayer dielectric
- FIG. 7-FIG . 18 illustrate articles undergoing a method to manufacture a via through a die containing integrated circuits.
- FIG. 7 illustrates a substrate 700 to which a method of manufacture may be applied.
- Metal pads 608 and a portion of a die 602 may be separated by an interlayer dielectric (ILD) material 604 .
- the die 602 may be silicon.
- a layer of ILD 604 coupled to a portion of the bulk silicon die 602 between metal pads 608 may underlie a layer of passivation material 610 or a protection layer 606 .
- FIG. 8 illustrates the substrate of FIG. 7 wherein a portion of a die with integrated circuits 800 has material removed in a vicinity near a metal pad 608 .
- the die 602 may be silicon. Removal of die material may be by photolithography followed by a dry or wet etching process. Alternatively, removal may be by a micromachining technique. In one embodiment, a micromachining technique may be blasting, drilling, or another micromachining technique, or a combination thereof. Further, a portion of the ILD 504 in a vicinity near a metal pad may similarly be removed. As in FIG. 7 , metal pads 608 and a portion of the bulk silicon die 602 may be separated by an interlayer dielectric (ILD) material 604 . A layer of ILD 604 coupled to a portion of the bulk silicon die 602 between metal pads 608 may underlie a layer of passivation material 610 or a protection layer 606 .
- ILD interlayer dielectric
- FIG. 9 illustrates the substrate of FIG. 8 during manufacture showing a portion of a die with integrated circuits 900 .
- a layer of material 616 may deposited on the surface of the die 602 .
- the die 602 may be silicon.
- the layer of material 616 may be a passivation layer.
- the layer of material 616 may be an electrical insulation material.
- metal pads 608 and a portion of the bulk silicon die 602 may be separated by an interlayer dielectric (ILD) material 604 .
- ILD interlayer dielectric
- a layer of ILD 604 coupled to a portion of the die 602 between metal pads 608 may underlie a layer of passivation material 610 or a protection layer 606 .
- FIG. 10 illustrates the substrate of FIG. 9 undergoing manufacture, showing a portion of a die with integrated circuits 1000 .
- a layer of material 616 proximate to a metal pad 608 may be removed, re-exposing a previously exposed metal pad 608 .
- the die 602 may be silicon and the metal pads 608 and a portion of the die 602 may be separated by an interlayer dielectric (ILD) material 604 .
- ILD 604 coupled to a portion of the bulk silicon die 602 between metal pads 608 may underlie a layer of passivation material 610 or a protection layer 606 .
- FIG. 11 illustrates a portion of the substrate of FIG. 10 with integrated circuits 1100 with a second layer of material 614 deposited on the surface of the previously deposited layer of material 616 .
- the second layer of material 614 may be a barrier layer.
- the layer of material 614 may be a seed layer to facilitate a later electroplating process.
- metal pads 608 and a portion of the bulk silicon die 602 may be separated by an interlayer dielectric (ILD) material 604 .
- ILD interlayer dielectric
- a layer of ILD 604 coupled to a portion of the bulk silicon die 602 between metal pads 608 may underlie a layer of passivation material 610 or a protection layer 606 .
- FIG. 12 illustrates the substrate of FIG. 11 with integrated circuits 1200 and a pattern of photoresist 1202 deposited on the surface of the previously deposited layer of material 614 .
- a layer of material 616 may overlie the bulk silicon die 502 and underlie a second layer of material 614 .
- Metal pads 608 and a portion of the bulk silicon die 602 may be separated by an interlayer dielectric (ILD) material 604 .
- ILD interlayer dielectric
- a layer of ILD 604 coupled to a portion of the bulk silicon die 602 between metal pads 608 may underlie a layer of passivation material 610 or a protection layer 606 .
- FIG. 13 illustrates the substrate of FIG. 12 showing a portion of a die with integrated circuits immersed in an electroplating bath 1300 .
- an electroplating bath 1302 may contain in solution or suspension particles 1304 of reduced CTE relative to a deposited matrix metal.
- a layer of material 616 may overlie the bulk silicon die 602 and underlie a second layer of material 614 .
- Metal pads 608 and a portion of the bulk silicon die 602 may be separated by an interlayer dielectric (ILD) material 604 .
- ILD interlayer dielectric
- a layer of ILD 604 coupled to a portion of the bulk silicon die 602 between metal pads 608 may underlie a layer of passivation material 610 or a protection layer 606 and a pattern of photoresist 1202 may be further present.
- FIG. 14 illustrates the substrate of FIG. 13 with integrated circuits immersed in an electroplating bath 1400 .
- a portion of a via 1402 may be deposited within a void previously generated in the die 602 .
- the via 1402 may be through silicon.
- the die 602 may be silicon.
- An electroplating bath 1302 may contain in solution or suspension particles 1304 of reduced CTE relative to a deposited matrix metal. During the electroplating process, filler particles 1304 may be co-deposited in a portion of the reduced CTE through silicon via 1402 . Further, to aid co-deposition of filler particles 1304 , a driving potential may be applied.
- the driving force may be gravity, or some other driving potential made to act on the electroplating bath 1302 or filler particles 1304 .
- a layer of material 616 may overlie the bulk silicon die 602 and underlie a second layer of material 614 .
- Metal pads 608 and a portion of the bulk silicon die 602 may be separated by an interlayer dielectric (ILD) material 604 .
- ILD interlayer dielectric
- a layer of ILD 604 coupled to a portion of the bulk silicon die 602 between metal pads 608 may underlie a layer of passivation material 610 or a protection layer 606 and a pattern of photoresist 1202 may be further present.
- FIG. 15 illustrates a portion of the substrate of FIG. 16 with integrated circuits immersed in an electroplating bath 1500 .
- a reduced via 612 may be fully deposited, the via being a composite comprising a metal matrix with greater CTE than the die 602 , the metal matrix forming a continuous phase, and embedded filler particles with a CTE less than the CTE of the metal matrix, the filler particles forming a dispersed phase, the composite exhibiting a bulk CTE less than the bulk CTE of the matrix metal.
- the die 602 is substantially silicon.
- an electroplating bath 1302 may contain in solution or suspension particles 1304 of reduced CTE relative to a deposited matrix metal.
- filler particles 1304 may be co-deposited in a portion of the reduced CTE through silicon via 1402 . Further, to aid co-deposition of filler particles 1304 , a driving potential may be applied. The driving force may be gravity, or some other driving potential made to act on the electroplating bath 1302 or filler particles 1304 . As in previous figures, a layer of material 616 may overlie the bulk silicon die 602 and underlie a second layer of material 614 . Metal pads 608 and a portion of the bulk silicon die 602 may be separated by an interlayer dielectric (ILD) material 604 . A layer of ILD 604 coupled to a portion of the bulk silicon die 602 between metal pads 608 may underlie a layer of passivation material 610 or a protection layer 606 and a pattern of photoresist 1202 may be further present.
- ILD interlayer dielectric
- FIG. 16 illustrates the substrate of FIG. 15 , a portion of die with integrated circuits 1600 with the electroplating bath removed.
- the die 602 may be silicon, a layer of material 616 may overlie the bulk silicon die 602 and underlie a second layer of material 614 .
- Metal pads 608 and a portion of the bulk silicon die 602 may be separated by an interlayer dielectric (ILD) material 604 .
- ILD interlayer dielectric
- a layer of ILD 604 coupled to a portion of the bulk silicon die 602 between metal pads 608 may underlie a layer of passivation material 610 or a protection layer 606 and a pattern of photoresist 1202 may be further present.
- FIG. 17 illustrates the substrate of FIG. 16 , showing a portion of die with integrated circuits 1700 , the pattern of photoresist removed.
- a layer of material 616 may overlie the bulk silicon die 602 and underlie a second layer of material 614 .
- Metal pads 608 and a portion of the bulk silicon die 602 may be separated by an interlayer dielectric (ILD) material 604 .
- ILD interlayer dielectric
- a layer of ILD 604 coupled to a portion of the bulk silicon die 602 between metal pads 608 may underlie a layer of passivation material 610 or a protection layer 606 .
- FIG. 18 illustrates the substrate of FIG. 17 showing a portion of bulk silicon die with integrated circuits 1800 and a first layer 614 and second layer 616 of material etched among the newly deposited vias 612 , exposing a portion of die 602 .
- the die 602 may be silicon.
- a layer of material 616 may overlie the bulk silicon die 602 and underlie a second layer of material 614 .
- Metal pads 608 and a portion of the bulk silicon die 602 may be separated by an interlayer dielectric (ILD) material 604 .
- ILD interlayer dielectric
- a layer of ILD 604 coupled to a portion of the bulk silicon die 602 between metal pads 608 may underlie a layer of passivation material 610 or a protection layer 606 .
- FIG. 19 illustrates a method of forming through hole vias comprising a matrix and dispersed filler particles.
- material may be removed 1902 from a backside of a bulk silicon wafer having a primary side and a backside
- a metal pad integrated on a primary side of the bulk silicon wafer may be exposed 1904 .
- a first layer of material may be deposited on an exposed metal pad and an interior surface of the void within the bulk silicon wafer created by material removal 1906 .
- the layer of material may be etched to expose a region of the metal pad 1908 .
- a layer of electrically conductive material may be deposited over the exposed region of the metal pad and the previously deposited material 1910 .
- a pattern of photoresist may be deposited over the layer of electrically conductive material 1912 .
- An electroplating technique may be applied to deposit an electrically conductive through silicon via made of a two phase bulk material 1914 , a continuous phase being a matrix metal and a dispersed phase being embedded filler particles.
- the pattern of photoresist may be removed 1916 and the two layers of material deposited on the backside of the bulk silicon wafer may be etched 1918 .
- FIG. 20 illustrates a partial list of materials, and several associated material properties, that may be used in one embodiment of a composite via.
- an alternative embodiment may exist where filler particles are packed into an open via hole within a die and a chemical vapor deposition (CVD) or physical vapor deposition (PVD) process (e.g., sputtering, evaporation, jet vapor deposition) may be used to fill in any volume in the through hole unfilled by packed particles.
- CVD chemical vapor deposition
- PVD physical vapor deposition
- solder balls containing filler particles may reflow into an open via hole within a die.
- Still another embodiment may reflow solder balls containing filler particles under vacuum to avoid air filled voids within a finished via.
Abstract
A method, apparatus and system with an electrically conductive through hole via of a composite material with a matrix forming a continuous phase and embedded particles, with a different material property than the matrix, forming a dispersed phase, the resulting composite material having a different material property than the matrix.
Description
- The invention relates to the field of microelectronics and more particularly, but not exclusively, to stacked packages and electrically conductive through silicon vias.
- The evolution of integrated circuit designs has resulted in higher operating frequency, increased numbers of transistors, and physically smaller devices. This continuing trend has generated ever-increasing area densities of integrated circuits. To further increase possible densities of integrated circuits, it may be desirable in some instances to electrically couple an active circuit layer on a die to another active circuit layer on the same, or a different, die by means of an electrically conductive through silicon via. A typical through silicon via may simply be a void within a bulk silicon portion of a die filled with a bulk material of approximately uniform composition, for example an alloy of copper.
- Many materials may undergo a physical expansion or contraction resulting from a change in temperature. A coefficient of thermal expansion (CTE) may represent a change in unit volume of a bulk material for a unit change in temperature. If a volume of a first bulk material encloses a second volume of a second bulk material with different coefficient of thermal expansion from the first bulk material with zero stress at a given temperature, a change in temperature may cause a non-zero stress to develop at an interface of the different bulk materials. In some cases, under a sufficient change in temperature, or a sufficient number of temperature excursion cycles, a stress at an interface of the different bulk materials may exceed a certain critical stress and cause a permanent deformation or dislocation in one or the other or both bulk materials. Alternatively, performance of the integrated circuit device may degrade from an increased stress at an interface of different bulk materials, without either material undergoing a permanent deformation or dislocation.
- During a normal manufacturing cycle, packages containing integrated circuits may undergo various processes, some of which may occur at an elevated temperature. For example, a package containing integrated circuits may undergo, for example, a solder reflow process, after perhaps being at room temperature. In a solder reflow process, various components within the package, including the integrated circuits and accompanying bulk silicon to which the integrated circuits may be coupled may approach, or even exceed a temperature at which a solder reflows, e.g., perhaps 230° C. for a representative Pb-free solder, contrasting with a normal storage temperature, for example, perhaps 25° C. In the present example, a package and its components may undergo a significant temperature change, e.g. based on the present example, as much or greater than 205° C.
- Further, under normal operation, integrated circuits such as processors generate heat that may cause various components within a package, including the integrated circuits and accompanying bulk silicon to which the integrated circuits may be coupled, to undergo temperature variations. While temperature excursions under normal operation may not be as extreme as those experienced in a manufacturing process, throughout a product's design life, a package and its components including the integrated circuits and accompanying bulk silicon to which the integrated circuits may be coupled may undergo a high number of temperature excursions resulting from normal operation.
- Copper has a bulk linear CTE of approximately 16.5 ppm/° C. in contrast to silicon, which has a bulk linear CTE of approximately 2.6 ppm/° C. Thus, a unit volume of copper expands considerably more than a unit volume of silicon. Because a typical through silicon via may simply be a void in a bulk silicon portion of an integrated circuit die filled with an alloy of copper and the CTE of each material is almost an order of magnitude different, a mechanical stress may be induced at a copper-silicon interface when the package undergoes a temperature excursion.
- For example,
FIG. 1( a) represents a group of prior art through silicon vias, showing a portion of a bulk silicon die with integratedcircuits 100. Prior art throughsilicon vias 112 may be electrically coupled tometal pads 108 through an electricallyconductive seed layer 114. Between an electricallyconductive seed layer 114 and a portion of thebulk silicon die 102 may be a passivation orelectrical insulation layer 116.Metal pads 108 and a portion of the bulk silicon die 102 may be separated by an interlayer dielectric (ILD)material 104. A layer of ILD 104 coupled to a portion of the bulk silicon die 102 betweenmetal pads 108 may underlie a layer ofpassivation material 110 or aprotection layer 106.FIG. 1( b) andFIG. 1( c) represent a prior art through silicon via suffering stress induced, mechanical failures ofdelamination 120 and diecracking 118, respectively. A prior art through silicon via may have a bulk CTE substantially similar in magnitude to the bulk CTE of the continuous metal phase and substantially different from the bulk CTE of silicon, leading to significant principal stresses under temperature excursions. The significant principal stresses in turn may cause mechanical failures of the integrated circuit such asdelamination 120 or diecracking 118. Further, significant principal stresses, without causingdelamination 120 or die cracking 118 may cause degraded performance within an integrated circuit. - To maintain a mechanical stress resulting from a CTE mismatch below a critical stress of either bulk material for a given temperature excursion, via size may be reduced, spacing between adjacent vias may be increased, or vias may be positioned far from active circuitry. Each of these solution options may lead to increased die size, lower density circuits than may otherwise be realized or increased cost per die.
-
FIG. 1 illustrates a representation of prior art through silicon vias made of a single phase bulk material (FIG. 1( a)) leading to delamination (FIG. 1( b)) and die cracking (FIG. 1( c)). -
FIG. 2 illustrates one embodiment of a system including an electronic package assembly having particle-filled through silicon vias with reduced thermal expansion. -
FIG. 3 illustrates a graph of normalized material stress variation with normalized coefficient of thermal expansion for a given array of through silicon vias. -
FIG. 4 illustrates a graph of normalized material stress variation with via array pitch for vias filled with pure copper and for vias filled with a bulk material with 25% of the CTE of pure copper. -
FIG. 5 illustrates variation of CTE and variation of Electrical Resistivity with volume fraction of embedded particles for two different filler materials. -
FIG. 6 illustrates an embodiment of electrically conductive through silicon vias made of a bulk material, the bulk material consisting of a matrix metal forming a continuous phase and embedded particles forming a dispersed phase. -
FIG. 7 illustrates a portion of a silicon die prior to applying. -
FIG. 8 illustrates the portion of a silicon die ofFIG. 7 with several areas of bulk silicon removed. -
FIG. 9 illustrates the portion of a silicon die ofFIG. 8 with a first layer of material deposited on a surface of the bulk silicon and an underside of a metal pad. -
FIG. 10 illustrates the portion of a silicon die ofFIG. 9 after exposing the metal pads through partial removal of the first layer of material deposited. -
FIG. 11 illustrates the portion of a silicon die ofFIG. 10 with a second layer of material deposited over the exposed metal pads and first layer of material. -
FIG. 12 illustrates the portion of a silicon die ofFIG. 11 with photoresist applied. -
FIG. 13 illustrates the portion of a silicon die ofFIG. 12 immersed in an electrolysis bath with dispersed particles. -
FIG. 14 illustrates the portion of a silicon die ofFIG. 13 with partially deposited through silicon vias with dispersed particles. -
FIG. 15 illustrates the portion of a silicon die ofFIG. 14 with fully deposited through silicon vias with dispersed particles. -
FIG. 16 illustrates the portion of a silicon die ofFIG. 15 with the electrolysis bath removed. -
FIG. 17 illustrates the portion of a silicon die ofFIG. 16 with the photoresist removed. -
FIG. 18 illustrates the portion of a silicon die ofFIG. 17 with the first and second layers of material removed in regions between the through silicon vias. -
FIG. 19 illustrates a method of manufacture of reduced CTE through silicon vias. -
FIG. 20 illustrates a table of possible materials used to form a composite via. - Herein disclosed are methods, apparatus, and systems for providing a through silicon via with a desirable bulk coefficient of thermal expansion. In the following detailed description, reference is made to the accompanying drawings which form a part hereof wherein like numerals designate like parts throughout, and in which is shown by way of illustration specific embodiments which may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the claims presented herein. It should also be noted that directions and references (e.g., up, down, top, bottom, primary side, backside, etc.) may be used to facilitate the discussion of the drawings and are not intended to restrict the breadth of application of the claims presented. Therefore, the following detailed description is not to be taken in a limiting sense and the scope of possible embodiments is defined only by the appended claims and their equivalents.
- Referring to
FIG. 2 , there is illustrated one of many possible systems in which embodiments presented may be used. Theintegrated circuit package 200 may contain a portion of a silicon die similar to the portion of asilicon die FIG. 6-FIG . 18, respectively. In one embodiment, theintegrated circuit package 200 may include a microprocessor. In an alternate embodiment, theintegrated circuit package 200 may include an application specific IC (ASIC). Integrated circuits found in chipsets (e.g., graphics, sound, and control chipsets) or memory may also be packaged in alternate embodiments. - For the embodiment depicted by
FIG. 2 , thesystem 90 may also include amain memory 202, agraphics processor 204, amass storage device 206, and an input/output module 208 coupled to each other by way of abus 210, as shown. Examples of thememory 202 include but are not limited to static random access memory (SRAM) and dynamic random access memory (DRAM). Examples of themass storage device 206 include but are not limited to a hard disk drive, a flash drive, a compact disk drive (CD), a digital versatile disk drive (DVD), and so forth. Examples of the input/output modules 208 include but are not limited to a keyboard, cursor control devices, a display, a network interface, and so forth. Examples of thebus 210 include but are not limited to a peripheral control interface (PCI) bus, and Industry Standard Architecture (ISA) bus, and so forth. In various embodiments, thesystem 90 may be a wireless mobile phone, a personal digital assistant, a pocket PC, a tablet PC, a notebook PC, a desktop computer, a set-top box, an audio/video controller, a DVD player, a network router, a network switching device, or a server. -
FIG. 3 illustrates a graph of results from a finite element simulation of a first principal stress with a normalized bulk CTE (reference CTE is that of copper) of a material used to fill a 20 micron via in an array of vias with a 500 micron pitch. A normalized CTE of 0.16 represents silicon. The data ofFIG. 3 shows the first principal stress may reduce as the via material's bulk CTE approaches that of silicon. -
FIG. 4 illustrates a graph of further finite element simulation showing a variation of a first principal stress with via pitch for a 20 micron pure copper via and a 20-micron via made of a material with a CTE 25% that of copper. The data ofFIG. 4 shows the first principal stress may decrease significantly at small pitch if a bulk material with reduced CTE forms a via. Further, a reduced CTE via may result in a lower first principal stress, at smaller pitch, than a conventional CTE via at large pitch. - A dispersed phase of filler particles may alter one or more bulk material properties of a through silicon via. For example, a resulting electrical resistivity of a composite of a metal matrix forming a continuous phase and an embedded spherical filler forming a dispersed phase may be approximated by the expression,
-
- where kcomposite represents the resulting bulk electrical resistivity, k1 represents the bulk electrical resistivity of the spherical filler and k2 represents the bulk electrical resistivity of the matrix metal and p represents the volume fraction of spherical filler to bulk composite volume.
- Further, a resulting CTE of a composite of a metal matrix forming a continuous phase and an embedded spherical filler forming a dispersed phase may be approximated by the expression, CTEcomposite=p·CTE1+(1−p)CTE2, where CTE composite represents the resulting bulk CTE, CTE1 represents the bulk CTE of the spherical filler and CTE2 represents the bulk CTE of the matrix metal and p again represents the volume fraction of spherical filler to bulk composite volume.
-
FIG. 5 illustrates a graph showing an increased volume fraction of a spherical filler with CTE less than a matrix metal may monotonically decrease the bulk CTE of a resulting composite of matrix metal and embedded spherical filler. Further,FIG. 5 illustrates that increased volume fraction of a spherical filler with electrical resistivity greater than a matrix metal may monotonically increase the bulk resistivity of a resulting composite of matrix metal and embedded spherical filler. Still further, the data ofFIG. 5 implies a choice of filler material may comprehend a tradeoff of reduced CTE with increased electrical resistivity. However, filler particle volume fractions may range up to more than 80%. - Although spherical particles are modeled for simplicity of calculation, spherical particles reduced to practice may be of arbitary shape. Further, filler particles comprising the dispersed phase may be any one, or combination, of silica, alumina, boron nitride, tungsten, Invar, Super Invar, Kovar or other material with CTE less than the surrounding bulk die material through which the via passes, e.g., silicon. Still further, filler particles made of a ferromagnetic material, e.g., Invar, Super Invar and Kovar, may be used in a magnetic-field assisted electroplating process.
- An embodiment may use one of many metals for the matrix. Exemplary matrix materials include copper (Cu), gold (Au), aluminum (Al), tungsten (W), silver (Ag) and both eutectic and non-eutectic solders. Exemplary eutectic solders include tin-lead (Pb/Sn) and gold-tin (Au/Sn) solders.
-
FIG. 6 illustrates one embodiment of a portion of a die withintegrated circuits 600. In one embodiment, throughsilicon vias 612 may be electrically coupled tometal pads 608 through an electricallyconductive seed layer 614. In a further embodiment, the throughsilicon vias 612 may be a composite wherein the bulk CTE of thevias 612 is less than the bulk CTE of the matrix metal. In still a further embodiment, a reduced CTE through silicon via 612 may comprise a matrix metal forming a continuous phase and embedded particles with a CTE less than the matrix metal, the embedded particles forming a dispersed phase and the reduced CTE through silicon via 612 having a bulk CTE less than the bulk CTE of the matrix metal. Between an electricallyconductive seed layer 614 and a portion of the bulk silicon die 602 may be a passivation orelectrical insulation layer 616.Metal pads 608 and a portion of the bulk silicon die 602 may be separated by an interlayer dielectric (ILD)material 604. A layer ofILD 604 coupled to a portion of the bulk silicon die 602 betweenmetal pads 608 may underlie a layer ofpassivation material 610 or aprotection layer 606. -
FIG. 7-FIG . 18 illustrate articles undergoing a method to manufacture a via through a die containing integrated circuits. -
FIG. 7 illustrates asubstrate 700 to which a method of manufacture may be applied.Metal pads 608 and a portion of adie 602 may be separated by an interlayer dielectric (ILD)material 604. In one embodiment, thedie 602 may be silicon. In still a further embodiment, a layer ofILD 604 coupled to a portion of the bulk silicon die 602 betweenmetal pads 608 may underlie a layer ofpassivation material 610 or aprotection layer 606. -
FIG. 8 illustrates the substrate ofFIG. 7 wherein a portion of a die withintegrated circuits 800 has material removed in a vicinity near ametal pad 608. In one embodiment, thedie 602 may be silicon. Removal of die material may be by photolithography followed by a dry or wet etching process. Alternatively, removal may be by a micromachining technique. In one embodiment, a micromachining technique may be blasting, drilling, or another micromachining technique, or a combination thereof. Further, a portion of the ILD 504 in a vicinity near a metal pad may similarly be removed. As inFIG. 7 ,metal pads 608 and a portion of the bulk silicon die 602 may be separated by an interlayer dielectric (ILD)material 604. A layer ofILD 604 coupled to a portion of the bulk silicon die 602 betweenmetal pads 608 may underlie a layer ofpassivation material 610 or aprotection layer 606. -
FIG. 9 illustrates the substrate ofFIG. 8 during manufacture showing a portion of a die withintegrated circuits 900. InFIG. 9 , a layer ofmaterial 616 may deposited on the surface of thedie 602. In one embodiment, thedie 602 may be silicon. The layer ofmaterial 616 may be a passivation layer. Alternatively, the layer ofmaterial 616 may be an electrical insulation material. As in previous figures,metal pads 608 and a portion of the bulk silicon die 602 may be separated by an interlayer dielectric (ILD)material 604. A layer ofILD 604 coupled to a portion of thedie 602 betweenmetal pads 608 may underlie a layer ofpassivation material 610 or aprotection layer 606. -
FIG. 10 illustrates the substrate ofFIG. 9 undergoing manufacture, showing a portion of a die withintegrated circuits 1000. InFIG. 10 , a layer ofmaterial 616 proximate to ametal pad 608 may be removed, re-exposing a previously exposedmetal pad 608. As in previous figures, thedie 602 may be silicon and themetal pads 608 and a portion of thedie 602 may be separated by an interlayer dielectric (ILD)material 604. A layer ofILD 604 coupled to a portion of the bulk silicon die 602 betweenmetal pads 608 may underlie a layer ofpassivation material 610 or aprotection layer 606. -
FIG. 11 illustrates a portion of the substrate ofFIG. 10 withintegrated circuits 1100 with a second layer ofmaterial 614 deposited on the surface of the previously deposited layer ofmaterial 616. The second layer ofmaterial 614 may be a barrier layer. Alternatively, the layer ofmaterial 614 may be a seed layer to facilitate a later electroplating process. As in previous figures,metal pads 608 and a portion of the bulk silicon die 602 may be separated by an interlayer dielectric (ILD)material 604. A layer ofILD 604 coupled to a portion of the bulk silicon die 602 betweenmetal pads 608 may underlie a layer ofpassivation material 610 or aprotection layer 606. -
FIG. 12 illustrates the substrate ofFIG. 11 withintegrated circuits 1200 and a pattern ofphotoresist 1202 deposited on the surface of the previously deposited layer ofmaterial 614. As in previous figures, a layer ofmaterial 616 may overlie the bulk silicon die 502 and underlie a second layer ofmaterial 614.Metal pads 608 and a portion of the bulk silicon die 602 may be separated by an interlayer dielectric (ILD)material 604. A layer ofILD 604 coupled to a portion of the bulk silicon die 602 betweenmetal pads 608 may underlie a layer ofpassivation material 610 or aprotection layer 606. -
FIG. 13 illustrates the substrate ofFIG. 12 showing a portion of a die with integrated circuits immersed in anelectroplating bath 1300. InFIG. 13 , anelectroplating bath 1302 may contain in solution orsuspension particles 1304 of reduced CTE relative to a deposited matrix metal. As in previous figures, a layer ofmaterial 616 may overlie the bulk silicon die 602 and underlie a second layer ofmaterial 614.Metal pads 608 and a portion of the bulk silicon die 602 may be separated by an interlayer dielectric (ILD)material 604. A layer ofILD 604 coupled to a portion of the bulk silicon die 602 betweenmetal pads 608 may underlie a layer ofpassivation material 610 or aprotection layer 606 and a pattern ofphotoresist 1202 may be further present. -
FIG. 14 illustrates the substrate ofFIG. 13 with integrated circuits immersed in anelectroplating bath 1400. InFIG. 14 , a portion of a via 1402 may be deposited within a void previously generated in thedie 602. In one embodiment, the via 1402 may be through silicon. In one embodiment, thedie 602 may be silicon. Anelectroplating bath 1302 may contain in solution orsuspension particles 1304 of reduced CTE relative to a deposited matrix metal. During the electroplating process,filler particles 1304 may be co-deposited in a portion of the reduced CTE through silicon via 1402. Further, to aid co-deposition offiller particles 1304, a driving potential may be applied. The driving force may be gravity, or some other driving potential made to act on theelectroplating bath 1302 orfiller particles 1304. As in previous figures, a layer ofmaterial 616 may overlie the bulk silicon die 602 and underlie a second layer ofmaterial 614.Metal pads 608 and a portion of the bulk silicon die 602 may be separated by an interlayer dielectric (ILD)material 604. A layer ofILD 604 coupled to a portion of the bulk silicon die 602 betweenmetal pads 608 may underlie a layer ofpassivation material 610 or aprotection layer 606 and a pattern ofphotoresist 1202 may be further present. -
FIG. 15 illustrates a portion of the substrate ofFIG. 16 with integrated circuits immersed in anelectroplating bath 1500. InFIG. 14 , a reduced via 612 may be fully deposited, the via being a composite comprising a metal matrix with greater CTE than thedie 602, the metal matrix forming a continuous phase, and embedded filler particles with a CTE less than the CTE of the metal matrix, the filler particles forming a dispersed phase, the composite exhibiting a bulk CTE less than the bulk CTE of the matrix metal. In one embodiment, thedie 602 is substantially silicon. As in previous figures, anelectroplating bath 1302 may contain in solution orsuspension particles 1304 of reduced CTE relative to a deposited matrix metal. During the electroplating process,filler particles 1304 may be co-deposited in a portion of the reduced CTE through silicon via 1402. Further, to aid co-deposition offiller particles 1304, a driving potential may be applied. The driving force may be gravity, or some other driving potential made to act on theelectroplating bath 1302 orfiller particles 1304. As in previous figures, a layer ofmaterial 616 may overlie the bulk silicon die 602 and underlie a second layer ofmaterial 614.Metal pads 608 and a portion of the bulk silicon die 602 may be separated by an interlayer dielectric (ILD)material 604. A layer ofILD 604 coupled to a portion of the bulk silicon die 602 betweenmetal pads 608 may underlie a layer ofpassivation material 610 or aprotection layer 606 and a pattern ofphotoresist 1202 may be further present. -
FIG. 16 illustrates the substrate ofFIG. 15 , a portion of die withintegrated circuits 1600 with the electroplating bath removed. As in previous figures, thedie 602 may be silicon, a layer ofmaterial 616 may overlie the bulk silicon die 602 and underlie a second layer ofmaterial 614.Metal pads 608 and a portion of the bulk silicon die 602 may be separated by an interlayer dielectric (ILD)material 604. A layer ofILD 604 coupled to a portion of the bulk silicon die 602 betweenmetal pads 608 may underlie a layer ofpassivation material 610 or aprotection layer 606 and a pattern ofphotoresist 1202 may be further present. -
FIG. 17 illustrates the substrate ofFIG. 16 , showing a portion of die withintegrated circuits 1700, the pattern of photoresist removed. As in previous figures, a layer ofmaterial 616 may overlie the bulk silicon die 602 and underlie a second layer ofmaterial 614.Metal pads 608 and a portion of the bulk silicon die 602 may be separated by an interlayer dielectric (ILD)material 604. A layer ofILD 604 coupled to a portion of the bulk silicon die 602 betweenmetal pads 608 may underlie a layer ofpassivation material 610 or aprotection layer 606. -
FIG. 18 illustrates the substrate ofFIG. 17 showing a portion of bulk silicon die withintegrated circuits 1800 and afirst layer 614 andsecond layer 616 of material etched among the newly depositedvias 612, exposing a portion ofdie 602. Thedie 602 may be silicon. As in previous figures, a layer ofmaterial 616 may overlie the bulk silicon die 602 and underlie a second layer ofmaterial 614.Metal pads 608 and a portion of the bulk silicon die 602 may be separated by an interlayer dielectric (ILD)material 604. A layer ofILD 604 coupled to a portion of the bulk silicon die 602 betweenmetal pads 608 may underlie a layer ofpassivation material 610 or aprotection layer 606. -
FIG. 19 illustrates a method of forming through hole vias comprising a matrix and dispersed filler particles. In the method illustrated inFIG. 19 , material may be removed 1902 from a backside of a bulk silicon wafer having a primary side and a backside A metal pad integrated on a primary side of the bulk silicon wafer may be exposed 1904. A first layer of material may be deposited on an exposed metal pad and an interior surface of the void within the bulk silicon wafer created bymaterial removal 1906. The layer of material may be etched to expose a region of themetal pad 1908. A layer of electrically conductive material may be deposited over the exposed region of the metal pad and the previously depositedmaterial 1910. A pattern of photoresist may be deposited over the layer of electricallyconductive material 1912. An electroplating technique may be applied to deposit an electrically conductive through silicon via made of a twophase bulk material 1914, a continuous phase being a matrix metal and a dispersed phase being embedded filler particles. The pattern of photoresist may be removed 1916 and the two layers of material deposited on the backside of the bulk silicon wafer may be etched 1918. -
FIG. 20 illustrates a partial list of materials, and several associated material properties, that may be used in one embodiment of a composite via. - Although specific embodiments have been illustrated and described herein for purposes of description of the preferred embodiment, it will be appreciated by those of ordinary skill in the art that a wide variety of alternate and/or equivalent implementations calculated to achieve the same purposes may be substituted for the specific embodiment shown and described without departing from the scope intended. For example, an alternative embodiment may exist where filler particles are packed into an open via hole within a die and a chemical vapor deposition (CVD) or physical vapor deposition (PVD) process (e.g., sputtering, evaporation, jet vapor deposition) may be used to fill in any volume in the through hole unfilled by packed particles. Yet another embodiment may exist wherein solder balls containing filler particles may reflow into an open via hole within a die. Still another embodiment may reflow solder balls containing filler particles under vacuum to avoid air filled voids within a finished via. Thus, those with skill in the art will readily appreciate implementation may be achieved using a very wide variety of embodiments. This application is intended to cover any adaptations or variations of the embodiments discussed herein. Therefore, it is manifestly intended only the claims and the equivalents thereof limit the scope of possible embodiments.
Claims (25)
1. A semiconductor package comprising:
an integrated circuit;
a material forming an electrically conductive through hole via coupled to the integrated circuit;
a matrix forming a continuous phase within the material of the via; and
particles embedded in the matrix forming a dispersed phase within the material of the via.
2. The semiconductor package of claim 1 , wherein a bulk material property of the material forming the via differs from the matrix.
3. The semiconductor package of claim 2 , wherein the material property is a coefficient of thermal expansion.
4. The semiconductor package of claim 2 , wherein the material property is electrical resistivity.
5. The semiconductor package of claim 1 , wherein the material forming the via has a lower coefficient of thermal expansion than the matrix.
6. The semiconductor package of claim 1 , wherein the matrix comprises a chosen one of the group consisting of copper (Cu), gold (Au), aluminum (Al), tungsten (W), silver (Ag), eutectic solder, and non-eutectic solder.
7. The semiconductor package of claim 6 , wherein the eutectic solder comprises one of the group consisting of tin-lead (Pb/Sn) solder and gold-tin (Au/Sn) solder.
8. The semiconductor package of claim 1 , wherein the filler particles comprise a chosen one of the group consisting of silica, alumina, boron nitride, tungsten, Invar, Super Invar, and Kovar.
9. The semiconductor package of claim 1 , wherein the filler particles comprise a ferromagnetic material.
10. A method comprising:
removing material from a die;
forming in the die an electrically conductive via of a material different from the die, the material being a composite of a matrix forming a continuous phase and embedded particles forming a dispersed phase.
11. The method of claim 10 , wherein forming in the die an electrically conductive via further comprises one of the group consisting of electroplating, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, evaporation, jet vapor deposition, and reflowing solder containing filler particles.
12. The method of claim 11 , wherein electroplating further comprises providing a driving potential to the first concentration of embedded particles to cause a second concentration of embedded particles in the material of the through hole via.
13. The method of claim 12 wherein the second concentration of embedded particles is greater than the first concentration of embedded particles.
14. The method of claim 12 wherein the driving potential comprises one of the group consisting of gravity and a magnetic field.
15. The method of claim 10 wherein the bulk material of the via has a different material property than the matrix metal.
16. The method of claim 15 wherein the material property is a coefficient of thermal expansion, the material of the via having a lower coefficient of thermal expansion than the matrix.
17. The method of claim 10 , wherein the matrix comprises a chosen one of the group consisting of copper (Cu), gold (Au), aluminum (Al), tungsten (W), silver (Ag), eutectic solder, and non-eutectic solder.
18. The method of claim 17 , wherein the eutectic solder comprises one of the group consisting of tin-lead (Pb/Sn) solder and gold-tin (Au/Sn) solder.
19. The method of claim 10 , wherein the filler particles comprise a chosen one of the group consisting of silica, alumina, boron nitride, tungsten, Invar, Super Invar, and Kovar.
20. The method of claim 10 , wherein the filler particles comprise a ferromagnetic material.
21. A system comprising:
a semiconductor package having an integrated circuit, the integrated circuit including,
an electrically conductive through hole via;
a matrix forming a continuous phase within the via;
particles with a coefficient of thermal expansion lower than the coefficient of thermal expansion of the matrix embedded in the matrix and forming a dispersed phase within the matrix; and
a mass storage device coupled to the semiconductor package.
22. The system of claim 21 , further comprising:
a dynamic random access memory coupled to the integrated circuit; and
an input/output interface coupled to the integrated circuit.
23. The system of claim 22 , wherein the input/output interface comprises a networking interface.
24. The system of claim 21 , wherein the integrated circuit is a processor.
25. The system of claim 24 , wherein the system is a selected one of a group comprising a set-top box, a media-center personal computer, and a digital versatile disk player.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/386,238 US20100193952A1 (en) | 2005-06-30 | 2009-04-14 | Integrated circuit die containing particale-filled through-silicon metal vias with reduced thermal expansion |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/174,125 US7528006B2 (en) | 2005-06-30 | 2005-06-30 | Integrated circuit die containing particle-filled through-silicon metal vias with reduced thermal expansion |
US12/386,238 US20100193952A1 (en) | 2005-06-30 | 2009-04-14 | Integrated circuit die containing particale-filled through-silicon metal vias with reduced thermal expansion |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/174,125 Division US7528006B2 (en) | 2005-06-30 | 2005-06-30 | Integrated circuit die containing particle-filled through-silicon metal vias with reduced thermal expansion |
Publications (1)
Publication Number | Publication Date |
---|---|
US20100193952A1 true US20100193952A1 (en) | 2010-08-05 |
Family
ID=37084662
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/174,125 Active 2026-04-24 US7528006B2 (en) | 2005-06-30 | 2005-06-30 | Integrated circuit die containing particle-filled through-silicon metal vias with reduced thermal expansion |
US12/386,238 Abandoned US20100193952A1 (en) | 2005-06-30 | 2009-04-14 | Integrated circuit die containing particale-filled through-silicon metal vias with reduced thermal expansion |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/174,125 Active 2026-04-24 US7528006B2 (en) | 2005-06-30 | 2005-06-30 | Integrated circuit die containing particle-filled through-silicon metal vias with reduced thermal expansion |
Country Status (8)
Country | Link |
---|---|
US (2) | US7528006B2 (en) |
JP (1) | JP5016596B2 (en) |
KR (2) | KR20100077062A (en) |
CN (2) | CN102280422B (en) |
DE (1) | DE112006001431B4 (en) |
HK (1) | HK1124959A1 (en) |
TW (1) | TWI332693B (en) |
WO (1) | WO2007005695A1 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2013061160A2 (en) * | 2011-10-29 | 2013-05-02 | Cima Nanotech Israel Ltd. | Conductive networks on patterned substrates |
US20140034354A1 (en) * | 2012-01-13 | 2014-02-06 | Zycube Co., Ltd. | Electrode, electrode material, and electrode formation method |
US9054162B2 (en) | 2010-11-22 | 2015-06-09 | Andreas Fischer | Method and an apparatus for forming electrically conductive vias in a substrate, an automated robot-based manufacturing system, a component comprising a substrate with via holes, and an interposer device |
US20180359866A1 (en) * | 2016-03-11 | 2018-12-13 | Ngk Insulators, Ltd. | Connection substrate |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100652554B1 (en) * | 2005-01-07 | 2006-12-01 | 재단법인서울대학교산학협력재단 | Flip-chip bonding structure using multi chip module-deposited substrate |
US7772115B2 (en) * | 2005-09-01 | 2010-08-10 | Micron Technology, Inc. | Methods for forming through-wafer interconnects, intermediate structures so formed, and devices and systems having at least one solder dam structure |
KR100713121B1 (en) * | 2005-09-27 | 2007-05-02 | 한국전자통신연구원 | Chip and a chip stack using the same and a method for manufacturing the same |
US7514797B2 (en) * | 2007-05-31 | 2009-04-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-die wafer level packaging |
TWI341554B (en) * | 2007-08-02 | 2011-05-01 | Enthone | Copper metallization of through silicon via |
US8049310B2 (en) * | 2008-04-01 | 2011-11-01 | Qimonda Ag | Semiconductor device with an interconnect element and method for manufacture |
KR100997788B1 (en) * | 2008-06-30 | 2010-12-02 | 주식회사 하이닉스반도체 | Semiconductor package |
US20100025848A1 (en) * | 2008-08-04 | 2010-02-04 | Infineon Technologies Ag | Method of fabricating a semiconductor device and semiconductor device |
US8136084B2 (en) * | 2009-09-09 | 2012-03-13 | International Business Machines Corporation | Arranging through silicon vias in IC layout |
US8587121B2 (en) * | 2010-03-24 | 2013-11-19 | International Business Machines Corporation | Backside dummy plugs for 3D integration |
TWI572750B (en) | 2010-05-24 | 2017-03-01 | 安頌股份有限公司 | Copper filling of through silicon vias |
US8518826B2 (en) | 2010-07-13 | 2013-08-27 | Lam Research Corporation | Metallization processes, mixtures, and electronic devices |
US9406562B2 (en) | 2011-01-13 | 2016-08-02 | GlobalFoundries, Inc. | Integrated circuit and design structure having reduced through silicon via-induced stress |
CN102683309B (en) * | 2011-03-15 | 2017-09-29 | 上海国增知识产权服务有限公司 | Wafer scale plants adapter plate structure of ball indentation brush filling through hole and preparation method thereof |
TWI436466B (en) | 2011-04-27 | 2014-05-01 | Ind Tech Res Inst | Filled through-silicon via and the fabrication method thereof |
US8816505B2 (en) | 2011-07-29 | 2014-08-26 | Tessera, Inc. | Low stress vias |
KR101612764B1 (en) * | 2011-11-14 | 2016-04-15 | 인텔 코포레이션 | Controlled solder-on-die integrations on packages and methods of assembling same |
WO2013147856A1 (en) | 2012-03-30 | 2013-10-03 | Intel Corporation | Process and material for preventing deleterious expansion of high aspect ratio copper filled through silicon vias (tsvs) |
KR20140011137A (en) | 2012-07-17 | 2014-01-28 | 삼성전자주식회사 | Integrated circuit device having through silicon via structure and method of manufacturing the same |
KR101992352B1 (en) | 2012-09-25 | 2019-06-24 | 삼성전자주식회사 | Semicondctor devices |
US9076783B2 (en) * | 2013-03-22 | 2015-07-07 | Freescale Semiconductor, Inc. | Methods and systems for selectively forming metal layers on lead frames after die attachment |
US9343359B2 (en) * | 2013-12-25 | 2016-05-17 | United Microelectronics Corp. | Integrated structure and method for fabricating the same |
TWI710671B (en) | 2014-09-15 | 2020-11-21 | 美商麥德美樂思公司 | Levelers for copper deposition in microelectronics |
US10418311B2 (en) | 2017-03-28 | 2019-09-17 | Micron Technology, Inc. | Method of forming vias using silicon on insulator substrate |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03203287A (en) * | 1989-12-29 | 1991-09-04 | Fujitsu Ltd | Formation of via |
EP0793405A2 (en) * | 1996-02-28 | 1997-09-03 | CTS Corporation | Multilayer electronic assembly utilizing a sinterable composition and related method of forming |
US6143421A (en) * | 1992-09-17 | 2000-11-07 | Coorstek, Inc. | Electronic components incorporating ceramic-metal composites |
US20050110509A1 (en) * | 2000-06-26 | 2005-05-26 | Fujitsu Limited | Contactor having conductive particles in a hole as a contact electrode |
US20050121768A1 (en) * | 2003-12-05 | 2005-06-09 | International Business Machines Corporation | Silicon chip carrier with conductive through-vias and method for fabricating same |
US20050189136A1 (en) * | 1999-10-26 | 2005-09-01 | Ibiden Co., Ltd. | Multi-layer printed circuit board and method of manufacturing multi-layer printed circuit board |
US20060012967A1 (en) * | 2002-04-01 | 2006-01-19 | Ibiden Co., Ltd. | Ic chip mounting substrate, ic chip mounting substrate manufacturing method, optical communication device, and optical communication device manufacturing method |
US20060084297A1 (en) * | 2002-08-27 | 2006-04-20 | Jsr Corporation | Anisotropic conductive sheet, its manufacturing method, and its application |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4881740A (en) * | 1972-02-04 | 1973-11-01 | ||
JPS5931894A (en) * | 1982-08-14 | 1984-02-21 | Matsushita Electric Works Ltd | Composite plating method |
JPS63121697A (en) * | 1986-11-10 | 1988-05-25 | Mitsubishi Heavy Ind Ltd | Dispersion plating method |
JP3397689B2 (en) * | 1998-06-01 | 2003-04-21 | 株式会社東芝 | Multi-chip semiconductor device and method of manufacturing the same |
KR100352993B1 (en) * | 1998-12-07 | 2002-09-18 | 가부시끼가이샤 히다치 세이사꾸쇼 | Composite material and application thereof |
JP2002088482A (en) * | 2000-09-14 | 2002-03-27 | Japan Science & Technology Corp | Dispersant magnetic field plating method, and dispersant magnetic field eutectoid plating method |
US6639309B2 (en) * | 2002-03-28 | 2003-10-28 | Sandisk Corporation | Memory package with a controller on one side of a printed circuit board and memory on another side of the circuit board |
CN1402342A (en) * | 2002-05-16 | 2003-03-12 | 株式会社日立制作所 | Composite material and its use |
US6800930B2 (en) * | 2002-07-31 | 2004-10-05 | Micron Technology, Inc. | Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies |
US20040159551A1 (en) * | 2003-02-14 | 2004-08-19 | Robert Barcell | Plating using an insoluble anode and separately supplied plating material |
US7019402B2 (en) * | 2003-10-17 | 2006-03-28 | International Business Machines Corporation | Silicon chip carrier with through-vias using laser assisted chemical vapor deposition of conductor |
US7202154B2 (en) * | 2004-01-05 | 2007-04-10 | International Business Machines Corporation | Suspension for filling via holes in silicon and method for making the same |
JP4626254B2 (en) * | 2004-10-12 | 2011-02-02 | パナソニック電工株式会社 | Plating embedding method and plating apparatus in through hole |
-
2005
- 2005-06-30 US US11/174,125 patent/US7528006B2/en active Active
-
2006
- 2006-06-29 KR KR1020107013881A patent/KR20100077062A/en not_active Application Discontinuation
- 2006-06-29 WO PCT/US2006/025748 patent/WO2007005695A1/en active Application Filing
- 2006-06-29 TW TW095123654A patent/TWI332693B/en active
- 2006-06-29 KR KR1020077030862A patent/KR100984240B1/en active IP Right Grant
- 2006-06-29 DE DE112006001431.5T patent/DE112006001431B4/en active Active
- 2006-06-29 CN CN201110224384.1A patent/CN102280422B/en active Active
- 2006-06-29 JP JP2008517236A patent/JP5016596B2/en active Active
- 2006-06-29 CN CN2006800228670A patent/CN101208798B/en active Active
-
2008
- 2008-12-17 HK HK08113690.8A patent/HK1124959A1/en unknown
-
2009
- 2009-04-14 US US12/386,238 patent/US20100193952A1/en not_active Abandoned
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03203287A (en) * | 1989-12-29 | 1991-09-04 | Fujitsu Ltd | Formation of via |
US6143421A (en) * | 1992-09-17 | 2000-11-07 | Coorstek, Inc. | Electronic components incorporating ceramic-metal composites |
EP0793405A2 (en) * | 1996-02-28 | 1997-09-03 | CTS Corporation | Multilayer electronic assembly utilizing a sinterable composition and related method of forming |
US20050189136A1 (en) * | 1999-10-26 | 2005-09-01 | Ibiden Co., Ltd. | Multi-layer printed circuit board and method of manufacturing multi-layer printed circuit board |
US20050110509A1 (en) * | 2000-06-26 | 2005-05-26 | Fujitsu Limited | Contactor having conductive particles in a hole as a contact electrode |
US20060012967A1 (en) * | 2002-04-01 | 2006-01-19 | Ibiden Co., Ltd. | Ic chip mounting substrate, ic chip mounting substrate manufacturing method, optical communication device, and optical communication device manufacturing method |
US20060084297A1 (en) * | 2002-08-27 | 2006-04-20 | Jsr Corporation | Anisotropic conductive sheet, its manufacturing method, and its application |
US20050121768A1 (en) * | 2003-12-05 | 2005-06-09 | International Business Machines Corporation | Silicon chip carrier with conductive through-vias and method for fabricating same |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9054162B2 (en) | 2010-11-22 | 2015-06-09 | Andreas Fischer | Method and an apparatus for forming electrically conductive vias in a substrate, an automated robot-based manufacturing system, a component comprising a substrate with via holes, and an interposer device |
WO2013061160A2 (en) * | 2011-10-29 | 2013-05-02 | Cima Nanotech Israel Ltd. | Conductive networks on patterned substrates |
WO2013061160A3 (en) * | 2011-10-29 | 2013-07-11 | Cima Nanotech Israel Ltd. | Conductive networks on patterned substrates |
US20140251667A1 (en) * | 2011-10-29 | 2014-09-11 | Cima Nanotech Israel Ltd. | Conductive Networks on Patterned Substrates |
US20140034354A1 (en) * | 2012-01-13 | 2014-02-06 | Zycube Co., Ltd. | Electrode, electrode material, and electrode formation method |
US9282638B2 (en) * | 2012-01-13 | 2016-03-08 | Zycube Co., Ltd. | Electrode, electrode material, and electrode formation method |
US20180359866A1 (en) * | 2016-03-11 | 2018-12-13 | Ngk Insulators, Ltd. | Connection substrate |
US10257941B2 (en) * | 2016-03-11 | 2019-04-09 | Ngk Insulators, Ltd. | Connection substrate |
Also Published As
Publication number | Publication date |
---|---|
TWI332693B (en) | 2010-11-01 |
TW200715495A (en) | 2007-04-16 |
JP2008547212A (en) | 2008-12-25 |
KR20100077062A (en) | 2010-07-06 |
US7528006B2 (en) | 2009-05-05 |
DE112006001431T5 (en) | 2008-05-15 |
CN102280422A (en) | 2011-12-14 |
CN101208798A (en) | 2008-06-25 |
US20070001266A1 (en) | 2007-01-04 |
WO2007005695A1 (en) | 2007-01-11 |
KR100984240B1 (en) | 2010-09-28 |
DE112006001431B4 (en) | 2014-04-24 |
CN102280422B (en) | 2015-09-23 |
HK1124959A1 (en) | 2009-07-24 |
KR20080018919A (en) | 2008-02-28 |
CN101208798B (en) | 2012-06-13 |
JP5016596B2 (en) | 2012-09-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7528006B2 (en) | Integrated circuit die containing particle-filled through-silicon metal vias with reduced thermal expansion | |
US11670577B2 (en) | Chip package with redistribution structure having multiple chips | |
US7666768B2 (en) | Through-die metal vias with a dispersed phase of graphitic structures of carbon for reduced thermal expansion and increased electrical conductance | |
US8344516B2 (en) | Integrated chip carrier with compliant interconnects | |
US9398699B2 (en) | Dual epoxy dielectric and photosensitive solder mask coatings, and processes of making same | |
JP5099377B2 (en) | Wiring board manufacturing method | |
US9385056B2 (en) | Packaging substrate having embedded interposer and fabrication method thereof | |
US7372133B2 (en) | Microelectronic package having a stiffening element and method of making same | |
US7038316B2 (en) | Bumpless die and heat spreader lid module bonded to bumped die carrier | |
US9299665B2 (en) | Formation of alpha particle shields in chip packaging | |
CN110880486B (en) | Fan-out semiconductor package | |
TWI381509B (en) | Semiconductor package and method for manufacturing the same | |
US20050073058A1 (en) | Integrated circuit package bond pad having plurality of conductive members | |
US20060246621A1 (en) | Microelectronic die including thermally conductive structure in a substrate thereof and method of forming same | |
JP2010092974A (en) | Semiconductor device and method of manufacturing the same, and electronic device | |
JP2005317704A (en) | Semiconductor device, and wiring board and its manufacturing method | |
US20030151132A1 (en) | Microelectronic die providing improved heat dissipation, and method of packaging same | |
JP2008153303A (en) | Circuit board, electronic device and manufacture thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |