US20100332887A1 - Storage control device having controller operated according to detection signal derived from monitoring power signal and related method thereof - Google Patents

Storage control device having controller operated according to detection signal derived from monitoring power signal and related method thereof Download PDF

Info

Publication number
US20100332887A1
US20100332887A1 US12/727,256 US72725610A US2010332887A1 US 20100332887 A1 US20100332887 A1 US 20100332887A1 US 72725610 A US72725610 A US 72725610A US 2010332887 A1 US2010332887 A1 US 2010332887A1
Authority
US
United States
Prior art keywords
controller
storage medium
storage
control device
power signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/727,256
Inventor
Tzu-Chieh Lin
Tzu-Li Hung
Kuan-Hua Chao
Shiue-Shin Liu
Hong-Ching Chen
Li-Chun Tu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MediaTek Inc
Original Assignee
MediaTek Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MediaTek Inc filed Critical MediaTek Inc
Priority to US12/727,256 priority Critical patent/US20100332887A1/en
Assigned to MEDIATEK INC. reassignment MEDIATEK INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHAO, KUAN-HUA, CHEN, HONG-CHING, HUNG, TZU-LI, LIN, TZU-CHIEH, LIU, SHIUE-SHIN, TU, LI-CHUN
Priority to TW099113251A priority patent/TWI406126B/en
Priority to CN201010158315.0A priority patent/CN101937318A/en
Publication of US20100332887A1 publication Critical patent/US20100332887A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7201—Logical to physical mapping or translation of blocks or pages

Definitions

  • the present invention is related to accessing a storage medium, and more particularly, to a storage control device having a controller operated according to a detection signal derived from monitoring a power signal and related method thereof.
  • the supply power of a storage subsystem is provided by a host which also issues read and write requests to the storage subsystem for reading data from and writing data into the storage subsystem.
  • a power signal derived from the externally supplied power is inputted to internal power elements of the storage subsystem. Therefore, anomaly of the power signal might severely damage the data storage of the storage subsystem.
  • a table such as a flash translation layer (FTL) table
  • FTL flash translation layer
  • the recording (encoding) and reading (decoding) qualities of the storage subsystem are deeply dominated by the power stability. Therefore, anomaly of the power signal used by the storage subsystem (e.g., an optical disc drive) might severely degrade the data access performance. In addition, the anomaly of the power signal might even damage the optical disc when the storage subsystem is operating under a write mode for emitting a laser beam with an unstable write power upon the optical disc.
  • the power signal used by the storage subsystem e.g., an optical disc drive
  • a storage control device having a controller operated according to a detection signal derived from monitoring a power signal and related method thereof are proposed to solve the problems mentioned above.
  • an exemplary storage control device for a storage medium.
  • the exemplary storage control device includes: a controller, for controlling data access of the storage medium; and a voltage detector, coupled to the controller, for monitoring a power signal and for asserting a detection signal to notify the controller when anomaly of the power signal is detected.
  • an exemplary storage control device for a storage medium.
  • the exemplary storage control device includes: a voltage detector, for monitoring a power signal to generate a detection signal; and a controller, coupled to the voltage detector, for controlling data access of the storage medium, where the controller enters a first operational state when the detection signal indicates that a voltage level of the power signal falls within a first voltage range, and the controller enters a second operational state different from the first operational state when the detection signal indicates that the voltage level of the power signal falls within a second voltage range different from the first voltage range.
  • an exemplary method applied to a controller utilized for controlling data access of a storage medium includes: monitoring a power signal to detect anomaly therein; and notifying the controller when the anomaly of the power signal is detected.
  • an exemplary method applied to a controller utilized for controlling data access of a storage medium includes: monitoring a power signal; when a voltage level of the power signal falls within a first voltage range, operating the controller under a first operational state; and when the voltage level of the power signal falls within a second voltage range different from the first voltage range, operating the controller under a second operational state different from the first operational state.
  • FIG. 1 is a diagram illustrating a first embodiment of a storage subsystem according to the present invention.
  • FIG. 2 is a circuit diagram illustrating one exemplary implementation of a voltage detector shown in FIG. 1 .
  • FIG. 3 is a diagram illustrating the relation between a detection signal and a power signal.
  • FIG. 4 is a diagram illustrating one exemplary controller chip having a voltage detector and a controller disposed therein.
  • FIG. 5 is a diagram illustrating a second embodiment of a storage subsystem according to the present invention.
  • FIG. 6 is a diagram illustrating another exemplary controller chip having a voltage detector and a controller disposed therein.
  • FIG. 7 is a flowchart of a generalized control method of a controller in a storage subsystem according to an embodiment of the present invention.
  • the conception of the present invention is to monitor a power signal to detect anomaly therein and to inform a controller of a storage subsystem when anomaly of the power signal is detected.
  • the controller of the storage subsystem is capable of taking appropriate action upon receiving the power anomaly notification.
  • FIG. 1 is a diagram illustrating a first embodiment of a storage subsystem according to the present invention.
  • the exemplary storage subsystem 100 includes, but is not limited to, a storage control device 102 , a first storage medium 104 , and a regulator 106 , where the storage control device 102 includes a controller 108 , a voltage detector 110 , and a second storage medium 112 .
  • the first storage medium 104 may be a non-volatile storage medium, such as a flash memory
  • the second storage medium 112 may be a volatile storage medium, such as a dynamic random access memory (DRAM)
  • the controller 108 is a flash memory controller.
  • the regulator 106 receives external supply power P ext from a host 116 , and accordingly generates a power signal P in for powering other elements included in the storage subsystem 100 .
  • the controller 108 communicates with the host 116 via a host interface 114 , and is employed for controlling data access (reading/recording) of the first storage medium 104 . For example, when the controller 108 receives a read request from the host 116 , the controller 108 serves the read request by reading stored data from the first storage medium 104 and transmitting the readout data to the host 116 . Additionally, when the controller 108 receives a write request and data to be recorded from the host 116 , the controller 108 serves the write request by recording the received data into the first storage medium 104 .
  • the voltage detector 110 is coupled to the controller 108 , and devised for monitoring a power status of the storage subsystem 100 .
  • the voltage detector 110 identifies the instant power status of the storage subsystem 100 by monitoring the power signal P in generated from the regulator 106 (i.e., a power signal received by the controller 108 ).
  • the voltage detector 110 will output a detection signal SD to notify the controller 108 when anomaly of the power signal P in is detected and will not output the detection signal SD when anomaly of the power signal P in is not detected.
  • FIG. 2 is a circuit diagram illustrating one exemplary implementation of the voltage detector 110 shown in FIG. 1 .
  • the voltage detector 110 includes a voltage divider 202 , a voltage generator 204 and a comparator 206 .
  • the voltage divider 202 divides a voltage level V in of the power signal P in according to resistance values of the resistors R 1 and R 2 , and generates a monitored voltage V M to the comparator 206 .
  • the monitored voltage V M can be simply expressed as follows:
  • V M V in ⁇ R ⁇ ⁇ 2 R ⁇ ⁇ 1 + R ⁇ ⁇ 2 .
  • the voltage generator 204 is used to provide a supply-independent reference voltage V REF to the comparator 206 .
  • the comparator 206 compares the monitored voltage V M with the reference voltage V REF to assert/deassert the detection signal SD. For example, when the monitored voltage V M is found lower than the reference voltage V REF , implying that the voltage level V in is lower than a predetermined threshold V TH (not shown), the comparator 206 generates a logic-high output to thereby assert the detection signal SD. However, when the monitored voltage V M is found higher than the reference voltage V REF , implying that the voltage level V in is higher than the predetermined threshold V TH , the comparator 206 generates a logic-low output to thereby deassert the detection signal SD.
  • the detection signal SD can be used to indicate whether the voltage level V in of the power signal P in is within a first voltage range (e.g., V TH ⁇ V in ⁇ V R , where V R represents a regular voltage level of the power signal P in ) or a second voltage range (e.g., 0 ⁇ V in ⁇ V TH ).
  • a first voltage range e.g., V TH ⁇ V in ⁇ V R , where V R represents a regular voltage level of the power signal P in
  • a second voltage range e.g., 0 ⁇ V in ⁇ V TH
  • the occurrence of power anomaly is detected by the voltage detector 110 when the voltage level V in of the power signal P in is found lower than the predetermined threshold V TH .
  • the occurrence of power anomaly is detected when the voltage level V in of the power signal P in is found greater than the predetermined threshold V TH . This also obeys the spirit of the present invention.
  • the controller 108 refers to the detection signal SD for switching its operational state to a normal state or an anomaly-power state.
  • FIG. 3 is a diagram illustrating the relation between the detection signal SD and the power signal P in .
  • the controller 108 operates in the normal state before the voltage level V in of the power signal P in is lower than the predetermined threshold V TH .
  • the voltage detector 110 determines that the anomaly of the power signal P in is detected and asserts the detection signal SD to notify the controller 108 . Therefore, the controller 108 leaves the normal state and enters the anomaly-power state upon receiving the detection signal SD asserted by the voltage detector 110 .
  • the voltage detector 110 determines that the anomaly of the power signal P in is not detected and deasserts the detection signal SD accordingly. Therefore, the controller 108 leaves the anomaly-power state and enters the normal state again when notified by the detection signal SD deasserted by the voltage detector 110 .
  • the controller 108 in order to avoid the loss of data stored in the storage subsystem 100 due to power anomaly, the controller 108 further takes predetermined action in response to the detection signal SD asserted by the voltage detector 110 .
  • the second storage medium 112 acting as a buffer may be implemented by a volatile storage medium. Therefore, system information (e.g., a table TB utilized for translating logical addresses of the host 116 to physical addresses of the first storage medium 104 ) and user data DATA_U (e.g., data waiting to be recorded into the first storage medium 104 or readout data waiting to be delivered to the host 116 ) will be buffered in the second storage medium 112 for achieving better performance.
  • system information e.g., a table TB utilized for translating logical addresses of the host 116 to physical addresses of the first storage medium 104
  • user data DATA_U e.g., data waiting to be recorded into the first storage medium 104 or readout data waiting to be delivered to the host 116
  • the table TB is an FTL table of the flash memory.
  • the predetermined action taken by the controller 108 may include recording a backup of the data stored in the second storage medium 112 into the first storage medium 104 and/or rejecting requests, such as read requests or write requests, issued by the host 116 for accessing the first storage medium 104 .
  • the backup of the data stored into the second storage medium 112 may include the table TB and/or the user data DATA_U.
  • the first storage medium 104 contains at least a first storage region SR_ 1 and a second storage region SR_ 2 with different inherent access speeds
  • the backup of the data stored in the second storage medium 112 will be stored into one storage region with faster access speed, say, the first storage region SR_ 1 .
  • the first storage medium 104 may be implemented by a flash memory having a first page group and a second page group within the same block, where the program time of each page included in the first page group is shorter than that of each page included in the second page group. Therefore, the backup of the data stored in the second storage medium 112 will be stored into page(s) selected from the first page group.
  • the voltage detector 110 and the controller 108 are individual elements within the storage subsystem 100 .
  • the voltage detector 110 may be embedded in the controller 108 to form a single element.
  • FIG. 4 is a diagram illustrating a controller chip 400 having the voltage detector 110 and the controller 108 disposed therein. Therefore, the controller chip 400 will have functionalities of the voltage detector 110 and the controller 108 , and can be employed in the storage subsystem 100 shown in FIG. 1 .
  • Such an alternative storage subsystem design also obeys the spirit of the present invention.
  • FIG. 5 is a diagram illustrating a second embodiment of a storage subsystem according to the present invention.
  • the storage subsystem 500 includes, but is not limited to, a storage control device 502 , a storage medium 504 , the aforementioned regulator 106 , and an access mechanism 506 .
  • the storage control device 502 includes a controller 508 and the aforementioned voltage detector 110 .
  • the regulator 106 receives supply power P ext from the host 116 , and accordingly generates the power signal P in for powering other elements included in the storage subsystem 100 .
  • the controller 508 communicates with the host 116 via the host interface 114 , and is employed for controlling data access of the storage medium 104 .
  • the controller 508 is unable to access the storage medium 504 directly.
  • the controller 508 therefore reads data from or writes data into the storage medium 504 by means of the access mechanism 506 .
  • the storage medium 104 is an optical storage medium (e.g., an optical disc)
  • the access mechanism 506 includes an optical pick-up unit (OPU) 510 and a servo system 512 .
  • OPU optical pick-up unit
  • servo system 512 e.g., a servo system
  • Any well-known architecture can be employed to realize the access mechanism 506 used for accessing an optical storage medium.
  • further description of the access mechanism 506 is omitted here for brevity.
  • the voltage detector 110 is capable of monitoring a power status of a storage subsystem, and informs the controller 508 of the instant power status of the storage subsystem.
  • the voltage detector 110 monitors the power signal P in generated from the regulator 106 (i.e., the power signal P in received by the controller 508 ).
  • the voltage detector 110 will assert the detection signal SD to notify the controller 508 when anomaly of the power signal P in is detected.
  • the controller 508 receives the detection signal SD from the voltage detector 110 , and switches its operational state to a normal state or an anomaly-power state according to the detection signal SD, as shown in FIG. 3 .
  • the controller 508 in order to improve the data access performance of the storage subsystem 500 and/or prevent the storage medium (e.g., an optical disc) 504 from being damaged due to power anomaly, the controller 508 further takes predetermined action in response to the detection signal SD asserted by the voltage detector 110 .
  • the predetermined action taken by the controller 508 may include lowering a processing speed of requests for accessing the storage medium 504 (e.g., lowering the recording (encoding) or reading (decoding) speed to reduce the overall system power consumption), suspending a current data access of the storage medium 504 (e.g., suspending the recording process in case the optical disc is damaged because of irregular write power), and/or rejecting requests, such as read requests or write requests, issued by the host 116 for accessing the first storage medium 504 .
  • lowering a processing speed of requests for accessing the storage medium 504 e.g., lowering the recording (encoding) or reading (decoding) speed to reduce the overall system power consumption
  • suspending a current data access of the storage medium 504 e.g., suspending the recording process in case the optical disc is damaged because of irregular write power
  • rejecting requests such as read requests or write requests, issued by the host 116 for accessing the first storage medium 504 .
  • the voltage detector 110 and the controller 508 are individual elements within the storage subsystem 500 .
  • the voltage detector 110 may be embedded in the controller 508 to form a single element.
  • FIG. 6 is a diagram illustrating a controller chip 600 having the voltage detector 110 and the controller 508 disposed therein. Therefore, the controller chip 600 will have functionalities of the voltage detector 110 and the controller 508 , and can be employed in the storage subsystem 500 shown in FIG. 1 .
  • Such an alternative storage subsystem design also obeys the spirit of the present invention.
  • the storage medium 104 may be a magnetic storage medium such as a hard disk, and the access mechanism 506 may contain elements required to access the magnetic storage medium. Such an application also falls within the scope of the present invention.
  • FIG. 7 is a flowchart of a generalized control method of a controller in a storage subsystem according to an embodiment of the present invention. Provided that the result is substantially the same, the steps are not required to be executed in the exact order shown in FIG. 7 .
  • the generalized control method may be employed to control operations of either of the exemplary controllers 108 and 508 , and includes the following steps.
  • Step 700 Start.
  • Step 702 The controller enters a first operational state (e.g., a normal state) to control data access of a storage medium (e.g., a non-volatile storage medium).
  • a first operational state e.g., a normal state
  • a storage medium e.g., a non-volatile storage medium
  • Step 704 The voltage detector monitors a power signal to detect anomaly therein and generates a detection signal accordingly, where the detection signal is asserted when the anomaly of the power signal is detected, and deasserted when the anomaly of the power signal is not detected.
  • Step 706 The controller receives the detection signal, and checks the logic level of the detection signal. If the detection signal is asserted to indicate the occurrence of power anomaly, the flow goes to step 708 ; if the detection signal is deasserted to indicate that no power anomaly occurs, the flow proceeds with step 702 .
  • Step 708 The controller enters a second operational state (e.g., an anomaly-power state) to take predetermined action.
  • the flow goes to step 706 .

Abstract

One exemplary storage control device for a storage medium includes a controller and a voltage detector, where the controller controls data access of the storage medium, and the voltage detector monitors a power signal and asserts a detection signal to notify the controller when anomaly of the power signal is detected. Another exemplary storage control device for a storage medium includes a voltage detector and a controller, where the voltage detector monitors a power signal to generate a detection signal, and the controller controls data access of the storage medium. In addition, the controller enters a first operational state when the detection signal indicates that a voltage level of the power signal falls within a first voltage range, and enters a second operational state when the detection signal indicates that the voltage level of the power signal falls within a second voltage range.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application claims the benefit of U.S. Provisional Application No. 61/221,569, filed on Jun. 30, 2009 and included herein by reference.
    • BACKGROUND
  • The present invention is related to accessing a storage medium, and more particularly, to a storage control device having a controller operated according to a detection signal derived from monitoring a power signal and related method thereof.
  • In general, the supply power of a storage subsystem is provided by a host which also issues read and write requests to the storage subsystem for reading data from and writing data into the storage subsystem. A power signal derived from the externally supplied power is inputted to internal power elements of the storage subsystem. Therefore, anomaly of the power signal might severely damage the data storage of the storage subsystem.
  • Taking one storage subsystem which uses a non-volatile memory (e.g., a flash memory) as a storage medium for example, a table, such as a flash translation layer (FTL) table, used to translate logical addresses of the host into physical addresses of the non-volatile memory is usually temporarily saved in a volatile memory (e.g., a dynamic random access memory) of the storage subsystem due to performance consideration. However, anomaly of the power signal used by the storage subsystem might damage the integrality of the table stored in the volatile memory, leading to loss of user data.
  • Taking another storage subsystem which uses an optical disc as a storage medium for example, the recording (encoding) and reading (decoding) qualities of the storage subsystem are deeply dominated by the power stability. Therefore, anomaly of the power signal used by the storage subsystem (e.g., an optical disc drive) might severely degrade the data access performance. In addition, the anomaly of the power signal might even damage the optical disc when the storage subsystem is operating under a write mode for emitting a laser beam with an unstable write power upon the optical disc.
    • SUMMARY
  • In accordance with embodiments of the present invention, a storage control device having a controller operated according to a detection signal derived from monitoring a power signal and related method thereof are proposed to solve the problems mentioned above.
  • According to a first aspect of the present invention, an exemplary storage control device for a storage medium is disclosed. The exemplary storage control device includes: a controller, for controlling data access of the storage medium; and a voltage detector, coupled to the controller, for monitoring a power signal and for asserting a detection signal to notify the controller when anomaly of the power signal is detected.
  • According to a second aspect of the present invention, an exemplary storage control device for a storage medium is disclosed. The exemplary storage control device includes: a voltage detector, for monitoring a power signal to generate a detection signal; and a controller, coupled to the voltage detector, for controlling data access of the storage medium, where the controller enters a first operational state when the detection signal indicates that a voltage level of the power signal falls within a first voltage range, and the controller enters a second operational state different from the first operational state when the detection signal indicates that the voltage level of the power signal falls within a second voltage range different from the first voltage range.
  • According to a third aspect of the present invention, an exemplary method applied to a controller utilized for controlling data access of a storage medium is disclosed. The exemplary method includes: monitoring a power signal to detect anomaly therein; and notifying the controller when the anomaly of the power signal is detected.
  • According to a fourth aspect of the present invention, an exemplary method applied to a controller utilized for controlling data access of a storage medium is disclosed. The exemplary method includes: monitoring a power signal; when a voltage level of the power signal falls within a first voltage range, operating the controller under a first operational state; and when the voltage level of the power signal falls within a second voltage range different from the first voltage range, operating the controller under a second operational state different from the first operational state.
  • These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a diagram illustrating a first embodiment of a storage subsystem according to the present invention.
  • FIG. 2 is a circuit diagram illustrating one exemplary implementation of a voltage detector shown in FIG. 1.
  • FIG. 3 is a diagram illustrating the relation between a detection signal and a power signal.
  • FIG. 4 is a diagram illustrating one exemplary controller chip having a voltage detector and a controller disposed therein.
  • FIG. 5 is a diagram illustrating a second embodiment of a storage subsystem according to the present invention.
  • FIG. 6 is a diagram illustrating another exemplary controller chip having a voltage detector and a controller disposed therein.
  • FIG. 7 is a flowchart of a generalized control method of a controller in a storage subsystem according to an embodiment of the present invention.
    •  DETAILED DESCRIPTION
  • Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
  • The conception of the present invention is to monitor a power signal to detect anomaly therein and to inform a controller of a storage subsystem when anomaly of the power signal is detected. In this way, the controller of the storage subsystem is capable of taking appropriate action upon receiving the power anomaly notification. For clarity, several exemplary embodiments are given as follows.
  • FIG. 1 is a diagram illustrating a first embodiment of a storage subsystem according to the present invention. The exemplary storage subsystem 100 includes, but is not limited to, a storage control device 102, a first storage medium 104, and a regulator 106, where the storage control device 102 includes a controller 108, a voltage detector 110, and a second storage medium 112. By way of example, but not limitation, the first storage medium 104 may be a non-volatile storage medium, such as a flash memory, the second storage medium 112 may be a volatile storage medium, such as a dynamic random access memory (DRAM), and the controller 108 is a flash memory controller. The regulator 106 receives external supply power Pext from a host 116, and accordingly generates a power signal Pin for powering other elements included in the storage subsystem 100. The controller 108 communicates with the host 116 via a host interface 114, and is employed for controlling data access (reading/recording) of the first storage medium 104. For example, when the controller 108 receives a read request from the host 116, the controller 108 serves the read request by reading stored data from the first storage medium 104 and transmitting the readout data to the host 116. Additionally, when the controller 108 receives a write request and data to be recorded from the host 116, the controller 108 serves the write request by recording the received data into the first storage medium 104.
  • The voltage detector 110 is coupled to the controller 108, and devised for monitoring a power status of the storage subsystem 100. In this exemplary embodiment, the voltage detector 110 identifies the instant power status of the storage subsystem 100 by monitoring the power signal Pin generated from the regulator 106 (i.e., a power signal received by the controller 108). The voltage detector 110 will output a detection signal SD to notify the controller 108 when anomaly of the power signal Pin is detected and will not output the detection signal SD when anomaly of the power signal Pin is not detected.
  • FIG. 2 is a circuit diagram illustrating one exemplary implementation of the voltage detector 110 shown in FIG. 1. The voltage detector 110 includes a voltage divider 202, a voltage generator 204 and a comparator 206. The voltage divider 202 divides a voltage level Vin of the power signal Pin according to resistance values of the resistors R1 and R2, and generates a monitored voltage VM to the comparator 206. The monitored voltage VM can be simply expressed as follows:
  • V M = V in · R 2 R 1 + R 2 .
  • The voltage generator 204 is used to provide a supply-independent reference voltage VREF to the comparator 206. The comparator 206 compares the monitored voltage VM with the reference voltage VREF to assert/deassert the detection signal SD. For example, when the monitored voltage VM is found lower than the reference voltage VREF, implying that the voltage level Vin is lower than a predetermined threshold VTH (not shown), the comparator 206 generates a logic-high output to thereby assert the detection signal SD. However, when the monitored voltage VM is found higher than the reference voltage VREF, implying that the voltage level Vin is higher than the predetermined threshold VTH, the comparator 206 generates a logic-low output to thereby deassert the detection signal SD. In this way, the detection signal SD can be used to indicate whether the voltage level Vin of the power signal Pin is within a first voltage range (e.g., VTH<Vin≦VR, where VR represents a regular voltage level of the power signal Pin) or a second voltage range (e.g., 0<Vin<VTH).
  • In above example, the occurrence of power anomaly is detected by the voltage detector 110 when the voltage level Vin of the power signal Pin is found lower than the predetermined threshold VTH. However, in an alternative design of the voltage detector 110, the occurrence of power anomaly is detected when the voltage level Vin of the power signal Pin is found greater than the predetermined threshold VTH. This also obeys the spirit of the present invention.
  • The controller 108 refers to the detection signal SD for switching its operational state to a normal state or an anomaly-power state. FIG. 3 is a diagram illustrating the relation between the detection signal SD and the power signal Pin. As can be seen from the figure, the controller 108 operates in the normal state before the voltage level Vin of the power signal Pin is lower than the predetermined threshold VTH. When the voltage level Vin of the power signal Pin goes below the predetermined threshold VTH, the voltage detector 110 determines that the anomaly of the power signal Pin is detected and asserts the detection signal SD to notify the controller 108. Therefore, the controller 108 leaves the normal state and enters the anomaly-power state upon receiving the detection signal SD asserted by the voltage detector 110. When the voltage level Vin of the power signal Pin increases to exceed the predetermined threshold VTH after the detection signal SD is asserted, the voltage detector 110 determines that the anomaly of the power signal Pin is not detected and deasserts the detection signal SD accordingly. Therefore, the controller 108 leaves the anomaly-power state and enters the normal state again when notified by the detection signal SD deasserted by the voltage detector 110.
  • In this embodiment, in order to avoid the loss of data stored in the storage subsystem 100 due to power anomaly, the controller 108 further takes predetermined action in response to the detection signal SD asserted by the voltage detector 110. For example, the second storage medium 112 acting as a buffer may be implemented by a volatile storage medium. Therefore, system information (e.g., a table TB utilized for translating logical addresses of the host 116 to physical addresses of the first storage medium 104) and user data DATA_U (e.g., data waiting to be recorded into the first storage medium 104 or readout data waiting to be delivered to the host 116) will be buffered in the second storage medium 112 for achieving better performance. In a case where the first storage medium 104 is a flash memory, the table TB is an FTL table of the flash memory. The predetermined action taken by the controller 108 may include recording a backup of the data stored in the second storage medium 112 into the first storage medium 104 and/or rejecting requests, such as read requests or write requests, issued by the host 116 for accessing the first storage medium 104. The backup of the data stored into the second storage medium 112 may include the table TB and/or the user data DATA_U.
  • In addition, provided that the first storage medium 104 contains at least a first storage region SR_1 and a second storage region SR_2 with different inherent access speeds, the backup of the data stored in the second storage medium 112 will be stored into one storage region with faster access speed, say, the first storage region SR_1. By way of example, but not limitation, the first storage medium 104 may be implemented by a flash memory having a first page group and a second page group within the same block, where the program time of each page included in the first page group is shorter than that of each page included in the second page group. Therefore, the backup of the data stored in the second storage medium 112 will be stored into page(s) selected from the first page group.
  • As shown in FIG. 1, the voltage detector 110 and the controller 108 are individual elements within the storage subsystem 100. However, the voltage detector 110 may be embedded in the controller 108 to form a single element. Please refer to FIG. 4, which is a diagram illustrating a controller chip 400 having the voltage detector 110 and the controller 108 disposed therein. Therefore, the controller chip 400 will have functionalities of the voltage detector 110 and the controller 108, and can be employed in the storage subsystem 100 shown in FIG. 1. Such an alternative storage subsystem design also obeys the spirit of the present invention.
  • FIG. 5 is a diagram illustrating a second embodiment of a storage subsystem according to the present invention. The storage subsystem 500 includes, but is not limited to, a storage control device 502, a storage medium 504, the aforementioned regulator 106, and an access mechanism 506. The storage control device 502 includes a controller 508 and the aforementioned voltage detector 110. The regulator 106 receives supply power Pext from the host 116, and accordingly generates the power signal Pin for powering other elements included in the storage subsystem 100. The controller 508 communicates with the host 116 via the host interface 114, and is employed for controlling data access of the storage medium 104. The major difference between the storage subsystems 100 and 500 is that the controller 508 is unable to access the storage medium 504 directly. For example, mechanical means is required to access the storage medium 504. The controller 508 therefore reads data from or writes data into the storage medium 504 by means of the access mechanism 506. In this exemplary embodiment, the storage medium 104 is an optical storage medium (e.g., an optical disc), and the access mechanism 506 includes an optical pick-up unit (OPU) 510 and a servo system 512. However, this is for illustrative purposes only. Any well-known architecture can be employed to realize the access mechanism 506 used for accessing an optical storage medium. In addition, as a person skilled in the optical storage field can readily understand details of recording data onto and reading data from the optical storage medium, further description of the access mechanism 506 is omitted here for brevity.
  • As mentioned above, the voltage detector 110 is capable of monitoring a power status of a storage subsystem, and informs the controller 508 of the instant power status of the storage subsystem. In this exemplary embodiment, the voltage detector 110 monitors the power signal Pin generated from the regulator 106 (i.e., the power signal Pin received by the controller 508). Similarly, the voltage detector 110 will assert the detection signal SD to notify the controller 508 when anomaly of the power signal Pin is detected. As details of the voltage detector 110 have been described in above paragraphs, further description is omitted here for brevity.
  • Similar to the controller 108 shown in FIG. 1, the controller 508 receives the detection signal SD from the voltage detector 110, and switches its operational state to a normal state or an anomaly-power state according to the detection signal SD, as shown in FIG. 3. In this embodiment, in order to improve the data access performance of the storage subsystem 500 and/or prevent the storage medium (e.g., an optical disc) 504 from being damaged due to power anomaly, the controller 508 further takes predetermined action in response to the detection signal SD asserted by the voltage detector 110. For example, the predetermined action taken by the controller 508 may include lowering a processing speed of requests for accessing the storage medium 504 (e.g., lowering the recording (encoding) or reading (decoding) speed to reduce the overall system power consumption), suspending a current data access of the storage medium 504 (e.g., suspending the recording process in case the optical disc is damaged because of irregular write power), and/or rejecting requests, such as read requests or write requests, issued by the host 116 for accessing the first storage medium 504.
  • As shown in FIG. 5, the voltage detector 110 and the controller 508 are individual elements within the storage subsystem 500. However, the voltage detector 110 may be embedded in the controller 508 to form a single element. Please refer to FIG. 6, which is a diagram illustrating a controller chip 600 having the voltage detector 110 and the controller 508 disposed therein. Therefore, the controller chip 600 will have functionalities of the voltage detector 110 and the controller 508, and can be employed in the storage subsystem 500 shown in FIG. 1. Such an alternative storage subsystem design also obeys the spirit of the present invention.
  • It should be noted that the storage medium 104 may be a magnetic storage medium such as a hard disk, and the access mechanism 506 may contain elements required to access the magnetic storage medium. Such an application also falls within the scope of the present invention.
  • FIG. 7 is a flowchart of a generalized control method of a controller in a storage subsystem according to an embodiment of the present invention. Provided that the result is substantially the same, the steps are not required to be executed in the exact order shown in FIG. 7. The generalized control method may be employed to control operations of either of the exemplary controllers 108 and 508, and includes the following steps.
  • Step 700: Start.
  • Step 702: The controller enters a first operational state (e.g., a normal state) to control data access of a storage medium (e.g., a non-volatile storage medium).
  • Step 704: The voltage detector monitors a power signal to detect anomaly therein and generates a detection signal accordingly, where the detection signal is asserted when the anomaly of the power signal is detected, and deasserted when the anomaly of the power signal is not detected.
  • Step 706: The controller receives the detection signal, and checks the logic level of the detection signal. If the detection signal is asserted to indicate the occurrence of power anomaly, the flow goes to step 708; if the detection signal is deasserted to indicate that no power anomaly occurs, the flow proceeds with step 702.
  • Step 708: The controller enters a second operational state (e.g., an anomaly-power state) to take predetermined action. The flow goes to step 706.
  • As a person skilled in the art can readily understand details of each step in FIG. 7 after reading above paragraphs directed to the exemplary storage subsystems 100 and 500, further description is omitted here for brevity.
  • Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (27)

1. A storage control device for a first storage medium, comprising:
a controller, for controlling data access of the first storage medium; and
a voltage detector, coupled to the controller, for monitoring a power signal and for asserting a detection signal to notify the controller when anomaly of the power signal is detected.
2. The storage control device of claim 1, wherein the controller further takes predetermined action in response to the anomaly of the power signal when notified by the detection signal.
3. The storage control device of claim 2, wherein the storage control device further comprises:
a second storage medium, coupled to the controller, for storing data accessible to the controller;
wherein the predetermined action includes recording a backup of the data stored in the second storage medium into the first storage medium.
4. The storage control device of claim 3, wherein the backup of the data stored in the second storage medium includes a table utilized for translating logical addresses of a host into physical addresses of the first storage medium.
5. The storage control device of claim 3, wherein the backup of the data stored in the second storage medium includes user data.
6. The storage control device of claim 3, wherein the first storage medium comprises a first storage region and a second storage region, where an inherent access speed of the first storage region is faster than an inherent access speed of the second storage region; and the backup of the data stored in the second storage medium is stored into the first storage region.
7. The storage control device of claim 2, wherein the predetermined action includes lowering a processing speed of requests for accessing the first storage medium.
8. The storage control device of claim 2, wherein the predetermined action includes suspending a current data access of the first storage medium.
9. The storage control device of claim 2, wherein the controller communicates with a host via a host interface, and the predetermined action includes rejecting requests issued by the host for accessing the first storage medium.
10. The storage system of claim 1, wherein after asserting the detection signal, the voltage detector further deasserts the detection signal when the anomaly of the power signal is not detected.
11. The storage control device of claim 1, wherein when a voltage level of the monitored power signal is lower than a predetermined threshold, the voltage detector determines that the anomaly of the power signal is detected.
12. The storage control device of claim 1, wherein the controller and the voltage detector are integrated in a controller chip.
13. The storage control device of claim 1, wherein the first storage medium is a non-volatile storage medium.
14. The storage control device of claim 13, wherein the non-volatile storage medium is a non-volatile memory or an optical storage medium.
15. A storage control device for a first storage medium, comprising:
a voltage detector, for monitoring a power signal to generate a detection signal; and
a controller, coupled to the voltage detector, for controlling data access of the first storage medium, wherein the controller enters a first operational state when the detection signal indicates that a voltage level of the power signal falls within a first voltage range, and the controller enters a second operational state different from the first operational state when the detection signal indicates that the voltage level of the power signal falls within a second voltage range different from the first voltage range.
16. The storage control device of claim 15, wherein the storage control device further comprises:
a second storage medium, coupled to the controller, for storing data accessible to the controller;
wherein when the controller operates under the second operational state, the controller records a backup of the data stored in the second storage medium into the first storage medium.
17. The storage control device of claim 16, wherein the backup of the data stored in the second storage medium includes a table utilized for translating logical addresses of a host to physical addresses of the first storage medium.
18. The storage control device of claim 16, wherein the backup of the data stored in the second storage medium includes user data.
19. The storage control device of claim 16, wherein the first storage medium comprises a first storage region and a second storage region, where an inherent access speed of the first storage region is faster than an inherent access speed of the second storage region; and the backup of the data stored in the second storage medium is stored into the first storage region.
20. The storage control device of claim 15, wherein when the controller operates under the second operational state, the controller lowers a processing speed of requests for accessing the first storage medium.
21. The storage control device of claim 15, wherein when the controller operates under the second operational state, the controller suspends a current data access of the first storage medium.
22. The storage control device of claim 15, wherein the controller communicates with a host via a host interface; and when the controller operates under the second operational state, the controller rejects requests issued by the host for accessing the first storage medium.
23. The storage control device of claim 15, wherein the controller and the voltage detector are integrated in a controller chip.
24. The storage control device of claim 15, wherein the first storage medium is a non-volatile storage medium.
25. The storage control device of claim 24, wherein the non-volatile storage medium is a non-volatile memory or an optical storage medium.
26. A control method of a controller utilized for controlling data access of a storage medium, comprising:
monitoring a power signal to detect anomaly therein; and
notifying the controller when the anomaly of the power signal is detected.
27. A control method of a controller utilized for controlling data access of a storage medium, comprising:
monitoring a power signal;
when a voltage level of the power signal falls within a first voltage range, operating the controller under a first operational state; and
when the voltage level of the power signal falls within a second voltage range different from the first voltage range, operating the controller under a second operational state different from the first operational state.
US12/727,256 2009-06-30 2010-03-19 Storage control device having controller operated according to detection signal derived from monitoring power signal and related method thereof Abandoned US20100332887A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US12/727,256 US20100332887A1 (en) 2009-06-30 2010-03-19 Storage control device having controller operated according to detection signal derived from monitoring power signal and related method thereof
TW099113251A TWI406126B (en) 2009-06-30 2010-04-27 Storage control device for storage medium and control method utilized for controlling data access of the storage medium
CN201010158315.0A CN101937318A (en) 2009-06-30 2010-04-28 Storage control device for a storage medium and data access control method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US22156909P 2009-06-30 2009-06-30
US12/727,256 US20100332887A1 (en) 2009-06-30 2010-03-19 Storage control device having controller operated according to detection signal derived from monitoring power signal and related method thereof

Publications (1)

Publication Number Publication Date
US20100332887A1 true US20100332887A1 (en) 2010-12-30

Family

ID=43382094

Family Applications (3)

Application Number Title Priority Date Filing Date
US12/721,692 Abandoned US20100332922A1 (en) 2009-06-30 2010-03-11 Method for managing device and solid state disk drive utilizing the same
US12/727,256 Abandoned US20100332887A1 (en) 2009-06-30 2010-03-19 Storage control device having controller operated according to detection signal derived from monitoring power signal and related method thereof
US12/759,822 Active 2031-05-18 US8458566B2 (en) 2009-06-30 2010-04-14 Method for performing copy back operations and flash storage device

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US12/721,692 Abandoned US20100332922A1 (en) 2009-06-30 2010-03-11 Method for managing device and solid state disk drive utilizing the same

Family Applications After (1)

Application Number Title Priority Date Filing Date
US12/759,822 Active 2031-05-18 US8458566B2 (en) 2009-06-30 2010-04-14 Method for performing copy back operations and flash storage device

Country Status (3)

Country Link
US (3) US20100332922A1 (en)
CN (3) CN101937318A (en)
TW (3) TWI406126B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150149706A1 (en) * 2013-11-27 2015-05-28 NXGN Data, Inc. System and method for efficient flash translation layer
TWI573142B (en) * 2015-02-02 2017-03-01 慧榮科技股份有限公司 Data storage device and data maintenance method thereof
US20230027611A1 (en) * 2021-07-26 2023-01-26 Realtek Semiconductor Corporation Power supply device, power supply system and non-transitory computer-readable recording medium

Families Citing this family (149)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2847695B1 (en) * 2002-11-25 2005-03-11 Oberthur Card Syst Sa SECURE ELECTRONIC ENTITY INTEGRATING THE MANAGEMENT OF THE LIFE OF AN OBJECT
US8307180B2 (en) 2008-02-28 2012-11-06 Nokia Corporation Extended utilization area for a memory device
US8261158B2 (en) 2009-03-13 2012-09-04 Fusion-Io, Inc. Apparatus, system, and method for using multi-level cell solid-state storage as single level cell solid-state storage
US8266503B2 (en) 2009-03-13 2012-09-11 Fusion-Io Apparatus, system, and method for using multi-level cell storage in a single-level cell mode
KR101586047B1 (en) 2009-03-25 2016-01-18 삼성전자주식회사 Nonvolatile memory device and program methods for the same
US8874824B2 (en) 2009-06-04 2014-10-28 Memory Technologies, LLC Apparatus and method to share host system RAM with mass storage memory RAM
KR101062755B1 (en) * 2009-07-29 2011-09-06 주식회사 하이닉스반도체 Semiconductor memory system including ECC circuit and control method thereof
US8854882B2 (en) 2010-01-27 2014-10-07 Intelligent Intellectual Property Holdings 2 Llc Configuring storage cells
US8661184B2 (en) 2010-01-27 2014-02-25 Fusion-Io, Inc. Managing non-volatile media
KR101663158B1 (en) * 2010-01-29 2016-10-06 삼성전자 주식회사 Semiconductor memory device
US9245653B2 (en) 2010-03-15 2016-01-26 Intelligent Intellectual Property Holdings 2 Llc Reduced level cell mode for non-volatile memory
US8656256B2 (en) * 2010-07-07 2014-02-18 Stec, Inc. Apparatus and method for multi-mode operation of a flash memory device
JP5651457B2 (en) * 2010-12-15 2015-01-14 株式会社東芝 Semiconductor memory device
KR20120097862A (en) * 2011-02-25 2012-09-05 삼성전자주식회사 Data storage system and data mapping method thereof
CN102693760B (en) * 2011-03-24 2015-07-15 扬智科技股份有限公司 Error correction method for NAND flash memory
US9176810B2 (en) * 2011-05-27 2015-11-03 SanDisk Technologies, Inc. Bit error reduction through varied data positioning
US8886911B2 (en) * 2011-05-31 2014-11-11 Micron Technology, Inc. Dynamic memory cache size adjustment in a memory device
CN102890645B (en) * 2011-07-20 2015-11-25 群联电子股份有限公司 Memorizer memory devices, Memory Controller and method for writing data
US8995196B2 (en) * 2011-08-15 2015-03-31 Skymedi Corporation Method of sorting a multi-bit per cell non-volatile memory and a multi-mode configuration method
KR20130052971A (en) 2011-11-14 2013-05-23 삼성전자주식회사 Method of operating non-volatile memory devices
JP5942512B2 (en) * 2012-03-19 2016-06-29 富士通株式会社 Storage control device and storage system
US9311226B2 (en) * 2012-04-20 2016-04-12 Memory Technologies Llc Managing operational state data of a memory module using host memory in association with state change
US8996957B1 (en) 2012-05-22 2015-03-31 Pmc-Sierra, Inc. Systems and methods for initializing regions of a flash drive having diverse error correction coding (ECC) schemes
US9021336B1 (en) 2012-05-22 2015-04-28 Pmc-Sierra, Inc. Systems and methods for redundantly storing error correction codes in a flash drive with secondary parity information spread out across each page of a group of pages
US9176812B1 (en) 2012-05-22 2015-11-03 Pmc-Sierra, Inc. Systems and methods for storing data in page stripes of a flash drive
US9021333B1 (en) 2012-05-22 2015-04-28 Pmc-Sierra, Inc. Systems and methods for recovering data from failed portions of a flash drive
US9183085B1 (en) 2012-05-22 2015-11-10 Pmc-Sierra, Inc. Systems and methods for adaptively selecting from among a plurality of error correction coding schemes in a flash drive for robustness and low latency
US9021337B1 (en) 2012-05-22 2015-04-28 Pmc-Sierra, Inc. Systems and methods for adaptively selecting among different error correction coding schemes in a flash drive
US8788910B1 (en) 2012-05-22 2014-07-22 Pmc-Sierra, Inc. Systems and methods for low latency, high reliability error correction in a flash drive
US8972824B1 (en) 2012-05-22 2015-03-03 Pmc-Sierra, Inc. Systems and methods for transparently varying error correction code strength in a flash drive
US8793556B1 (en) 2012-05-22 2014-07-29 Pmc-Sierra, Inc. Systems and methods for reclaiming flash blocks of a flash drive
US9047214B1 (en) 2012-05-22 2015-06-02 Pmc-Sierra, Inc. System and method for tolerating a failed page in a flash device
TWI477104B (en) * 2012-09-13 2015-03-11 Mstar Semiconductor Inc Apparatus and method for correcting error
KR102025263B1 (en) * 2012-10-05 2019-09-25 삼성전자주식회사 Memory system and read reclaim method thereof
KR101997794B1 (en) 2012-12-11 2019-07-09 삼성전자주식회사 Memory controller and memory system including the same
CN103116550A (en) * 2013-01-11 2013-05-22 深圳市硅格半导体有限公司 Method and device for switching physical block work mode in flash memory
US9043668B2 (en) * 2013-02-08 2015-05-26 Seagate Technology Llc Using ECC data for write deduplication processing
US9026867B1 (en) 2013-03-15 2015-05-05 Pmc-Sierra, Inc. Systems and methods for adapting to changing characteristics of multi-level cells in solid-state memory
US10042750B2 (en) * 2013-03-15 2018-08-07 Micron Technology, Inc. Apparatuses and methods for adaptive control of memory using an adaptive memory controller with a memory management hypervisor
US9208018B1 (en) 2013-03-15 2015-12-08 Pmc-Sierra, Inc. Systems and methods for reclaiming memory for solid-state memory
US9053012B1 (en) 2013-03-15 2015-06-09 Pmc-Sierra, Inc. Systems and methods for storing data for solid-state memory
US9081701B1 (en) 2013-03-15 2015-07-14 Pmc-Sierra, Inc. Systems and methods for decoding data for solid-state memory
US9009565B1 (en) 2013-03-15 2015-04-14 Pmc-Sierra, Inc. Systems and methods for mapping for solid-state memory
CN104217762B (en) * 2013-05-31 2017-11-24 慧荣科技股份有限公司 Data storage device and error correction method and data reading method thereof
US9442670B2 (en) 2013-09-03 2016-09-13 Sandisk Technologies Llc Method and system for rebalancing data stored in flash memory devices
US9519577B2 (en) 2013-09-03 2016-12-13 Sandisk Technologies Llc Method and system for migrating data between flash memory devices
US20150169406A1 (en) * 2013-12-16 2015-06-18 Sandisk Technologies Inc. Decoding techniques for a data storage device
US9553608B2 (en) 2013-12-20 2017-01-24 Sandisk Technologies Llc Data storage device decoder and method of operation
CN103927262A (en) * 2014-03-21 2014-07-16 深圳市硅格半导体有限公司 Flash memory physical block control method and flash memory physical block control device
US9495232B2 (en) * 2014-03-28 2016-11-15 Intel IP Corporation Error correcting (ECC) memory compatibility
JP6269253B2 (en) * 2014-03-29 2018-01-31 富士通株式会社 Distributed storage system, storage device control method, and storage device control program
CN103942151A (en) * 2014-04-10 2014-07-23 深圳市硅格半导体有限公司 Data storage method and device for flash memory
CN103984506B (en) * 2014-04-30 2017-06-30 深圳市江波龙电子有限公司 The method and system that data of flash memory storage equipment is write
US9645749B2 (en) 2014-05-30 2017-05-09 Sandisk Technologies Llc Method and system for recharacterizing the storage density of a memory device or a portion thereof
US8891303B1 (en) 2014-05-30 2014-11-18 Sandisk Technologies Inc. Method and system for dynamic word line based configuration of a three-dimensional memory device
US9972393B1 (en) * 2014-07-03 2018-05-15 Avago Technologies General Ip (Singapore) Pte. Ltd. Accelerating programming of a flash memory module
CN105320464B (en) * 2014-07-21 2018-07-31 群联电子股份有限公司 Prevent method, memorizer control circuit unit and the storage device of reading interference
US20160041760A1 (en) * 2014-08-08 2016-02-11 International Business Machines Corporation Multi-Level Cell Flash Memory Control Mechanisms
US9519427B2 (en) 2014-09-02 2016-12-13 Sandisk Technologies Llc Triggering, at a host system, a process to reduce declared capacity of a storage device
US9582193B2 (en) * 2014-09-02 2017-02-28 Sandisk Technologies Llc Triggering a process to reduce declared capacity of a storage device in a multi-storage-device storage system
US9563362B2 (en) 2014-09-02 2017-02-07 Sandisk Technologies Llc Host system and process to reduce declared capacity of a storage device by trimming
US9582202B2 (en) 2014-09-02 2017-02-28 Sandisk Technologies Llc Process and apparatus to reduce declared capacity of a storage device by moving data
US9524105B2 (en) 2014-09-02 2016-12-20 Sandisk Technologies Llc Process and apparatus to reduce declared capacity of a storage device by altering an encoding format
US9582212B2 (en) * 2014-09-02 2017-02-28 Sandisk Technologies Llc Notification of trigger condition to reduce declared capacity of a storage device
US9563370B2 (en) 2014-09-02 2017-02-07 Sandisk Technologies Llc Triggering a process to reduce declared capacity of a storage device
US9582203B2 (en) * 2014-09-02 2017-02-28 Sandisk Technologies Llc Process and apparatus to reduce declared capacity of a storage device by reducing a range of logical addresses
US9652153B2 (en) 2014-09-02 2017-05-16 Sandisk Technologies Llc Process and apparatus to reduce declared capacity of a storage device by reducing a count of logical addresses
US9524112B2 (en) 2014-09-02 2016-12-20 Sandisk Technologies Llc Process and apparatus to reduce declared capacity of a storage device by trimming
US9552166B2 (en) 2014-09-02 2017-01-24 Sandisk Technologies Llc. Process and apparatus to reduce declared capacity of a storage device by deleting data
US9582220B2 (en) * 2014-09-02 2017-02-28 Sandisk Technologies Llc Notification of trigger condition to reduce declared capacity of a storage device in a multi-storage-device storage system
US9665311B2 (en) 2014-09-02 2017-05-30 Sandisk Technologies Llc Process and apparatus to reduce declared capacity of a storage device by making specific logical addresses unavailable
US9852799B2 (en) * 2014-11-19 2017-12-26 Sandisk Technologies Llc Configuration parameter management for non-volatile data storage
TWI578320B (en) 2014-11-25 2017-04-11 旺宏電子股份有限公司 Memory operating method and memory device using the same
CN105843748B (en) * 2015-01-15 2019-06-11 华为技术有限公司 The processing method and processing device of page in a kind of pair of memory
CN105988716A (en) * 2015-02-09 2016-10-05 深圳市硅格半导体有限公司 Storage device and mode conversion method thereof
US9639282B2 (en) 2015-05-20 2017-05-02 Sandisk Technologies Llc Variable bit encoding per NAND flash cell to improve device endurance and extend life of flash-based storage devices
US9606737B2 (en) 2015-05-20 2017-03-28 Sandisk Technologies Llc Variable bit encoding per NAND flash cell to extend life of flash-based storage devices and preserve over-provisioning
CN106356093B (en) * 2015-07-17 2019-11-01 旺宏电子股份有限公司 The operating method of memory and the memory device for applying it
US10096355B2 (en) * 2015-09-01 2018-10-09 Sandisk Technologies Llc Dynamic management of programming states to improve endurance
WO2017075747A1 (en) * 2015-11-02 2017-05-11 Shine Bright Technology Limited Methods, systems, and media for programming storage device
CN106843744B (en) * 2015-12-03 2020-05-26 群联电子股份有限公司 Data programming method and memory storage device
US9946483B2 (en) 2015-12-03 2018-04-17 Sandisk Technologies Llc Efficiently managing unmapped blocks to extend life of solid state drive with low over-provisioning
US9946473B2 (en) 2015-12-03 2018-04-17 Sandisk Technologies Llc Efficiently managing unmapped blocks to extend life of solid state drive
KR20170076883A (en) * 2015-12-24 2017-07-05 에스케이하이닉스 주식회사 Memory system and operation method for the same
US10110255B2 (en) 2016-04-27 2018-10-23 Silicon Motion Inc. Method for accessing flash memory module and associated flash memory controller and memory device
US9910772B2 (en) 2016-04-27 2018-03-06 Silicon Motion Inc. Flash memory apparatus and storage management method for flash memory
US10019314B2 (en) 2016-04-27 2018-07-10 Silicon Motion Inc. Flash memory apparatus and storage management method for flash memory
CN107391296B (en) 2016-04-27 2020-11-06 慧荣科技股份有限公司 Method for accessing flash memory module and related flash memory controller and memory device
CN111679787B (en) 2016-04-27 2023-07-18 慧荣科技股份有限公司 Flash memory device, flash memory controller and flash memory storage management method
US10289487B2 (en) 2016-04-27 2019-05-14 Silicon Motion Inc. Method for accessing flash memory module and associated flash memory controller and memory device
CN107391026B (en) * 2016-04-27 2020-06-02 慧荣科技股份有限公司 Flash memory device and flash memory management method
US10025662B2 (en) 2016-04-27 2018-07-17 Silicon Motion Inc. Flash memory apparatus and storage management method for flash memory
US10983865B2 (en) * 2016-08-01 2021-04-20 Hewlett Packard Enterprise Development Lp Adjusting memory parameters
JP6730604B2 (en) * 2016-11-01 2020-07-29 富士通株式会社 Control circuit, semiconductor memory device, and method of controlling semiconductor memory device
KR20180101760A (en) * 2017-03-06 2018-09-14 에스케이하이닉스 주식회사 Storage device, data processing system and operating method thereof
US10452282B2 (en) * 2017-04-07 2019-10-22 Micron Technology, Inc. Memory management
US10346335B1 (en) * 2017-07-11 2019-07-09 American Megatrends, Inc. Solid-state drive dock having local and network interfaces
CN107689796B (en) * 2017-07-28 2021-03-26 同济大学 Lossless compressed file fault-tolerant decompression method based on prior information
US10877898B2 (en) 2017-11-16 2020-12-29 Alibaba Group Holding Limited Method and system for enhancing flash translation layer mapping flexibility for performance and lifespan improvements
US10496548B2 (en) 2018-02-07 2019-12-03 Alibaba Group Holding Limited Method and system for user-space storage I/O stack with user-space flash translation layer
WO2019222958A1 (en) 2018-05-24 2019-11-28 Alibaba Group Holding Limited System and method for flash storage management using multiple open page stripes
US11209998B2 (en) * 2018-06-11 2021-12-28 Western Digital Technologies, Inc. Adjustment of storage device parameters based on workload characteristics
WO2020000136A1 (en) 2018-06-25 2020-01-02 Alibaba Group Holding Limited System and method for managing resources of a storage device and quantifying the cost of i/o requests
US10921992B2 (en) 2018-06-25 2021-02-16 Alibaba Group Holding Limited Method and system for data placement in a hard disk drive based on access frequency for improved IOPS and utilization efficiency
US10996886B2 (en) 2018-08-02 2021-05-04 Alibaba Group Holding Limited Method and system for facilitating atomicity and latency assurance on variable sized I/O
US11327929B2 (en) 2018-09-17 2022-05-10 Alibaba Group Holding Limited Method and system for reduced data movement compression using in-storage computing and a customized file system
CN109388343B (en) * 2018-09-26 2020-08-28 深圳市德明利技术股份有限公司 Data storage method and memory
CN111324283B (en) * 2018-12-14 2024-02-20 兆易创新科技集团股份有限公司 Memory device
CN111324291B (en) * 2018-12-14 2024-02-20 兆易创新科技集团股份有限公司 Memory device
US10977122B2 (en) 2018-12-31 2021-04-13 Alibaba Group Holding Limited System and method for facilitating differentiated error correction in high-density flash devices
US11061735B2 (en) 2019-01-02 2021-07-13 Alibaba Group Holding Limited System and method for offloading computation to storage nodes in distributed system
US11132291B2 (en) 2019-01-04 2021-09-28 Alibaba Group Holding Limited System and method of FPGA-executed flash translation layer in multiple solid state drives
US11200337B2 (en) 2019-02-11 2021-12-14 Alibaba Group Holding Limited System and method for user data isolation
US10970212B2 (en) 2019-02-15 2021-04-06 Alibaba Group Holding Limited Method and system for facilitating a distributed storage system with a total cost of ownership reduction for multiple available zones
US11061834B2 (en) 2019-02-26 2021-07-13 Alibaba Group Holding Limited Method and system for facilitating an improved storage system by decoupling the controller from the storage medium
US10891065B2 (en) * 2019-04-01 2021-01-12 Alibaba Group Holding Limited Method and system for online conversion of bad blocks for improvement of performance and longevity in a solid state drive
US10922234B2 (en) 2019-04-11 2021-02-16 Alibaba Group Holding Limited Method and system for online recovery of logical-to-physical mapping table affected by noise sources in a solid state drive
US10908960B2 (en) 2019-04-16 2021-02-02 Alibaba Group Holding Limited Resource allocation based on comprehensive I/O monitoring in a distributed storage system
US11169873B2 (en) 2019-05-21 2021-11-09 Alibaba Group Holding Limited Method and system for extending lifespan and enhancing throughput in a high-density solid state drive
US10860223B1 (en) 2019-07-18 2020-12-08 Alibaba Group Holding Limited Method and system for enhancing a distributed storage system by decoupling computation and network tasks
US11074124B2 (en) 2019-07-23 2021-07-27 Alibaba Group Holding Limited Method and system for enhancing throughput of big data analysis in a NAND-based read source storage
CN110473586B (en) * 2019-07-31 2021-05-14 珠海博雅科技有限公司 Replacement method, device and equipment for write failure storage unit and storage medium
US11126561B2 (en) 2019-10-01 2021-09-21 Alibaba Group Holding Limited Method and system for organizing NAND blocks and placing data to facilitate high-throughput for random writes in a solid state drive
US11617282B2 (en) 2019-10-01 2023-03-28 Alibaba Group Holding Limited System and method for reshaping power budget of cabinet to facilitate improved deployment density of servers
US11449455B2 (en) 2020-01-15 2022-09-20 Alibaba Group Holding Limited Method and system for facilitating a high-capacity object storage system with configuration agility and mixed deployment flexibility
US11150986B2 (en) 2020-02-26 2021-10-19 Alibaba Group Holding Limited Efficient compaction on log-structured distributed file system using erasure coding for resource consumption reduction
US11200114B2 (en) 2020-03-17 2021-12-14 Alibaba Group Holding Limited System and method for facilitating elastic error correction code in memory
US11385833B2 (en) 2020-04-20 2022-07-12 Alibaba Group Holding Limited Method and system for facilitating a light-weight garbage collection with a reduced utilization of resources
US11281575B2 (en) 2020-05-11 2022-03-22 Alibaba Group Holding Limited Method and system for facilitating data placement and control of physical addresses with multi-queue I/O blocks
US11494115B2 (en) 2020-05-13 2022-11-08 Alibaba Group Holding Limited System method for facilitating memory media as file storage device based on real-time hashing by performing integrity check with a cyclical redundancy check (CRC)
US11461262B2 (en) 2020-05-13 2022-10-04 Alibaba Group Holding Limited Method and system for facilitating a converged computation and storage node in a distributed storage system
US11218165B2 (en) 2020-05-15 2022-01-04 Alibaba Group Holding Limited Memory-mapped two-dimensional error correction code for multi-bit error tolerance in DRAM
US11507499B2 (en) 2020-05-19 2022-11-22 Alibaba Group Holding Limited System and method for facilitating mitigation of read/write amplification in data compression
US11556277B2 (en) 2020-05-19 2023-01-17 Alibaba Group Holding Limited System and method for facilitating improved performance in ordering key-value storage with input/output stack simplification
US11263132B2 (en) 2020-06-11 2022-03-01 Alibaba Group Holding Limited Method and system for facilitating log-structure data organization
US11422931B2 (en) 2020-06-17 2022-08-23 Alibaba Group Holding Limited Method and system for facilitating a physically isolated storage unit for multi-tenancy virtualization
US11354200B2 (en) 2020-06-17 2022-06-07 Alibaba Group Holding Limited Method and system for facilitating data recovery and version rollback in a storage device
US11138071B1 (en) 2020-06-22 2021-10-05 Western Digital Technologies, Inc. On-chip parity buffer management for storage block combining in non-volatile memory
US11354233B2 (en) 2020-07-27 2022-06-07 Alibaba Group Holding Limited Method and system for facilitating fast crash recovery in a storage device
US11372774B2 (en) 2020-08-24 2022-06-28 Alibaba Group Holding Limited Method and system for a solid state drive with on-chip memory integration
US11487465B2 (en) 2020-12-11 2022-11-01 Alibaba Group Holding Limited Method and system for a local storage engine collaborating with a solid state drive controller
US11734115B2 (en) 2020-12-28 2023-08-22 Alibaba Group Holding Limited Method and system for facilitating write latency reduction in a queue depth of one scenario
US11416365B2 (en) 2020-12-30 2022-08-16 Alibaba Group Holding Limited Method and system for open NAND block detection and correction in an open-channel SSD
US11726699B2 (en) 2021-03-30 2023-08-15 Alibaba Singapore Holding Private Limited Method and system for facilitating multi-stream sequential read performance improvement with reduced read amplification
US11461173B1 (en) 2021-04-21 2022-10-04 Alibaba Singapore Holding Private Limited Method and system for facilitating efficient data compression based on error correction code and reorganization of data placement
US11476874B1 (en) 2021-05-14 2022-10-18 Alibaba Singapore Holding Private Limited Method and system for facilitating a storage server with hybrid memory for journaling and data storage
TWI788161B (en) * 2021-12-27 2022-12-21 技嘉科技股份有限公司 Control method for dynamically adjusting the ratio of single-level cells and three-level cells
US11687290B1 (en) * 2022-01-13 2023-06-27 Silicon Motion, Inc. Method for improve read disturbance phenomenon of flash memory module and associated flash memory controller and electronic device
CN115657972B (en) * 2022-12-27 2023-06-06 北京特纳飞电子技术有限公司 Solid state disk writing control method and device and solid state disk

Citations (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5283792A (en) * 1990-10-19 1994-02-01 Benchmarq Microelectronics, Inc. Power up/power down controller and power fail detector for processor
US5420798A (en) * 1993-09-30 1995-05-30 Macronix International Co., Ltd. Supply voltage detection circuit
US5438549A (en) * 1994-02-28 1995-08-01 Intel Corporation Nonvolatile memory with volatile memory buffer and a backup power supply system
US5914543A (en) * 1991-06-11 1999-06-22 Dallas Semiconductor Corporation Systems and methods for memory control
US20040080858A1 (en) * 2002-11-12 2004-04-29 Fujitsu Limited Disk apparatus, head retracting method and head actuator control circuit
US20040158778A1 (en) * 2003-02-07 2004-08-12 Renesas Technology Corp. Nonvolatile memory system
US20040177216A1 (en) * 2003-03-03 2004-09-09 Renesas Technology Corp. Nonvolatile memory and method of address management
US6856556B1 (en) * 2003-04-03 2005-02-15 Siliconsystems, Inc. Storage subsystem with embedded circuit for protecting against anomalies in power signal from host
US20050169057A1 (en) * 2004-01-30 2005-08-04 Noboru Shibata Semiconductor memory device which stores plural data in a cell
US20060020855A1 (en) * 2004-07-21 2006-01-26 Naoki Okada Storage device and storage device power consumption control method
US20070006013A1 (en) * 2000-12-22 2007-01-04 Simpletech, Inc. Solid-state memory device with protection against power failure
US20070240017A1 (en) * 2006-04-11 2007-10-11 Hitachi, Ltd. Storage apparatus power supply unit and storage apparatus management method
US20080010483A1 (en) * 2006-05-11 2008-01-10 Fuji Xerox Co., Ltd. Computer readable medium storing an error recovery program, error recovery method, error recovery apparatus, and computer system
US20080082849A1 (en) * 2006-09-29 2008-04-03 Hitachi, Ltd. Method and apparatus for monitoring power supply failure
US20080172523A1 (en) * 2007-01-11 2008-07-17 Hitachi, Ltd. Flash memory module, storage apparatus using flash memory module as storage medium, and address translation table verification method for flash memory module
US20090031099A1 (en) * 2007-07-25 2009-01-29 Simtek Power interrupt recovery in a hybrid memory subsystem
US20090106484A1 (en) * 2007-10-19 2009-04-23 Phison Electronics Corp. Data writing method for non-volatile memory and controller using the same
US20090154280A1 (en) * 2007-12-13 2009-06-18 Kabushiki Kaisha Toshiba Nonvolatile memory device
US20090204852A1 (en) * 2008-02-07 2009-08-13 Siliconsystems, Inc. Solid state storage subsystem that maintains and provides access to data reflective of a failure risk
US20090235038A1 (en) * 2007-07-25 2009-09-17 Agiga Tech Inc. Hybrid memory system with backup power source and multiple backup an restore methodology
US20100005229A1 (en) * 2008-07-02 2010-01-07 Silicon Motion, Inc. Flash memory apparatus and method for securing a flash memory from data damage
US20100011153A1 (en) * 2008-07-10 2010-01-14 Phison Electronics Corp. Block management method, and storage system and controller using the same
US20100107016A1 (en) * 2007-03-23 2010-04-29 Gerald Adolph Colman System and method for preventing errors ina storage medium
US20100146333A1 (en) * 2008-12-09 2010-06-10 Samsung Electronics Co., Ltd. Auxiliary power supply and user device including the same
US20100332860A1 (en) * 2009-06-26 2010-12-30 Jon David Trantham Systems, methods and devices for configurable power control with storage devices

Family Cites Families (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5539690A (en) * 1994-06-02 1996-07-23 Intel Corporation Write verify schemes for flash memory with multilevel cells
US5485422A (en) * 1994-06-02 1996-01-16 Intel Corporation Drain bias multiplexing for multiple bit flash cell
US5671388A (en) * 1995-05-03 1997-09-23 Intel Corporation Method and apparatus for performing write operations in multi-level cell storage device
JP3200012B2 (en) * 1996-04-19 2001-08-20 株式会社東芝 Storage system
US6538923B1 (en) * 2001-02-26 2003-03-25 Advanced Micro Devices, Inc. Staircase program verify for multi-level cell flash memory designs
US7554842B2 (en) * 2001-09-17 2009-06-30 Sandisk Corporation Multi-purpose non-volatile memory card
US6714457B1 (en) * 2001-09-19 2004-03-30 Aplus Flash Technology, Inc. Parallel channel programming scheme for MLC flash memory
TW594466B (en) * 2002-06-10 2004-06-21 Micro Star Int Co Ltd Power management method for microprocessor
JP4073799B2 (en) * 2003-02-07 2008-04-09 株式会社ルネサステクノロジ Memory system
US7089461B2 (en) * 2003-03-20 2006-08-08 International Business Machines Corporation Method and apparatus for isolating uncorrectable errors while system continues to run
JP3878573B2 (en) * 2003-04-16 2007-02-07 株式会社東芝 Nonvolatile semiconductor memory device
TWI231901B (en) * 2003-09-19 2005-05-01 Topro Technology Inc Integration control chip having the power control
US7012835B2 (en) * 2003-10-03 2006-03-14 Sandisk Corporation Flash memory data correction and scrub techniques
KR100719380B1 (en) * 2006-03-31 2007-05-18 삼성전자주식회사 Multi-valued nonvolatile memory device with enhanced reliability and memory system having the same
KR100574989B1 (en) * 2004-11-04 2006-05-02 삼성전자주식회사 Memory device for improving efficiency of data strobe bus line and memory system including the same, and data strobe signal control method thereof
TWI258074B (en) * 2004-12-24 2006-07-11 Phison Electronics Corp Method for reducing data error when flash memory storage device executing copy back command
US7221592B2 (en) * 2005-02-25 2007-05-22 Micron Technology, Inc. Multiple level programming in a non-volatile memory device
US7958430B1 (en) * 2005-06-20 2011-06-07 Cypress Semiconductor Corporation Flash memory device and method
KR100616214B1 (en) * 2005-06-30 2006-08-28 주식회사 하이닉스반도체 Control circuit and method for programming a flash memory device with multi-level cells
US7362611B2 (en) * 2005-08-30 2008-04-22 Micron Technology, Inc. Non-volatile memory copy back
KR20070076849A (en) * 2006-01-20 2007-07-25 삼성전자주식회사 Apparatus and method for accomplishing copy-back operation in memory card
US8046660B2 (en) * 2006-08-07 2011-10-25 Marvell World Trade Ltd. System and method for correcting errors in non-volatile memory using product codes
KR100919156B1 (en) * 2006-08-24 2009-09-28 삼성전자주식회사 Multi-bit flash memory device and program method thereof
KR100755718B1 (en) * 2006-09-04 2007-09-05 삼성전자주식회사 Apparatus and method for managing run-time bad block in mlc flash memory
KR100764747B1 (en) * 2006-09-15 2007-10-08 삼성전자주식회사 Flash memory device and program method thereof
US7692949B2 (en) * 2006-12-04 2010-04-06 Qimonda North America Corp. Multi-bit resistive memory
KR100918707B1 (en) * 2007-03-12 2009-09-23 삼성전자주식회사 Flash memory-based memory system
WO2009013879A1 (en) * 2007-07-20 2009-01-29 Panasonic Corporation Memory controller and non-volatile storage device using same
JP2009087509A (en) * 2007-10-03 2009-04-23 Toshiba Corp Semiconductor storage device
US20090106513A1 (en) * 2007-10-22 2009-04-23 Chuang Cheng Method for copying data in non-volatile memory system
US8694714B2 (en) * 2008-01-18 2014-04-08 Spansion Llc Retargeting of a write operation retry in the event of a write operation failure
US8271515B2 (en) * 2008-01-29 2012-09-18 Cadence Design Systems, Inc. System and method for providing copyback data integrity in a non-volatile memory system
CN101226774A (en) * 2008-02-15 2008-07-23 祥硕科技股份有限公司 Method for reducing data error in flash memory device when using copy back instruction
US8060719B2 (en) * 2008-05-28 2011-11-15 Micron Technology, Inc. Hybrid memory management
TWI473117B (en) * 2008-06-04 2015-02-11 A Data Technology Co Ltd Flash storage device with data correction function
TWI416524B (en) * 2008-06-25 2013-11-21 Silicon Motion Inc Memory device and data storing method
US8843691B2 (en) * 2008-06-25 2014-09-23 Stec, Inc. Prioritized erasure of data blocks in a flash storage device
KR101490421B1 (en) * 2008-07-11 2015-02-06 삼성전자주식회사 Nonvolatile memory device supressing interference between memory cells, computing system and programming method thereof
US7864587B2 (en) * 2008-09-22 2011-01-04 Micron Technology, Inc. Programming a memory device to increase data reliability
JP5192352B2 (en) * 2008-10-30 2013-05-08 株式会社日立製作所 Storage device and data storage area management method
CN101446927B (en) * 2008-12-26 2010-12-01 祥硕科技股份有限公司 Flash memory system and control method thereof
US8151137B2 (en) * 2009-05-28 2012-04-03 Lsi Corporation Systems and methods for governing the life cycle of a solid state drive
US9170879B2 (en) * 2009-06-24 2015-10-27 Headway Technologies, Inc. Method and apparatus for scrubbing accumulated data errors from a memory system
US8261136B2 (en) * 2009-06-29 2012-09-04 Sandisk Technologies Inc. Method and device for selectively refreshing a region of a memory of a data storage device
TWI408688B (en) * 2009-10-12 2013-09-11 Phison Electronics Corp Data writing method for a flash memory, and controller and storage system using the same
US8656256B2 (en) * 2010-07-07 2014-02-18 Stec, Inc. Apparatus and method for multi-mode operation of a flash memory device

Patent Citations (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5283792A (en) * 1990-10-19 1994-02-01 Benchmarq Microelectronics, Inc. Power up/power down controller and power fail detector for processor
US5914543A (en) * 1991-06-11 1999-06-22 Dallas Semiconductor Corporation Systems and methods for memory control
US5420798A (en) * 1993-09-30 1995-05-30 Macronix International Co., Ltd. Supply voltage detection circuit
US5438549A (en) * 1994-02-28 1995-08-01 Intel Corporation Nonvolatile memory with volatile memory buffer and a backup power supply system
US20070006013A1 (en) * 2000-12-22 2007-01-04 Simpletech, Inc. Solid-state memory device with protection against power failure
US20040080858A1 (en) * 2002-11-12 2004-04-29 Fujitsu Limited Disk apparatus, head retracting method and head actuator control circuit
US20040158778A1 (en) * 2003-02-07 2004-08-12 Renesas Technology Corp. Nonvolatile memory system
US20040177216A1 (en) * 2003-03-03 2004-09-09 Renesas Technology Corp. Nonvolatile memory and method of address management
US20050122791A1 (en) * 2003-04-03 2005-06-09 Hajeck Michael J. Storage subsystem with embedded circuit for protecting against anomalies in power signal from host
US7126857B2 (en) * 2003-04-03 2006-10-24 Siliconsystems, Inc. Storage subsystem with embedded circuit for protecting against anomalies in power signal from host
US6856556B1 (en) * 2003-04-03 2005-02-15 Siliconsystems, Inc. Storage subsystem with embedded circuit for protecting against anomalies in power signal from host
US20050169057A1 (en) * 2004-01-30 2005-08-04 Noboru Shibata Semiconductor memory device which stores plural data in a cell
US20060020855A1 (en) * 2004-07-21 2006-01-26 Naoki Okada Storage device and storage device power consumption control method
US20070240017A1 (en) * 2006-04-11 2007-10-11 Hitachi, Ltd. Storage apparatus power supply unit and storage apparatus management method
US20080010483A1 (en) * 2006-05-11 2008-01-10 Fuji Xerox Co., Ltd. Computer readable medium storing an error recovery program, error recovery method, error recovery apparatus, and computer system
US20080082849A1 (en) * 2006-09-29 2008-04-03 Hitachi, Ltd. Method and apparatus for monitoring power supply failure
US20080172523A1 (en) * 2007-01-11 2008-07-17 Hitachi, Ltd. Flash memory module, storage apparatus using flash memory module as storage medium, and address translation table verification method for flash memory module
US20100107016A1 (en) * 2007-03-23 2010-04-29 Gerald Adolph Colman System and method for preventing errors ina storage medium
US20090031099A1 (en) * 2007-07-25 2009-01-29 Simtek Power interrupt recovery in a hybrid memory subsystem
US20090235038A1 (en) * 2007-07-25 2009-09-17 Agiga Tech Inc. Hybrid memory system with backup power source and multiple backup an restore methodology
US20090106484A1 (en) * 2007-10-19 2009-04-23 Phison Electronics Corp. Data writing method for non-volatile memory and controller using the same
US20090154280A1 (en) * 2007-12-13 2009-06-18 Kabushiki Kaisha Toshiba Nonvolatile memory device
US20090204852A1 (en) * 2008-02-07 2009-08-13 Siliconsystems, Inc. Solid state storage subsystem that maintains and provides access to data reflective of a failure risk
US20100005229A1 (en) * 2008-07-02 2010-01-07 Silicon Motion, Inc. Flash memory apparatus and method for securing a flash memory from data damage
US20100011153A1 (en) * 2008-07-10 2010-01-14 Phison Electronics Corp. Block management method, and storage system and controller using the same
US20100146333A1 (en) * 2008-12-09 2010-06-10 Samsung Electronics Co., Ltd. Auxiliary power supply and user device including the same
US20100332860A1 (en) * 2009-06-26 2010-12-30 Jon David Trantham Systems, methods and devices for configurable power control with storage devices

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150149706A1 (en) * 2013-11-27 2015-05-28 NXGN Data, Inc. System and method for efficient flash translation layer
US9348760B2 (en) * 2013-11-27 2016-05-24 NXGN Data, Inc. System and method for efficient flash translation layer
TWI573142B (en) * 2015-02-02 2017-03-01 慧榮科技股份有限公司 Data storage device and data maintenance method thereof
US20230027611A1 (en) * 2021-07-26 2023-01-26 Realtek Semiconductor Corporation Power supply device, power supply system and non-transitory computer-readable recording medium

Also Published As

Publication number Publication date
CN101937710A (en) 2011-01-05
TWI406126B (en) 2013-08-21
CN101937724A (en) 2011-01-05
CN101937318A (en) 2011-01-05
TW201101320A (en) 2011-01-01
TW201101026A (en) 2011-01-01
TW201101309A (en) 2011-01-01
TWI449052B (en) 2014-08-11
CN101937724B (en) 2013-11-06
US20100332922A1 (en) 2010-12-30
US8458566B2 (en) 2013-06-04
US20100332951A1 (en) 2010-12-30
TWI457937B (en) 2014-10-21

Similar Documents

Publication Publication Date Title
US20100332887A1 (en) Storage control device having controller operated according to detection signal derived from monitoring power signal and related method thereof
US8009502B2 (en) Systems, methods and devices for power control in mass storage devices
US9639131B2 (en) Systems, methods and devices for control of the operation of data storage devices using solid-state memory
US8504762B2 (en) Flash memory storage device with data interface
US7134032B2 (en) Method and apparatus for changing power modes based on monitored I/O packets
US7525745B2 (en) Magnetic disk drive apparatus and method of controlling the same
US7318118B2 (en) System and method for selective write to flash memory in HDD
US9645769B2 (en) Performance acceleration during shutdown of a data storage device
US20080172519A1 (en) Methods For Supporting Readydrive And Readyboost Accelerators In A Single Flash-Memory Storage Device
US6775744B2 (en) Disk memory device
US9396755B2 (en) Temperature-defined data-storage policy for a hybrid disk drive
CN110764964B (en) Memory device and control method thereof
US20180059970A1 (en) Storage device and method of writing data into storage device
US6633450B1 (en) Method of and apparatus for controlling disk drive
US7174421B2 (en) HDD with rapid availability of critical data after critical event
US10096371B2 (en) Data storage device and operating method thereof
US20070143535A1 (en) Memory apparatus
US20100037004A1 (en) Storage system for backup data of flash memory and method for the same
JP4078155B2 (en) Magnetic disk apparatus and control method thereof
JP3892007B2 (en) Disk drive control method and control apparatus
JP4426223B2 (en) Information processing apparatus and information processing system
JP2007180693A (en) Video signal recording device
US20120236702A1 (en) Method of controlling mechanical mechanisms of electronic device for peak power/current reduction
KR100904431B1 (en) Apparatus and method for repreoducing data of recording medium
CN113535616A (en) Computer readable storage medium, method and device for controlling access of flash memory device

Legal Events

Date Code Title Description
AS Assignment

Owner name: MEDIATEK INC., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LIN, TZU-CHIEH;HUNG, TZU-LI;CHAO, KUAN-HUA;AND OTHERS;REEL/FRAME:024105/0139

Effective date: 20100302

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION