US20110042759A1 - Switching device having a molybdenum oxynitride metal gate - Google Patents

Switching device having a molybdenum oxynitride metal gate Download PDF

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US20110042759A1
US20110042759A1 US12/545,343 US54534309A US2011042759A1 US 20110042759 A1 US20110042759 A1 US 20110042759A1 US 54534309 A US54534309 A US 54534309A US 2011042759 A1 US2011042759 A1 US 2011042759A1
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fet
dielectric
region
mon
gate
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US12/545,343
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Nestor A. Bojarczuk
Michael P. Chudzik
Matthew W. Copel
Supratik Guha
Richard A. Haight
Vijay Narayanan
Martin P. O'Boyle
Vamsi K. Paruchuri
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GlobalFoundries Inc
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International Business Machines Corp
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Priority to US12/545,343 priority Critical patent/US20110042759A1/en
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHUDZIK, MICHAEL P., PARUCHURI, VAMSI K., BOJARCZUK, NESTOR A., COPEL, MATTHEW W., GUHA, SUPRATIK, HAIGHT, RICHARD A., NARAYANAN, VIJAY, O'BOYLE, MARTIN P.
Publication of US20110042759A1 publication Critical patent/US20110042759A1/en
Priority to US13/536,366 priority patent/US8518766B2/en
Assigned to GLOBALFOUNDRIES U.S. 2 LLC reassignment GLOBALFOUNDRIES U.S. 2 LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INTERNATIONAL BUSINESS MACHINES CORPORATION
Assigned to GLOBALFOUNDRIES INC. reassignment GLOBALFOUNDRIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GLOBALFOUNDRIES U.S. 2 LLC, GLOBALFOUNDRIES U.S. INC.
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith

Definitions

  • the present invention relates to switching devices, and more specifically, to metal gate transistors.
  • high-k dielectric refers to a material with a high dielectric constant (k) (as compared to silicon dioxide) used in semiconductor manufacturing processes which replaces the silicon dioxide gate dielectric.
  • k dielectric constant
  • the implementation of high-k gate dielectrics is one of several strategies developed to allow further miniaturization of microelectronic components.
  • Silicon dioxide has been used as a gate oxide material for decades. As transistors have decreased in size, the thickness of the silicon dioxide gate dielectric has steadily decreased to increase the gate capacitance and thereby drive current and device performance. As the thickness scales below 2 nm, leakage currents due to tunneling increase drastically, leading to unwieldy power consumption and reduced device reliability. Replacing the silicon dioxide gate dielectric with a high-k material allows increased gate capacitance without the concomitant leakage effects.
  • a field effect transistor FET
  • the FET of this embodiment includes a body region and a source region disposed at least partially in the body region.
  • the FET of this embodiment also includes a drain region disposed at least partially in the body region and a molybdenum oxynitride (MoNO) gate.
  • MoNO molybdenum oxynitride
  • the FET of this embodiment also includes a dielectric having a high dielectric constant (k) disposed between the body region and the MoNO gate.
  • Another embodiment of the present invention is directed to a method of forming a field effect transistor (FET).
  • the method of this embodiment includes forming a high k dielectric layer over a body region, forming a molybdenum nitride (MoN x ) layer over the high k dielectric layer, and converting the MoN x to molybdenum oxynitride (MoNO).
  • MoN x molybdenum nitride
  • MoNO molybdenum oxynitride
  • FIG. 1 is a cross-sectional view of a field-effect transistor (FET) according to one embodiment of the present invention.
  • FIG. 2 is a flow diagram illustrating a method for forming a gate structure for a P-FET according to one embodiment of the present invention.
  • a high work function material In order to fabricate a useful field-effect transistor (FET) metal-oxide-semiconductor (MOS) a high work function material must be deposited as the gate metal atop a dielectric material resident on a silicon (Si) substrate.
  • the dielectric can be silicon dioxide (SiO 2 ).
  • a high dielectric having a higher k value than SiO 2 such haffiium oxide (HfO 2 ), to allow for a physically thicker layer, and hence reduced current leakage.
  • the use of a high work function metal is needed to induce band bending in the underlying Si body which brings the valence band edge of Si close to the Fermi level, thereby reducing the threshold voltage to a minimum ( ⁇ 100-200 meV) acceptable level for good device performance.
  • the “work function” of a metal is the minimum energy (usually measured in electron volts) needed to remove an electron from a solid to a point immediately outside the solid surface (or energy needed to move an electron from the Fermi energy level into vacuum).
  • the gate metal in order for the gate metal to be acceptable, it should maintain this high effective work function by withstanding integration process anneal temperatures up to 1000° C. Typically after this high temperature anneal the Fermi level moves to the middle of the Si gap which is unsuitable for P-FET operation. Prior to the invention disclosed herein, no candidate P-FET gate metals have been identified which maintain this high effective work function after 1000° C. anneals.
  • the FET 100 may include a substrate 102 .
  • the substrate 102 may be formed, for example, of a semiconductor material.
  • the FET 100 may also include a source region 104 and a drain region 106 .
  • the substrate 102 in the event that the FET 100 is a P-FET, the substrate 102 may be formed of an N-type semiconductor and referred to as a “body” or “base” and the source region 104 and the drain region 106 may be formed of a P-type semiconductor.
  • the FET 100 may also include a source contact 108 formed on top of the source region 104 and a drain contact 110 formed on top of the drain region 106 .
  • the portion of the body 102 between the source region 104 and the drain region 106 is referred to herein as the channel 112 .
  • the FET 100 may also include a gate dielectric 114 disposed above the channel 112 .
  • the gate dielectric 114 may also be disposed such that it is above a portion of one or both of the source region 104 and the drain region 106 .
  • the gate dielectric 114 is disposed only over the channel 112 . That is, the gate dielectric 114 may not be disposed over either the source region 104 or the drain region 106 .
  • the gate dielectric 114 contacts the source contact 108 and the drain contact 110 . In one embodiment, the gate dielectric 114 does not contact one or both of the source contact 108 and the drain contact 110 .
  • the gate dielectric 114 is formed a dielectric having a high-k value as compared to silicon dioxide.
  • a material is a hafnium based material such as HfO 2 or a similar material.
  • a high-k dielectric shall refer to a material that has a k value of 3.0 or greater. In a particular embodiment, the high-k dielectric may have a k value between 4.0 and 100.
  • the FET 100 may also include a gate metal 116 disposed above the gate dielectric 114 .
  • the gate metal 116 is formed of molybdenum oxynitride (MoNO).
  • MoNO molybdenum oxynitride
  • the gate metal may be formed of MoNO x .
  • MoNO MoNO x
  • the gate metal is a one nanometer thick layer of MoNO.
  • MoNO maintains an effective work function stability after anneals to 1000° C. for 5 seconds, the typical temperature and length of anneal that devices are subjected to during processing.
  • FIG. 2 shows a method of forming a P-FET with a metal gate according to one embodiment of the present invention.
  • a block 202 at least an n-doped silicon silicon substrate is provided.
  • a high k dielectric is formed over the substrate.
  • the high k dielectric may be, for example, HfO 2 .
  • HfO 2 high k dielectrics
  • a 2.5-3 nm thick layer of HfO 2 is formed over the substrate.
  • the resultant structure may be annealed at 450° C. to remove atmospheric water an other adsorbed contaminants but this is not required.
  • a layer of MoN x is formed over the high k dielectric layer.
  • this may include depositing a layer molybdenum (Mo) by electron deposition.
  • the layer may be, for example, 2 nm thick.
  • the structure may then be exposed to NH 3 which forms MoNx (here x represents several possible stoichiometries). In one embodiment, the structure is exposed to 100 millitorr of NH 3 at 450° C.
  • electron beam deposition of Mo is carried out to a thickness of 5 nm in an NH 3 ambient at a temperature of 450° C.
  • the NH 3 ambient may have a partial pressure of 3 ⁇ 10 ⁇ 6 torr.
  • MoNx is formed by deposition of Mo while a beam of nitrogen (N) atoms (dissociated in a remote plasma) is directed to the structure resulting in the formation of molybdenum nitride (MoNx). This may be carried out, for example, at 300° C.
  • the MoN x is converted to MoNO.
  • The may be done, for example, by annealing the structure in the presence of oxygen.
  • the structure may be exposed to 0.1 torr to 10 torr O 2 for a predetermined time.
  • the structure could be exposed to 1 torr O 2 for 2 minutes at a temperature of 450° C. to convert the MoN x to MoNO.
  • the resulting structure is annealed.
  • the structure is annealed at a temperature above 500° C.
  • the structure is annealed at a temperature at or about 1000° C.
  • One advantage of utilizing MoNO as a gate metal for a high-k PFET as disclosed herein is that test data has shown after exposure to a 1000° C. anneal MoNO retains a work function suitable for use in a high-k P-FET.

Abstract

A field effect transistor (FET) includes a body region and a source region disposed at least partially in the body region. The FET also includes a drain region disposed at least partially in the body region and a molybdenum oxynitride (MoNO) gate. The FET also includes a dielectric having a high dielectric constant (k) disposed between the body region and the MoNO gate.

Description

    BACKGROUND
  • The present invention relates to switching devices, and more specifically, to metal gate transistors.
  • The term high-k dielectric refers to a material with a high dielectric constant (k) (as compared to silicon dioxide) used in semiconductor manufacturing processes which replaces the silicon dioxide gate dielectric. The implementation of high-k gate dielectrics is one of several strategies developed to allow further miniaturization of microelectronic components.
  • Silicon dioxide has been used as a gate oxide material for decades. As transistors have decreased in size, the thickness of the silicon dioxide gate dielectric has steadily decreased to increase the gate capacitance and thereby drive current and device performance. As the thickness scales below 2 nm, leakage currents due to tunneling increase drastically, leading to unwieldy power consumption and reduced device reliability. Replacing the silicon dioxide gate dielectric with a high-k material allows increased gate capacitance without the concomitant leakage effects.
    • SUMMARY
  • According to one embodiment of the present invention, a field effect transistor (FET) is disclosed. The FET of this embodiment includes a body region and a source region disposed at least partially in the body region. The FET of this embodiment also includes a drain region disposed at least partially in the body region and a molybdenum oxynitride (MoNO) gate. The FET of this embodiment also includes a dielectric having a high dielectric constant (k) disposed between the body region and the MoNO gate.
  • Another embodiment of the present invention is directed to a method of forming a field effect transistor (FET). The method of this embodiment includes forming a high k dielectric layer over a body region, forming a molybdenum nitride (MoNx) layer over the high k dielectric layer, and converting the MoNx to molybdenum oxynitride (MoNO).
  • Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the advantages and the features, refer to the description and to the drawings.
    • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
  • The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
  • FIG. 1 is a cross-sectional view of a field-effect transistor (FET) according to one embodiment of the present invention; and
  • FIG. 2 is a flow diagram illustrating a method for forming a gate structure for a P-FET according to one embodiment of the present invention.
    •  DETAILED DESCRIPTION
  • In order to fabricate a useful field-effect transistor (FET) metal-oxide-semiconductor (MOS) a high work function material must be deposited as the gate metal atop a dielectric material resident on a silicon (Si) substrate. In some applications the dielectric can be silicon dioxide (SiO2). In more advanced devices, however, a high dielectric having a higher k value than SiO2, such haffiium oxide (HfO2), to allow for a physically thicker layer, and hence reduced current leakage.
  • The use of a high work function metal is needed to induce band bending in the underlying Si body which brings the valence band edge of Si close to the Fermi level, thereby reducing the threshold voltage to a minimum (˜100-200 meV) acceptable level for good device performance. The “work function” of a metal is the minimum energy (usually measured in electron volts) needed to remove an electron from a solid to a point immediately outside the solid surface (or energy needed to move an electron from the Fermi energy level into vacuum).
  • In addition, in order for the gate metal to be acceptable, it should maintain this high effective work function by withstanding integration process anneal temperatures up to 1000° C. Typically after this high temperature anneal the Fermi level moves to the middle of the Si gap which is unsuitable for P-FET operation. Prior to the invention disclosed herein, no candidate P-FET gate metals have been identified which maintain this high effective work function after 1000° C. anneals.
  • With reference now to FIG. 1, a FET 100 according to an embodiment of the present invention is disclosed. In one embodiment, the FET 100 may include a substrate 102. The substrate 102 may be formed, for example, of a semiconductor material. The FET 100 may also include a source region 104 and a drain region 106. In one embodiment, in the event that the FET 100 is a P-FET, the substrate 102 may be formed of an N-type semiconductor and referred to as a “body” or “base” and the source region 104 and the drain region 106 may be formed of a P-type semiconductor.
  • The FET 100 may also include a source contact 108 formed on top of the source region 104 and a drain contact 110 formed on top of the drain region 106. The portion of the body 102 between the source region 104 and the drain region 106 is referred to herein as the channel 112.
  • The FET 100 may also include a gate dielectric 114 disposed above the channel 112. In one embodiment, the gate dielectric 114 may also be disposed such that it is above a portion of one or both of the source region 104 and the drain region 106. In one embodiment, the gate dielectric 114 is disposed only over the channel 112. That is, the gate dielectric 114 may not be disposed over either the source region 104 or the drain region 106. As shown, the gate dielectric 114 contacts the source contact 108 and the drain contact 110. In one embodiment, the gate dielectric 114 does not contact one or both of the source contact 108 and the drain contact 110.
  • In one embodiment, the gate dielectric 114 is formed a dielectric having a high-k value as compared to silicon dioxide. An example of such a material is a hafnium based material such as HfO2 or a similar material. As used herein, a high-k dielectric shall refer to a material that has a k value of 3.0 or greater. In a particular embodiment, the high-k dielectric may have a k value between 4.0 and 100.
  • The FET 100 may also include a gate metal 116 disposed above the gate dielectric 114. In one embodiment, the gate metal 116 is formed of molybdenum oxynitride (MoNO). Of course, variations may exist so, in one embodiment, the gate metal may be formed of MoNOx.
  • In has been discovered that that MoNO (or MoNOx) exhibits high thermal stability and maintains a high effective work function suitable for the gate metal of a P-FET MOS device. In one embodiment, the gate metal is a one nanometer thick layer of MoNO. Experimentation has shown that MoNO maintains an effective work function stability after anneals to 1000° C. for 5 seconds, the typical temperature and length of anneal that devices are subjected to during processing.
  • FIG. 2 shows a method of forming a P-FET with a metal gate according to one embodiment of the present invention. At a block 202 at least an n-doped silicon silicon substrate is provided. At a block 204 a high k dielectric is formed over the substrate. Of course, other layers may be between the high k dielectric and the substrate. The high k dielectric may be, for example, HfO2. Of course, other high k dielectrics may be utilized. In one embodiment, a 2.5-3 nm thick layer of HfO2 is formed over the substrate. At this point, in one embodiment, the resultant structure may be annealed at 450° C. to remove atmospheric water an other adsorbed contaminants but this is not required.
  • At a block 206 a layer of MoNx is formed over the high k dielectric layer. In one embodiment, this may include depositing a layer molybdenum (Mo) by electron deposition. The layer may be, for example, 2 nm thick. The structure may then be exposed to NH3 which forms MoNx (here x represents several possible stoichiometries). In one embodiment, the structure is exposed to 100 millitorr of NH3 at 450° C.
  • In another embodiment, electron beam deposition of Mo is carried out to a thickness of 5 nm in an NH3 ambient at a temperature of 450° C. In this embodiment, the NH3 ambient may have a partial pressure of 3×10−6 torr.
  • In yet another embodiment, in a molecular beam epitaxy (MBE) system, MoNx is formed by deposition of Mo while a beam of nitrogen (N) atoms (dissociated in a remote plasma) is directed to the structure resulting in the formation of molybdenum nitride (MoNx). This may be carried out, for example, at 300° C.
  • Regardless of how the MoNx is formed, at a block 208, the MoNx is converted to MoNO. The may be done, for example, by annealing the structure in the presence of oxygen. In one embodiment, the structure may be exposed to 0.1 torr to 10 torr O2 for a predetermined time. In a specific example, the the structure could be exposed to 1 torr O2 for 2 minutes at a temperature of 450° C. to convert the MoNx to MoNO.
  • Many subsequent processing steps may be performed following block 208. Regardless, at a block 210 the resulting structure is annealed. In one embodiment, the structure is annealed at a temperature above 500° C. In another embodiment, the structure is annealed at a temperature at or about 1000° C.
  • One advantage of utilizing MoNO as a gate metal for a high-k PFET as disclosed herein is that test data has shown after exposure to a 1000° C. anneal MoNO retains a work function suitable for use in a high-k P-FET.
  • The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one ore more other features, integers, steps, operations, element components, and/or groups thereof.
  • The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated
  • The flow diagrams depicted herein are just one example. There may be many variations to this diagram or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention.
  • While the preferred embodiment to the invention had been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.

Claims (16)

1. A field effect transistor (FET) comprising:
a body region;
a source region disposed at least partially in the body region;
a drain region disposed at least partially in the body region;
a molybdenum oxynitride (MoNO) gate; and
a dielectric having a high dielectric constant (k) disposed between the body region and the MoNO gate.
2. The FET of claim 1, wherein the body region is formed of a N-type semiconductor material.
3. The FET of claim 1, wherein the source region and the drain region are formed of a P-type semiconductor material.
4. The FET of claim 1, wherein a region between the source region and drain region forms a channel and wherein channel is formed between at least a portion the high k dielectric and a portion of the body.
5. The FET of claim 1, wherein a portion of at least one of the source region and drain region is disposed between the high k dielectric and the body region.
6. The FET of claim 1, wherein k is above 3.
7. The FET of claim 1, wherein k is between 4 and 100.
8. A method of forming a field effect transistor (FET), the method comprising:
forming a high k dielectric layer over a body region;
forming a molybdenum nitride (MoNx) layer over the high k dielectric layer; and
converting the MoNx to molybdenum oxynitride (MoNO).
9. The method of claim 8, wherein converting includes exposing the MoNx to O2.
10. The method of claim 9, wherein the MoNx is exposed to 0.1 torr to 10 torr O2.
11. The method of claim 9, wherein the MoNx is exposed to 1 torr O2 at a temperature of about 450° C.
12. The method of claim 8, further comprising:
annealing the FET at a temperature in excess of 500° C.
13. The method of claim 12, wherein annealing includes annealing the FET at a temperature of about 1000° C.
14. The method of claim 8, wherein forming the MoNx layer includes:
depositing a layer of molybdenum (Mo) having a thickness of about 2 nanometers (nm); and
exposing the Mo layer to 100 millitorr of NH3.
15. The method of claim 8, wherein forming the MoNx layer includes:
depositing molybdenum (Mo) to a thickness of about 5 nm in an NH3 ambient.
16. The method of claim 8, wherein forming the MoNx layer includes:
depositing molybdenum (Mo) while a beam of nitrogen (N) is directed at the FET.
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Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6472278B1 (en) * 1998-06-22 2002-10-29 Motorola, Inc. Method and apparatus for creating a voltage threshold in a FET
US6514828B2 (en) * 2001-04-20 2003-02-04 Micron Technology, Inc. Method of fabricating a highly reliable gate oxide
US7030430B2 (en) * 2003-08-15 2006-04-18 Intel Corporation Transition metal alloys for use as a gate electrode and devices incorporating these alloys
US20060267113A1 (en) * 2005-05-27 2006-11-30 Tobin Philip J Semiconductor device structure and method therefor
US7172955B2 (en) * 2001-12-27 2007-02-06 Kabushiki Kaisha Toshiba Silicon composition in CMOS gates
US20070272975A1 (en) * 2006-05-26 2007-11-29 Schaeffer James K Method of forming a semiconductor device having an interlayer and structure therefor
US20070284677A1 (en) * 2006-06-08 2007-12-13 Weng Chang Metal oxynitride gate
US20080061333A1 (en) * 2006-09-08 2008-03-13 Kabushiki Kaisha Toshiba Semiconductor memory device and method of fabricating semiconductor memory device
US7365378B2 (en) * 2005-03-31 2008-04-29 International Business Machines Corporation MOSFET structure with ultra-low K spacer
US20080193798A1 (en) * 2004-08-31 2008-08-14 H. C. Starck Inc. Molybdenum Tubular Sputtering Targets with Uniform Grain Size and Texture
US20080233693A1 (en) * 2004-10-11 2008-09-25 Samung Electronics Co., Ltd. Complementary metal-oxide semiconductor (cmos) devices including a thin-body channel and dual gate dielectric layers and methods of manufacturing the same
US20080258822A1 (en) * 2006-10-31 2008-10-23 Semiconductor Energy Laboratory Co., Ltd. Oscillator circuit and semiconductor device including the same
US20090095980A1 (en) * 2007-10-16 2009-04-16 Chen-Hua Yu Reducing Resistance in Source and Drain Regions of FinFETs
US7521706B2 (en) * 2003-11-24 2009-04-21 Samsung Electronics Co., Ltd. Phase change memory devices with contact surface area to a phase changeable material defined by a sidewall of an electrode hole and methods of forming the same
US20090108370A1 (en) * 2007-10-31 2009-04-30 Renesas Technology Corp. Semiconductor device and manufacturing method thereof
US20090231911A1 (en) * 2008-03-14 2009-09-17 Micron Technology, Inc. Phase change memory cell with constriction structure
US7655550B2 (en) * 2006-06-30 2010-02-02 Freescale Semiconductor, Inc. Method of making metal gate transistors

Patent Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6472278B1 (en) * 1998-06-22 2002-10-29 Motorola, Inc. Method and apparatus for creating a voltage threshold in a FET
US6514828B2 (en) * 2001-04-20 2003-02-04 Micron Technology, Inc. Method of fabricating a highly reliable gate oxide
US7172955B2 (en) * 2001-12-27 2007-02-06 Kabushiki Kaisha Toshiba Silicon composition in CMOS gates
US7030430B2 (en) * 2003-08-15 2006-04-18 Intel Corporation Transition metal alloys for use as a gate electrode and devices incorporating these alloys
US7521706B2 (en) * 2003-11-24 2009-04-21 Samsung Electronics Co., Ltd. Phase change memory devices with contact surface area to a phase changeable material defined by a sidewall of an electrode hole and methods of forming the same
US20080193798A1 (en) * 2004-08-31 2008-08-14 H. C. Starck Inc. Molybdenum Tubular Sputtering Targets with Uniform Grain Size and Texture
US20080233693A1 (en) * 2004-10-11 2008-09-25 Samung Electronics Co., Ltd. Complementary metal-oxide semiconductor (cmos) devices including a thin-body channel and dual gate dielectric layers and methods of manufacturing the same
US7365378B2 (en) * 2005-03-31 2008-04-29 International Business Machines Corporation MOSFET structure with ultra-low K spacer
US20060267113A1 (en) * 2005-05-27 2006-11-30 Tobin Philip J Semiconductor device structure and method therefor
US20070272975A1 (en) * 2006-05-26 2007-11-29 Schaeffer James K Method of forming a semiconductor device having an interlayer and structure therefor
US20070284677A1 (en) * 2006-06-08 2007-12-13 Weng Chang Metal oxynitride gate
US7655550B2 (en) * 2006-06-30 2010-02-02 Freescale Semiconductor, Inc. Method of making metal gate transistors
US20080061333A1 (en) * 2006-09-08 2008-03-13 Kabushiki Kaisha Toshiba Semiconductor memory device and method of fabricating semiconductor memory device
US20080258822A1 (en) * 2006-10-31 2008-10-23 Semiconductor Energy Laboratory Co., Ltd. Oscillator circuit and semiconductor device including the same
US20090095980A1 (en) * 2007-10-16 2009-04-16 Chen-Hua Yu Reducing Resistance in Source and Drain Regions of FinFETs
US20090108370A1 (en) * 2007-10-31 2009-04-30 Renesas Technology Corp. Semiconductor device and manufacturing method thereof
US20090231911A1 (en) * 2008-03-14 2009-09-17 Micron Technology, Inc. Phase change memory cell with constriction structure

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Definite of above. (n.d.) The American Heritage® Dictionary of the English Language, Fourth Edition. (2003). Retrieved May 3 2012 from http://www.thefreedictionary.com/above *

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