US20110084407A1 - System and method for preventing metal corrosion on bond pads - Google Patents

System and method for preventing metal corrosion on bond pads Download PDF

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US20110084407A1
US20110084407A1 US12/971,513 US97151310A US2011084407A1 US 20110084407 A1 US20110084407 A1 US 20110084407A1 US 97151310 A US97151310 A US 97151310A US 2011084407 A1 US2011084407 A1 US 2011084407A1
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layer
bond pad
reflective coating
arc layer
integrated circuit
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Rodney Hill
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National Semiconductor Corp
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National Semiconductor Corp
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
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    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2924/14—Integrated circuits

Definitions

  • the present invention is generally directed to the manufacture of integrated circuits and, in particular, to a system and method for preventing corrosion on bond pads.
  • bond pads are created on the device to receive circuit connectors that provide external electrical connection to the metal layers of the integrated circuit device.
  • the methods that are used in the prior art to create a bond pad opening in the device typically etch through the various layers of the integrated circuit device.
  • the uppermost layer is usually a passivation layer.
  • Under the passivation layer is an anti-reflective coating layer (sometimes referred to as an ARC layer) that comprises the top layer of a metal stack.
  • the remainder of the metal stack is located under the ARC layer.
  • the metal stack is typically located on an underlying oxide layer.
  • Prior art methods mask and etch a bond pad opening through the passivation layer and through the ARC layer down to the metal stack. This method leaves the interior edges of the ARC layer exposed to the ambient atmosphere during the subsequent assembly operations of the integrated circuit device.
  • the interior edges of the ARC layer corrode rapidly when exposed to the high temperatures and high humidity that are present during subsequent accelerated reliability testing procedures.
  • corrosion can occur in the assembly process from the exposure to corrosive materials used in die packaging.
  • the corrosion of the exposed interior edges of the ARC layer can extend for hundreds of microns through the ARC layer. Corrosion in the ARC layer leads to device failure by creating high electrical resistance and cracks in the overlying passivation layer.
  • FIG. 1 shows a schematic diagram of a plan view of a prior art bond pad structure 100 .
  • the top layer shown in FIG. 1 is the anti-reflective coating layer 110 (ARC layer 110 ).
  • FIG. 2 shows a schematic diagram 200 of a cross sectional view of the bond pad structure 110 taken along the line A-A in FIG. 1 .
  • the top layer is ARC layer 110 .
  • the ARC layer 110 is typically formed of titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), titanium tungsten (TiW), or other metals.
  • the bottom layer shown in FIG. 2 is an oxide layer 210 that is located on a substrate (not shown).
  • Metal stack 220 is located on oxide layer 210 .
  • Metal stack 220 may typically comprise metals such as aluminum (Al), copper (Cu), titanium (Ti), titanium nitride (TiN), and other metals.
  • the ARC layer 110 is located on the metal stack 220 .
  • the thicknesses of the various layers of the prior art bond pad structure shown in FIG. 2 are not necessarily drawn to scale. For clarity the thicknesses of the various layers in FIG. 2 are shown larger than actual size.
  • FIG. 3 shows a schematic diagram 300 of a plan view of the prior art bond pad structure 100 covered with passivation layer 310 .
  • the top layer shown in FIG. 3 is the passivation layer 310 that is located over the ARC layer 110 .
  • the metal stack 220 (not numbered in FIG. 3 ) is visible through the bond pad opening 320 .
  • FIG. 4 shows a schematic diagram 400 of a cross sectional view of the bond pad structure shown in FIG. 3 taken along the line B-B in FIG. 3 .
  • the etch process that creates bond pad opening 320 exposes the interior edges 410 of the ARC layer 110 to the ambient atmosphere.
  • the interior edges 410 of the ARC layer 110 are subject to corrosion during their exposure to high temperature, high humidity and corrosive materials during the subsequent assembly operations of the integrated circuit device.
  • the thicknesses of the various layers of prior art bond pad structure shown in FIG. 4 are not necessarily drawn to scale. For clarity the thicknesses of the various layers in FIG. 4 are shown larger than actual size.
  • FIG. 5 illustrates a flowchart 500 showing the steps of the prior art method and how the prior art method exposes the interior edges 410 of the ARC layer 110 to corrosion.
  • an oxide layer 210 is deposited on a substrate (not shown) (step 510 ).
  • a metal stack 220 is deposited on the oxide layer 210 (step 520 ).
  • an anti-reflective coating layer 110 (ARC layer 110 ) is deposited on the metal layer 220 (step 530 ).
  • a passivation layer 310 is deposited on the ARC layer 110 (step 540 ). Then a mask and etch process is performed on the passivation layer 310 to etch the bond pad opening 320 through the passivation layer 310 and through the anti-reflective coating layer 110 (ARC layer 110 ) down to the metal stack 220 .
  • the mask and etch process exposes the interior edge portions 410 of the ARC layer 110 in the bond pad opening 320 .
  • the interior edge portions 410 of the ARC layer 110 become corroded due to exposure to the ambient atmosphere during the subsequent assembly operations of the integrated circuit device (step 560 ).
  • the present invention provides a system and method that seals the interior edges of the ARC layer so that the interior edges of the ARC layer are not subject to corrosion.
  • An ARC layer removal mask and etch step is inserted between a metal pad define step and a subsequent passivation deposition step. During the ARC layer removal mask and etch step a central portion of the ARC layer is removed from a central portion of the bond pad.
  • FIG. 1 illustrates a schematic diagram of a plan view of a prior art bond pad structure
  • FIG. 2 illustrates a schematic diagram of a cross sectional view of the prior art bond pad structure shown in FIG. 1 taken along the line A-A;
  • FIG. 3 illustrates a schematic diagram of a plan view of a prior art bond pad structure covered with a passivation layer
  • FIG. 4 illustrates a schematic diagram of a cross sectional view of the prior art bond pad structure shown in FIG. 3 taken along the line B-B;
  • FIG. 5 illustrates a flowchart showing the steps of a prior art method and how the prior art method exposes the interior edges of an ARC layer to corrosion
  • FIG. 6 illustrates a schematic diagram of a plan view of a bond pad structure of the present invention
  • FIG. 7 illustrates a schematic diagram of a cross sectional view of the bond pad structure of the present invention shown in FIG. 6 taken along the line C-C;
  • FIG. 8 illustrates a schematic diagram of a plan view of the bond pad structure of the present invention covered with a passivation layer
  • FIG. 9 illustrates a schematic diagram of a cross sectional view of the bond pad structure of the present invention shown in FIG. 8 taken along the line D-D;
  • FIG. 10 illustrates a flowchart showing the steps of an advantageous embodiment of a method of the present invention and how the method of the present invention prevents corrosion of the interior edges of the ARC layer in the bond pad structure of the present invention
  • FIGS. 6 through 10 discussed below, and the various embodiments used to describe the principles of the present invention in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the invention. Those skilled in the art will understand that the principles of the present invention may be implemented with any type of suitably arranged integrated circuit device.
  • FIG. 6 illustrates a schematic diagram of a plan view of a bond pad structure 600 of the present invention.
  • the top layer shown in FIG. 6 is an anti-reflective coating layer 610 (ARC layer 610 ).
  • a mask and etch process has been performed to etch through the ARC layer 610 down to the underlying metal stack 220 .
  • a central portion of the ARC layer 610 has been removed by the mask and etch process to form an ARC layer aperture 620 through the ARC layer 610 .
  • the interior edges of the ARC layer aperture 620 are designated with the reference numeral 630 .
  • the metal stack 220 (not numbered in FIG. 6 ) is visible through the ARC layer aperture 620 .
  • FIG. 7 illustrates a schematic diagram of a cross sectional view of the bond pad structure 600 of the present invention shown in FIG. 6 taken along the line C-C.
  • the top layer comprises ARC layer 610 having the ARC layer aperture 620 etched through the central portion of ARC layer 610 .
  • the ARC layer 610 is typically formed of titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), titanium tungsten (TiW), or other metals.
  • the bottom layer shown in FIG. 7 is an oxide layer 210 that is located on a substrate (not shown).
  • Metal stack 220 is located on oxide layer 210 .
  • Metal stack 220 may typically comprise metals such as aluminum (Al), copper (Cu), titanium (Ti), titanium nitride (TiN), and other metals.
  • the ARC layer 610 is located on the metal stack 220 .
  • the thicknesses of the various layers of bond pad structure of the present invention shown in FIG. 7 are not necessarily drawn to scale. For clarity the thicknesses of the various layers in FIG. 7 are shown larger than actual size.
  • the bond pad structure 600 is subsequently covered with a passivation layer 810 .
  • a mask and etch process is performed to etch a bond pad opening 820 through the passivation layer 810 down to the metal stack 220 .
  • the mask and etch process that etches through the passivation layer 810 to the metal stack 220 does not touch the ARC layer 610 .
  • the mask and etch process that etches through the passivation layer 810 to form bond pad opening 820 leaves portions of the passivation layer 810 over the interior edges 630 of the ARC layer 610 to seal the interior edges 630 from the ambient atmosphere.
  • FIG. 8 shows a schematic diagram 800 of a plan view of the bond pad structure 600 of the present invention covered with passivation layer 810 .
  • the top layer shown in FIG. 8 is the passivation layer 810 that is located over the ARC layer 610 .
  • the interior edges of the passivation layer 810 are designated with reference numeral 830 .
  • the extent of the bond pad opening 820 is shown in the central portion of the bond pad structure.
  • the metal stack 220 (not numbered in FIG. 8 ) is visible through the bond pad opening 820 .
  • FIG. 9 illustrates a schematic diagram 900 of a cross sectional view of the bond pad structure of the present invention shown in FIG. 8 taken along the line D-D.
  • the etch process that creates the bond pad opening 820 covers (and does not expose) the interior edges 630 of the ARC layer 610 . Therefore, the interior edges 630 of the ARC layer 610 are not exposed to the high temperature and high humidity of the subsequent assembly operations of the integrated circuit device. This prevents corrosion from occurring in the ARC layer 610 .
  • FIG. 10 illustrates a flowchart 1000 showing the steps of an advantageous embodiment of a method of the present invention and how the method of the present invention prevents corrosion of the interior edges 630 of the ARC layer 610 in the bond pad structure of the present invention.
  • an oxide layer 210 is deposited on a substrate (not shown) (step 1010 ).
  • a metal stack 220 is deposited on the oxide layer 210 (step 1020 ).
  • an anti-reflective coating layer 610 is deposited on the metal layer 220 (step 1030 ).
  • a mask and etch process is used to etch an ARC layer aperture 620 through the ARC layer 610 down to the metal stack 220 (step 1040 ).
  • a passivation layer 810 is deposited over the ARC layer aperture 620 and over the interior edge portions 630 of ARC layer 610 (step 1050 ).
  • a mask and etch process is performed on the passivation layer 810 to etch a bond pad opening 820 through the passivation layer 810 inside the ARC layer aperture 620 down to the metal stack 220 .
  • the mask and etch process leaves the edge portions 630 of the ARC layer 610 covered with portions of the passivation layer 810 (step 1060 ).
  • the interior edge portions 630 of the ARC layer 610 do not become corroded during the subsequent assembly operations of the integrated circuit device because the interior edge portions 630 are not exposed to the ambient atmosphere (step 1070 ). This prevents corrosion of the ARC layer 610 in the present invention.

Abstract

A system and method are disclosed for preventing metal corrosion on bond pads. During manufacture of an integrated circuit device an anti-reflective coating (ARC) layer is applied to a metal stack of a bond pad. A mask and etch process is applied to etch an aperture through the ARC layer down to the metal stack. Then a passivation layer is applied to cover the ARC layer and the aperture through the ARC layer. Then another mask and etch process is applied to etch a bond pad opening through the passivation layer inside the ARC layer aperture down to the metal stack. Interior edge portions of the passivation layer seal the interior edge portions of the ARC layer aperture to prevent corrosion of the ARC layer due to high temperatures, high humidity and corrosive materials encountered in subsequent assembly operations of the integrated circuit device.

Description

    TECHNICAL FIELD OF THE INVENTION
  • The present invention is generally directed to the manufacture of integrated circuits and, in particular, to a system and method for preventing corrosion on bond pads.
    • BACKGROUND OF THE INVENTION
  • In the manufacture of an integrated circuit device bond pads are created on the device to receive circuit connectors that provide external electrical connection to the metal layers of the integrated circuit device. The methods that are used in the prior art to create a bond pad opening in the device typically etch through the various layers of the integrated circuit device. The uppermost layer is usually a passivation layer. Under the passivation layer is an anti-reflective coating layer (sometimes referred to as an ARC layer) that comprises the top layer of a metal stack. The remainder of the metal stack is located under the ARC layer. The metal stack is typically located on an underlying oxide layer.
  • Prior art methods mask and etch a bond pad opening through the passivation layer and through the ARC layer down to the metal stack. This method leaves the interior edges of the ARC layer exposed to the ambient atmosphere during the subsequent assembly operations of the integrated circuit device. The interior edges of the ARC layer corrode rapidly when exposed to the high temperatures and high humidity that are present during subsequent accelerated reliability testing procedures. In addition, corrosion can occur in the assembly process from the exposure to corrosive materials used in die packaging. The corrosion of the exposed interior edges of the ARC layer can extend for hundreds of microns through the ARC layer. Corrosion in the ARC layer leads to device failure by creating high electrical resistance and cracks in the overlying passivation layer.
  • To better illustrate the problem FIG. 1 shows a schematic diagram of a plan view of a prior art bond pad structure 100. The top layer shown in FIG. 1 is the anti-reflective coating layer 110 (ARC layer 110). FIG. 2 shows a schematic diagram 200 of a cross sectional view of the bond pad structure 110 taken along the line A-A in FIG. 1. As shown in FIG. 2, the top layer is ARC layer 110. The ARC layer 110 is typically formed of titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), titanium tungsten (TiW), or other metals.
  • The bottom layer shown in FIG. 2 is an oxide layer 210 that is located on a substrate (not shown). Metal stack 220 is located on oxide layer 210. Metal stack 220 may typically comprise metals such as aluminum (Al), copper (Cu), titanium (Ti), titanium nitride (TiN), and other metals. The ARC layer 110 is located on the metal stack 220. The thicknesses of the various layers of the prior art bond pad structure shown in FIG. 2 are not necessarily drawn to scale. For clarity the thicknesses of the various layers in FIG. 2 are shown larger than actual size.
  • The bond pad structure 100 is subsequently covered with a passivation layer 310. A mask and etch process is performed to etch a bond pad opening 320 through the passivation layer 310 and through the ARC layer 110 down to the metal stack 220. FIG. 3 shows a schematic diagram 300 of a plan view of the prior art bond pad structure 100 covered with passivation layer 310. The top layer shown in FIG. 3 is the passivation layer 310 that is located over the ARC layer 110. The metal stack 220 (not numbered in FIG. 3) is visible through the bond pad opening 320.
  • FIG. 4 shows a schematic diagram 400 of a cross sectional view of the bond pad structure shown in FIG. 3 taken along the line B-B in FIG. 3. As shown in FIG. 4, the etch process that creates bond pad opening 320 exposes the interior edges 410 of the ARC layer 110 to the ambient atmosphere. As previously described, the interior edges 410 of the ARC layer 110 are subject to corrosion during their exposure to high temperature, high humidity and corrosive materials during the subsequent assembly operations of the integrated circuit device.
  • The thicknesses of the various layers of prior art bond pad structure shown in FIG. 4 are not necessarily drawn to scale. For clarity the thicknesses of the various layers in FIG. 4 are shown larger than actual size.
  • FIG. 5 illustrates a flowchart 500 showing the steps of the prior art method and how the prior art method exposes the interior edges 410 of the ARC layer 110 to corrosion. First, an oxide layer 210 is deposited on a substrate (not shown) (step 510). Then a metal stack 220 is deposited on the oxide layer 210 (step 520). Then an anti-reflective coating layer 110 (ARC layer 110) is deposited on the metal layer 220 (step 530).
  • Then a passivation layer 310 is deposited on the ARC layer 110 (step 540). Then a mask and etch process is performed on the passivation layer 310 to etch the bond pad opening 320 through the passivation layer 310 and through the anti-reflective coating layer 110 (ARC layer 110) down to the metal stack 220. The mask and etch process exposes the interior edge portions 410 of the ARC layer 110 in the bond pad opening 320. The interior edge portions 410 of the ARC layer 110 become corroded due to exposure to the ambient atmosphere during the subsequent assembly operations of the integrated circuit device (step 560).
  • Therefore, there is a need in the art for a system and method that is capable of solving the above described corrosion problem that occurs in ARC layers of prior art bond pad structures.
  • The present invention provides a system and method that seals the interior edges of the ARC layer so that the interior edges of the ARC layer are not subject to corrosion. An ARC layer removal mask and etch step is inserted between a metal pad define step and a subsequent passivation deposition step. During the ARC layer removal mask and etch step a central portion of the ARC layer is removed from a central portion of the bond pad.
  • Normal processing is resumed after the ARC layer removal mask and etch step. A passivation deposition step is performed. Then a mask and etch process is performed to etch the bond pad opening through the passivation layer. A design rule of the present invention ensures that the interior edges of the etched passivation layer always overlap and cover the interior edges of the ARC layer.
  • Before undertaking the Detailed Description of the Invention below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like.
  • Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior uses, as well as to future uses, of such defined words and phrases.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which like reference numerals represent like parts:
  • FIG. 1 illustrates a schematic diagram of a plan view of a prior art bond pad structure;
  • FIG. 2 illustrates a schematic diagram of a cross sectional view of the prior art bond pad structure shown in FIG. 1 taken along the line A-A;
  • FIG. 3 illustrates a schematic diagram of a plan view of a prior art bond pad structure covered with a passivation layer;
  • FIG. 4 illustrates a schematic diagram of a cross sectional view of the prior art bond pad structure shown in FIG. 3 taken along the line B-B;
  • FIG. 5 illustrates a flowchart showing the steps of a prior art method and how the prior art method exposes the interior edges of an ARC layer to corrosion;
  • FIG. 6 illustrates a schematic diagram of a plan view of a bond pad structure of the present invention;
  • FIG. 7 illustrates a schematic diagram of a cross sectional view of the bond pad structure of the present invention shown in FIG. 6 taken along the line C-C;
  • FIG. 8 illustrates a schematic diagram of a plan view of the bond pad structure of the present invention covered with a passivation layer;
  • FIG. 9 illustrates a schematic diagram of a cross sectional view of the bond pad structure of the present invention shown in FIG. 8 taken along the line D-D; and
  • FIG. 10 illustrates a flowchart showing the steps of an advantageous embodiment of a method of the present invention and how the method of the present invention prevents corrosion of the interior edges of the ARC layer in the bond pad structure of the present invention;
    •  DETAILED DESCRIPTION OF THE INVENTION
  • FIGS. 6 through 10, discussed below, and the various embodiments used to describe the principles of the present invention in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the invention. Those skilled in the art will understand that the principles of the present invention may be implemented with any type of suitably arranged integrated circuit device.
  • FIG. 6 illustrates a schematic diagram of a plan view of a bond pad structure 600 of the present invention. The top layer shown in FIG. 6 is an anti-reflective coating layer 610 (ARC layer 610). A mask and etch process has been performed to etch through the ARC layer 610 down to the underlying metal stack 220. A central portion of the ARC layer 610 has been removed by the mask and etch process to form an ARC layer aperture 620 through the ARC layer 610. The interior edges of the ARC layer aperture 620 are designated with the reference numeral 630. The metal stack 220 (not numbered in FIG. 6) is visible through the ARC layer aperture 620.
  • FIG. 7 illustrates a schematic diagram of a cross sectional view of the bond pad structure 600 of the present invention shown in FIG. 6 taken along the line C-C. As shown in FIG. 7, the top layer comprises ARC layer 610 having the ARC layer aperture 620 etched through the central portion of ARC layer 610. The ARC layer 610 is typically formed of titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), titanium tungsten (TiW), or other metals.
  • The bottom layer shown in FIG. 7 is an oxide layer 210 that is located on a substrate (not shown). Metal stack 220 is located on oxide layer 210. Metal stack 220 may typically comprise metals such as aluminum (Al), copper (Cu), titanium (Ti), titanium nitride (TiN), and other metals. The ARC layer 610 is located on the metal stack 220. The thicknesses of the various layers of bond pad structure of the present invention shown in FIG. 7 are not necessarily drawn to scale. For clarity the thicknesses of the various layers in FIG. 7 are shown larger than actual size.
  • The bond pad structure 600 is subsequently covered with a passivation layer 810. A mask and etch process is performed to etch a bond pad opening 820 through the passivation layer 810 down to the metal stack 220. The mask and etch process that etches through the passivation layer 810 to the metal stack 220 does not touch the ARC layer 610. By a design rule of the present invention the mask and etch process that etches through the passivation layer 810 to form bond pad opening 820 leaves portions of the passivation layer 810 over the interior edges 630 of the ARC layer 610 to seal the interior edges 630 from the ambient atmosphere.
  • FIG. 8 shows a schematic diagram 800 of a plan view of the bond pad structure 600 of the present invention covered with passivation layer 810. The top layer shown in FIG. 8 is the passivation layer 810 that is located over the ARC layer 610. The interior edges of the passivation layer 810 are designated with reference numeral 830. The extent of the bond pad opening 820 is shown in the central portion of the bond pad structure. The metal stack 220 (not numbered in FIG. 8) is visible through the bond pad opening 820.
  • FIG. 9 illustrates a schematic diagram 900 of a cross sectional view of the bond pad structure of the present invention shown in FIG. 8 taken along the line D-D. As shown in FIG. 9, the etch process that creates the bond pad opening 820 covers (and does not expose) the interior edges 630 of the ARC layer 610. Therefore, the interior edges 630 of the ARC layer 610 are not exposed to the high temperature and high humidity of the subsequent assembly operations of the integrated circuit device. This prevents corrosion from occurring in the ARC layer 610.
  • FIG. 10 illustrates a flowchart 1000 showing the steps of an advantageous embodiment of a method of the present invention and how the method of the present invention prevents corrosion of the interior edges 630 of the ARC layer 610 in the bond pad structure of the present invention. First, an oxide layer 210 is deposited on a substrate (not shown) (step 1010). Then a metal stack 220 is deposited on the oxide layer 210 (step 1020). Then an anti-reflective coating layer 610 (ARC layer 610) is deposited on the metal layer 220 (step 1030).
  • Then a mask and etch process is used to etch an ARC layer aperture 620 through the ARC layer 610 down to the metal stack 220 (step 1040). Then a passivation layer 810 is deposited over the ARC layer aperture 620 and over the interior edge portions 630 of ARC layer 610 (step 1050). Then a mask and etch process is performed on the passivation layer 810 to etch a bond pad opening 820 through the passivation layer 810 inside the ARC layer aperture 620 down to the metal stack 220. The mask and etch process leaves the edge portions 630 of the ARC layer 610 covered with portions of the passivation layer 810 (step 1060).
  • The interior edge portions 630 of the ARC layer 610 do not become corroded during the subsequent assembly operations of the integrated circuit device because the interior edge portions 630 are not exposed to the ambient atmosphere (step 1070). This prevents corrosion of the ARC layer 610 in the present invention.
  • The foregoing description has outlined in detail the features and technical advantages of the present invention so that persons who are skilled in the art may understand the advantages of the invention. Persons who are skilled in the art should appreciate that they may readily use the conception and the specific embodiment of the invention that is disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Persons who are skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
  • Although the present invention has been described with an exemplary embodiment, various changes and modifications may be suggested to one skilled in the art. It is intended that the present invention encompass such changes and modifications as fall within the scope of the appended claims.

Claims (8)

1-7. (canceled)
8. An integrated circuit device comprising at least one bond pad that comprises:
a metal stack;
an anti-reflective coating layer on said metal stack, said anti-reflective coating layer having portions that define an anti-reflective coating layer aperture through said anti-reflective coating layer down to said metal stack; and
a passivation layer over said anti-reflective coating layer that seals interior edges of said anti-reflective coating layer aperture from an ambient atmosphere.
9. The integrated circuit device as set forth in claim 8, wherein said passivation layer comprises portions that form a bond pad opening through said passivation layer down to said metal stack.
10. The integrated circuit device as set forth in claim 9, wherein interior edges of said passivation layer that form said bond pad opening through said passivation layer cover said interior edges of said anti-reflective coating layer.
11. The integrated circuit device as set forth in claim 10, wherein said portions of said passivation layer protect said interior edges of said anti-reflective coating layer aperture from at least one of: a high temperature and a high humidity of said ambient atmosphere associated with subsequent assembly operations of said integrated circuit.
12. The integrated circuit device as set forth in claim 10, wherein said portions of said passivation layer protect said interior edges of said anti-reflective coating layer aperture from corrosive materials used in subsequent assembly operations of said integrated circuit device.
13. The integrated circuit device as set forth in claim 8, wherein said passivation layer over said anti-reflective coating layer that seals said interior edges of said anti-reflective coating layer aperture from said ambient atmosphere prevents corrosion of said anti-reflective coating layer on said bond pad.
14.-20. (canceled)
US12/971,513 2006-09-01 2010-12-17 System and method for preventing metal corrosion on bond pads Abandoned US20110084407A1 (en)

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Citations (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5444012A (en) * 1993-07-20 1995-08-22 Hitachi, Ltd. Method for manufacturing semiconductor integrated circuit device having a fuse element
US5563762A (en) * 1994-11-28 1996-10-08 Northern Telecom Limited Capacitor for an integrated circuit and method of formation thereof, and a method of adding on-chip capacitors to an integrated circuit
US5798568A (en) * 1996-08-26 1998-08-25 Motorola, Inc. Semiconductor component with multi-level interconnect system and method of manufacture
US5814893A (en) * 1995-01-20 1998-09-29 Motorola Inc. Semiconductor device having a bond pad
US5814563A (en) * 1996-04-29 1998-09-29 Applied Materials, Inc. Method for etching dielectric using fluorohydrocarbon gas, NH3 -generating gas, and carbon-oxygen gas
US5925931A (en) * 1996-10-31 1999-07-20 Casio Computer Co., Ltd. Semiconductor device having interconnect lines and connection electrodes formed in groove portions of an insulating layer
US5930664A (en) * 1997-07-24 1999-07-27 Taiwan Semiconductor Manufacturing Company, Ltd. Process for preventing corrosion of aluminum bonding pads after passivation/ARC layer etching
US6002179A (en) * 1997-09-15 1999-12-14 Winbond Electronics Corporation Bonding pad structure for integrated circuit (I)
US6006764A (en) * 1997-01-28 1999-12-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of stripping photoresist from Al bonding pads that prevents corrosion
US6177355B1 (en) * 1999-08-31 2001-01-23 Advanced Micro Devices, Inc. Pad etch process capable of thick titanium nitride arc removal
US6221752B1 (en) * 1998-08-20 2001-04-24 United Microelectronics Corp. Method of mending erosion of bonding pad
US6376353B1 (en) * 2000-07-03 2002-04-23 Chartered Semiconductor Manufacturing Ltd. Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects
US20020146898A1 (en) * 2001-04-09 2002-10-10 Shigenari Aoki Bonding pad, semiconductor device and wire bonding method
US6593222B2 (en) * 2001-09-07 2003-07-15 Lattice Corporation Method to improve the reliability of thermosonic gold to aluminum wire bonds
US6600174B2 (en) * 2000-01-24 2003-07-29 Sharp Kabushiki Kaisha Light receiving element and semiconductor laser device
US6650021B2 (en) * 2000-05-04 2003-11-18 International Business Machines Corporation Recessed bond pad
US6677226B1 (en) * 1998-05-11 2004-01-13 Motorola, Inc. Method for forming an integrated circuit having a bonding pad and a fuse
US6750129B2 (en) * 2002-11-12 2004-06-15 Infineon Technologies Ag Process for forming fusible links
US6866943B2 (en) * 2002-04-30 2005-03-15 Infineon Technologies Ag Bond pad structure comprising tungsten or tungsten compound layer on top of metallization level
US20050116357A1 (en) * 2002-10-31 2005-06-02 International Business Machines Corporation Method and structure to enhance temperature/humidity/bias performance of semiconductor devices by surface modification
US6924172B2 (en) * 2003-08-26 2005-08-02 Freescale Semiconductor, Inc. Method of forming a bond pad
US7091609B2 (en) * 2000-03-27 2006-08-15 Seiko Epson Corporation Semiconductor devices including an alloy layer and a wetting layer on an interlayer dielectric
US20060249845A1 (en) * 2005-03-25 2006-11-09 Sanyo Electric Co., Ltd. Semiconductor device and manufacturing method of the same
US20070238304A1 (en) * 2006-04-11 2007-10-11 Jui-Hung Wu Method of etching passivation layer
US7432536B2 (en) * 2004-11-04 2008-10-07 Cree, Inc. LED with self aligned bond pad
US20100295044A1 (en) * 2009-05-20 2010-11-25 Renesas Technology Corp. Semiconductor device and method of manufacturing the same

Patent Citations (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5444012A (en) * 1993-07-20 1995-08-22 Hitachi, Ltd. Method for manufacturing semiconductor integrated circuit device having a fuse element
US5563762A (en) * 1994-11-28 1996-10-08 Northern Telecom Limited Capacitor for an integrated circuit and method of formation thereof, and a method of adding on-chip capacitors to an integrated circuit
US5814893A (en) * 1995-01-20 1998-09-29 Motorola Inc. Semiconductor device having a bond pad
US5814563A (en) * 1996-04-29 1998-09-29 Applied Materials, Inc. Method for etching dielectric using fluorohydrocarbon gas, NH3 -generating gas, and carbon-oxygen gas
US5798568A (en) * 1996-08-26 1998-08-25 Motorola, Inc. Semiconductor component with multi-level interconnect system and method of manufacture
US5925931A (en) * 1996-10-31 1999-07-20 Casio Computer Co., Ltd. Semiconductor device having interconnect lines and connection electrodes formed in groove portions of an insulating layer
US6006764A (en) * 1997-01-28 1999-12-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of stripping photoresist from Al bonding pads that prevents corrosion
US5930664A (en) * 1997-07-24 1999-07-27 Taiwan Semiconductor Manufacturing Company, Ltd. Process for preventing corrosion of aluminum bonding pads after passivation/ARC layer etching
US6002179A (en) * 1997-09-15 1999-12-14 Winbond Electronics Corporation Bonding pad structure for integrated circuit (I)
US6677226B1 (en) * 1998-05-11 2004-01-13 Motorola, Inc. Method for forming an integrated circuit having a bonding pad and a fuse
US6221752B1 (en) * 1998-08-20 2001-04-24 United Microelectronics Corp. Method of mending erosion of bonding pad
US6177355B1 (en) * 1999-08-31 2001-01-23 Advanced Micro Devices, Inc. Pad etch process capable of thick titanium nitride arc removal
US6600174B2 (en) * 2000-01-24 2003-07-29 Sharp Kabushiki Kaisha Light receiving element and semiconductor laser device
US7091609B2 (en) * 2000-03-27 2006-08-15 Seiko Epson Corporation Semiconductor devices including an alloy layer and a wetting layer on an interlayer dielectric
US6650021B2 (en) * 2000-05-04 2003-11-18 International Business Machines Corporation Recessed bond pad
US6376353B1 (en) * 2000-07-03 2002-04-23 Chartered Semiconductor Manufacturing Ltd. Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects
US20020146898A1 (en) * 2001-04-09 2002-10-10 Shigenari Aoki Bonding pad, semiconductor device and wire bonding method
US6593222B2 (en) * 2001-09-07 2003-07-15 Lattice Corporation Method to improve the reliability of thermosonic gold to aluminum wire bonds
US6866943B2 (en) * 2002-04-30 2005-03-15 Infineon Technologies Ag Bond pad structure comprising tungsten or tungsten compound layer on top of metallization level
US20050116357A1 (en) * 2002-10-31 2005-06-02 International Business Machines Corporation Method and structure to enhance temperature/humidity/bias performance of semiconductor devices by surface modification
US6750129B2 (en) * 2002-11-12 2004-06-15 Infineon Technologies Ag Process for forming fusible links
US6924172B2 (en) * 2003-08-26 2005-08-02 Freescale Semiconductor, Inc. Method of forming a bond pad
US7432536B2 (en) * 2004-11-04 2008-10-07 Cree, Inc. LED with self aligned bond pad
US20060249845A1 (en) * 2005-03-25 2006-11-09 Sanyo Electric Co., Ltd. Semiconductor device and manufacturing method of the same
US20070238304A1 (en) * 2006-04-11 2007-10-11 Jui-Hung Wu Method of etching passivation layer
US20100295044A1 (en) * 2009-05-20 2010-11-25 Renesas Technology Corp. Semiconductor device and method of manufacturing the same

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