US20110089551A1 - Semiconductor device with double-sided electrode structure and its manufacturing method - Google Patents

Semiconductor device with double-sided electrode structure and its manufacturing method Download PDF

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Publication number
US20110089551A1
US20110089551A1 US12/978,877 US97887710A US2011089551A1 US 20110089551 A1 US20110089551 A1 US 20110089551A1 US 97887710 A US97887710 A US 97887710A US 2011089551 A1 US2011089551 A1 US 2011089551A1
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Prior art keywords
multilayer substrate
lsi chip
wiring
semiconductor device
accordance
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US12/978,877
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Masamichi Ishihara
Fumihiko Ooka
Yoshihiko Ino
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Oki Electric Industry Co Ltd
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Oki Electric Industry Co Ltd
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Priority to US12/978,877 priority Critical patent/US20110089551A1/en
Publication of US20110089551A1 publication Critical patent/US20110089551A1/en
Abandoned legal-status Critical Current

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Definitions

  • the present invention relates to a semiconductor device having a double-sided electrode structure which can be used in small-sized electronic devices, such as cellular phones and digital cameras, small-sized robots, and small-sized sensors, and to a method of manufacturing such a semiconductor device.
  • Patent Document 2 discloses a lead-frame-type double-sided electrode package in which the package is vertically penetrated by a lead frame. However, since the arrangement of electrodes on the lower face of the package is identical with that of electrodes on the upper face of the package, the package has no flexibility in connection between the upper and lower faces.
  • Patent document 3 discloses a BGA-type double-sided electrode package in which electrodes penetrating through a substrate are provided so as to form a double-sided electrode structure. However, since electrode placement portions on the upper surface are the penetrating electrodes themselves, the package has no flexible in a pattern of connection with an upper-side IC.
  • Patent Document 4 discloses a double-sided electrode structure in which protrusion electrodes are formed on a substrate. However, Patent Document 4 discloses neither a method of forming the protrusion electrodes nor a connection method. Although Patent Document 4 discloses rewiring on the upper surface, the disclosed method for effecting rewiring is a conventional method in which a low-resistance metallic film is formed through upper surface plating, and a pattern is formed by use of lithography. Therefore, the disclosed double-sided electrode structure has a big problem in terms of cost.
  • Patent Document 1 Japanese Patent Application Laid-Open (kokai) No. 2001-127243
  • Patent Document 2 Japanese Patent Application Laid-Open (kokai) No. 2003-249604
  • Patent Document 3 Japanese Patent Application Laid-Open (kokai) No. 2005-235824
  • Patent Document 4 Japanese Patent Application Laid-Open (kokai) No. 2002-158312
  • An object of the present invention is to solve the above-mentioned problems and to allow low-cost manufacture of a thin double-sided electrode package in which rewiring can be freely formed on an upper surface of a substrate, to thereby facilitate connection with an upper side IC.
  • Another object of the present invention is to enable a plurality of chips to be embedded in a single substrate, and to enable an arbitrary number of wiring traces to extend to arbitrary positions of upper and lower portions of the substrate, to thereby impart flexibility to a pattern of connection with an upper side IC.
  • a semiconductor device having a double-sided electrode structure of the present invention includes a package substrate which is formed of a multilayer organic substrate having a multilayer wiring.
  • a recess portion is formed in the package substrate, and an LSI chip is accommodated within the recess portion.
  • a resin is charged for sealing around and on the LSI chip to a height equal to that of the uppermost surface of the package substrate, the LSI chip being mounted in the recess portion of the package substrate and being connected to the multilayer wiring.
  • Wiring traces are formed on an upper surface of the charged resin such that the wiring traces are connected to wiring traces for terminals (hereinafter referred to as “terminal wiring traces”) connected to the multilayer wiring on a front face of the package substrate, and are connected to front-face bump electrodes for external connection on the upper surface of the resin.
  • terminal wiring traces wiring traces for terminals
  • front-face bump electrodes for external connection are formed and connected to the multilayer wiring.
  • Step portions are formed around the recess portion of the package substrate, and the terminal wiring traces connected to the multilayer wiring are formed on the step portions.
  • the terminal wiring traces which serve as bonding wire connection electrodes, are connected to electrodes formed on an upper surface of an LSI chip.
  • Metal pad portions connected to the multilayer wiring are formed on the uppermost layer of the bottom portion of the recess portion of the package substrate, and upper-surface electrodes of an LSI chip disposed to face downward are flip-chip connected to the metal pad portions.
  • the resin sealing is performed by injecting a resin around and on the LSI chip mounted in the recess portion of the package substrate to the same height as the uppermost surface of the package substrate, such that the surface of the resin seal becomes flush with the upper surface of the package.
  • Wiring on the upper surface of the resin is performed by ink-jet printing or screen printing in which metal particles are used. Copper particles may be used as the metal particles. In this case, a reduction process is carried out by use of atomic hydrogen.
  • a recess portion is formed in a package substrate which is formed of a multilayer organic substrate having a multilayer wiring and in which terminal wiring traces are connected to the multilayer wiring on front and back faces of the substrate.
  • An LSI chip is accommodated within the recess portion.
  • a resin is charged, for sealing, around and on the LSI chip to a height equal to that of the uppermost surface of the package substrate, the LSI chip being mounted in the recess portion of the package substrate and being connected to the multilayer wiring.
  • Wiring traces which are connected to the terminal wiring traces on the front face of the package substrate are formed on the upper surface of the resin, and front-face bump electrodes for external connection are formed at distal ends of the wiring traces.
  • Back-face bump electrodes for external connection which are connected to the terminal wiring traces on the back face of the package substrate are formed.
  • a high-density, thin double-sided electrode package can be readily manufactured at low cost through employment of a devised package substrate, rather than side-surface wiring or internal connection.
  • a plurality of chips can be readily incorporated into a single substrate.
  • an arbitrary number of wiring traces can be extended to arbitrary positions of upper and lower portions of the substrate, and rewiring can be freely formed on the upper surface of the substrate, whereby flexibility can be imparted to a pattern of connection with an upper side IC.
  • FIG. 1 is a pair of views exemplifying a semiconductor device having a double-sided electrode structure (an organic-substrate-type double-sided electrode package) of the present invention
  • FIG. 2(A) is a sectional view of a package substrate
  • FIG. 2(B) is a perspective view of the package substrate
  • FIG. 3 is a set of views used for explaining an example method of manufacturing the package substrate
  • FIG. 4 is a view used for explaining chip die bonding for bonding an LSI chip
  • FIG. 5 is a view used for explaining wire bonding between a multilayer organic substrate and the LSI chip
  • FIGS. 6(A) and 6(B) are views showing a state in which a cavity portion is sealed with a resin, wherein FIG. 6(A) is a sectional view, and FIG. 6(B) is a perspective view;
  • FIG. 7 is a view used for explaining rewiring on a front face of a mold
  • FIG. 8 is a view used for explaining connection of bump electrodes
  • FIG. 9 is a pair of plan views exemplifying wiring patterns different from that of FIG. 1(B) ;
  • FIG. 10 is a schematic view, in cross section, of a processing apparatus used as a cupper wiring cleaning apparatus.
  • FIG. 1 is a pair of views exemplifying a semiconductor device having a double-sided electrode structure (an organic-substrate-type double-sided electrode package) of the present invention.
  • FIG. 1(A) is a perspective view of the package, as viewed from the upper side thereof, the view showing a state in which an LSI chip is accommodated in a package substrate, and wire bonding is performed.
  • FIG. 1(B) is a perspective view of the package, as viewed from the upper side thereof, the view showing a state in which rewiring is performed after resin sealing, and bumps for external connection are formed, whereby the package is completed.
  • the package substrate formed from a multilayer organic substrate with multilayer wiring has a recess portion for accommodating the LSI chip, and a step portion formed around the recess portion.
  • the multilayer organic substrate includes a wiring layer on the bottom surface of the recess portion and the step portion, respectively.
  • the front-face-side wiring layer is shown as terminal wiring traces.
  • the terminal wiring traces are also provided on the back face side of the multilayer organic substrate, on the bottom surface of the recess portion (for flip chip connection), and on the step portion (for wire bonding).
  • Metal pad portions (terminal wiring traces) on the upper surface of the step portion which are connected to the wiring layers of the multilayer organic substrate, serve as bonding wire connection electrodes, and are connected via Au wires to electrodes formed on the upper surface of the LSI chip.
  • downward-facing upper-surface electrodes of the LSI chip may be flip-chip-connected to metal pad portions (terminal wiring traces) of the uppermost layer at the bottom of the recess portion.
  • the wiring layer at the bottom of the recess portion is not necessarily required; however, even when wiring is present at a die bonding portion, die bonding can be performed without any problem if an insulating layer is applied thereto or an insulative die bond material is used.
  • the package substrate is sealed with an epoxy resin in order to protect the package substrate from external stress and contamination.
  • This resin sealing is performed by injecting the resin into a space around the LSI chip disposed within the recess portion of the multilayer organic substrate, and on the upper surface of the LSI chip (a cavity portion), to the same height as the uppermost surface of the package substrate, such that the surface of the resin seal becomes flush with the upper surface of the package.
  • wiring traces for connection with the terminal wiring traces formed on the uppermost surface of the package substrate (rewiring).
  • the wiring traces extending from the upper surface of the package substrate are formed to extend to the resin surface by means of screen printing or ink jet printing which uses nanoparticles of metal (in particular, nano-particles of copper).
  • Bump electrodes connection projections
  • the bump electrodes are formed not only on the front face but also on the back face. As shown in FIG. 1(B) , in order to dispose the bump electrodes at equal intervals, instead of extending the wiring traces to the resin surface (rewiring), wiring traces may be extended within the package substrate, with bump electrodes formed at the distal ends of the wiring traces. Further, excessive bump electrodes which are not connected to anything may be provided in order to secure the strength of vertical connection.
  • FIG. 2(A) is a sectional view of a package substrate
  • FIG. 2(B) is a perspective view of the package substrate.
  • the package substrate formed from a multilayer organic substrate with multilayer wiring has a recess portion for accommodating an LSI chip, and a step portion formed around the recess portion.
  • the multilayer organic substrate has advantageous features. That is, since its circuit is formed of a conductor of a pure metal (copper), the electrical resistance of the circuit is very low.
  • the multilayer organic substrate is light in weight.
  • the wiring layers (including terminal wiring traces) of the multilayer organic substrate are formed on the bottom surface of the recess portion and the step portion, respectively, as well as on the back face side and the front face side of the substrate.
  • the terminal wiring traces of FIG. 2(B) are the font-face-side wiring layer.
  • the step portion having the terminal wiring traces for connection to the LSI chip is provided along all four sides of the rectangular recess portion.
  • such a step portion is not necessarily required to be provided along all of the four sides.
  • the surface on which the recess portion is formed to accommodate a semiconductor chip is referred to as the front face, and the opposite surface is referred to as the back face.
  • the multilayer organic substrate is fabricated in such a manner that a wiring pattern is formed on each of the layers of a multilayer substrate; and, if necessary, via holes are formed so as to connect the wiring pattern of the layers.
  • a conductor layer is formed in each via hole, and is connected to a land (an end surface electrode portion) formed on the lower surface side. Further, a solder material is applied to the land so as to form a bump electrode for external connection.
  • copper film for forming a metal conductor is formed on the upper and lower surfaces of an organic resin insulating layer (substrate) formed of glass epoxy.
  • the copper film can be formed through, for example, chemical plating.
  • hole (via hole) forming machining is performed by use of a laser, whereby spaces for three-dimensional connection are formed in the insulating layer; that is, via portions are formed so as to interconnect wiring patterns which are formed on the upper and lower surfaces of the insulating layer in a step shown in FIG. 3(D) , which will be described later.
  • the via holes are filled with copper plating.
  • wiring patterns are formed by use of the copper films on the upper and lower surfaces.
  • the wiring patterns are formed by applying photo resist to the copper foils on the insulting layer, transferring corresponding patterns thereto through mask exposure, and performing development, etching, resist removal, etc.
  • an organic resin insulating layer (glass epoxy) is laminated (layered) on each of the upper and lower surfaces, and copper film is formed on each of the organic resin insulating layers.
  • holes via holes, which are to become via portions, are formed in the two newly formed organic resin insulating layers (glass epoxy).
  • the via holes are filled with copper plating. Subsequently, wiring patterns are formed from the upper and lower copper films, whereby a four-layer (wiring layer) substrate is completed.
  • an LSI chip is bonded (chip die bond).
  • the LSI chip is bonded, by use of an insulative bond material, to the bottom surface of the recess portion formed in the multilayer organic substrate.
  • a single LSI chip is incorporated into the substrate; however, a plurality of chips may be incorporated into the substrate, as will be described later with reference to FIG. 9(B) .
  • the multilayer organic substrate and the LSI chip are connected together by means of wire bonding.
  • Metal pad portions terminal wiring traces
  • the metal pad portions which serve as bonding wire connection electrodes, are connected, by use of Au wire, to electrodes formed on the upper surface of the LSI chip.
  • the state after this wire bonding corresponds to that having been described with reference to FIG. 1(A) .
  • the LSI chip may be flip-chip bonded to metal pad portions of the uppermost layer at the bottom portion of the recess portion.
  • chip die bonding and electrode connection are carried out simultaneously.
  • the LSI chip is connected such that its LSI-formed surface faces downward, whereby the upper surface electrodes of the downward-facing LSI chip are connected by wiring patterns (traces) including the metal pad portions of the uppermost layer at the bottom portion of the recess portion of the multilayer organic substrate.
  • the step portions of the package substrate and the wiring layer provided on the step portions are not necessarily required.
  • FIGS. 6(A) and 6(B) are views showing a state where the cavity portion is sealed by use of a resin, wherein FIG. 6(A) is a sectional view of the package substrate, and FIG. 6(B) is a perspective view of the package substrate.
  • the cavity portion is sealed with an epoxy resin in order to protect the LSI from external stress and contamination.
  • This resin sealing is performed by injecting the resin (mold) into a space around the LSI chip disposed within the recess portion of the multilayer organic substrate, and on the upper surface of the LSI chip (the cavity portion), to the same height as the uppermost surface of the package substrate, such that the surface of the resin seal becomes flush with the upper surface of the package.
  • wiring traces for connection with the metal pad portions terminal wiring traces formed on the uppermost surface of the package substrate (rewiring).
  • the wiring traces extending from the upper surface of the package substrate are formed to extend to the resin surface, by means of screen printing or ink jet printing which uses nano-particles of metal (in particular, nano-particles of copper).
  • nano-particles of copper contained in an organic solvent are applied in a desired pattern by an ink jet method practically employed in printers. After that, heat treatment is performed so as to evaporate the organic solvent.
  • nano-paste prepared by mixing nano-particles of copper into an organic solvent is applied onto the substrate by a screen printing method, and the substrate is then fired through application of heat, whereby circuit wiring traces are formed.
  • wiring traces are formed on the upper surface by use of nano-particles of copper, as will be described in detail, dirt and oxides are removed from copper wiring traces through a reduction process performed by use of atomic hydrogen.
  • FIG. 8 is a view showing a state after bump electrodes are connected to the substrate.
  • Bump electrodes connection projections
  • the bump electrodes are formed not only on the front face but also on the back face.
  • the front-face-side bump electrodes may be formed by a process of applying solder resist (formation of an insulating film) after the rewiring, forming holes serving as bump portions, and forming bump electrodes at the bump portions.
  • FIGS. 9(A) and 9(B) are plan views exemplifying wiring patterns different from that of FIG. 1(B) .
  • FIG. 9(A) shows an example in which one LSI chip is incorporated into one package substrate
  • FIG. 9(B) shows an example in which two LSI chips are incorporated into one package substrate.
  • manufacture of a single double-sided electrode package has been described as an example.
  • a large number of double-sided electrode packages are manufactured in a state where they are connected two-dimensionally, and are diced for separation after the step of FIG. 8 ; i.e., after formation of bump electrodes on the front and back faces.
  • Copper wiring traces are formed by an ink jet method.
  • Nano-particles of copper contained in an organic solvent are applied in a desired pattern by an ink jet method practically employed in printers. Subsequently, heat treatment is performed so as to evaporate the organic solvent.
  • oxides and dirt attributable to the organic solvent are removed from the copper wiring traces formed in a manner described above.
  • heat treatment is performed so as to evaporate the organic solvent, through surface oxidation of copper, copper oxide is formed.
  • this copper oxide can be removed through subsequent atomic hydrogen treatment.
  • the present invention can be applied to the case where heat treatment for evaporating the organic solvent is not performed. In the case where heat treatment is not performed, the organic solvent remains. However, the organic solvent can be removed through subsequent atomic hydrogen treatment.
  • FIG. 10 is a schematic view, in cross section, of a processing apparatus used as a copper wiring cleaning apparatus.
  • a cleaning gas supply mechanism supplies into a reaction chamber, via a gas inlet formed in the upper wall of the reaction chamber, a hydrogen-containing raw material, such as hydrogen, ammonia, or hydrazine, as a raw material of atomic hydrogen or ammonia-decomposed species.
  • a hydrogen-containing raw material such as hydrogen, ammonia, or hydrazine
  • a substrate heating mechanism such as a heater is disposed underneath the reaction chamber, and a sample stage is provided within the reaction chamber to be located immediately above the heating mechanism.
  • a sample (a substrate) is placed on the sample stage such that the surface on which wiring traces are formed faces upward.
  • a catalyst formed of, for example, tungsten wire is disposed between the sample and a shower head for diffusing the gas from the gas inlet.
  • a catalyst heating mechanism heats the catalyst to a high temperature so as to decompose the gas having flowed into the chamber.
  • Oxides of the copper wiring traces are removed through reduction of atomic hydrogen, and organic dirt is removed through formation of hydro carbon as a result of reaction between atomic hydrogen and carbon.
  • Compounds containing nitrogen such as ammonia and hydrazine, may be used as the above-described hydrogen-containing compound, which is the raw material of atomic hydrogen or ammonia-decomposed species.
  • nitrogen when a gas of such a compound comes into contact with the heated catalyst, atomic nitrogen is generated simultaneously with generation of atomic hydrogen, whereby metal surfaces can be nitrided by atomic nitrogen, simultaneously with reduction of oxide film on metal surfaces and/or removal of organic substances by atomic hydrogen.
  • the catalyst may be formed of an element selected from a group consisting of tantalum, molybdenum, vanadium, rhenium, platinum, thorium, zirconium, yttrium, hafnium, palladium, iridium, ruthenium, iron, nickel, chromium, aluminum, silicon, and carbon; an oxide of any one of these elements; a nitride of anyone of these elements; a carbide of any one of these elements (excluding carbon); an oxide of a mixed crystal or compound formed of two or more elements selected from the group; a nitride of a mixed crystal or compound formed of two or more elements selected from the group; or a carbide of a mixed crystal or compound formed of two or more elements selected from the group (excluding carbon).
  • the catalyst is formed of tungsten, preferably, the catalyst is heated to a temperature within a range of 1000° C. to 2200° C.
  • a material supply mechanism in FIG. 10 is used to supply hexamethyldisilazane, shiran, or the like so as to deposit, for example, SiN-based film when necessary. Further, a vacuum system is used to discharge reaction residual gasses.
  • a wafer (including a plurality of packages connected two-dimensionally) on which wiring traces are formed by use of nano copper particles, or package substrates diced from the wafer are placed on the sample stage of the copper wiring cleaning apparatus, as a sample (substrate).
  • hydrogen gas is supplied at a flow rate of 30 sccm for 10 minutes.
  • the contaminants are removed.

Abstract

According to the present invention, a recess portion is formed in a package substrate which is formed of a multilayer organic substrate having a multilayer wiring, and an LSI chip is accommodated within the recess portion. Wiring traces are formed on the upper surface of a resin which seals the LSI chip connected to the multilayer wiring. The wiring traces are connected to terminal wiring traces connected to the multilayer wiring on the front face of the package substrate and to front-face bump electrodes for external connection on the upper surface of the resin. On the back face side of the package substrate, back-face bump electrodes for external connection are formed and connected to the multilayer wiring.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application is a continuation under 37 CFR 1.53(b) of pending prior application Ser. No. 12/279,402 filed Aug. 14, 2008, which is a United States National Phase Application of International Application PCT/JP2007/057812 filed Apr. 9, 2007 and claims the benefit of priority under 35 U.S.C. §119 of Japanese Patent Application No. 2006-120127 filed Apr. 25, 2006, the entire contents of each of the applications are incorporated herein by reference.
  • FIELD OF THE INVENTION
  • The present invention relates to a semiconductor device having a double-sided electrode structure which can be used in small-sized electronic devices, such as cellular phones and digital cameras, small-sized robots, and small-sized sensors, and to a method of manufacturing such a semiconductor device.
  • BACKGROUND OF THE INVENTION
  • In association with an increase in the degree of integration of LSI chips, there has been strong demand for a reduction in package size. Under the circumstances, various package structures have been proposed. In recent years, developments have been carried out intensively for stacking semiconductor bare chips through utilization of through-silicon vias formed therein. Meanwhile, dual-face packages of real chip size are also highly likely to be commercialized. Conventional dual-face packages of any technology require a through-silicon via structure (refer to Patent Document 1). Since existing insulation methods for through holes in a semiconductor substrate involve high-temperature treatment, application of such insulation methods to a semiconductor packaging process is difficult. Formation of through holes in a semiconductor substrate and insulation for the through holes still involve problems to be solved; therefore, wiring that does not require through-silicon vias is desired.
  • Patent Document 2 discloses a lead-frame-type double-sided electrode package in which the package is vertically penetrated by a lead frame. However, since the arrangement of electrodes on the lower face of the package is identical with that of electrodes on the upper face of the package, the package has no flexibility in connection between the upper and lower faces.
  • Patent document 3 discloses a BGA-type double-sided electrode package in which electrodes penetrating through a substrate are provided so as to form a double-sided electrode structure. However, since electrode placement portions on the upper surface are the penetrating electrodes themselves, the package has no flexible in a pattern of connection with an upper-side IC.
  • Patent Document 4 discloses a double-sided electrode structure in which protrusion electrodes are formed on a substrate. However, Patent Document 4 discloses neither a method of forming the protrusion electrodes nor a connection method. Although Patent Document 4 discloses rewiring on the upper surface, the disclosed method for effecting rewiring is a conventional method in which a low-resistance metallic film is formed through upper surface plating, and a pattern is formed by use of lithography. Therefore, the disclosed double-sided electrode structure has a big problem in terms of cost.
  • Patent Document 1: Japanese Patent Application Laid-Open (kokai) No. 2001-127243
  • Patent Document 2: Japanese Patent Application Laid-Open (kokai) No. 2003-249604
  • Patent Document 3: Japanese Patent Application Laid-Open (kokai) No. 2005-235824
  • Patent Document 4: Japanese Patent Application Laid-Open (kokai) No. 2002-158312
  • SUMMARY OF THE INVENTION
  • An object of the present invention is to solve the above-mentioned problems and to allow low-cost manufacture of a thin double-sided electrode package in which rewiring can be freely formed on an upper surface of a substrate, to thereby facilitate connection with an upper side IC.
  • Another object of the present invention is to enable a plurality of chips to be embedded in a single substrate, and to enable an arbitrary number of wiring traces to extend to arbitrary positions of upper and lower portions of the substrate, to thereby impart flexibility to a pattern of connection with an upper side IC.
  • Means for Solving the Problems
  • A semiconductor device having a double-sided electrode structure of the present invention includes a package substrate which is formed of a multilayer organic substrate having a multilayer wiring. A recess portion is formed in the package substrate, and an LSI chip is accommodated within the recess portion. A resin is charged for sealing around and on the LSI chip to a height equal to that of the uppermost surface of the package substrate, the LSI chip being mounted in the recess portion of the package substrate and being connected to the multilayer wiring. Wiring traces are formed on an upper surface of the charged resin such that the wiring traces are connected to wiring traces for terminals (hereinafter referred to as “terminal wiring traces”) connected to the multilayer wiring on a front face of the package substrate, and are connected to front-face bump electrodes for external connection on the upper surface of the resin. On the back face side of the package substrate, back-face bump electrodes for external connection are formed and connected to the multilayer wiring.
  • Step portions are formed around the recess portion of the package substrate, and the terminal wiring traces connected to the multilayer wiring are formed on the step portions. The terminal wiring traces, which serve as bonding wire connection electrodes, are connected to electrodes formed on an upper surface of an LSI chip. Metal pad portions connected to the multilayer wiring are formed on the uppermost layer of the bottom portion of the recess portion of the package substrate, and upper-surface electrodes of an LSI chip disposed to face downward are flip-chip connected to the metal pad portions. The resin sealing is performed by injecting a resin around and on the LSI chip mounted in the recess portion of the package substrate to the same height as the uppermost surface of the package substrate, such that the surface of the resin seal becomes flush with the upper surface of the package. Wiring on the upper surface of the resin is performed by ink-jet printing or screen printing in which metal particles are used. Copper particles may be used as the metal particles. In this case, a reduction process is carried out by use of atomic hydrogen.
  • According to a method of manufacturing a semiconductor device having a double-sided electrode structure of the present invention, a recess portion is formed in a package substrate which is formed of a multilayer organic substrate having a multilayer wiring and in which terminal wiring traces are connected to the multilayer wiring on front and back faces of the substrate. An LSI chip is accommodated within the recess portion. A resin is charged, for sealing, around and on the LSI chip to a height equal to that of the uppermost surface of the package substrate, the LSI chip being mounted in the recess portion of the package substrate and being connected to the multilayer wiring. Wiring traces which are connected to the terminal wiring traces on the front face of the package substrate are formed on the upper surface of the resin, and front-face bump electrodes for external connection are formed at distal ends of the wiring traces. Back-face bump electrodes for external connection which are connected to the terminal wiring traces on the back face of the package substrate are formed.
  • Effects of the Invention
  • According to the present invention, a high-density, thin double-sided electrode package can be readily manufactured at low cost through employment of a devised package substrate, rather than side-surface wiring or internal connection.
  • Further, according to the present invention, a plurality of chips can be readily incorporated into a single substrate. In addition, an arbitrary number of wiring traces can be extended to arbitrary positions of upper and lower portions of the substrate, and rewiring can be freely formed on the upper surface of the substrate, whereby flexibility can be imparted to a pattern of connection with an upper side IC.
  • The various features of novelty which characterize the invention are pointed out with particularity in the claims annexed to and forming a part of this disclosure. For a better understanding of the invention, its operating advantages and specific objects attained by its uses, reference is made to the accompanying drawings and descriptive matter in which preferred embodiments of the invention are illustrated.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • In the drawings:
  • FIG. 1 is a pair of views exemplifying a semiconductor device having a double-sided electrode structure (an organic-substrate-type double-sided electrode package) of the present invention;
  • FIG. 2(A) is a sectional view of a package substrate, and FIG. 2(B) is a perspective view of the package substrate;
  • FIG. 3 is a set of views used for explaining an example method of manufacturing the package substrate;
  • FIG. 4 is a view used for explaining chip die bonding for bonding an LSI chip;
  • FIG. 5 is a view used for explaining wire bonding between a multilayer organic substrate and the LSI chip;
  • FIGS. 6(A) and 6(B) are views showing a state in which a cavity portion is sealed with a resin, wherein FIG. 6(A) is a sectional view, and FIG. 6(B) is a perspective view;
  • FIG. 7 is a view used for explaining rewiring on a front face of a mold;
  • FIG. 8 is a view used for explaining connection of bump electrodes;
  • FIG. 9 is a pair of plan views exemplifying wiring patterns different from that of FIG. 1(B); and
  • FIG. 10 is a schematic view, in cross section, of a processing apparatus used as a cupper wiring cleaning apparatus.
  • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • The present invention will now be described by way of examples. FIG. 1 is a pair of views exemplifying a semiconductor device having a double-sided electrode structure (an organic-substrate-type double-sided electrode package) of the present invention. FIG. 1(A) is a perspective view of the package, as viewed from the upper side thereof, the view showing a state in which an LSI chip is accommodated in a package substrate, and wire bonding is performed. FIG. 1(B) is a perspective view of the package, as viewed from the upper side thereof, the view showing a state in which rewiring is performed after resin sealing, and bumps for external connection are formed, whereby the package is completed.
  • As shown in FIG. 1(A), the package substrate formed from a multilayer organic substrate with multilayer wiring has a recess portion for accommodating the LSI chip, and a step portion formed around the recess portion. In addition to the back face side and the front face side, the multilayer organic substrate includes a wiring layer on the bottom surface of the recess portion and the step portion, respectively. In FIGS. 1(A) and 1(B), the front-face-side wiring layer is shown as terminal wiring traces. Similarly, the terminal wiring traces are also provided on the back face side of the multilayer organic substrate, on the bottom surface of the recess portion (for flip chip connection), and on the step portion (for wire bonding). Metal pad portions (terminal wiring traces) on the upper surface of the step portion, which are connected to the wiring layers of the multilayer organic substrate, serve as bonding wire connection electrodes, and are connected via Au wires to electrodes formed on the upper surface of the LSI chip. Alternatively, downward-facing upper-surface electrodes of the LSI chip may be flip-chip-connected to metal pad portions (terminal wiring traces) of the uppermost layer at the bottom of the recess portion. Notably, in the case of wire boding connection, the wiring layer at the bottom of the recess portion is not necessarily required; however, even when wiring is present at a die bonding portion, die bonding can be performed without any problem if an insulating layer is applied thereto or an insulative die bond material is used.
  • As shown in FIG. 1(B), after wire bonding, the package substrate is sealed with an epoxy resin in order to protect the package substrate from external stress and contamination. This resin sealing is performed by injecting the resin into a space around the LSI chip disposed within the recess portion of the multilayer organic substrate, and on the upper surface of the LSI chip (a cavity portion), to the same height as the uppermost surface of the package substrate, such that the surface of the resin seal becomes flush with the upper surface of the package. After that, on the front face of the resultant mold, there are formed wiring traces for connection with the terminal wiring traces formed on the uppermost surface of the package substrate (rewiring). The wiring traces extending from the upper surface of the package substrate are formed to extend to the resin surface by means of screen printing or ink jet printing which uses nanoparticles of metal (in particular, nano-particles of copper). Bump electrodes (connection projections), which serve as terminals for external connection, are formed at the distal ends of the wiring traces extending to the resin surface. The bump electrodes are formed not only on the front face but also on the back face. As shown in FIG. 1(B), in order to dispose the bump electrodes at equal intervals, instead of extending the wiring traces to the resin surface (rewiring), wiring traces may be extended within the package substrate, with bump electrodes formed at the distal ends of the wiring traces. Further, excessive bump electrodes which are not connected to anything may be provided in order to secure the strength of vertical connection.
  • Next, the details of a manufacturing process of the above-described semiconductor device having a double-sided electrode structure (the organic-substrate-type double-sided electrode package) will be further described with reference to FIGS. 2 to 8. FIG. 2(A) is a sectional view of a package substrate, and FIG. 2(B) is a perspective view of the package substrate. The package substrate formed from a multilayer organic substrate with multilayer wiring has a recess portion for accommodating an LSI chip, and a step portion formed around the recess portion. The multilayer organic substrate has advantageous features. That is, since its circuit is formed of a conductor of a pure metal (copper), the electrical resistance of the circuit is very low. In addition, since its insulating layers are formed of an organic resin, the dielectric constant of the insulating layers is low, and the multilayer organic substrate is light in weight. The wiring layers (including terminal wiring traces) of the multilayer organic substrate are formed on the bottom surface of the recess portion and the step portion, respectively, as well as on the back face side and the front face side of the substrate. The terminal wiring traces of FIG. 2(B) are the font-face-side wiring layer. In the illustrated example, the step portion having the terminal wiring traces for connection to the LSI chip is provided along all four sides of the rectangular recess portion. However, such a step portion is not necessarily required to be provided along all of the four sides. Notably, in the illustrated organic-substrate-type double-sided electrode package, the surface on which the recess portion is formed to accommodate a semiconductor chip is referred to as the front face, and the opposite surface is referred to as the back face.
  • The multilayer organic substrate is fabricated in such a manner that a wiring pattern is formed on each of the layers of a multilayer substrate; and, if necessary, via holes are formed so as to connect the wiring pattern of the layers. A conductor layer is formed in each via hole, and is connected to a land (an end surface electrode portion) formed on the lower surface side. Further, a solder material is applied to the land so as to form a bump electrode for external connection.
  • Next, an example method of manufacturing the above-described package substrate will be described with reference to FIG. 3. First, in a step shown in FIG. 3(A), copper film for forming a metal conductor is formed on the upper and lower surfaces of an organic resin insulating layer (substrate) formed of glass epoxy. The copper film can be formed through, for example, chemical plating.
  • In a step shown in FIG. 3(B), hole (via hole) forming machining is performed by use of a laser, whereby spaces for three-dimensional connection are formed in the insulating layer; that is, via portions are formed so as to interconnect wiring patterns which are formed on the upper and lower surfaces of the insulating layer in a step shown in FIG. 3(D), which will be described later.
  • In a step shown in FIG. 3(C), after removal (desmearing) of residues within the via holes, the via holes are filled with copper plating.
  • In a step shown in FIG. 3(D), wiring patterns are formed by use of the copper films on the upper and lower surfaces. The wiring patterns are formed by applying photo resist to the copper foils on the insulting layer, transferring corresponding patterns thereto through mask exposure, and performing development, etching, resist removal, etc.
  • In a step shown in FIG. 3(E), an organic resin insulating layer (glass epoxy) is laminated (layered) on each of the upper and lower surfaces, and copper film is formed on each of the organic resin insulating layers.
  • In a step shown in FIG. 3(F), by use of a laser, holes (via holes), which are to become via portions, are formed in the two newly formed organic resin insulating layers (glass epoxy).
  • In a step shown in FIG. 3(G), after removal (desmearing) of residues within the via holes, the via holes are filled with copper plating. Subsequently, wiring patterns are formed from the upper and lower copper films, whereby a four-layer (wiring layer) substrate is completed.
  • Next, as shown in FIG. 4, an LSI chip is bonded (chip die bond). The LSI chip is bonded, by use of an insulative bond material, to the bottom surface of the recess portion formed in the multilayer organic substrate. In the illustrated example, a single LSI chip is incorporated into the substrate; however, a plurality of chips may be incorporated into the substrate, as will be described later with reference to FIG. 9(B).
  • Next, as shown in FIG. 5, the multilayer organic substrate and the LSI chip are connected together by means of wire bonding. Metal pad portions (terminal wiring traces) are formed on step portions adjacent to the side walls of the recess portion of the multilayer organic substrate, and the metal pad portions are connected to the multilayer wiring layer. The metal pad portions, which serve as bonding wire connection electrodes, are connected, by use of Au wire, to electrodes formed on the upper surface of the LSI chip. The state after this wire bonding corresponds to that having been described with reference to FIG. 1(A).
  • Alternatively, by means of anisotropic conductive resin bonding or the like, the LSI chip may be flip-chip bonded to metal pad portions of the uppermost layer at the bottom portion of the recess portion. In the case of flip-chip connection, chip die bonding and electrode connection are carried out simultaneously. In the case of flip-chip connection, the LSI chip is connected such that its LSI-formed surface faces downward, whereby the upper surface electrodes of the downward-facing LSI chip are connected by wiring patterns (traces) including the metal pad portions of the uppermost layer at the bottom portion of the recess portion of the multilayer organic substrate. Notably, in the case of flip-chip connection, the step portions of the package substrate and the wiring layer provided on the step portions are not necessarily required.
  • FIGS. 6(A) and 6(B) are views showing a state where the cavity portion is sealed by use of a resin, wherein FIG. 6(A) is a sectional view of the package substrate, and FIG. 6(B) is a perspective view of the package substrate. After wire bonding, the cavity portion is sealed with an epoxy resin in order to protect the LSI from external stress and contamination. This resin sealing is performed by injecting the resin (mold) into a space around the LSI chip disposed within the recess portion of the multilayer organic substrate, and on the upper surface of the LSI chip (the cavity portion), to the same height as the uppermost surface of the package substrate, such that the surface of the resin seal becomes flush with the upper surface of the package.
  • Next, as shown in FIG. 7, on the front face of a mold formed as a result of charging of the resin, there are formed wiring traces for connection with the metal pad portions (terminal wiring traces) formed on the uppermost surface of the package substrate (rewiring). The wiring traces extending from the upper surface of the package substrate are formed to extend to the resin surface, by means of screen printing or ink jet printing which uses nano-particles of metal (in particular, nano-particles of copper). In the case of the ink jet printing, nano-particles of copper contained in an organic solvent are applied in a desired pattern by an ink jet method practically employed in printers. After that, heat treatment is performed so as to evaporate the organic solvent. In the case of the screen printing, nano-paste prepared by mixing nano-particles of copper into an organic solvent is applied onto the substrate by a screen printing method, and the substrate is then fired through application of heat, whereby circuit wiring traces are formed. In the case where wiring traces are formed on the upper surface by use of nano-particles of copper, as will be described in detail, dirt and oxides are removed from copper wiring traces through a reduction process performed by use of atomic hydrogen.
  • FIG. 8 is a view showing a state after bump electrodes are connected to the substrate. Bump electrodes (connection projections), which serve as terminals for external connection, are formed at the distal ends of the wiring traces extending to the resin surface. The bump electrodes are formed not only on the front face but also on the back face. The front-face-side bump electrodes may be formed by a process of applying solder resist (formation of an insulating film) after the rewiring, forming holes serving as bump portions, and forming bump electrodes at the bump portions. Through the above-described steps, manufacture of the organic-substrate-type double-sided electrode package is completed.
  • FIGS. 9(A) and 9(B) are plan views exemplifying wiring patterns different from that of FIG. 1(B). FIG. 9(A) shows an example in which one LSI chip is incorporated into one package substrate, and FIG. 9(B) shows an example in which two LSI chips are incorporated into one package substrate.
  • In the above, manufacture of a single double-sided electrode package has been described as an example. However, in actuality, a large number of double-sided electrode packages are manufactured in a state where they are connected two-dimensionally, and are diced for separation after the step of FIG. 8; i.e., after formation of bump electrodes on the front and back faces.
  • As described above, in the case where wiring traces are formed on the upper surface by use of nano-particles of copper, a reduction process is performed by use of atomic hydrogen, whereby oxides and dirt on copper wiring traces attributable to the organic solvent are removed at a low temperature of 200° C. or lower. This reduction process will now be described.
  • (1) Copper wiring traces are formed by an ink jet method.
  • Nano-particles of copper contained in an organic solvent are applied in a desired pattern by an ink jet method practically employed in printers. Subsequently, heat treatment is performed so as to evaporate the organic solvent.
  • In the present invention, oxides and dirt attributable to the organic solvent are removed from the copper wiring traces formed in a manner described above. In the case where heat treatment is performed so as to evaporate the organic solvent, through surface oxidation of copper, copper oxide is formed. However, this copper oxide can be removed through subsequent atomic hydrogen treatment. The present invention can be applied to the case where heat treatment for evaporating the organic solvent is not performed. In the case where heat treatment is not performed, the organic solvent remains. However, the organic solvent can be removed through subsequent atomic hydrogen treatment.
  • (2) Next, in a copper wiring cleaning apparatus, the copper oxide and the organic solvent dirt are removed by use of atomic hydrogen or an ammonia-decomposed-specie.
  • FIG. 10 is a schematic view, in cross section, of a processing apparatus used as a copper wiring cleaning apparatus. A cleaning gas supply mechanism supplies into a reaction chamber, via a gas inlet formed in the upper wall of the reaction chamber, a hydrogen-containing raw material, such as hydrogen, ammonia, or hydrazine, as a raw material of atomic hydrogen or ammonia-decomposed species.
  • A substrate heating mechanism such as a heater is disposed underneath the reaction chamber, and a sample stage is provided within the reaction chamber to be located immediately above the heating mechanism. A sample (a substrate) is placed on the sample stage such that the surface on which wiring traces are formed faces upward. A catalyst formed of, for example, tungsten wire is disposed between the sample and a shower head for diffusing the gas from the gas inlet. A catalyst heating mechanism heats the catalyst to a high temperature so as to decompose the gas having flowed into the chamber. Thus, atomic hydrogen or ammonia-decomposed species are generated as a result of a catalytic cracking reaction caused by the heated catalyst. Oxides of the copper wiring traces are removed through reduction of atomic hydrogen, and organic dirt is removed through formation of hydro carbon as a result of reaction between atomic hydrogen and carbon.
  • Compounds containing nitrogen, such as ammonia and hydrazine, may be used as the above-described hydrogen-containing compound, which is the raw material of atomic hydrogen or ammonia-decomposed species. In such a case, when a gas of such a compound comes into contact with the heated catalyst, atomic nitrogen is generated simultaneously with generation of atomic hydrogen, whereby metal surfaces can be nitrided by atomic nitrogen, simultaneously with reduction of oxide film on metal surfaces and/or removal of organic substances by atomic hydrogen.
  • In addition to the above-mentioned tungsten, the catalyst may be formed of an element selected from a group consisting of tantalum, molybdenum, vanadium, rhenium, platinum, thorium, zirconium, yttrium, hafnium, palladium, iridium, ruthenium, iron, nickel, chromium, aluminum, silicon, and carbon; an oxide of any one of these elements; a nitride of anyone of these elements; a carbide of any one of these elements (excluding carbon); an oxide of a mixed crystal or compound formed of two or more elements selected from the group; a nitride of a mixed crystal or compound formed of two or more elements selected from the group; or a carbide of a mixed crystal or compound formed of two or more elements selected from the group (excluding carbon). In the case where the catalyst is formed of tungsten, preferably, the catalyst is heated to a temperature within a range of 1000° C. to 2200° C.
  • Notably, a material supply mechanism in FIG. 10 is used to supply hexamethyldisilazane, shiran, or the like so as to deposit, for example, SiN-based film when necessary. Further, a vacuum system is used to discharge reaction residual gasses.
  • A wafer (including a plurality of packages connected two-dimensionally) on which wiring traces are formed by use of nano copper particles, or package substrates diced from the wafer are placed on the sample stage of the copper wiring cleaning apparatus, as a sample (substrate). Subsequently, in order to remove contaminants originating from wiring by use of nano copper particles, hydrogen gas is supplied at a flow rate of 30 sccm for 10 minutes. Thus, the contaminants are removed.
  • While specific embodiments of the invention have been described in detail to illustrate the application of the principles of the invention, it will be understood that the invention may be embodied otherwise without departing from such principles.

Claims (20)

1. A semiconductor device, comprising:
a multilayer substrate having a plurality of package substrates and first and second wirings therein;
an LSI chip mounted on a front-side surface of the multilayer substrate, wherein the LSI chip is electrically connected to the first and second wirings;
a sealing resin which covers the LSI chip on the multilayer substrate;
a plurality of metallic pads formed on the front-side surface of the multilayer substrate and around the sealing resin, wherein at least one of the metallic pads is electrically connected to the first wiring; and
a plurality of back-face electrodes formed on a backside surface of the multilayer substrate, wherein at least one of the electrodes is electrically connected to the second wiring.
2. A semiconductor device in accordance with claim 1, further comprising a bonding wire connecting the LSI chip and the multilayer substrate, wherein the bonding wire is covered with the sealing resin.
3. A semiconductor device in accordance with claim 1, wherein the multilayer substrate has a recess portion in which the LSI chip is disposed.
4. A semiconductor device in accordance with claim 1, wherein the multilayer substrate has a via hole therein and the one of the metallic pads is electrically connected to the first wiring through a conductive member in the via hole.
5. A semiconductor device in accordance with claim 1, wherein the multilayer substrate has a via hole therein and the one of the electrodes is electrically connected to the second wiring through a conductive member in the via hole.
6. A semiconductor device in accordance with claim 1, further comprising another LSI chip mounted on the front-side surface of the multilayer substrate, wherein the another LSI chip is covered with the sealing resin.
7. A semiconductor device in accordance with claim 1, wherein the LSI chip has a main surface in which an LSI circuit is formed, said LSI chip being mounted on the front-side surface of the multilayer substrate with the main surface of the LSI chip facing the front-side surface of the multilayer substrate.
8. A semiconductor device, comprising:
a multilayer substrate having a plurality of package substrates and first and second wirings therein, said multilayer substrate having a front-side surface;
an LSI chip mounted on said front-side surface of the multilayer substrate, wherein the LSI chip is electrically connected to the first and second wirings;
a sealing resin which covers the LSI chip on the multilayer substrate;
a plurality of metallic pads provided on at least a portion of said front-side surface of the multilayer substrate, said plurality of metallic pads being arranged about said sealing resin, wherein at least one of the metallic pads is electrically connected to the first wiring; and
a plurality of back-face electrodes formed on a backside surface of the multilayer substrate, wherein at least one of the electrodes is electrically connected to the second wiring.
9. A semiconductor device in accordance with claim 8, further comprising a bonding wire connecting the LSI chip and the multilayer substrate, wherein the bonding wire is covered with the sealing resin.
10. A semiconductor device in accordance with claim 8, wherein at least a portion of said front-side surface defines a recessed portion, said LSI chip being disposed in said recessed portion.
11. A semiconductor device in accordance with claim 8, wherein the multilayer substrate has a via hole therein and the one of the metallic pads is electrically connected to the first wiring through a conductive member in the via hole.
12. A semiconductor device in accordance with claim 8, wherein the multilayer substrate has a via hole therein and the one of the electrodes is electrically connected to the second wiring through a conductive member in the via hole.
13. A semiconductor device in accordance with claim 8, further comprising another LSI chip mounted on the front-side surface of the multilayer substrate, wherein the another LSI chip is covered with the sealing resin.
14. A semiconductor device in accordance with claim 8, wherein the LSI chip has a main surface in which an LSI circuit is formed, said LSI chip being mounted on the front-side surface of the multilayer substrate with the main surface of the LSI chip facing the front-side surface of the multilayer substrate.
15. A semiconductor device, comprising:
a multilayer substrate having a plurality of package substrates and first and second wirings therein, said multilayer substrate having a front-side surface;
an LSI chip mounted on said front-side surface of the multilayer substrate, wherein the LSI chip is electrically connected to the first and second wirings;
a sealing resin which covers the LSI chip on the multilayer substrate, at least a portion of said sealing resin engaging said front-side surface;
a plurality of metallic pads provided on at least a portion of said front-side surface of the multilayer substrate, said plurality of metallic pads being arranged about said sealing resin, wherein at least one of the metallic pads is electrically connected to the first wiring;
a plurality of back-face electrodes formed on a backside surface of the multilayer substrate, wherein at least one of the electrodes is electrically connected to the second wiring.
16. A semiconductor device in accordance with claim 15, further comprising a bonding wire connecting the LSI chip and the multilayer substrate, wherein the bonding wire is covered with the sealing resin.
17. A semiconductor device in accordance with claim 15, wherein at least a portion of said front-side surface defines a recessed portion, said LSI chip being disposed in said recessed portion.
18. A semiconductor device in accordance with claim 15, wherein the multilayer substrate has a via hole therein and the one of the metallic pads is electrically connected to the first wiring through a conductive member in the via hole.
19. A semiconductor device in accordance with claim 15, wherein the multilayer substrate has a via hole therein and the one of the electrodes is electrically connected to the second wiring through a conductive member in the via hole.
20. A semiconductor device in accordance with claim 15, further comprising another LSI chip mounted on the front-side surface of the multilayer substrate, wherein the another LSI chip is covered with the sealing resin.
US12/978,877 2006-04-25 2010-12-27 Semiconductor device with double-sided electrode structure and its manufacturing method Abandoned US20110089551A1 (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130044448A1 (en) * 2011-08-18 2013-02-21 Biotronik Se & Co. Kg Method for Mounting a Component to an Electric Circuit Board, Electric Circuit Board and Electric Circuit Board Arrangement
US20130313002A1 (en) * 2012-05-28 2013-11-28 Zhen Ding Technology Co., Ltd. Multilayer printed circuit board and method for manufacturing same
US8987869B2 (en) 2012-01-11 2015-03-24 Samsung Electronics Co., Ltd. Integrated circuit devices including through-silicon-vias having integral contact pads
US20150125993A1 (en) * 2013-11-04 2015-05-07 Amkor Technology, Inc. Interposer, manufacturing method thereof, semiconductor package using the same, and method for fabricating the semiconductor package
US10347550B2 (en) * 2016-09-15 2019-07-09 Rohm Co., Ltd. Semiconductor package and method of making the same

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5280014B2 (en) 2007-04-27 2013-09-04 ラピスセミコンダクタ株式会社 Semiconductor device and manufacturing method thereof
JP5215587B2 (en) 2007-04-27 2013-06-19 ラピスセミコンダクタ株式会社 Semiconductor device
US7894199B1 (en) * 2008-02-20 2011-02-22 Altera Corporation Hybrid package
US7989950B2 (en) * 2008-08-14 2011-08-02 Stats Chippac Ltd. Integrated circuit packaging system having a cavity
US8823160B2 (en) * 2008-08-22 2014-09-02 Stats Chippac Ltd. Integrated circuit package system having cavity
KR101040311B1 (en) * 2008-12-24 2011-06-10 에스티에스반도체통신 주식회사 Semiconductor package and method of formation of the same
US9406561B2 (en) * 2009-04-20 2016-08-02 International Business Machines Corporation Three dimensional integrated circuit integration using dielectric bonding first and through via formation last
US8400782B2 (en) * 2009-07-24 2013-03-19 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
EP2309535A1 (en) * 2009-10-09 2011-04-13 Telefonaktiebolaget L M Ericsson (Publ) Chip package with a chip embedded in a wiring body
US8421210B2 (en) 2010-05-24 2013-04-16 Stats Chippac Ltd. Integrated circuit packaging system with dual side connection and method of manufacture thereof
JP5622494B2 (en) * 2010-09-09 2014-11-12 スタンレー電気株式会社 Light emitting device and manufacturing method thereof
JP2012248583A (en) * 2011-05-25 2012-12-13 Jjtech Co Ltd Manufacturing method of semiconductor device, semiconductor device and manufacturing method of intermediate plate
US8563403B1 (en) 2012-06-27 2013-10-22 International Business Machines Corporation Three dimensional integrated circuit integration using alignment via/dielectric bonding first and through via formation last
US9406533B2 (en) * 2013-06-27 2016-08-02 STATS ChipPAC Pte. Ltd. Methods of forming conductive and insulating layers
US11257998B2 (en) 2017-03-21 2022-02-22 Lg Innotek Co., Ltd. Semiconductor element package and autofocusing device
KR102334644B1 (en) * 2017-03-21 2021-12-06 엘지이노텍 주식회사 Semiconductor device package and auto focusing apparatus
WO2019132970A1 (en) 2017-12-29 2019-07-04 Intel Corporation Microelectronic assemblies
DE112017008327T5 (en) 2017-12-29 2020-10-08 Intel Corporation MICROELECTRONIC ARRANGEMENTS
DE112017008326T5 (en) 2017-12-29 2020-10-08 Intel Corporation Microelectronic assemblies
CN116798983A (en) 2017-12-29 2023-09-22 英特尔公司 Microelectronic assembly with communication network
WO2019132963A1 (en) 2017-12-29 2019-07-04 Intel Corporation Quantum computing assemblies
US11469206B2 (en) 2018-06-14 2022-10-11 Intel Corporation Microelectronic assemblies
US11772178B2 (en) 2019-01-08 2023-10-03 American Battery Solutions, Inc. Multi-layer contact plate and method thereof
US11222834B2 (en) 2019-03-22 2022-01-11 Analog Devices International Unlimited Company Package with electrical pathway
EP3799539B1 (en) * 2019-09-27 2022-03-16 Siemens Aktiengesellschaft Circuit carrier, package and method for its production

Citations (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4513355A (en) * 1983-06-15 1985-04-23 Motorola, Inc. Metallization and bonding means and method for VLSI packages
US4729061A (en) * 1985-04-29 1988-03-01 Advanced Micro Devices, Inc. Chip on board package for integrated circuit devices using printed circuit boards and means for conveying the heat to the opposite side of the package from the chip mounting side to permit the heat to dissipate therefrom
US5237204A (en) * 1984-05-25 1993-08-17 Compagnie D'informatique Militaire Spatiale Et Aeronautique Electric potential distribution device and an electronic component case incorporating such a device
US5432677A (en) * 1993-02-09 1995-07-11 Texas Instruments Incorporated Multi-chip integrated circuit module
US5468999A (en) * 1994-05-26 1995-11-21 Motorola, Inc. Liquid encapsulated ball grid array semiconductor device with fine pitch wire bonding
US5689091A (en) * 1996-09-19 1997-11-18 Vlsi Technology, Inc. Multi-layer substrate structure
US5761044A (en) * 1995-02-14 1998-06-02 Nec Corporation Semiconductor module for microprocessor
US5861670A (en) * 1979-10-04 1999-01-19 Fujitsu Limited Semiconductor device package
US5863815A (en) * 1997-02-25 1999-01-26 Oki Electric Industry Co., Ltd. Method of manufacturing semiconductor device
US5909058A (en) * 1996-09-25 1999-06-01 Kabushiki Kaisha Toshiba Semiconductor package and semiconductor mounting part
US6144090A (en) * 1997-02-13 2000-11-07 Fujitsu Limited Ball grid array package having electrodes on peripheral side surfaces of a package board
US6154366A (en) * 1999-11-23 2000-11-28 Intel Corporation Structures and processes for fabricating moisture resistant chip-on-flex packages
US6324067B1 (en) * 1995-11-16 2001-11-27 Matsushita Electric Industrial Co., Ltd. Printed wiring board and assembly of the same
US20020022300A1 (en) * 1998-10-24 2002-02-21 Hyundai Electronics Industries Co., Ltd. Method for fabricating a stacked semiconductor chip package
US20020020898A1 (en) * 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
US20020020916A1 (en) * 2000-07-07 2002-02-21 Mutsuyoshi Ito Semiconductor package and method for producing the same
US20020117743A1 (en) * 2000-12-27 2002-08-29 Matsushita Electric Industrial Co., Ltd. Component built-in module and method for producing the same
US6507119B2 (en) * 2000-11-30 2003-01-14 Siliconware Precision Industries Co., Ltd. Direct-downset flip-chip package assembly and method of fabricating the same
US6538210B2 (en) * 1999-12-20 2003-03-25 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module, radio device having the same, and method for producing the same
US6548330B1 (en) * 1999-11-17 2003-04-15 Sony Corporation Semiconductor apparatus and method of fabricating semiconductor apparatus
US6680529B2 (en) * 2002-02-15 2004-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor build-up package
US6698093B2 (en) * 1999-12-15 2004-03-02 Matsushita Electric Industrial Co., Ltd. Method of manufacturing circuit forming board to improve adhesion of a circuit to the circuit forming board
US20040048421A1 (en) * 2000-02-17 2004-03-11 Takashi Noguchi Method of encapsulating conductive lines of semiconductor devices
US20040183187A1 (en) * 2003-03-17 2004-09-23 Tomoo Yamasaki Semiconductor device, semiconductor device substrate, and manufacturing method thereof that can increase reliability in mounting a semiconductor element
US20050017347A1 (en) * 2003-07-22 2005-01-27 Matsushita Electric Industrial Co., Ltd. Circuit module and manufacturing method thereof
US6865089B2 (en) * 2002-06-27 2005-03-08 Via Technologies, Inc. Module board having embedded chips and components and method of forming the same
US6879493B2 (en) * 1999-04-16 2005-04-12 Matsushita Electric Industrial Co., Ltd. Module component and method of manufacturing the same
US20050253244A1 (en) * 2004-05-11 2005-11-17 Wen-Yuan Chang Chip embedded package structure
US20050269128A1 (en) * 2004-06-08 2005-12-08 Ryosuke Usui Semiconductor module with high process accuracy, manufacturing method thereof, and semiconductor device therewith
US20060068332A1 (en) * 2004-09-29 2006-03-30 Phoenix Precision Technology Corporation Method for fabricating carrier structure integrated with semiconductor element
US20060087037A1 (en) * 2004-10-22 2006-04-27 Phoenix Precision Technology Corporation Substrate structure with embedded chip of semiconductor package and method for fabricating the same
US7050304B2 (en) * 2003-08-28 2006-05-23 Phoenix Precision Technology Corporation Heat sink structure with embedded electronic components for semiconductor package
US7087988B2 (en) * 2002-07-30 2006-08-08 Kabushiki Kaisha Toshiba Semiconductor packaging apparatus
US20060186531A1 (en) * 2005-02-22 2006-08-24 Phoenix Precision Technology Corporation Package structure with chip embedded in substrate
US20060214288A1 (en) * 2005-03-02 2006-09-28 Takashi Ohsumi Semiconductor device
US7230332B2 (en) * 2005-01-19 2007-06-12 Via Technologies, Inc. Chip package with embedded component
US7242092B2 (en) * 2005-02-02 2007-07-10 Phoenix Precision Technology Corporation Substrate assembly with direct electrical connection as a semiconductor package
US7312405B2 (en) * 2005-02-01 2007-12-25 Phoenix Precision Technology Corporation Module structure having embedded chips
US7365421B2 (en) * 2004-11-05 2008-04-29 Altus Technology Inc. IC chip package with isolated vias
US20090020882A1 (en) * 2007-07-17 2009-01-22 Oki Electric Industry Co., Ltd. Semiconductor device and method of producing the same
US20090188703A1 (en) * 2008-01-25 2009-07-30 Ibiden Co., Ltd. Multilayer wiring board and method of manufacturing the same
US7602062B1 (en) * 2005-08-10 2009-10-13 Altera Corporation Package substrate with dual material build-up layers
US7653991B2 (en) * 2007-04-30 2010-02-02 Samsung Electro-Mechanics Co., Ltd. Method for manufacturing printed circuit board having embedded component
US7730612B2 (en) * 2007-08-22 2010-06-08 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing component-embedded printed circuit board
US7894203B2 (en) * 2003-02-26 2011-02-22 Ibiden Co., Ltd. Multilayer printed wiring board
US7989944B2 (en) * 2002-01-31 2011-08-02 Imbera Electronics Oy Method for embedding a component in a base
US8101868B2 (en) * 2005-10-14 2012-01-24 Ibiden Co., Ltd. Multilayered printed circuit board and method for manufacturing the same
US8320134B2 (en) * 2010-02-05 2012-11-27 Advanced Semiconductor Engineering, Inc. Embedded component substrate and manufacturing methods thereof
US8320135B2 (en) * 2005-12-16 2012-11-27 Ibiden Co., Ltd. Multilayer printed circuit board

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51150068A (en) * 1975-06-19 1976-12-23 Citizen Watch Co Ltd Electronic circuit block
JPS6361150A (en) 1986-09-01 1988-03-17 Ricoh Co Ltd Method for inspecting flaw of optical information recording medium
JPS6361150U (en) * 1986-10-13 1988-04-22
US5583378A (en) * 1994-05-16 1996-12-10 Amkor Electronics, Inc. Ball grid array integrated circuit package with thermal conductor
US5907187A (en) * 1994-07-18 1999-05-25 Kabushiki Kaisha Toshiba Electronic component and electronic component connecting structure
KR0179921B1 (en) * 1996-05-17 1999-03-20 문정환 Stacked semiconductor package
JPH10150118A (en) 1996-11-15 1998-06-02 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacture
US5847935A (en) * 1996-12-16 1998-12-08 Sarnoff Corporation Electronic circuit chip package
US6020637A (en) * 1997-05-07 2000-02-01 Signetics Kp Co., Ltd. Ball grid array semiconductor package
US6107683A (en) * 1997-06-20 2000-08-22 Substrate Technologies Incorporated Sequentially built integrated circuit package
JP3147053B2 (en) * 1997-10-27 2001-03-19 日本電気株式会社 Resin-sealed ball grid array IC package and method of manufacturing the same
JPH11168150A (en) 1997-12-04 1999-06-22 Mitsubishi Electric Corp Semiconductor integrated circuit device
CN100381026C (en) * 1999-09-02 2008-04-09 伊比登株式会社 Printed wiring board and method of producing same
JP2001127243A (en) 1999-10-26 2001-05-11 Sharp Corp Laminated semiconductor device
JP2001230515A (en) 2000-02-15 2001-08-24 Matsushita Electric Ind Co Ltd Mounting member of electronic component, method of manufacturing mounting member of electronic component, and secondary mounting structure of mounting member
JP2002158312A (en) 2000-11-17 2002-05-31 Oki Electric Ind Co Ltd Semiconductor package for three-dimensional mounting, its manufacturing method and semiconductor device
JP3614776B2 (en) * 2000-12-19 2005-01-26 シャープ株式会社 Chip component type LED and its manufacturing method
US20040012698A1 (en) 2001-03-05 2004-01-22 Yasuo Suda Image pickup model and image pickup device
JP3733419B2 (en) * 2001-07-17 2006-01-11 日立エーアイシー株式会社 Electronic component built-in type multilayer substrate, method for manufacturing the same, and metal core substrate used therefor
US6916682B2 (en) * 2001-11-08 2005-07-12 Freescale Semiconductor, Inc. Semiconductor package device for use with multiple integrated circuits in a stacked configuration and method of formation and testing
FI115285B (en) * 2002-01-31 2005-03-31 Imbera Electronics Oy Method of immersing a component in a base material and forming a contact
JP4045143B2 (en) * 2002-02-18 2008-02-13 テセラ・インターコネクト・マテリアルズ,インコーポレイテッド Manufacturing method of wiring film connecting member and manufacturing method of multilayer wiring board
JP2003249604A (en) 2002-02-25 2003-09-05 Kato Denki Seisakusho:Kk Resin-sealed semiconductor device and method of the same, lead frame used in resin-sealed semiconductor device, and semiconductor module device
US6713856B2 (en) * 2002-09-03 2004-03-30 Ultratera Corporation Stacked chip package with enhanced thermal conductivity
TWI220782B (en) * 2002-10-14 2004-09-01 Siliconware Precision Industries Co Ltd Cavity-down ball grid array package with heat spreader
US6841883B1 (en) * 2003-03-31 2005-01-11 Micron Technology, Inc. Multi-dice chip scale semiconductor components and wafer level methods of fabrication
US6864165B1 (en) * 2003-09-15 2005-03-08 International Business Machines Corporation Method of fabricating integrated electronic chip with an interconnect device
JP2005197491A (en) * 2004-01-08 2005-07-21 Matsushita Electric Ind Co Ltd Semiconductor device
JP4403821B2 (en) * 2004-02-17 2010-01-27 ソニー株式会社 Package substrate and manufacturing method thereof, semiconductor device and manufacturing method thereof, and laminated structure
JP2005317861A (en) * 2004-04-30 2005-11-10 Toshiba Corp Semiconductor device and method of manufacturing the same
WO2005122230A1 (en) * 2004-06-07 2005-12-22 Kyushu Institute Of Technology Method for processing copper surface, method for forming copper pattern wiring and semiconductor device manufactured using such method
JP4765055B2 (en) 2004-06-07 2011-09-07 国立大学法人九州工業大学 Copper surface treatment method
JP3870273B2 (en) 2004-12-28 2007-01-17 国立大学法人九州工業大学 Copper pattern wiring formation method, semiconductor device created using the method, and nano copper metal particles

Patent Citations (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5861670A (en) * 1979-10-04 1999-01-19 Fujitsu Limited Semiconductor device package
US4513355A (en) * 1983-06-15 1985-04-23 Motorola, Inc. Metallization and bonding means and method for VLSI packages
US5237204A (en) * 1984-05-25 1993-08-17 Compagnie D'informatique Militaire Spatiale Et Aeronautique Electric potential distribution device and an electronic component case incorporating such a device
US4729061A (en) * 1985-04-29 1988-03-01 Advanced Micro Devices, Inc. Chip on board package for integrated circuit devices using printed circuit boards and means for conveying the heat to the opposite side of the package from the chip mounting side to permit the heat to dissipate therefrom
US5432677A (en) * 1993-02-09 1995-07-11 Texas Instruments Incorporated Multi-chip integrated circuit module
US5468999A (en) * 1994-05-26 1995-11-21 Motorola, Inc. Liquid encapsulated ball grid array semiconductor device with fine pitch wire bonding
US5761044A (en) * 1995-02-14 1998-06-02 Nec Corporation Semiconductor module for microprocessor
US6324067B1 (en) * 1995-11-16 2001-11-27 Matsushita Electric Industrial Co., Ltd. Printed wiring board and assembly of the same
US5689091A (en) * 1996-09-19 1997-11-18 Vlsi Technology, Inc. Multi-layer substrate structure
US5909058A (en) * 1996-09-25 1999-06-01 Kabushiki Kaisha Toshiba Semiconductor package and semiconductor mounting part
US6144090A (en) * 1997-02-13 2000-11-07 Fujitsu Limited Ball grid array package having electrodes on peripheral side surfaces of a package board
US5863815A (en) * 1997-02-25 1999-01-26 Oki Electric Industry Co., Ltd. Method of manufacturing semiconductor device
US20020022300A1 (en) * 1998-10-24 2002-02-21 Hyundai Electronics Industries Co., Ltd. Method for fabricating a stacked semiconductor chip package
US6879493B2 (en) * 1999-04-16 2005-04-12 Matsushita Electric Industrial Co., Ltd. Module component and method of manufacturing the same
US6548330B1 (en) * 1999-11-17 2003-04-15 Sony Corporation Semiconductor apparatus and method of fabricating semiconductor apparatus
US6154366A (en) * 1999-11-23 2000-11-28 Intel Corporation Structures and processes for fabricating moisture resistant chip-on-flex packages
US6698093B2 (en) * 1999-12-15 2004-03-02 Matsushita Electric Industrial Co., Ltd. Method of manufacturing circuit forming board to improve adhesion of a circuit to the circuit forming board
US6538210B2 (en) * 1999-12-20 2003-03-25 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module, radio device having the same, and method for producing the same
US20040048421A1 (en) * 2000-02-17 2004-03-11 Takashi Noguchi Method of encapsulating conductive lines of semiconductor devices
US6707166B1 (en) * 2000-02-17 2004-03-16 Oki Electric Industry Co., Ltd. Semiconductor devices and manufacturing method thereof
US6780671B2 (en) * 2000-02-17 2004-08-24 Oki Electric Industry Co., Ltd. Method of encapsulating conductive lines of semiconductor devices
US7002236B2 (en) * 2000-07-07 2006-02-21 Sony Corporation Semiconductor package and method for producing the same
US20020020916A1 (en) * 2000-07-07 2002-02-21 Mutsuyoshi Ito Semiconductor package and method for producing the same
US20020020898A1 (en) * 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
US6507119B2 (en) * 2000-11-30 2003-01-14 Siliconware Precision Industries Co., Ltd. Direct-downset flip-chip package assembly and method of fabricating the same
US20020117743A1 (en) * 2000-12-27 2002-08-29 Matsushita Electric Industrial Co., Ltd. Component built-in module and method for producing the same
US7989944B2 (en) * 2002-01-31 2011-08-02 Imbera Electronics Oy Method for embedding a component in a base
US6680529B2 (en) * 2002-02-15 2004-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor build-up package
US6865089B2 (en) * 2002-06-27 2005-03-08 Via Technologies, Inc. Module board having embedded chips and components and method of forming the same
US7087988B2 (en) * 2002-07-30 2006-08-08 Kabushiki Kaisha Toshiba Semiconductor packaging apparatus
US7894203B2 (en) * 2003-02-26 2011-02-22 Ibiden Co., Ltd. Multilayer printed wiring board
US20040183187A1 (en) * 2003-03-17 2004-09-23 Tomoo Yamasaki Semiconductor device, semiconductor device substrate, and manufacturing method thereof that can increase reliability in mounting a semiconductor element
US20050017347A1 (en) * 2003-07-22 2005-01-27 Matsushita Electric Industrial Co., Ltd. Circuit module and manufacturing method thereof
US7050304B2 (en) * 2003-08-28 2006-05-23 Phoenix Precision Technology Corporation Heat sink structure with embedded electronic components for semiconductor package
US20050253244A1 (en) * 2004-05-11 2005-11-17 Wen-Yuan Chang Chip embedded package structure
US20050269128A1 (en) * 2004-06-08 2005-12-08 Ryosuke Usui Semiconductor module with high process accuracy, manufacturing method thereof, and semiconductor device therewith
US20060068332A1 (en) * 2004-09-29 2006-03-30 Phoenix Precision Technology Corporation Method for fabricating carrier structure integrated with semiconductor element
US20060087037A1 (en) * 2004-10-22 2006-04-27 Phoenix Precision Technology Corporation Substrate structure with embedded chip of semiconductor package and method for fabricating the same
US7365421B2 (en) * 2004-11-05 2008-04-29 Altus Technology Inc. IC chip package with isolated vias
US7230332B2 (en) * 2005-01-19 2007-06-12 Via Technologies, Inc. Chip package with embedded component
US7312405B2 (en) * 2005-02-01 2007-12-25 Phoenix Precision Technology Corporation Module structure having embedded chips
US7242092B2 (en) * 2005-02-02 2007-07-10 Phoenix Precision Technology Corporation Substrate assembly with direct electrical connection as a semiconductor package
US20060186531A1 (en) * 2005-02-22 2006-08-24 Phoenix Precision Technology Corporation Package structure with chip embedded in substrate
US20060214288A1 (en) * 2005-03-02 2006-09-28 Takashi Ohsumi Semiconductor device
US7602062B1 (en) * 2005-08-10 2009-10-13 Altera Corporation Package substrate with dual material build-up layers
US8101868B2 (en) * 2005-10-14 2012-01-24 Ibiden Co., Ltd. Multilayered printed circuit board and method for manufacturing the same
US8320135B2 (en) * 2005-12-16 2012-11-27 Ibiden Co., Ltd. Multilayer printed circuit board
US7653991B2 (en) * 2007-04-30 2010-02-02 Samsung Electro-Mechanics Co., Ltd. Method for manufacturing printed circuit board having embedded component
US20090020882A1 (en) * 2007-07-17 2009-01-22 Oki Electric Industry Co., Ltd. Semiconductor device and method of producing the same
US7730612B2 (en) * 2007-08-22 2010-06-08 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing component-embedded printed circuit board
US20090188703A1 (en) * 2008-01-25 2009-07-30 Ibiden Co., Ltd. Multilayer wiring board and method of manufacturing the same
US8320134B2 (en) * 2010-02-05 2012-11-27 Advanced Semiconductor Engineering, Inc. Embedded component substrate and manufacturing methods thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130044448A1 (en) * 2011-08-18 2013-02-21 Biotronik Se & Co. Kg Method for Mounting a Component to an Electric Circuit Board, Electric Circuit Board and Electric Circuit Board Arrangement
US8987869B2 (en) 2012-01-11 2015-03-24 Samsung Electronics Co., Ltd. Integrated circuit devices including through-silicon-vias having integral contact pads
US20130313002A1 (en) * 2012-05-28 2013-11-28 Zhen Ding Technology Co., Ltd. Multilayer printed circuit board and method for manufacturing same
US20150125993A1 (en) * 2013-11-04 2015-05-07 Amkor Technology, Inc. Interposer, manufacturing method thereof, semiconductor package using the same, and method for fabricating the semiconductor package
US9704842B2 (en) * 2013-11-04 2017-07-11 Amkor Technology, Inc. Interposer, manufacturing method thereof, semiconductor package using the same, and method for fabricating the semiconductor package
US10347550B2 (en) * 2016-09-15 2019-07-09 Rohm Co., Ltd. Semiconductor package and method of making the same

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