US20110090648A1 - Electronic package structure - Google Patents

Electronic package structure Download PDF

Info

Publication number
US20110090648A1
US20110090648A1 US12/971,671 US97167110A US2011090648A1 US 20110090648 A1 US20110090648 A1 US 20110090648A1 US 97167110 A US97167110 A US 97167110A US 2011090648 A1 US2011090648 A1 US 2011090648A1
Authority
US
United States
Prior art keywords
electronic
electronic package
package structure
disposed
electronic element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/971,671
Inventor
Da-Jung Chen
Chau-Chun Wen
Chun-Tiao Liu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cyntec Co Ltd
Original Assignee
Cyntec Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cyntec Co Ltd filed Critical Cyntec Co Ltd
Priority to US12/971,671 priority Critical patent/US20110090648A1/en
Publication of US20110090648A1 publication Critical patent/US20110090648A1/en
Priority to US13/481,887 priority patent/US9271398B2/en
Priority to US13/485,954 priority patent/US9001527B2/en
Priority to US13/754,910 priority patent/US8837168B2/en
Priority to US14/594,084 priority patent/US9538660B2/en
Priority to US14/594,083 priority patent/US9451701B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00Details of transformers or inductances, in general
    • H01F27/28Coils; Windings; Conductive connections
    • H01F27/29Terminals; Tapping arrangements for signal inductances
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/645Inductive arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K9/00Screening of apparatus or components against electric or magnetic fields
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00Details of transformers or inductances, in general
    • H01F27/02Casings
    • H01F27/027Casings specially adapted for combination of signal type inductors or transformers with electronic circuits, e.g. mounting on printed circuit boards
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/16Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007Types of components
    • H05K2201/1003Non-printed inductor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431Details of mounted components
    • H05K2201/10507Involving several components
    • H05K2201/10515Stacked components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431Details of mounted components
    • H05K2201/10507Involving several components
    • H05K2201/10537Attached components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10742Details of leads
    • H05K2201/10886Other details
    • H05K2201/10924Leads formed from a punched metal foil
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/4902Electromagnet, transformer or inductor
    • Y10T29/49071Electromagnet, transformer or inductor by winding or coiling
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.

Definitions

  • the present invention relates to a package structure. More particularly, the present invention relates to an electronic package structure.
  • Electronic package structures are formed by complicated package processes. Different electronic package structures have different electrical performances and capacities of heat dissipation, and therefore a designer may select an electronic package structure with a desired electrical performance and capacity of heat dissipation according to a design requirement.
  • FIG. 1 is a schematic diagram of a conventional electronic package structure.
  • the conventional electronic package structure 100 includes a printed circuit board (PCB) 110 and a plurality of electronic elements 120 .
  • the electronic elements 120 are disposed on a surface 112 of the PCB 110 and electrically connected to the PCB 110 .
  • the PCB 110 has a plurality of pins 116 extending out from another surface 114 of the PCB 110 to be electrically connected to an electronic device, for example, a motherboard (not shown).
  • FIG. 2 is a schematic diagram of another conventional electronic package structure.
  • the conventional electronic package structure 200 includes a circuit substrate 210 and a plurality of electronic elements 220 .
  • the electronic elements 220 are disposed on a surface 212 of the circuit substrate 210 , and electrically connected to the circuit substrate 210 via a wire bonding technology, a flip-chip bonding technology or a surface mount technology.
  • the conventional electronic package structure 200 may be electrically connected to an electronic device, for example, a motherboard (not shown), via a solder paste or a plurality of solder balls (not shown).
  • the electronic elements 120 of the conventional electronic package structure 100 are all disposed on the surface 112 of the PCB 110
  • the electronic elements 220 of the conventional electronic package structure 200 are all disposed on the surface 212 of the circuit substrate 210 . Therefore, in the conventional electronic package structures 100 and 200 , spatial utilization of the PCB 110 and the circuit substrate 210 is relatively low, and sizes of the conventional electronic package structures 100 and 200 are relatively great.
  • an electronic package structure can achieve a relatively high utilization of an internal space thereof, so that a size of the electronic package structure can be reduced.
  • an electronic package structure includes at least a first electronic element, a second electronic element and a first lead frame.
  • the second electronic element includes a body having a cavity.
  • the first electronic element is disposed in the cavity.
  • the lead frame has a plurality of leads. Each of the leads has a first end and a second end, and the first end of at least one of the leads extends to the cavity to electrically connect the first electronic element.
  • an electronic package structure includes at least one first electronic element, a second electronic element and a lead frame.
  • the second electronic element includes a body having a first surface.
  • the lead frame has a plurality of leads. Each of the leads has a first end and a second end. The first ends are disposed on the first surface, and the first electronic element is disposed on the first surface and electrically connected to at least one of the leads.
  • an electronic package structure in one embodiment, includes a circuit substrate, at least one first electronic element and a second electronic element.
  • the circuit substrate has a first surface.
  • the first electronic element is disposed on the first surface of the circuit substrate and electrically connected to the circuit substrate.
  • the second electronic element is disposed above the first surface of the circuit substrate and includes a body and a plurality of leads.
  • Each of the leads has a first end and second end, and the second end of each of the leads extends out from the body to electrically connect the circuit substrate.
  • the first electronic element is located among the body of the second electronic element, the first surface of the circuit substrate and the leads.
  • the first electronic element can be disposed in the cavity of the second electronic element or on the second electronic element, or the second electronic element can be stacked on the first electronic element, compared to the conventional electronic package structures, utilization of an internal space of the electronic package structure is relatively high.
  • FIG. 1 is a schematic diagram of a conventional electronic package structure.
  • FIG. 2 is a schematic diagram of another conventional electronic package structure.
  • FIG. 3A is a schematic diagram of an electronic package structure according to a first embodiment of the present invention.
  • FIG. 3B is a schematic diagram of another electronic package structure according to the first embodiment of the present invention.
  • FIG. 3C is a schematic diagram of another electronic package structure according to the first embodiment of the present invention.
  • FIG. 3D is a schematic diagram of still another electronic package structure according to the first embodiment of the present invention.
  • FIG. 4A is a schematic diagram of an electronic package structure according to a second embodiment of the present invention.
  • FIG. 4B is a schematic diagram of another electronic package structure according to the second embodiment of the present invention.
  • FIG. 5A is a schematic diagram of an electronic package structure according to a third embodiment of the present invention.
  • FIG. 5B is a schematic diagram of another electronic package structure according to the third embodiment of the present invention.
  • FIG. 3A is a schematic diagram of an electronic package structure according to a first embodiment of the present invention.
  • the electronic package structure 300 includes at least one first electronic element 310 (two first electronic elements are illustrated in FIG. 3A ), a second electronic element 320 and a first lead frame 330 .
  • the electronic package structure 300 is generally applied to a voltage regulator module, a network adapter, a graphics processing unit, a DC/DC converter or a point-of-load (POL) converter.
  • Each of the first electronic elements 310 can be a logical control element, a driving element or a passive element.
  • the passive element can be a capacitor, an inductor with lesser inductance, or a resistor.
  • Each of the first electronic elements 310 can also be a power element, such as a metal-oxide-semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT) or a diode.
  • MOSFET metal-oxide-semiconductor field effect
  • the second electronic element 320 includes a body 322 having a cavity 322 a .
  • the first electronic elements 310 are disposed in the cavity 322 a.
  • the body 322 of the second electronic element 320 has a first surface 322 b, a second surface 322 c opposite to the first surface 322 b and a side surface 322 d.
  • the cavity 322 a sinks in a direction from the second surface 322 c towards the first surface 322 b .
  • the side surface 322 d connects the first surface 322 b and the second surface 322 c .
  • the second electronic element 320 can be an energy-storage element used for storing electric energy.
  • the second electronic element 320 further includes a coil 324 and a plurality of first external electrodes 326 .
  • the coil 324 is disposed within the body 322 .
  • the first external electrodes 326 are respectively connected to two opposite ends of the coil 324 , and extend outside the body 322 to locate on the first surface 322 b and the side surface 322 d.
  • the body 322 comprising a magnetic body encloses the coil 324 .
  • the second electronic element 320 can be an inductive element with a greater inductance and a greater size than the first electronic elements 310 .
  • the first lead frame 330 has a plurality of leads 332 .
  • Each of the leads 332 has a first end 332 a and a second end 332 b, and the first end 332 a of each of the leads 332 can be embedded in the body 322 and extends to the cavity 322 a for electrically connecting to the first electronic elements 310 .
  • the second end 332 b of each of the leads 332 is disposed on the first surface 322 b of the body 322 to form a second external electrode 332 c, and a part of each of the leads 332 connecting the first end 332 a and the second end 332 b is disposed on the side surface 322 d of the body 322 .
  • the electronic package structure 300 further includes a circuit substrate 340 and an insulating encapsulant 350 .
  • the circuit substrate 340 is disposed in the cavity 322 a of the body 322 .
  • the first electronic elements 310 can be disposed on the circuit substrate 340 and electrically connected to the circuit substrate 340 .
  • the circuit substrate 340 is electrically connected to the first end 332 a of each of the leads 332 extending to the cavity 322 a.
  • the first electronic elements 310 may be electrically connected to the circuit substrate 340 via a wire bonding technology, a flip-chip bonding technology or a surface mount technology.
  • the circuit substrate 340 has a first circuit layer 342 , a second circuit layer 344 , a dielectric layer 346 disposed between the first circuit layer 342 and the second circuit layer 344 , and at least a conductive channel 348 .
  • the first electronic elements 310 are disposed on the first circuit layer 342 , and the conductive channel 348 penetrates the dielectric layer 346 for electrically connecting the first circuit layer 342 and the second circuit layer 344 .
  • the circuit board 340 of the electronic package structure 300 may be omitted according to a design requirement of a designer, though it is not illustrated.
  • the insulating encapsulant 350 is disposed in the cavity 322 a and encapsulates the first electronic elements 310 and the circuit substrate 340 for protecting the first electronic elements 310 and the circuit substrate 340 , and enhancing a whole mechanical strength of the electronic package structure 300 .
  • the first electronic elements 310 and the circuit substrate 340 are disposed in the cavity 322 a of the second electronic element 320 , compared to a conventional electronic package structures of FIG. 1 and FIG. 2 , utilization of an internal space of the electronic package structure 300 is relatively high, and the first electronic elements 310 and the circuit substrate 340 can be protected by the cavity 322 a .
  • the insulating encapsulant 350 is disposed in the cavity 322 a, material of the insulating encapsulant 350 can be directly filled into the cavity 322 a without aiding of extra mold during formation of the insulating encapsulant 350 .
  • FIG. 3B is a schematic diagram of another electronic package structure according to the first embodiment of the present invention.
  • a difference between the electronic package structure 300 ′ and the electronic package structure 300 is that a part of each lead 332 ′ connecting a first end 332 a ′ and a second end 332 b ′ penetrates a body 322 ′.
  • the insulating encapsulant 350 of the electronic package structure 300 is different from a magnetic encapsulant 350 ′ of the electronic package structure 300 ′.
  • the magnetic encapsulant 350 ′ is disposed in a cavity 322 a ′ of the body 322 ′.
  • a second electronic element 320 ′ is an inductive element
  • an inductive characteristic of the second electronic element 320 ′ influenced by the cavity 322 ′ then can be compensated by the magnetic encapsulant 350 ′.
  • a part of each of the leads 332 connecting the first end 332 a and the second end 332 b may also penetrate the body 322 according to a design requirement, though it is not illustrated.
  • FIG. 3C is a schematic diagram of another electronic package structure according to the first embodiment of the present invention.
  • a difference between the electronic package structure 300 ′′ and the electronic package structure 300 is that a cavity 322 a ′′ of a body 322 ′′ sinks in a direction from a first surface 322 b ′′ towards a second surface 322 c ′′.
  • an insulating encapsulant 350 ′′ can be substituted by a magnetic encapsulant according to a design requirement, and a part of each lead 332 ′′ connecting a first end 332 a ′′ and a second end 332 b ′′ may also penetrate the body 322 ′′ according to a design requirement, though it is not illustrated.
  • FIG. 3D is a schematic diagram of still another electronic package structure according to the first embodiment of the present invention.
  • a second lead frame 360 is applied in the electronic package structure 300 ′′′ for substituting the circuit substrate 340 of the electronic package structure 300 according to a design requirement.
  • a plurality of first electronic elements 310 ′′′ are disposed on the second lead frame 360 and electrically connected to the second lead frame 360 .
  • the second lead frame 360 is electrically connected to a first end 332 a ′′′ of each lead 332 ′′′ of a first lead frame 330 ′′′ that extends to a cavity 322 a ′′′.
  • FIG. 4A is a schematic diagram of an electronic package structure according to a second embodiment of the present invention.
  • a difference between the electronic package structure 400 of the second embodiment and the electronic package structure 300 of the first embodiment is that a body 422 of a second electronic element 420 does not have the cavity 322 a.
  • a first end 432 a of each lead 432 of a lead frame 430 is disposed on a first surface 422 a of a body 422
  • a plurality of first electronic elements 410 are disposed on the first surface 422 a and electrically connected to the leads 432 .
  • a second end 432 b of each of the leads 432 is disposed on a second surface 422 b of the body 422 opposite to the first surface 422 a, and a part of each of the leads 432 connecting the first end 432 a and the second end 432 b is disposed on a side surface 422 c of the body 422 .
  • a circuit substrate 440 is disposed on the first surface 422 a and electrically connected to the leads 432 , and the first electronic elements 410 are disposed on the circuit substrate 440 and electrically connected to the circuit substrate 440 .
  • the circuit substrate 440 of the electronic package structure 400 may be omitted according to a design requirement of the designer, or the circuit substrate 440 may be substituted by a lead frame, though it is not illustrated.
  • FIG. 4B is a schematic diagram of another electronic package structure according to the second embodiment of the present invention.
  • a difference between the electronic package structure 400 ′ and the electronic package structure 400 is that a part of each lead 432 ′ connecting a first end 432 a ′ and a second end 432 b ′ penetrates a body 422 ′.
  • FIG. 5A is a schematic diagram of an electronic package structure according to a third embodiment of the present invention.
  • a plurality of first electronic elements 510 are disposed on a first surface 532 of a circuit substrate 530 and electrically connected to the circuit substrate 530 .
  • a second electronic element 520 is disposed above the first surface 532 of the circuit substrate 530 .
  • the first electronic elements 510 are located between a body 522 of the second electronic element 520 and the first surface 532 of the circuit substrate 530
  • the first electronic elements 510 are located between leads 524 of the second electronic element 520 .
  • the second electronic element 520 covers the first electronic elements 510 .
  • an insulating encapsulant 540 is disposed between the second electronic element 520 and the circuit substrate 530 and encapsulating the first electronic elements 510 for protecting the first electronic elements 510 and enhancing a whole mechanical strength of the electronic package structure 500 .
  • the circuit substrate 530 may further include at least a conductive channel 539 , and each of the conductive channels 539 penetrates a dielectric layer 538 for electrically connecting a first circuit layer 534 and a second circuit layer 536 . At least one of the conductive channels 539 (for example, the two conductive channels 539 located at a left side of FIG. 5A ) is located below at least one of the first electronic elements 510 (for example, the first electronic element 510 located at the left side of FIG.
  • a second end 524 b of each of the leads 524 of the second electronic element 520 extends out from the body 522 to electrically connect the circuit substrate 530 .
  • the second electronic element 520 may be an inductive element including a coil 526 .
  • the body 522 which is a magnetic wrap wraps the coil 526 , and a first end 524 a of each of the leads 524 is connected to one of two opposite ends of the coil 526 .
  • the electronic package structure 500 further includes an electromagnetic-interference-shielding element (EMI-shielding element) 550 covering the first electronic elements 510 .
  • EMI-shielding element electromagnetic-interference-shielding element
  • the EMI-shielding element 550 is disposed on the body 522 of the second electronic element 520 , and is located between the body 522 of the second electronic element 520 and the circuit substrate 530 . Therefore, during operation of the electronic package structure 500 , it may be reduced by means of the EMI-shielding element 550 that electrical signals transmitted in the circuit substrate 530 is interfered by a magnetic force generated by the second electronic element 520 which functions as an inductive element.
  • FIG. 5B is a schematic diagram of another electronic package structure according to the third embodiment of the present invention.
  • a difference between the electronic package structure 500 ′ and the electronic package structure 500 is that an EMI-shielding element 550 ′ of the electronic package structure 500 ′ is disposed in a cavity 522 ′ of a second electronic element 520 ′.
  • the first electronic elements can be disposed in the cavity of the second electronic element or can be disposed on the second electronic element, or the second electronic element can be stacked on the first electronic elements, compared to the conventional electronic package structures, utilization of an internal space of the electronic package structure is relatively high, so that a size of the electronic package structure can be reduced.

Abstract

An electronic package structure including at least one first electronic element, a second electronic element and a lead frame is provided. The second electronic element includes a body having a cavity. The first electronic element is disposed in the cavity. The lead frame has a plurality of leads. Each of the leads has a first end and a second end. The first end of at least one of the leads extends to the cavity to electrically connect the first electronic element.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application claims the priority benefit of Taiwan application serial no. 97105555, filed on Feb. 18, 2008. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of specification.
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a package structure. More particularly, the present invention relates to an electronic package structure.
  • 2. Description of Related Art
  • Electronic package structures are formed by complicated package processes. Different electronic package structures have different electrical performances and capacities of heat dissipation, and therefore a designer may select an electronic package structure with a desired electrical performance and capacity of heat dissipation according to a design requirement.
  • FIG. 1 is a schematic diagram of a conventional electronic package structure. Referring to FIG. 1, the conventional electronic package structure 100 includes a printed circuit board (PCB) 110 and a plurality of electronic elements 120. The electronic elements 120 are disposed on a surface 112 of the PCB 110 and electrically connected to the PCB 110. The PCB 110 has a plurality of pins 116 extending out from another surface 114 of the PCB 110 to be electrically connected to an electronic device, for example, a motherboard (not shown).
  • FIG. 2 is a schematic diagram of another conventional electronic package structure. Referring to FIG. 2, the conventional electronic package structure 200 includes a circuit substrate 210 and a plurality of electronic elements 220. The electronic elements 220 are disposed on a surface 212 of the circuit substrate 210, and electrically connected to the circuit substrate 210 via a wire bonding technology, a flip-chip bonding technology or a surface mount technology. Moreover, the conventional electronic package structure 200 may be electrically connected to an electronic device, for example, a motherboard (not shown), via a solder paste or a plurality of solder balls (not shown).
  • It should be noted that the electronic elements 120 of the conventional electronic package structure 100 are all disposed on the surface 112 of the PCB 110, and the electronic elements 220 of the conventional electronic package structure 200 are all disposed on the surface 212 of the circuit substrate 210. Therefore, in the conventional electronic package structures 100 and 200, spatial utilization of the PCB 110 and the circuit substrate 210 is relatively low, and sizes of the conventional electronic package structures 100 and 200 are relatively great.
  • SUMMARY OF THE INVENTION
  • In accordance with the present invention, an electronic package structure can achieve a relatively high utilization of an internal space thereof, so that a size of the electronic package structure can be reduced.
  • In one embodiment of the present invention, an electronic package structure includes at least a first electronic element, a second electronic element and a first lead frame. The second electronic element includes a body having a cavity. The first electronic element is disposed in the cavity. The lead frame has a plurality of leads. Each of the leads has a first end and a second end, and the first end of at least one of the leads extends to the cavity to electrically connect the first electronic element.
  • In one embodiment of the present invention, an electronic package structure includes at least one first electronic element, a second electronic element and a lead frame. The second electronic element includes a body having a first surface. The lead frame has a plurality of leads. Each of the leads has a first end and a second end. The first ends are disposed on the first surface, and the first electronic element is disposed on the first surface and electrically connected to at least one of the leads.
  • In one embodiment, an electronic package structure includes a circuit substrate, at least one first electronic element and a second electronic element. The circuit substrate has a first surface. The first electronic element is disposed on the first surface of the circuit substrate and electrically connected to the circuit substrate. The second electronic element is disposed above the first surface of the circuit substrate and includes a body and a plurality of leads. Each of the leads has a first end and second end, and the second end of each of the leads extends out from the body to electrically connect the circuit substrate. The first electronic element is located among the body of the second electronic element, the first surface of the circuit substrate and the leads.
  • In the above embodiments of the present invention, since the first electronic element can be disposed in the cavity of the second electronic element or on the second electronic element, or the second electronic element can be stacked on the first electronic element, compared to the conventional electronic package structures, utilization of an internal space of the electronic package structure is relatively high.
  • In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, a preferred embodiment accompanied with figures is described in detail below.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a schematic diagram of a conventional electronic package structure.
  • FIG. 2 is a schematic diagram of another conventional electronic package structure.
  • FIG. 3A is a schematic diagram of an electronic package structure according to a first embodiment of the present invention.
  • FIG. 3B is a schematic diagram of another electronic package structure according to the first embodiment of the present invention.
  • FIG. 3C is a schematic diagram of another electronic package structure according to the first embodiment of the present invention.
  • FIG. 3D is a schematic diagram of still another electronic package structure according to the first embodiment of the present invention.
  • FIG. 4A is a schematic diagram of an electronic package structure according to a second embodiment of the present invention.
  • FIG. 4B is a schematic diagram of another electronic package structure according to the second embodiment of the present invention.
  • FIG. 5A is a schematic diagram of an electronic package structure according to a third embodiment of the present invention.
  • FIG. 5B is a schematic diagram of another electronic package structure according to the third embodiment of the present invention.
  • DESCRIPTION OF EMBODIMENTS First Embodiment
  • FIG. 3A is a schematic diagram of an electronic package structure according to a first embodiment of the present invention. Referring to FIG. 3A, the electronic package structure 300 includes at least one first electronic element 310 (two first electronic elements are illustrated in FIG. 3A), a second electronic element 320 and a first lead frame 330. The electronic package structure 300 is generally applied to a voltage regulator module, a network adapter, a graphics processing unit, a DC/DC converter or a point-of-load (POL) converter. Each of the first electronic elements 310 can be a logical control element, a driving element or a passive element. The passive element can be a capacitor, an inductor with lesser inductance, or a resistor. Each of the first electronic elements 310 can also be a power element, such as a metal-oxide-semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT) or a diode.
  • The second electronic element 320 includes a body 322 having a cavity 322 a. The first electronic elements 310 are disposed in the cavity 322 a. In the embodiment, the body 322 of the second electronic element 320 has a first surface 322 b, a second surface 322 c opposite to the first surface 322 b and a side surface 322 d. The cavity 322 a sinks in a direction from the second surface 322 c towards the first surface 322 b. The side surface 322 d connects the first surface 322 b and the second surface 322 c. Besides, the second electronic element 320 can be an energy-storage element used for storing electric energy. In detail, the second electronic element 320 further includes a coil 324 and a plurality of first external electrodes 326. The coil 324 is disposed within the body 322. The first external electrodes 326 are respectively connected to two opposite ends of the coil 324, and extend outside the body 322 to locate on the first surface 322 b and the side surface 322 d. The body 322 comprising a magnetic body encloses the coil 324. The second electronic element 320 can be an inductive element with a greater inductance and a greater size than the first electronic elements 310.
  • The first lead frame 330 has a plurality of leads 332. Each of the leads 332 has a first end 332 a and a second end 332 b, and the first end 332 a of each of the leads 332 can be embedded in the body 322 and extends to the cavity 322 a for electrically connecting to the first electronic elements 310. The second end 332 b of each of the leads 332 is disposed on the first surface 322 b of the body 322 to form a second external electrode 332 c, and a part of each of the leads 332 connecting the first end 332 a and the second end 332 b is disposed on the side surface 322 d of the body 322.
  • In the present embodiment, the electronic package structure 300 further includes a circuit substrate 340 and an insulating encapsulant 350. The circuit substrate 340 is disposed in the cavity 322 a of the body 322. The first electronic elements 310 can be disposed on the circuit substrate 340 and electrically connected to the circuit substrate 340. The circuit substrate 340 is electrically connected to the first end 332 a of each of the leads 332 extending to the cavity 322 a. The first electronic elements 310 may be electrically connected to the circuit substrate 340 via a wire bonding technology, a flip-chip bonding technology or a surface mount technology.
  • The circuit substrate 340 has a first circuit layer 342, a second circuit layer 344, a dielectric layer 346 disposed between the first circuit layer 342 and the second circuit layer 344, and at least a conductive channel 348. The first electronic elements 310 are disposed on the first circuit layer 342, and the conductive channel 348 penetrates the dielectric layer 346 for electrically connecting the first circuit layer 342 and the second circuit layer 344. It should be noted that the circuit board 340 of the electronic package structure 300 may be omitted according to a design requirement of a designer, though it is not illustrated.
  • Moreover, the insulating encapsulant 350 is disposed in the cavity 322 a and encapsulates the first electronic elements 310 and the circuit substrate 340 for protecting the first electronic elements 310 and the circuit substrate 340, and enhancing a whole mechanical strength of the electronic package structure 300.
  • Since the first electronic elements 310 and the circuit substrate 340 are disposed in the cavity 322 a of the second electronic element 320, compared to a conventional electronic package structures of FIG. 1 and FIG. 2, utilization of an internal space of the electronic package structure 300 is relatively high, and the first electronic elements 310 and the circuit substrate 340 can be protected by the cavity 322 a. Besides, since the insulating encapsulant 350 is disposed in the cavity 322 a, material of the insulating encapsulant 350 can be directly filled into the cavity 322 a without aiding of extra mold during formation of the insulating encapsulant 350.
  • FIG. 3B is a schematic diagram of another electronic package structure according to the first embodiment of the present invention. Referring to FIG. 3A and FIG. 3B, a difference between the electronic package structure 300′ and the electronic package structure 300 is that a part of each lead 332′ connecting a first end 332 a′ and a second end 332 b′ penetrates a body 322′. Besides, the insulating encapsulant 350 of the electronic package structure 300 is different from a magnetic encapsulant 350′ of the electronic package structure 300′. The magnetic encapsulant 350′ is disposed in a cavity 322 a′ of the body 322′. Therefore, if a second electronic element 320′ is an inductive element, an inductive characteristic of the second electronic element 320′ influenced by the cavity 322′ then can be compensated by the magnetic encapsulant 350′. It should be noted that a part of each of the leads 332 connecting the first end 332 a and the second end 332 b may also penetrate the body 322 according to a design requirement, though it is not illustrated.
  • FIG. 3C is a schematic diagram of another electronic package structure according to the first embodiment of the present invention. Referring to FIG. 3A and FIG. 3C, a difference between the electronic package structure 300″ and the electronic package structure 300 is that a cavity 322 a″ of a body 322″ sinks in a direction from a first surface 322 b″ towards a second surface 322 c″. It should be noted that an insulating encapsulant 350″ can be substituted by a magnetic encapsulant according to a design requirement, and a part of each lead 332″ connecting a first end 332 a″ and a second end 332 b″ may also penetrate the body 322″ according to a design requirement, though it is not illustrated.
  • FIG. 3D is a schematic diagram of still another electronic package structure according to the first embodiment of the present invention. Referring to FIG. 3A and FIG. 3D, a second lead frame 360 is applied in the electronic package structure 300′″ for substituting the circuit substrate 340 of the electronic package structure 300 according to a design requirement. A plurality of first electronic elements 310′″ are disposed on the second lead frame 360 and electrically connected to the second lead frame 360. The second lead frame 360 is electrically connected to a first end 332 a′″ of each lead 332′″ of a first lead frame 330′″ that extends to a cavity 322 a′″.
  • Second Embodiment
  • FIG. 4A is a schematic diagram of an electronic package structure according to a second embodiment of the present invention. Referring to FIG. 4A and FIG. 3A, a difference between the electronic package structure 400 of the second embodiment and the electronic package structure 300 of the first embodiment is that a body 422 of a second electronic element 420 does not have the cavity 322 a. In detail, a first end 432 a of each lead 432 of a lead frame 430 is disposed on a first surface 422 a of a body 422, and a plurality of first electronic elements 410 are disposed on the first surface 422 a and electrically connected to the leads 432. Moreover, a second end 432 b of each of the leads 432 is disposed on a second surface 422 b of the body 422 opposite to the first surface 422 a, and a part of each of the leads 432 connecting the first end 432 a and the second end 432 b is disposed on a side surface 422 c of the body 422.
  • Furthermore, a circuit substrate 440 is disposed on the first surface 422 a and electrically connected to the leads 432, and the first electronic elements 410 are disposed on the circuit substrate 440 and electrically connected to the circuit substrate 440. It should be noted that the circuit substrate 440 of the electronic package structure 400 may be omitted according to a design requirement of the designer, or the circuit substrate 440 may be substituted by a lead frame, though it is not illustrated.
  • FIG. 4B is a schematic diagram of another electronic package structure according to the second embodiment of the present invention. Referring to FIG. 4A and FIG. 4B, a difference between the electronic package structure 400′ and the electronic package structure 400 is that a part of each lead 432′ connecting a first end 432 a′ and a second end 432 b′ penetrates a body 422′.
  • Third Embodiment
  • FIG. 5A is a schematic diagram of an electronic package structure according to a third embodiment of the present invention. Referring to FIG. 5A, in the electronic package structure 500 of the present embodiment, a plurality of first electronic elements 510 are disposed on a first surface 532 of a circuit substrate 530 and electrically connected to the circuit substrate 530. A second electronic element 520 is disposed above the first surface 532 of the circuit substrate 530. The first electronic elements 510 are located between a body 522 of the second electronic element 520 and the first surface 532 of the circuit substrate 530, and the first electronic elements 510 are located between leads 524 of the second electronic element 520. In other words, in the present embodiment, the second electronic element 520 covers the first electronic elements 510. Besides, an insulating encapsulant 540 is disposed between the second electronic element 520 and the circuit substrate 530 and encapsulating the first electronic elements 510 for protecting the first electronic elements 510 and enhancing a whole mechanical strength of the electronic package structure 500. Moreover, the circuit substrate 530 may further include at least a conductive channel 539, and each of the conductive channels 539 penetrates a dielectric layer 538 for electrically connecting a first circuit layer 534 and a second circuit layer 536. At least one of the conductive channels 539 (for example, the two conductive channels 539 located at a left side of FIG. 5A) is located below at least one of the first electronic elements 510 (for example, the first electronic element 510 located at the left side of FIG. 5A), so that heat generated by the first electronic element 510 located at the left side may be quickly transmitted to where is outside the electronic package structure 500 via the two conductive channels 539 located at the left side. A second end 524 b of each of the leads 524 of the second electronic element 520 extends out from the body 522 to electrically connect the circuit substrate 530. The second electronic element 520 may be an inductive element including a coil 526. The body 522 which is a magnetic wrap wraps the coil 526, and a first end 524 a of each of the leads 524 is connected to one of two opposite ends of the coil 526.
  • It should be noted that the electronic package structure 500 further includes an electromagnetic-interference-shielding element (EMI-shielding element) 550 covering the first electronic elements 510. In the present embodiment, the EMI-shielding element 550 is disposed on the body 522 of the second electronic element 520, and is located between the body 522 of the second electronic element 520 and the circuit substrate 530. Therefore, during operation of the electronic package structure 500, it may be reduced by means of the EMI-shielding element 550 that electrical signals transmitted in the circuit substrate 530 is interfered by a magnetic force generated by the second electronic element 520 which functions as an inductive element.
  • FIG. 5B is a schematic diagram of another electronic package structure according to the third embodiment of the present invention. Referring to FIG. 5A and FIG. 5B, a difference between the electronic package structure 500′ and the electronic package structure 500 is that an EMI-shielding element 550′ of the electronic package structure 500′ is disposed in a cavity 522′ of a second electronic element 520′.
  • In summary, in the aforementioned embodiments of the present invention, since the first electronic elements can be disposed in the cavity of the second electronic element or can be disposed on the second electronic element, or the second electronic element can be stacked on the first electronic elements, compared to the conventional electronic package structures, utilization of an internal space of the electronic package structure is relatively high, so that a size of the electronic package structure can be reduced.
  • It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Claims (17)

1-13. (canceled)
14. An electronic package, comprising:
a substrate;
at least an electronic element on top of the substrate;
a coil;
a body encapsulating at least said coil and being positioned on top of said electronic element; and
a pair of leads each having
a top end electrically coupled to a respective end of the coil,
a bottom end electrically coupled to the substrate, and
a middle section connecting said top end and said bottom end to define a bracket shape.
15. An electronic package as claimed in claim 14, wherein the electronic element is disposed on a top face of the substrate between the bottom ends of the leads.
16. An electronic package as claimed in claim 14, wherein said middle section of each said lead is entirely exposed out of said body.
17. An electronic package as claimed in claim 14, wherein said top end of each said lead is at least partially embedded in the body.
18. An electronic package as claimed in claim 14, wherein said substrate includes
first and second conductive layers on opposite top and bottom faces of said substrate; and
at least one conductive via penetrating the substrate to electrically connect the first and second conductive layers;
wherein said conductive via is disposed immediately under the electronic element for dissipating heat generated by said electronic element away.
19. An electronic package as claimed in claim 14, further comprising:
an insulating encapsulant encapsulating the electronic element and disposed under the body.
20. An electronic package as claimed in claim 19, wherein a width of said encapsulant is smaller than that of said body.
21. An electronic package as claimed in claim 20, wherein said encapsulant is disposed between the bottom ends of the leads.
22. An electronic package as claimed in claim 14, wherein the top end and bottom end of each said lead are positioned in parallel planes and the middle section of said lead is perpendicular to the top end and the bottom end.
23. An electronic package as claimed in claim 14, wherein said electronic element is one selected from the group consisting of a capacitor, a resistor, and an inductor with a smaller inductance than the coil.
24. An electronic package as claimed in claim 14, wherein said electronic element is one selected from the group consisting of a metal-oxide-semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), and a diode.
25. An electronic package as claimed in claim 14, comprising multiple said electronic elements disposed under the body and between the bottom ends of the leads.
26. An electronic package as claimed in claim 14, further comprising:
an electromagnetic-interference (EMI) shielding element between the coil and the electronic element.
27. An electronic package as claimed in claim 26, further comprising
an insulating encapsulant encapsulating the electronic element and disposed under the body;
wherein the EMI shielding element is embedded in the encapsulant.
28. An electronic package as claimed in claim 26, wherein the EMI shielding element is embedded in the body.
29. An electronic package as claimed in claim 28, wherein the body includes a magnetic wrap that wraps the coil.
US12/971,671 2008-02-18 2010-12-17 Electronic package structure Abandoned US20110090648A1 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
US12/971,671 US20110090648A1 (en) 2008-02-18 2010-12-17 Electronic package structure
US13/481,887 US9271398B2 (en) 2008-02-18 2012-05-28 Power supply module
US13/485,954 US9001527B2 (en) 2008-02-18 2012-06-01 Electronic package structure
US13/754,910 US8837168B2 (en) 2008-02-18 2013-01-31 Electronic package structure
US14/594,084 US9538660B2 (en) 2008-02-18 2015-01-10 Electronic package structure
US14/594,083 US9451701B2 (en) 2008-02-18 2015-01-10 Electronic package structure

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
TW097105555A TWI355068B (en) 2008-02-18 2008-02-18 Electronic package structure
TW97105555 2008-02-18
US12/143,143 US20090207574A1 (en) 2008-02-18 2008-06-20 Electronic package structure
US12/971,671 US20110090648A1 (en) 2008-02-18 2010-12-17 Electronic package structure

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US12/143,143 Division US20090207574A1 (en) 2008-02-18 2008-06-20 Electronic package structure

Related Child Applications (3)

Application Number Title Priority Date Filing Date
US13/481,887 Continuation-In-Part US9271398B2 (en) 2008-02-18 2012-05-28 Power supply module
US13/485,954 Continuation-In-Part US9001527B2 (en) 2008-02-18 2012-06-01 Electronic package structure
US13/754,910 Continuation US8837168B2 (en) 2008-02-18 2013-01-31 Electronic package structure

Publications (1)

Publication Number Publication Date
US20110090648A1 true US20110090648A1 (en) 2011-04-21

Family

ID=40954921

Family Applications (3)

Application Number Title Priority Date Filing Date
US12/143,143 Abandoned US20090207574A1 (en) 2008-02-18 2008-06-20 Electronic package structure
US12/971,671 Abandoned US20110090648A1 (en) 2008-02-18 2010-12-17 Electronic package structure
US13/754,910 Active US8837168B2 (en) 2008-02-18 2013-01-31 Electronic package structure

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US12/143,143 Abandoned US20090207574A1 (en) 2008-02-18 2008-06-20 Electronic package structure

Family Applications After (1)

Application Number Title Priority Date Filing Date
US13/754,910 Active US8837168B2 (en) 2008-02-18 2013-01-31 Electronic package structure

Country Status (2)

Country Link
US (3) US20090207574A1 (en)
TW (1) TWI355068B (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090273913A1 (en) * 2008-04-30 2009-11-05 Infineon Technologies Ag Circuit arrangement having two semiconductor switching elements and one freewheeling element
US20120161900A1 (en) * 2010-12-24 2012-06-28 Kabushiki Kaisha Toyota Jidoshokki Electronic device
US20130299131A1 (en) * 2012-05-14 2013-11-14 Alexander Timashov Adjustable heat dissipation assembly for magnetic devices
US9883579B1 (en) * 2016-10-07 2018-01-30 Unimicron Technology Corp. Package structure and manufacturing method thereof
US20210166987A1 (en) * 2018-11-20 2021-06-03 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor manufacturing process

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10126942B2 (en) 2007-09-19 2018-11-13 Apple Inc. Systems and methods for detecting a press on a touch-sensitive surface
US9110590B2 (en) 2007-09-19 2015-08-18 Typesoft Technologies, Inc. Dynamically located onscreen keyboard
US9454270B2 (en) 2008-09-19 2016-09-27 Apple Inc. Systems and methods for detecting a press on a touch-sensitive surface
US10203873B2 (en) 2007-09-19 2019-02-12 Apple Inc. Systems and methods for adaptively presenting a keyboard on a touch-sensitive display
US9489086B1 (en) 2013-04-29 2016-11-08 Apple Inc. Finger hover detection for improved typing
US9001527B2 (en) * 2008-02-18 2015-04-07 Cyntec Co., Ltd. Electronic package structure
US10111333B2 (en) * 2010-03-16 2018-10-23 Intersil Americas Inc. Molded power-supply module with bridge inductor over other components
CN102256443B (en) * 2010-04-02 2015-12-16 雅达电子国际有限公司 Occupy the inductor in the space on circuit board component
US9723766B2 (en) 2010-09-10 2017-08-01 Intersil Americas LLC Power supply module with electromagnetic-interference (EMI) shielding, cooling, or both shielding and cooling, along two or more sides
KR20120026870A (en) * 2010-09-10 2012-03-20 삼성전자주식회사 Circuit board and semiconductor module including the same
EP2665497A2 (en) 2011-01-20 2013-11-27 Cleankeys Inc. Systems and methods for monitoring surface sanitation
US8476720B2 (en) * 2011-06-29 2013-07-02 Honeywell International Inc. Systems and methods for vertically stacking a sensor on an integrated circuit chip
US8653635B2 (en) 2011-08-16 2014-02-18 General Electric Company Power overlay structure with leadframe connections
US9104260B2 (en) 2012-04-10 2015-08-11 Typesoft Technologies, Inc. Systems and methods for detecting a press on a touch-sensitive surface
CN102857088B (en) * 2012-08-28 2016-01-20 胜美达电机(香港)有限公司 Power supply module
US10269688B2 (en) 2013-03-14 2019-04-23 General Electric Company Power overlay structure and method of making same
CN203166744U (en) * 2013-03-22 2013-08-28 胜美达电机(香港)有限公司 Power source supply module
CN104135139B (en) * 2013-05-03 2018-01-26 胜美达电机(香港)有限公司 A kind of power supply module
CN103441124B (en) * 2013-08-27 2016-01-06 矽力杰半导体技术(杭州)有限公司 The lamination encapsulating method of voltage regulator and corresponding stacked package device
US10289302B1 (en) 2013-09-09 2019-05-14 Apple Inc. Virtual keyboard animation
US9711279B2 (en) 2013-10-28 2017-07-18 Infineon Technologies Austria Ag DC-DC converter assembly with an output inductor accommodating a power stage attached to a circuit board
US9859250B2 (en) * 2013-12-20 2018-01-02 Cyntec Co., Ltd. Substrate and the method to fabricate thereof
US10333407B2 (en) * 2015-05-06 2019-06-25 Infineon Technologies Austria Ag Power stage packages of a multi-phase DC-DC converter under a coupled inductor
US10855178B2 (en) 2015-05-29 2020-12-01 Infineon Technologies Austria Ag Discrete power stage transistor dies of a DC-DC converter under an inductor
CN108140629A (en) * 2015-08-07 2018-06-08 韦沙戴尔电子有限公司 Molding and the electric device with molding for high voltage applications
US10396046B2 (en) * 2017-12-29 2019-08-27 Intel Corporation Substrate assembly with magnetic feature
WO2019218344A1 (en) * 2018-05-18 2019-11-21 瑞典爱立信有限公司 Power supply device and printed circuit board device comprising same

Citations (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4012723A (en) * 1975-05-29 1977-03-15 Texas Instruments Incorporated Magnetic bubble memory packaging arrangement and its method of fabrication
US4096581A (en) * 1976-08-16 1978-06-20 Texas Instruments Incorporated External drive coil magnetic bubble package
US4845452A (en) * 1987-10-08 1989-07-04 Tdk Corporation Composite bead element
US5212345A (en) * 1992-01-24 1993-05-18 Pulse Engineering, Inc. Self leaded surface mounted coplanar header
US5621635A (en) * 1995-03-03 1997-04-15 National Semiconductor Corporation Integrated circuit packaged power supply
US5760471A (en) * 1994-04-20 1998-06-02 Fujitsu Limited Semiconductor device having an inner lead extending over a central portion of a semiconductor device sealed in a plastic package and an outer lead exposed to the outside of a side face of the plastic package
US5793108A (en) * 1995-05-30 1998-08-11 Sharp Kabushiki Kaisha Semiconductor integrated circuit having a plurality of semiconductor chips
US6005463A (en) * 1997-01-30 1999-12-21 Pulse Engineering Through-hole interconnect device with isolated wire-leads and component barriers
US6198375B1 (en) * 1999-03-16 2001-03-06 Vishay Dale Electronics, Inc. Inductor coil structure
US6225558B1 (en) * 1997-12-12 2001-05-01 Hyundai Electronics Industries Co., Ltd. Chip size semiconductor package and fabrication method thereof
US6242798B1 (en) * 1996-11-22 2001-06-05 Hyundai Electronics Industries Co., Ltd. Stacked bottom lead package in semiconductor devices
US6320251B1 (en) * 2000-01-18 2001-11-20 Amkor Technology, Inc. Stackable package for an integrated circuit
US20020034026A1 (en) * 2000-09-20 2002-03-21 Orcutt John W. Molded packages for optical wireless network micromirror assemblies
US20020074145A1 (en) * 2000-11-15 2002-06-20 Klaus Fischer System and method for converting a DC input voltage to a DC ouput voltage
US20020105052A1 (en) * 2000-11-09 2002-08-08 Hiromichi Tokuda Method of manufacturing laminated ceramic electronic component, and laminated ceramic electronic component
US20030031339A1 (en) * 2000-01-13 2003-02-13 Marshall Bowen F. Packaging and rf shielding for telecoils
US20030038347A1 (en) * 2001-08-22 2003-02-27 Walton Advanced Electronics Ltd Stackable-type semiconductor package
US20030042508A1 (en) * 1999-02-26 2003-03-06 Micron Technology Inc. Open pattern inductor
US20030052393A1 (en) * 2001-09-18 2003-03-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6593841B1 (en) * 1990-05-31 2003-07-15 Kabushiki Kaisha Toshiba Planar magnetic element
US6632881B1 (en) * 1999-04-13 2003-10-14 Hitachi Chemical Co., Ltd. Encapsulant of epoxy resin and liquid aromatic amine curing agent
US6730544B1 (en) * 1999-12-20 2004-05-04 Amkor Technology, Inc. Stackable semiconductor package and method for manufacturing same
US6741451B2 (en) * 2002-05-30 2004-05-25 Rohm Co., Ltd. Solid electrolytic capacitor and method of making the same
US6885278B2 (en) * 2002-07-26 2005-04-26 Fdk Corporation Microconverter and laminated magnetic-core inductor
US6972479B2 (en) * 2004-03-17 2005-12-06 Cyntec Co., Ltd. Package with stacked substrates
US20060023389A1 (en) * 2002-12-09 2006-02-02 Tomoaki Ito Recorded data erasing device of magnetic storage
US20060051928A1 (en) * 2004-09-09 2006-03-09 Showa Denko K.K. Reaction vessel for producing capacitor element, production method for capacitor element, capacitor element and capacitor
US20060113598A1 (en) * 2004-11-16 2006-06-01 Chen Howard H Device and method for fabricating double-sided SOI wafer scale package with optical through via connections
US20060215342A1 (en) * 2005-03-28 2006-09-28 Wayne Montoya Surface mount multi-layer electrical circuit protection device with active element between PPTC layers
US20060267167A1 (en) * 2004-10-25 2006-11-30 Mccain Joseph H Microelectronic device with integrated energy source
US20060284340A1 (en) * 2005-06-17 2006-12-21 Cyntec Co., Ltd. Method for preventing the overflowing of molding compound during fabricating package device
US7282785B2 (en) * 2004-01-05 2007-10-16 Stanley Electric Co., Ltd. Surface mount type semiconductor device and lead frame structure thereof
US20070247268A1 (en) * 2006-03-17 2007-10-25 Yoichi Oya Inductor element and method for production thereof, and semiconductor module with inductor element
US20070262328A1 (en) * 2006-05-10 2007-11-15 Nichia Corporation Semiconductor light emitting device and a method for producing the same
US20080029907A1 (en) * 2006-07-19 2008-02-07 Texas Instruments Incorporated Power Semiconductor Devices Having Integrated Inductor
US20080036566A1 (en) * 2006-08-09 2008-02-14 Andrzej Klesyk Electronic Component And Methods Relating To Same
US20080074229A1 (en) * 2006-09-27 2008-03-27 Shahriar Moinian Differential Inductor for Use in Integrated Circuits
US20080180921A1 (en) * 2007-01-31 2008-07-31 Cyntec Co., Ltd. Electronic package structure
US20080179722A1 (en) * 2007-01-31 2008-07-31 Cyntec Co., Ltd. Electronic package structure
US20080303125A1 (en) * 2007-06-08 2008-12-11 Da-Jung Chen Three-dimensional package structure
US20080309442A1 (en) * 2007-06-12 2008-12-18 Francois Hebert Semiconductor power device having a stacked discrete inductor structure
US20090057822A1 (en) * 2007-09-05 2009-03-05 Yenting Wen Semiconductor component and method of manufacture
US20090121253A1 (en) * 2006-04-12 2009-05-14 Showa Denko K.K. Light-emitting apparatus and method of manufacturing the same
US7545021B1 (en) * 2005-07-14 2009-06-09 National Semiconductor Corporation Apparatus and method for making integrated circuit packages having integrated circuits mounted onto passive electrical components
US20090166845A1 (en) * 2007-12-27 2009-07-02 Zigmund Ramirez Camacho Integrated circuit package system with extended corner leads
US7560811B2 (en) * 2005-12-08 2009-07-14 Yamaha Corporation Semiconductor device
US20090200650A1 (en) * 2008-02-08 2009-08-13 Infineon Technologies Ag Integrated circuit package and a method of making
US7598603B2 (en) * 2006-03-15 2009-10-06 Infineon Technologies Ag Electronic component having a power switch with an anode thereof mounted on a die attach region of a heat sink
US7612641B2 (en) * 2004-09-21 2009-11-03 Pulse Engineering, Inc. Simplified surface-mount devices and methods
US7675396B2 (en) * 2007-09-28 2010-03-09 Cyntec Co., Ltd. Inductor and manufacture method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4696100A (en) * 1985-02-21 1987-09-29 Matsushita Electric Industrial Co., Ltd. Method of manufacturing a chip coil
JP2001244116A (en) * 2000-02-29 2001-09-07 Taiyo Yuden Co Ltd Electronic component and method of manufacturing the same

Patent Citations (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4012723A (en) * 1975-05-29 1977-03-15 Texas Instruments Incorporated Magnetic bubble memory packaging arrangement and its method of fabrication
US4096581A (en) * 1976-08-16 1978-06-20 Texas Instruments Incorporated External drive coil magnetic bubble package
US4845452A (en) * 1987-10-08 1989-07-04 Tdk Corporation Composite bead element
US6593841B1 (en) * 1990-05-31 2003-07-15 Kabushiki Kaisha Toshiba Planar magnetic element
US5212345A (en) * 1992-01-24 1993-05-18 Pulse Engineering, Inc. Self leaded surface mounted coplanar header
US5760471A (en) * 1994-04-20 1998-06-02 Fujitsu Limited Semiconductor device having an inner lead extending over a central portion of a semiconductor device sealed in a plastic package and an outer lead exposed to the outside of a side face of the plastic package
US5621635A (en) * 1995-03-03 1997-04-15 National Semiconductor Corporation Integrated circuit packaged power supply
US5793108A (en) * 1995-05-30 1998-08-11 Sharp Kabushiki Kaisha Semiconductor integrated circuit having a plurality of semiconductor chips
US6242798B1 (en) * 1996-11-22 2001-06-05 Hyundai Electronics Industries Co., Ltd. Stacked bottom lead package in semiconductor devices
US6005463A (en) * 1997-01-30 1999-12-21 Pulse Engineering Through-hole interconnect device with isolated wire-leads and component barriers
US6225558B1 (en) * 1997-12-12 2001-05-01 Hyundai Electronics Industries Co., Ltd. Chip size semiconductor package and fabrication method thereof
US20030042508A1 (en) * 1999-02-26 2003-03-06 Micron Technology Inc. Open pattern inductor
US6198375B1 (en) * 1999-03-16 2001-03-06 Vishay Dale Electronics, Inc. Inductor coil structure
US6632881B1 (en) * 1999-04-13 2003-10-14 Hitachi Chemical Co., Ltd. Encapsulant of epoxy resin and liquid aromatic amine curing agent
US6730544B1 (en) * 1999-12-20 2004-05-04 Amkor Technology, Inc. Stackable semiconductor package and method for manufacturing same
US20030031339A1 (en) * 2000-01-13 2003-02-13 Marshall Bowen F. Packaging and rf shielding for telecoils
US6320251B1 (en) * 2000-01-18 2001-11-20 Amkor Technology, Inc. Stackable package for an integrated circuit
US20020034026A1 (en) * 2000-09-20 2002-03-21 Orcutt John W. Molded packages for optical wireless network micromirror assemblies
US20020105052A1 (en) * 2000-11-09 2002-08-08 Hiromichi Tokuda Method of manufacturing laminated ceramic electronic component, and laminated ceramic electronic component
US20020074145A1 (en) * 2000-11-15 2002-06-20 Klaus Fischer System and method for converting a DC input voltage to a DC ouput voltage
US20030038347A1 (en) * 2001-08-22 2003-02-27 Walton Advanced Electronics Ltd Stackable-type semiconductor package
US20030052393A1 (en) * 2001-09-18 2003-03-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6741451B2 (en) * 2002-05-30 2004-05-25 Rohm Co., Ltd. Solid electrolytic capacitor and method of making the same
US6885278B2 (en) * 2002-07-26 2005-04-26 Fdk Corporation Microconverter and laminated magnetic-core inductor
US20060023389A1 (en) * 2002-12-09 2006-02-02 Tomoaki Ito Recorded data erasing device of magnetic storage
US7282785B2 (en) * 2004-01-05 2007-10-16 Stanley Electric Co., Ltd. Surface mount type semiconductor device and lead frame structure thereof
US6972479B2 (en) * 2004-03-17 2005-12-06 Cyntec Co., Ltd. Package with stacked substrates
US20060051928A1 (en) * 2004-09-09 2006-03-09 Showa Denko K.K. Reaction vessel for producing capacitor element, production method for capacitor element, capacitor element and capacitor
US7612641B2 (en) * 2004-09-21 2009-11-03 Pulse Engineering, Inc. Simplified surface-mount devices and methods
US20060267167A1 (en) * 2004-10-25 2006-11-30 Mccain Joseph H Microelectronic device with integrated energy source
US20060113598A1 (en) * 2004-11-16 2006-06-01 Chen Howard H Device and method for fabricating double-sided SOI wafer scale package with optical through via connections
US20060215342A1 (en) * 2005-03-28 2006-09-28 Wayne Montoya Surface mount multi-layer electrical circuit protection device with active element between PPTC layers
US20060284340A1 (en) * 2005-06-17 2006-12-21 Cyntec Co., Ltd. Method for preventing the overflowing of molding compound during fabricating package device
US7545021B1 (en) * 2005-07-14 2009-06-09 National Semiconductor Corporation Apparatus and method for making integrated circuit packages having integrated circuits mounted onto passive electrical components
US7560811B2 (en) * 2005-12-08 2009-07-14 Yamaha Corporation Semiconductor device
US7598603B2 (en) * 2006-03-15 2009-10-06 Infineon Technologies Ag Electronic component having a power switch with an anode thereof mounted on a die attach region of a heat sink
US20070247268A1 (en) * 2006-03-17 2007-10-25 Yoichi Oya Inductor element and method for production thereof, and semiconductor module with inductor element
US20090121253A1 (en) * 2006-04-12 2009-05-14 Showa Denko K.K. Light-emitting apparatus and method of manufacturing the same
US20070262328A1 (en) * 2006-05-10 2007-11-15 Nichia Corporation Semiconductor light emitting device and a method for producing the same
US20080029907A1 (en) * 2006-07-19 2008-02-07 Texas Instruments Incorporated Power Semiconductor Devices Having Integrated Inductor
US7531893B2 (en) * 2006-07-19 2009-05-12 Texas Instruments Incorporated Power semiconductor devices having integrated inductor
US20080036566A1 (en) * 2006-08-09 2008-02-14 Andrzej Klesyk Electronic Component And Methods Relating To Same
US20080074229A1 (en) * 2006-09-27 2008-03-27 Shahriar Moinian Differential Inductor for Use in Integrated Circuits
US20080179722A1 (en) * 2007-01-31 2008-07-31 Cyntec Co., Ltd. Electronic package structure
US20080180921A1 (en) * 2007-01-31 2008-07-31 Cyntec Co., Ltd. Electronic package structure
US20080303125A1 (en) * 2007-06-08 2008-12-11 Da-Jung Chen Three-dimensional package structure
US20080309442A1 (en) * 2007-06-12 2008-12-18 Francois Hebert Semiconductor power device having a stacked discrete inductor structure
US20090057822A1 (en) * 2007-09-05 2009-03-05 Yenting Wen Semiconductor component and method of manufacture
US7675396B2 (en) * 2007-09-28 2010-03-09 Cyntec Co., Ltd. Inductor and manufacture method thereof
US20090166845A1 (en) * 2007-12-27 2009-07-02 Zigmund Ramirez Camacho Integrated circuit package system with extended corner leads
US20090200650A1 (en) * 2008-02-08 2009-08-13 Infineon Technologies Ag Integrated circuit package and a method of making

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090273913A1 (en) * 2008-04-30 2009-11-05 Infineon Technologies Ag Circuit arrangement having two semiconductor switching elements and one freewheeling element
US8098499B2 (en) * 2008-04-30 2012-01-17 Infineon Technologies Ag Circuit arrangement having two semiconductor switching elements and one freewheeling element
US20120161900A1 (en) * 2010-12-24 2012-06-28 Kabushiki Kaisha Toyota Jidoshokki Electronic device
US8787037B2 (en) * 2010-12-24 2014-07-22 Kabushiki Kaisha Toyota Jidoshokki Electronic device
US20130299131A1 (en) * 2012-05-14 2013-11-14 Alexander Timashov Adjustable heat dissipation assembly for magnetic devices
US9883579B1 (en) * 2016-10-07 2018-01-30 Unimicron Technology Corp. Package structure and manufacturing method thereof
US20210166987A1 (en) * 2018-11-20 2021-06-03 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor manufacturing process

Also Published As

Publication number Publication date
US20130141886A1 (en) 2013-06-06
US20090207574A1 (en) 2009-08-20
TW200937612A (en) 2009-09-01
TWI355068B (en) 2011-12-21
US8837168B2 (en) 2014-09-16

Similar Documents

Publication Publication Date Title
US8837168B2 (en) Electronic package structure
US9538660B2 (en) Electronic package structure
US10991681B2 (en) Three-dimensional package structure
US8824165B2 (en) Electronic package structure
US8338933B2 (en) Three-dimensional package structure
US9271398B2 (en) Power supply module
KR101619473B1 (en) Semiconductor package having heat slug
US10134710B2 (en) Semiconductor package
US7411278B2 (en) Package device with electromagnetic interference shield
US11134570B2 (en) Electronic module with a magnetic device
US20080180921A1 (en) Electronic package structure
US9907180B2 (en) Multilayer electronic device and manufacturing method therefor
US20080179722A1 (en) Electronic package structure
US8754462B2 (en) Semiconductor device
US10433424B2 (en) Electronic module and the fabrication method thereof
US20160155559A1 (en) Electronic package
CN102623442B (en) Electron package structure
CN108738367B (en) Electronic module

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION