US20110090648A1 - Electronic package structure - Google Patents
Electronic package structure Download PDFInfo
- Publication number
- US20110090648A1 US20110090648A1 US12/971,671 US97167110A US2011090648A1 US 20110090648 A1 US20110090648 A1 US 20110090648A1 US 97167110 A US97167110 A US 97167110A US 2011090648 A1 US2011090648 A1 US 2011090648A1
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- Prior art keywords
- electronic
- electronic package
- package structure
- disposed
- electronic element
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
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- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
- H01F27/29—Terminals; Tapping arrangements for signal inductances
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- H01L23/64—Impedance arrangements
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
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- H05K9/00—Screening of apparatus or components against electric or magnetic fields
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- H01F27/027—Casings specially adapted for combination of signal type inductors or transformers with electronic circuits, e.g. mounting on printed circuit boards
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10507—Involving several components
- H05K2201/10515—Stacked components
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10507—Involving several components
- H05K2201/10537—Attached components
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10742—Details of leads
- H05K2201/10886—Other details
- H05K2201/10924—Leads formed from a punched metal foil
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
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- Y10T29/4902—Electromagnet, transformer or inductor
- Y10T29/49071—Electromagnet, transformer or inductor by winding or coiling
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
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- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
Definitions
- the present invention relates to a package structure. More particularly, the present invention relates to an electronic package structure.
- Electronic package structures are formed by complicated package processes. Different electronic package structures have different electrical performances and capacities of heat dissipation, and therefore a designer may select an electronic package structure with a desired electrical performance and capacity of heat dissipation according to a design requirement.
- FIG. 1 is a schematic diagram of a conventional electronic package structure.
- the conventional electronic package structure 100 includes a printed circuit board (PCB) 110 and a plurality of electronic elements 120 .
- the electronic elements 120 are disposed on a surface 112 of the PCB 110 and electrically connected to the PCB 110 .
- the PCB 110 has a plurality of pins 116 extending out from another surface 114 of the PCB 110 to be electrically connected to an electronic device, for example, a motherboard (not shown).
- FIG. 2 is a schematic diagram of another conventional electronic package structure.
- the conventional electronic package structure 200 includes a circuit substrate 210 and a plurality of electronic elements 220 .
- the electronic elements 220 are disposed on a surface 212 of the circuit substrate 210 , and electrically connected to the circuit substrate 210 via a wire bonding technology, a flip-chip bonding technology or a surface mount technology.
- the conventional electronic package structure 200 may be electrically connected to an electronic device, for example, a motherboard (not shown), via a solder paste or a plurality of solder balls (not shown).
- the electronic elements 120 of the conventional electronic package structure 100 are all disposed on the surface 112 of the PCB 110
- the electronic elements 220 of the conventional electronic package structure 200 are all disposed on the surface 212 of the circuit substrate 210 . Therefore, in the conventional electronic package structures 100 and 200 , spatial utilization of the PCB 110 and the circuit substrate 210 is relatively low, and sizes of the conventional electronic package structures 100 and 200 are relatively great.
- an electronic package structure can achieve a relatively high utilization of an internal space thereof, so that a size of the electronic package structure can be reduced.
- an electronic package structure includes at least a first electronic element, a second electronic element and a first lead frame.
- the second electronic element includes a body having a cavity.
- the first electronic element is disposed in the cavity.
- the lead frame has a plurality of leads. Each of the leads has a first end and a second end, and the first end of at least one of the leads extends to the cavity to electrically connect the first electronic element.
- an electronic package structure includes at least one first electronic element, a second electronic element and a lead frame.
- the second electronic element includes a body having a first surface.
- the lead frame has a plurality of leads. Each of the leads has a first end and a second end. The first ends are disposed on the first surface, and the first electronic element is disposed on the first surface and electrically connected to at least one of the leads.
- an electronic package structure in one embodiment, includes a circuit substrate, at least one first electronic element and a second electronic element.
- the circuit substrate has a first surface.
- the first electronic element is disposed on the first surface of the circuit substrate and electrically connected to the circuit substrate.
- the second electronic element is disposed above the first surface of the circuit substrate and includes a body and a plurality of leads.
- Each of the leads has a first end and second end, and the second end of each of the leads extends out from the body to electrically connect the circuit substrate.
- the first electronic element is located among the body of the second electronic element, the first surface of the circuit substrate and the leads.
- the first electronic element can be disposed in the cavity of the second electronic element or on the second electronic element, or the second electronic element can be stacked on the first electronic element, compared to the conventional electronic package structures, utilization of an internal space of the electronic package structure is relatively high.
- FIG. 1 is a schematic diagram of a conventional electronic package structure.
- FIG. 2 is a schematic diagram of another conventional electronic package structure.
- FIG. 3A is a schematic diagram of an electronic package structure according to a first embodiment of the present invention.
- FIG. 3B is a schematic diagram of another electronic package structure according to the first embodiment of the present invention.
- FIG. 3C is a schematic diagram of another electronic package structure according to the first embodiment of the present invention.
- FIG. 3D is a schematic diagram of still another electronic package structure according to the first embodiment of the present invention.
- FIG. 4A is a schematic diagram of an electronic package structure according to a second embodiment of the present invention.
- FIG. 4B is a schematic diagram of another electronic package structure according to the second embodiment of the present invention.
- FIG. 5A is a schematic diagram of an electronic package structure according to a third embodiment of the present invention.
- FIG. 5B is a schematic diagram of another electronic package structure according to the third embodiment of the present invention.
- FIG. 3A is a schematic diagram of an electronic package structure according to a first embodiment of the present invention.
- the electronic package structure 300 includes at least one first electronic element 310 (two first electronic elements are illustrated in FIG. 3A ), a second electronic element 320 and a first lead frame 330 .
- the electronic package structure 300 is generally applied to a voltage regulator module, a network adapter, a graphics processing unit, a DC/DC converter or a point-of-load (POL) converter.
- Each of the first electronic elements 310 can be a logical control element, a driving element or a passive element.
- the passive element can be a capacitor, an inductor with lesser inductance, or a resistor.
- Each of the first electronic elements 310 can also be a power element, such as a metal-oxide-semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT) or a diode.
- MOSFET metal-oxide-semiconductor field effect
- the second electronic element 320 includes a body 322 having a cavity 322 a .
- the first electronic elements 310 are disposed in the cavity 322 a.
- the body 322 of the second electronic element 320 has a first surface 322 b, a second surface 322 c opposite to the first surface 322 b and a side surface 322 d.
- the cavity 322 a sinks in a direction from the second surface 322 c towards the first surface 322 b .
- the side surface 322 d connects the first surface 322 b and the second surface 322 c .
- the second electronic element 320 can be an energy-storage element used for storing electric energy.
- the second electronic element 320 further includes a coil 324 and a plurality of first external electrodes 326 .
- the coil 324 is disposed within the body 322 .
- the first external electrodes 326 are respectively connected to two opposite ends of the coil 324 , and extend outside the body 322 to locate on the first surface 322 b and the side surface 322 d.
- the body 322 comprising a magnetic body encloses the coil 324 .
- the second electronic element 320 can be an inductive element with a greater inductance and a greater size than the first electronic elements 310 .
- the first lead frame 330 has a plurality of leads 332 .
- Each of the leads 332 has a first end 332 a and a second end 332 b, and the first end 332 a of each of the leads 332 can be embedded in the body 322 and extends to the cavity 322 a for electrically connecting to the first electronic elements 310 .
- the second end 332 b of each of the leads 332 is disposed on the first surface 322 b of the body 322 to form a second external electrode 332 c, and a part of each of the leads 332 connecting the first end 332 a and the second end 332 b is disposed on the side surface 322 d of the body 322 .
- the electronic package structure 300 further includes a circuit substrate 340 and an insulating encapsulant 350 .
- the circuit substrate 340 is disposed in the cavity 322 a of the body 322 .
- the first electronic elements 310 can be disposed on the circuit substrate 340 and electrically connected to the circuit substrate 340 .
- the circuit substrate 340 is electrically connected to the first end 332 a of each of the leads 332 extending to the cavity 322 a.
- the first electronic elements 310 may be electrically connected to the circuit substrate 340 via a wire bonding technology, a flip-chip bonding technology or a surface mount technology.
- the circuit substrate 340 has a first circuit layer 342 , a second circuit layer 344 , a dielectric layer 346 disposed between the first circuit layer 342 and the second circuit layer 344 , and at least a conductive channel 348 .
- the first electronic elements 310 are disposed on the first circuit layer 342 , and the conductive channel 348 penetrates the dielectric layer 346 for electrically connecting the first circuit layer 342 and the second circuit layer 344 .
- the circuit board 340 of the electronic package structure 300 may be omitted according to a design requirement of a designer, though it is not illustrated.
- the insulating encapsulant 350 is disposed in the cavity 322 a and encapsulates the first electronic elements 310 and the circuit substrate 340 for protecting the first electronic elements 310 and the circuit substrate 340 , and enhancing a whole mechanical strength of the electronic package structure 300 .
- the first electronic elements 310 and the circuit substrate 340 are disposed in the cavity 322 a of the second electronic element 320 , compared to a conventional electronic package structures of FIG. 1 and FIG. 2 , utilization of an internal space of the electronic package structure 300 is relatively high, and the first electronic elements 310 and the circuit substrate 340 can be protected by the cavity 322 a .
- the insulating encapsulant 350 is disposed in the cavity 322 a, material of the insulating encapsulant 350 can be directly filled into the cavity 322 a without aiding of extra mold during formation of the insulating encapsulant 350 .
- FIG. 3B is a schematic diagram of another electronic package structure according to the first embodiment of the present invention.
- a difference between the electronic package structure 300 ′ and the electronic package structure 300 is that a part of each lead 332 ′ connecting a first end 332 a ′ and a second end 332 b ′ penetrates a body 322 ′.
- the insulating encapsulant 350 of the electronic package structure 300 is different from a magnetic encapsulant 350 ′ of the electronic package structure 300 ′.
- the magnetic encapsulant 350 ′ is disposed in a cavity 322 a ′ of the body 322 ′.
- a second electronic element 320 ′ is an inductive element
- an inductive characteristic of the second electronic element 320 ′ influenced by the cavity 322 ′ then can be compensated by the magnetic encapsulant 350 ′.
- a part of each of the leads 332 connecting the first end 332 a and the second end 332 b may also penetrate the body 322 according to a design requirement, though it is not illustrated.
- FIG. 3C is a schematic diagram of another electronic package structure according to the first embodiment of the present invention.
- a difference between the electronic package structure 300 ′′ and the electronic package structure 300 is that a cavity 322 a ′′ of a body 322 ′′ sinks in a direction from a first surface 322 b ′′ towards a second surface 322 c ′′.
- an insulating encapsulant 350 ′′ can be substituted by a magnetic encapsulant according to a design requirement, and a part of each lead 332 ′′ connecting a first end 332 a ′′ and a second end 332 b ′′ may also penetrate the body 322 ′′ according to a design requirement, though it is not illustrated.
- FIG. 3D is a schematic diagram of still another electronic package structure according to the first embodiment of the present invention.
- a second lead frame 360 is applied in the electronic package structure 300 ′′′ for substituting the circuit substrate 340 of the electronic package structure 300 according to a design requirement.
- a plurality of first electronic elements 310 ′′′ are disposed on the second lead frame 360 and electrically connected to the second lead frame 360 .
- the second lead frame 360 is electrically connected to a first end 332 a ′′′ of each lead 332 ′′′ of a first lead frame 330 ′′′ that extends to a cavity 322 a ′′′.
- FIG. 4A is a schematic diagram of an electronic package structure according to a second embodiment of the present invention.
- a difference between the electronic package structure 400 of the second embodiment and the electronic package structure 300 of the first embodiment is that a body 422 of a second electronic element 420 does not have the cavity 322 a.
- a first end 432 a of each lead 432 of a lead frame 430 is disposed on a first surface 422 a of a body 422
- a plurality of first electronic elements 410 are disposed on the first surface 422 a and electrically connected to the leads 432 .
- a second end 432 b of each of the leads 432 is disposed on a second surface 422 b of the body 422 opposite to the first surface 422 a, and a part of each of the leads 432 connecting the first end 432 a and the second end 432 b is disposed on a side surface 422 c of the body 422 .
- a circuit substrate 440 is disposed on the first surface 422 a and electrically connected to the leads 432 , and the first electronic elements 410 are disposed on the circuit substrate 440 and electrically connected to the circuit substrate 440 .
- the circuit substrate 440 of the electronic package structure 400 may be omitted according to a design requirement of the designer, or the circuit substrate 440 may be substituted by a lead frame, though it is not illustrated.
- FIG. 4B is a schematic diagram of another electronic package structure according to the second embodiment of the present invention.
- a difference between the electronic package structure 400 ′ and the electronic package structure 400 is that a part of each lead 432 ′ connecting a first end 432 a ′ and a second end 432 b ′ penetrates a body 422 ′.
- FIG. 5A is a schematic diagram of an electronic package structure according to a third embodiment of the present invention.
- a plurality of first electronic elements 510 are disposed on a first surface 532 of a circuit substrate 530 and electrically connected to the circuit substrate 530 .
- a second electronic element 520 is disposed above the first surface 532 of the circuit substrate 530 .
- the first electronic elements 510 are located between a body 522 of the second electronic element 520 and the first surface 532 of the circuit substrate 530
- the first electronic elements 510 are located between leads 524 of the second electronic element 520 .
- the second electronic element 520 covers the first electronic elements 510 .
- an insulating encapsulant 540 is disposed between the second electronic element 520 and the circuit substrate 530 and encapsulating the first electronic elements 510 for protecting the first electronic elements 510 and enhancing a whole mechanical strength of the electronic package structure 500 .
- the circuit substrate 530 may further include at least a conductive channel 539 , and each of the conductive channels 539 penetrates a dielectric layer 538 for electrically connecting a first circuit layer 534 and a second circuit layer 536 . At least one of the conductive channels 539 (for example, the two conductive channels 539 located at a left side of FIG. 5A ) is located below at least one of the first electronic elements 510 (for example, the first electronic element 510 located at the left side of FIG.
- a second end 524 b of each of the leads 524 of the second electronic element 520 extends out from the body 522 to electrically connect the circuit substrate 530 .
- the second electronic element 520 may be an inductive element including a coil 526 .
- the body 522 which is a magnetic wrap wraps the coil 526 , and a first end 524 a of each of the leads 524 is connected to one of two opposite ends of the coil 526 .
- the electronic package structure 500 further includes an electromagnetic-interference-shielding element (EMI-shielding element) 550 covering the first electronic elements 510 .
- EMI-shielding element electromagnetic-interference-shielding element
- the EMI-shielding element 550 is disposed on the body 522 of the second electronic element 520 , and is located between the body 522 of the second electronic element 520 and the circuit substrate 530 . Therefore, during operation of the electronic package structure 500 , it may be reduced by means of the EMI-shielding element 550 that electrical signals transmitted in the circuit substrate 530 is interfered by a magnetic force generated by the second electronic element 520 which functions as an inductive element.
- FIG. 5B is a schematic diagram of another electronic package structure according to the third embodiment of the present invention.
- a difference between the electronic package structure 500 ′ and the electronic package structure 500 is that an EMI-shielding element 550 ′ of the electronic package structure 500 ′ is disposed in a cavity 522 ′ of a second electronic element 520 ′.
- the first electronic elements can be disposed in the cavity of the second electronic element or can be disposed on the second electronic element, or the second electronic element can be stacked on the first electronic elements, compared to the conventional electronic package structures, utilization of an internal space of the electronic package structure is relatively high, so that a size of the electronic package structure can be reduced.
Abstract
An electronic package structure including at least one first electronic element, a second electronic element and a lead frame is provided. The second electronic element includes a body having a cavity. The first electronic element is disposed in the cavity. The lead frame has a plurality of leads. Each of the leads has a first end and a second end. The first end of at least one of the leads extends to the cavity to electrically connect the first electronic element.
Description
- This application claims the priority benefit of Taiwan application serial no. 97105555, filed on Feb. 18, 2008. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of specification.
- 1. Field of the Invention
- The present invention relates to a package structure. More particularly, the present invention relates to an electronic package structure.
- 2. Description of Related Art
- Electronic package structures are formed by complicated package processes. Different electronic package structures have different electrical performances and capacities of heat dissipation, and therefore a designer may select an electronic package structure with a desired electrical performance and capacity of heat dissipation according to a design requirement.
-
FIG. 1 is a schematic diagram of a conventional electronic package structure. Referring toFIG. 1 , the conventionalelectronic package structure 100 includes a printed circuit board (PCB) 110 and a plurality ofelectronic elements 120. Theelectronic elements 120 are disposed on asurface 112 of thePCB 110 and electrically connected to thePCB 110. ThePCB 110 has a plurality ofpins 116 extending out from anothersurface 114 of thePCB 110 to be electrically connected to an electronic device, for example, a motherboard (not shown). -
FIG. 2 is a schematic diagram of another conventional electronic package structure. Referring toFIG. 2 , the conventionalelectronic package structure 200 includes acircuit substrate 210 and a plurality ofelectronic elements 220. Theelectronic elements 220 are disposed on asurface 212 of thecircuit substrate 210, and electrically connected to thecircuit substrate 210 via a wire bonding technology, a flip-chip bonding technology or a surface mount technology. Moreover, the conventionalelectronic package structure 200 may be electrically connected to an electronic device, for example, a motherboard (not shown), via a solder paste or a plurality of solder balls (not shown). - It should be noted that the
electronic elements 120 of the conventionalelectronic package structure 100 are all disposed on thesurface 112 of thePCB 110, and theelectronic elements 220 of the conventionalelectronic package structure 200 are all disposed on thesurface 212 of thecircuit substrate 210. Therefore, in the conventionalelectronic package structures PCB 110 and thecircuit substrate 210 is relatively low, and sizes of the conventionalelectronic package structures - In accordance with the present invention, an electronic package structure can achieve a relatively high utilization of an internal space thereof, so that a size of the electronic package structure can be reduced.
- In one embodiment of the present invention, an electronic package structure includes at least a first electronic element, a second electronic element and a first lead frame. The second electronic element includes a body having a cavity. The first electronic element is disposed in the cavity. The lead frame has a plurality of leads. Each of the leads has a first end and a second end, and the first end of at least one of the leads extends to the cavity to electrically connect the first electronic element.
- In one embodiment of the present invention, an electronic package structure includes at least one first electronic element, a second electronic element and a lead frame. The second electronic element includes a body having a first surface. The lead frame has a plurality of leads. Each of the leads has a first end and a second end. The first ends are disposed on the first surface, and the first electronic element is disposed on the first surface and electrically connected to at least one of the leads.
- In one embodiment, an electronic package structure includes a circuit substrate, at least one first electronic element and a second electronic element. The circuit substrate has a first surface. The first electronic element is disposed on the first surface of the circuit substrate and electrically connected to the circuit substrate. The second electronic element is disposed above the first surface of the circuit substrate and includes a body and a plurality of leads. Each of the leads has a first end and second end, and the second end of each of the leads extends out from the body to electrically connect the circuit substrate. The first electronic element is located among the body of the second electronic element, the first surface of the circuit substrate and the leads.
- In the above embodiments of the present invention, since the first electronic element can be disposed in the cavity of the second electronic element or on the second electronic element, or the second electronic element can be stacked on the first electronic element, compared to the conventional electronic package structures, utilization of an internal space of the electronic package structure is relatively high.
- In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, a preferred embodiment accompanied with figures is described in detail below.
-
FIG. 1 is a schematic diagram of a conventional electronic package structure. -
FIG. 2 is a schematic diagram of another conventional electronic package structure. -
FIG. 3A is a schematic diagram of an electronic package structure according to a first embodiment of the present invention. -
FIG. 3B is a schematic diagram of another electronic package structure according to the first embodiment of the present invention. -
FIG. 3C is a schematic diagram of another electronic package structure according to the first embodiment of the present invention. -
FIG. 3D is a schematic diagram of still another electronic package structure according to the first embodiment of the present invention. -
FIG. 4A is a schematic diagram of an electronic package structure according to a second embodiment of the present invention. -
FIG. 4B is a schematic diagram of another electronic package structure according to the second embodiment of the present invention. -
FIG. 5A is a schematic diagram of an electronic package structure according to a third embodiment of the present invention. -
FIG. 5B is a schematic diagram of another electronic package structure according to the third embodiment of the present invention. -
FIG. 3A is a schematic diagram of an electronic package structure according to a first embodiment of the present invention. Referring toFIG. 3A , theelectronic package structure 300 includes at least one first electronic element 310 (two first electronic elements are illustrated inFIG. 3A ), a secondelectronic element 320 and afirst lead frame 330. Theelectronic package structure 300 is generally applied to a voltage regulator module, a network adapter, a graphics processing unit, a DC/DC converter or a point-of-load (POL) converter. Each of the firstelectronic elements 310 can be a logical control element, a driving element or a passive element. The passive element can be a capacitor, an inductor with lesser inductance, or a resistor. Each of the firstelectronic elements 310 can also be a power element, such as a metal-oxide-semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT) or a diode. - The second
electronic element 320 includes abody 322 having acavity 322 a. The firstelectronic elements 310 are disposed in thecavity 322 a. In the embodiment, thebody 322 of the secondelectronic element 320 has afirst surface 322 b, asecond surface 322 c opposite to thefirst surface 322 b and aside surface 322 d. Thecavity 322 a sinks in a direction from thesecond surface 322 c towards thefirst surface 322 b. Theside surface 322 d connects thefirst surface 322 b and thesecond surface 322 c. Besides, the secondelectronic element 320 can be an energy-storage element used for storing electric energy. In detail, the secondelectronic element 320 further includes acoil 324 and a plurality of firstexternal electrodes 326. Thecoil 324 is disposed within thebody 322. The firstexternal electrodes 326 are respectively connected to two opposite ends of thecoil 324, and extend outside thebody 322 to locate on thefirst surface 322 b and theside surface 322 d. Thebody 322 comprising a magnetic body encloses thecoil 324. The secondelectronic element 320 can be an inductive element with a greater inductance and a greater size than the firstelectronic elements 310. - The
first lead frame 330 has a plurality of leads 332. Each of theleads 332 has afirst end 332 a and asecond end 332 b, and thefirst end 332 a of each of theleads 332 can be embedded in thebody 322 and extends to thecavity 322 a for electrically connecting to the firstelectronic elements 310. Thesecond end 332 b of each of theleads 332 is disposed on thefirst surface 322 b of thebody 322 to form a secondexternal electrode 332 c, and a part of each of theleads 332 connecting thefirst end 332 a and thesecond end 332 b is disposed on theside surface 322 d of thebody 322. - In the present embodiment, the
electronic package structure 300 further includes acircuit substrate 340 and an insulatingencapsulant 350. Thecircuit substrate 340 is disposed in thecavity 322 a of thebody 322. The firstelectronic elements 310 can be disposed on thecircuit substrate 340 and electrically connected to thecircuit substrate 340. Thecircuit substrate 340 is electrically connected to thefirst end 332 a of each of theleads 332 extending to thecavity 322 a. The firstelectronic elements 310 may be electrically connected to thecircuit substrate 340 via a wire bonding technology, a flip-chip bonding technology or a surface mount technology. - The
circuit substrate 340 has afirst circuit layer 342, asecond circuit layer 344, adielectric layer 346 disposed between thefirst circuit layer 342 and thesecond circuit layer 344, and at least aconductive channel 348. The firstelectronic elements 310 are disposed on thefirst circuit layer 342, and theconductive channel 348 penetrates thedielectric layer 346 for electrically connecting thefirst circuit layer 342 and thesecond circuit layer 344. It should be noted that thecircuit board 340 of theelectronic package structure 300 may be omitted according to a design requirement of a designer, though it is not illustrated. - Moreover, the insulating
encapsulant 350 is disposed in thecavity 322 a and encapsulates the firstelectronic elements 310 and thecircuit substrate 340 for protecting the firstelectronic elements 310 and thecircuit substrate 340, and enhancing a whole mechanical strength of theelectronic package structure 300. - Since the first
electronic elements 310 and thecircuit substrate 340 are disposed in thecavity 322 a of the secondelectronic element 320, compared to a conventional electronic package structures ofFIG. 1 andFIG. 2 , utilization of an internal space of theelectronic package structure 300 is relatively high, and the firstelectronic elements 310 and thecircuit substrate 340 can be protected by thecavity 322 a. Besides, since the insulatingencapsulant 350 is disposed in thecavity 322 a, material of the insulatingencapsulant 350 can be directly filled into thecavity 322 a without aiding of extra mold during formation of the insulatingencapsulant 350. -
FIG. 3B is a schematic diagram of another electronic package structure according to the first embodiment of the present invention. Referring toFIG. 3A andFIG. 3B , a difference between theelectronic package structure 300′ and theelectronic package structure 300 is that a part of each lead 332′ connecting afirst end 332 a′ and asecond end 332 b′ penetrates abody 322′. Besides, the insulatingencapsulant 350 of theelectronic package structure 300 is different from amagnetic encapsulant 350′ of theelectronic package structure 300′. Themagnetic encapsulant 350′ is disposed in acavity 322 a′ of thebody 322′. Therefore, if a secondelectronic element 320′ is an inductive element, an inductive characteristic of the secondelectronic element 320′ influenced by thecavity 322′ then can be compensated by themagnetic encapsulant 350′. It should be noted that a part of each of theleads 332 connecting thefirst end 332 a and thesecond end 332 b may also penetrate thebody 322 according to a design requirement, though it is not illustrated. -
FIG. 3C is a schematic diagram of another electronic package structure according to the first embodiment of the present invention. Referring toFIG. 3A andFIG. 3C , a difference between theelectronic package structure 300″ and theelectronic package structure 300 is that acavity 322 a″ of abody 322″ sinks in a direction from afirst surface 322 b″ towards asecond surface 322 c″. It should be noted that an insulatingencapsulant 350″ can be substituted by a magnetic encapsulant according to a design requirement, and a part of each lead 332″ connecting afirst end 332 a″ and asecond end 332 b″ may also penetrate thebody 322″ according to a design requirement, though it is not illustrated. -
FIG. 3D is a schematic diagram of still another electronic package structure according to the first embodiment of the present invention. Referring toFIG. 3A andFIG. 3D , asecond lead frame 360 is applied in theelectronic package structure 300′″ for substituting thecircuit substrate 340 of theelectronic package structure 300 according to a design requirement. A plurality of firstelectronic elements 310′″ are disposed on thesecond lead frame 360 and electrically connected to thesecond lead frame 360. Thesecond lead frame 360 is electrically connected to afirst end 332 a′″ of each lead 332′″ of afirst lead frame 330′″ that extends to acavity 322 a′″. -
FIG. 4A is a schematic diagram of an electronic package structure according to a second embodiment of the present invention. Referring toFIG. 4A andFIG. 3A , a difference between theelectronic package structure 400 of the second embodiment and theelectronic package structure 300 of the first embodiment is that abody 422 of a secondelectronic element 420 does not have thecavity 322 a. In detail, afirst end 432 a of each lead 432 of alead frame 430 is disposed on afirst surface 422 a of abody 422, and a plurality of firstelectronic elements 410 are disposed on thefirst surface 422 a and electrically connected to theleads 432. Moreover, asecond end 432 b of each of theleads 432 is disposed on asecond surface 422 b of thebody 422 opposite to thefirst surface 422 a, and a part of each of theleads 432 connecting thefirst end 432 a and thesecond end 432 b is disposed on aside surface 422 c of thebody 422. - Furthermore, a
circuit substrate 440 is disposed on thefirst surface 422 a and electrically connected to theleads 432, and the firstelectronic elements 410 are disposed on thecircuit substrate 440 and electrically connected to thecircuit substrate 440. It should be noted that thecircuit substrate 440 of theelectronic package structure 400 may be omitted according to a design requirement of the designer, or thecircuit substrate 440 may be substituted by a lead frame, though it is not illustrated. -
FIG. 4B is a schematic diagram of another electronic package structure according to the second embodiment of the present invention. Referring toFIG. 4A andFIG. 4B , a difference between theelectronic package structure 400′ and theelectronic package structure 400 is that a part of each lead 432′ connecting afirst end 432 a′ and asecond end 432 b′ penetrates abody 422′. -
FIG. 5A is a schematic diagram of an electronic package structure according to a third embodiment of the present invention. Referring toFIG. 5A , in theelectronic package structure 500 of the present embodiment, a plurality of firstelectronic elements 510 are disposed on afirst surface 532 of acircuit substrate 530 and electrically connected to thecircuit substrate 530. A secondelectronic element 520 is disposed above thefirst surface 532 of thecircuit substrate 530. The firstelectronic elements 510 are located between abody 522 of the secondelectronic element 520 and thefirst surface 532 of thecircuit substrate 530, and the firstelectronic elements 510 are located betweenleads 524 of the secondelectronic element 520. In other words, in the present embodiment, the secondelectronic element 520 covers the firstelectronic elements 510. Besides, an insulatingencapsulant 540 is disposed between the secondelectronic element 520 and thecircuit substrate 530 and encapsulating the firstelectronic elements 510 for protecting the firstelectronic elements 510 and enhancing a whole mechanical strength of theelectronic package structure 500. Moreover, thecircuit substrate 530 may further include at least aconductive channel 539, and each of theconductive channels 539 penetrates adielectric layer 538 for electrically connecting afirst circuit layer 534 and asecond circuit layer 536. At least one of the conductive channels 539 (for example, the twoconductive channels 539 located at a left side ofFIG. 5A ) is located below at least one of the first electronic elements 510 (for example, the firstelectronic element 510 located at the left side ofFIG. 5A ), so that heat generated by the firstelectronic element 510 located at the left side may be quickly transmitted to where is outside theelectronic package structure 500 via the twoconductive channels 539 located at the left side. Asecond end 524 b of each of theleads 524 of the secondelectronic element 520 extends out from thebody 522 to electrically connect thecircuit substrate 530. The secondelectronic element 520 may be an inductive element including acoil 526. Thebody 522 which is a magnetic wrap wraps thecoil 526, and afirst end 524 a of each of theleads 524 is connected to one of two opposite ends of thecoil 526. - It should be noted that the
electronic package structure 500 further includes an electromagnetic-interference-shielding element (EMI-shielding element) 550 covering the firstelectronic elements 510. In the present embodiment, the EMI-shieldingelement 550 is disposed on thebody 522 of the secondelectronic element 520, and is located between thebody 522 of the secondelectronic element 520 and thecircuit substrate 530. Therefore, during operation of theelectronic package structure 500, it may be reduced by means of the EMI-shieldingelement 550 that electrical signals transmitted in thecircuit substrate 530 is interfered by a magnetic force generated by the secondelectronic element 520 which functions as an inductive element. -
FIG. 5B is a schematic diagram of another electronic package structure according to the third embodiment of the present invention. Referring toFIG. 5A andFIG. 5B , a difference between theelectronic package structure 500′ and theelectronic package structure 500 is that an EMI-shieldingelement 550′ of theelectronic package structure 500′ is disposed in acavity 522′ of a secondelectronic element 520′. - In summary, in the aforementioned embodiments of the present invention, since the first electronic elements can be disposed in the cavity of the second electronic element or can be disposed on the second electronic element, or the second electronic element can be stacked on the first electronic elements, compared to the conventional electronic package structures, utilization of an internal space of the electronic package structure is relatively high, so that a size of the electronic package structure can be reduced.
- It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Claims (17)
1-13. (canceled)
14. An electronic package, comprising:
a substrate;
at least an electronic element on top of the substrate;
a coil;
a body encapsulating at least said coil and being positioned on top of said electronic element; and
a pair of leads each having
a top end electrically coupled to a respective end of the coil,
a bottom end electrically coupled to the substrate, and
a middle section connecting said top end and said bottom end to define a bracket shape.
15. An electronic package as claimed in claim 14 , wherein the electronic element is disposed on a top face of the substrate between the bottom ends of the leads.
16. An electronic package as claimed in claim 14 , wherein said middle section of each said lead is entirely exposed out of said body.
17. An electronic package as claimed in claim 14 , wherein said top end of each said lead is at least partially embedded in the body.
18. An electronic package as claimed in claim 14 , wherein said substrate includes
first and second conductive layers on opposite top and bottom faces of said substrate; and
at least one conductive via penetrating the substrate to electrically connect the first and second conductive layers;
wherein said conductive via is disposed immediately under the electronic element for dissipating heat generated by said electronic element away.
19. An electronic package as claimed in claim 14 , further comprising:
an insulating encapsulant encapsulating the electronic element and disposed under the body.
20. An electronic package as claimed in claim 19 , wherein a width of said encapsulant is smaller than that of said body.
21. An electronic package as claimed in claim 20 , wherein said encapsulant is disposed between the bottom ends of the leads.
22. An electronic package as claimed in claim 14 , wherein the top end and bottom end of each said lead are positioned in parallel planes and the middle section of said lead is perpendicular to the top end and the bottom end.
23. An electronic package as claimed in claim 14 , wherein said electronic element is one selected from the group consisting of a capacitor, a resistor, and an inductor with a smaller inductance than the coil.
24. An electronic package as claimed in claim 14 , wherein said electronic element is one selected from the group consisting of a metal-oxide-semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), and a diode.
25. An electronic package as claimed in claim 14 , comprising multiple said electronic elements disposed under the body and between the bottom ends of the leads.
26. An electronic package as claimed in claim 14 , further comprising:
an electromagnetic-interference (EMI) shielding element between the coil and the electronic element.
27. An electronic package as claimed in claim 26 , further comprising
an insulating encapsulant encapsulating the electronic element and disposed under the body;
wherein the EMI shielding element is embedded in the encapsulant.
28. An electronic package as claimed in claim 26 , wherein the EMI shielding element is embedded in the body.
29. An electronic package as claimed in claim 28 , wherein the body includes a magnetic wrap that wraps the coil.
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/971,671 US20110090648A1 (en) | 2008-02-18 | 2010-12-17 | Electronic package structure |
US13/481,887 US9271398B2 (en) | 2008-02-18 | 2012-05-28 | Power supply module |
US13/485,954 US9001527B2 (en) | 2008-02-18 | 2012-06-01 | Electronic package structure |
US13/754,910 US8837168B2 (en) | 2008-02-18 | 2013-01-31 | Electronic package structure |
US14/594,084 US9538660B2 (en) | 2008-02-18 | 2015-01-10 | Electronic package structure |
US14/594,083 US9451701B2 (en) | 2008-02-18 | 2015-01-10 | Electronic package structure |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW097105555A TWI355068B (en) | 2008-02-18 | 2008-02-18 | Electronic package structure |
TW97105555 | 2008-02-18 | ||
US12/143,143 US20090207574A1 (en) | 2008-02-18 | 2008-06-20 | Electronic package structure |
US12/971,671 US20110090648A1 (en) | 2008-02-18 | 2010-12-17 | Electronic package structure |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/143,143 Division US20090207574A1 (en) | 2008-02-18 | 2008-06-20 | Electronic package structure |
Related Child Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/481,887 Continuation-In-Part US9271398B2 (en) | 2008-02-18 | 2012-05-28 | Power supply module |
US13/485,954 Continuation-In-Part US9001527B2 (en) | 2008-02-18 | 2012-06-01 | Electronic package structure |
US13/754,910 Continuation US8837168B2 (en) | 2008-02-18 | 2013-01-31 | Electronic package structure |
Publications (1)
Publication Number | Publication Date |
---|---|
US20110090648A1 true US20110090648A1 (en) | 2011-04-21 |
Family
ID=40954921
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/143,143 Abandoned US20090207574A1 (en) | 2008-02-18 | 2008-06-20 | Electronic package structure |
US12/971,671 Abandoned US20110090648A1 (en) | 2008-02-18 | 2010-12-17 | Electronic package structure |
US13/754,910 Active US8837168B2 (en) | 2008-02-18 | 2013-01-31 | Electronic package structure |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/143,143 Abandoned US20090207574A1 (en) | 2008-02-18 | 2008-06-20 | Electronic package structure |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/754,910 Active US8837168B2 (en) | 2008-02-18 | 2013-01-31 | Electronic package structure |
Country Status (2)
Country | Link |
---|---|
US (3) | US20090207574A1 (en) |
TW (1) | TWI355068B (en) |
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Also Published As
Publication number | Publication date |
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US20130141886A1 (en) | 2013-06-06 |
US20090207574A1 (en) | 2009-08-20 |
TW200937612A (en) | 2009-09-01 |
TWI355068B (en) | 2011-12-21 |
US8837168B2 (en) | 2014-09-16 |
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