US20110097890A1 - Method of fabricating semiconductor device - Google Patents
Method of fabricating semiconductor device Download PDFInfo
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- US20110097890A1 US20110097890A1 US12/983,700 US98370011A US2011097890A1 US 20110097890 A1 US20110097890 A1 US 20110097890A1 US 98370011 A US98370011 A US 98370011A US 2011097890 A1 US2011097890 A1 US 2011097890A1
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- wiring formation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76864—Thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
Definitions
- a method of fabricating a semiconductor device having a wiring structure in which a barrier film for preventing diffusion of Cu is formed in a self-aligned manner between a wiring main body layer containing therein Cu as a basic constituent and an interlayer insulating film is known as a conventional method of fabricating a semiconductor device.
- a method of fabricating a semiconductor device includes: forming a precursor film containing therein a predetermined metallic element on a surface of a recess portion formed in an insulating film on a semiconductor substrate; forming a wiring formation film on the precursor film; performing a heat treatment in an oxidation ambient atmosphere to cause the precursor film and the insulating film to react with each other, thereby forming a self-formed barrier film containing a compound, containing therein the predetermined metallic element and a constituent element of the insulating film, as a basic constituent in a boundary surface between the precursor film and the insulating film, and moving the predetermined metallic element unreacted into the wiring formation film through diffusion to cause the predetermined metallic element unreacted to react with oxygen contained in the oxidation ambient atmosphere on a surface of the wiring formation film, thereby precipitating an unreacted metallic oxide film including the predetermined metallic element; forming the same material as that of the wiring formation film on the wiring formation film after the unreacted metallic oxide film is removed; and flattening the
- a method of fabricating a semiconductor device includes: forming a precursor film containing therein a predetermined metallic element on a surface of a recess portion formed in an insulating film on a semiconductor substrate; forming a wiring formation film on the precursor film; performing a heat treatment to cause the precursor film and the insulating film to react with each other, thereby forming a self-formed barrier film containing a compound, containing therein the predetermined metallic element and a constituent element of the insulating film, as a basic constituent in a boundary surface between the precursor film and the insulating film, and diffusing the predetermined metallic element unreacted into the wiring formation film; reducing a thickness of the wiring formation film by removing a part of the wiring formation film after the self-formed barrier film is formed and the predetermined metallic element unreacted is diffused into the wiring formation film; performing a heat treatment in an oxidation ambient atmosphere, after the thickness of the wiring formation film is reduced, to cause the predetermined metallic element diffused into the wiring formation film to reactive with oxygen
- a method of fabricating a semiconductor device includes: forming a precursor film containing therein a predetermined metallic element on a surface of a recess portion formed in an insulating film on a semiconductor substrate; forming a wiring formation film on the precursor film; performing a heat treatment to cause the precursor film and the insulating film to react with each other, thereby forming a self-formed barrier film containing a compound, containing therein the predetermined metallic element and a constituent element of the insulating film, as a basic constituent in a boundary surface between the precursor film and the insulating film, and diffusing the predetermined metallic element unreacted into the wiring formation film; flattening the wiring formation film, until a portion of the insulating film located outside the recess portion is exposed, after the self-formed barrier film is formed and the predetermined metallic element unreacted is diffused into the wiring formation film; and performing a heat treatment in an oxidation ambient atmosphere, after the wiring formation film is flattened, to cause the predetermined metallic element diffused into
- FIGS. 1A to 1H are respectively cross sectional views showing processes for fabricating a wiring structure in a semiconductor device according to a first embodiment
- FIGS. 2A to 2F are respectively cross sectional views showing processes for fabricating a wiring structure in a semiconductor device according to a second embodiment
- FIGS. 3A to 3D are respectively cross sectional views showing processes for fabricating a wiring structure in a semiconductor device according to a third embodiment
- FIG. 4 is a graph representing leakage current characteristics of the wiring structure in the semiconductor device fabricated by utilizing the method according to the third embodiment
- FIGS. 5A and 5B are respectively cross sectional views showing processes for fabricating a wiring structure in a semiconductor device according to a fourth embodiment
- FIG. 6 is a cross sectional views showing a process for fabricating a wiring structure in a semiconductor device according to a fifth embodiment
- FIG. 7 is a cross sectional views showing a process for fabricating a wiring structure in a semiconductor device according to a sixth embodiment
- FIGS. 8A and 8B are respectively cross sectional views showing processes for fabricating a wiring structure in a semiconductor device according to a seventh embodiment.
- FIGS. 9A and 9B are respectively cross sectional views showing processes for fabricating a wiring structure in a semiconductor device according to an eighth embodiment.
- a wiring is made of a material containing therein Cu as a basic constituent (50 atomic % or more of the totality), and a self-formed barrier film is made of a material containing therein any one of ⁇ Si x O y , ⁇ C x O y and ⁇ F x O y (x, y: real numbers), each containing therein a predetermined metallic element ⁇ , as a basic constituent.
- the predetermined metallic element a is any one of Mn, V, Zn, Nb, Zr, Cr, Y, Tc and Re.
- a film containing therein the predetermined metallic element ⁇ is used as a precursor film for formation of the self-formed barrier film.
- the predetermined metallic element ⁇ is Mn
- the self-formed barrier film is made of MnSi x O y
- the precursor film is made of a CuMn alloy.
- FIGS. 1A to 1H are respectively cross sectional views showing processes for fabricating a wiring structure in a semiconductor device according to a first embodiment.
- a first barrier film 4 a, a second interlayer insulating film 5 , a second barrier film 6 , an upper first interlayer insulating film 2 b, and a cap layer 3 b are laminated in order on the first interlayer insulating film 2 a and a cap layer 3 a in which a first wiring 11 , having a side surface and a bottom surface covered with a self-formed barrier film 12 a, is formed.
- each of the first interlayer insulating films 2 a and 2 b can be formed of an organic insulating film, having a low relative permittivity, such as polyarylenether (PAr).
- PAr polyarylenether
- the first interlayer insulating film 2 b on the second barrier film 6 for example, has a thickness of 50 nm.
- Each of the cap layers 3 a and 3 b can be formed of an inorganic insulating film which is made of SiO 2 or the like, and which, for example, has a thickness of 50 to 80 nm.
- the first barrier film 4 a can be formed of an inorganic insulating film which is made of SiCN, SiC or the like, and which, for example, has a thickness of 10 to 30 nm. It is noted that the first barrier film 4 a serves to prevent diffusion of Cu contained in the first wiring 11 , and also functions as an etching stopper in a phase of formation of the wiring.
- the second interlayer insulating film 5 can be formed of an inorganic insulating film which is made of SiOC or the like, and which, for example, has a thickness of 50 nm.
- the second barrier film 6 can be formed of an inorganic insulating film which is made of SiOC or the like and which, for example, has a thickness of 10 nm. It is noted that the second barrier film 6 functions as an etching stopper in the phase of formation of the wiring.
- the first barrier film 4 a, the second interlayer insulating film 5 , the second barrier film 6 , the first interlayer insulating film 2 b, and the cap layer 3 b may be formed of insulating films each containing therein Si, respectively.
- the first barrier film 4 a, the second interlayer insulating film 5 , the second barrier film 6 , the first interlayer insulating film 2 b, and the cap layer 3 b may be formed of insulating films each containing therein either C or F.
- a precursor film 14 is formed by a sputtering method, a chemical vapor deposition (CVD) method or the like so as to cover portions of the first barrier film 4 a, the second interlayer insulating film 5 , the second barrier film 6 , the first interlayer insulating film 2 b, and the cap layer 3 b which are exposed from the wiring trench 13 .
- CVD chemical vapor deposition
- the precursor film 14 for example, is made of a CuMn alloy (having an Mn concentration of 4 to 10 atomic %) which has a thickness of 20 to 90 nm.
- a wiring formation film 15 is deposited on the precursor film 14 by a suitable plating method using the precursor film 14 as a seed layer, the CVD method or the like.
- the wiring formation film 15 is made of Cu which has a thickness from a surface of the precursor film 14 on the cap layer 3 b falling in the range of 10 to 110 nm.
- a heat treatment for example, is performed at 200 to 400° C. for 5 to 60 minutes in an oxidation ambient atmosphere, which results in that the precursor film 14 reacts with each of the first barrier film 4 a, the second interlayer insulating film 5 , the second barrier film 6 , the first interlayer insulating film 2 b, and the cap layer 3 b, so that the self-formed barrier film 12 b is formed in a self-aligned manner.
- a thickness, of the wiring formation film 15 from the surface of the precursor film 14 on the cap layer 3 b is not smaller than 10 nm, cohesion of the wiring formation film 15 due to the heat treatment hardly occurs.
- predetermined metallic elements ⁇ unreacted within the precursor film 14 diffuse into and move within the wiring formation film 15 , so that an unreacted metallic oxide film 16 , including predetermined metallic elements ⁇ , precipitates on the surface of the wiring formation film 15 .
- a thickness, of the wiring formation film 15 from the surface of the precursor film 14 on the cap layer 3 b exceeds 110 nm, a precipitation of the unreacted predetermined metallic elements ⁇ may not progress and thus a large quantity of unreacted predetermined metallic element ⁇ may remain in the wiring formation film 15 because of an increase in distance of the movement of the predetermined metallic elements ⁇ to the surface of the wiring formation film 15 .
- the precursor film 14 is made of a CuMn alloy
- the self-formed barrier film 12 b is made of MnSi x O y
- an MnSi x O y film having a thickness of about 2 to about 10 nm is formed in the form of the self-formed barrier film 12 b from Mn contained in the precursor film 14 , and Si and O contained in each of the second interlayer insulating film 5 , the second barrier film 6 , the cap layer 3 b and the like. It is noted that Cu contained in the precursor film 14 diffuses into the wiring formation film 15 .
- the unreacted metallic oxide film 16 is removed by using an acid such as a hydrochloric acid, and the wiring formation film 15 is further formed so as to be stacked on the previous wiring formation film 15 by a suitable plating method, the CVD method or the like to have a thickness enough to permit chemical mechanical polishing (CMP) to be performed in a subsequent process, for example, to have up to the thickness of 0.8 to 1.5 ⁇ m.
- CMP chemical mechanical polishing
- the thickness of the stacked wiring formation film 15 is preferably larger than that of the unreacted metallic oxide film 16 thus removed.
- the reason for this is because if the thickness of the stacked wiring formation film 15 is permitted to be smaller than that of the unreacted metallic oxide film 16 , the wiring formation film 15 does not have the thickness enough to permit the CMP to be performed even after the wiring formation film 15 is stacked on the previous wiring formation film 15 .
- the wiring formation film 15 is flattened until the cap layer 3 b is exposed, thereby forming a second wiring 17 , and a via 18 through which the first wiring 11 and the second wiring 17 are connected to each other.
- the self-formed barrier film 12 b formed on the cap layer 3 b is removed through the CMP process.
- the first barrier film 4 b is formed on the second wiring 17 and the cap layer 3 b. While not illustrated in the figure, an insulating film and the like are formed as upper layers, thereby forming a semiconductor device 1 .
- the unreacted metallic oxide film 16 is precipitated after the wiring formation film 15 is formed so that its thickness from the surface of the precursor film 14 on the cap layer 3 b falls in the range of 10 to 110 nm, which results in that the quantity of unreacted predetermined metallic element ⁇ remaining in the wiring formation film 15 can be suppressed, and thus it is possible to obtain the high reliability against the electromigration and the stress voids without hardly increasing the specific resistance of the second wiring 17 .
- first wiring 11 can be formed in the same manner as that for the second wiring 17 .
- a second embodiment is different from the first embodiment in that the unreacted metallic oxide film 16 is precipitated after the wiring formation film 15 is flattened through the CMP process. Note that, the same respects, such as the constitutions and the like of other portions, as those in the first embodiment are omitted here in their descriptions for the sake of simplicity.
- FIGS. 2A to 2F are respectively cross sectional views showing processes for fabricating a wiring structure in a semiconductor device according to the second embodiment.
- the wiring formation film 15 is deposited on the precursor film 14 by utilizing the suitable plating method, the CVD method or the like using the precursor film 14 as a seed layer.
- the wiring formation film 15 is formed to have a thickness enough to permit the CMP to be performed in the subsequent process, for example, to have a thickness from the surface of the precursor film 14 on the cap layer 3 b falling in the range of 1 to 1.5 ⁇ m.
- a heat treatment for example, is performed at 200 to 400° C. for 5 to 60 minutes, preferably, in a reduction ambient atmosphere, which results in that the precursor film 14 reacts with each of the first barrier film 4 a, the second interlayer insulating film 5 , the second barrier film 6 , the first interlayer insulating film 2 b, and the cap layer 3 b to turn into the self-formed barrier film 12 b.
- the unreacted predetermined metallic elements ⁇ which are contained in the precursor film 14 is in a state of diffusing into the wiring formation film 15 , and thus does not yet precipitate in the form of the unreacted metallic oxide film 16 .
- the unreacted predetermined metallic elements ⁇ may be permitted to precipitate in the form of the unreacted metallic oxide film 16 , it is difficult for a sufficient quantity of metallic element ⁇ to precipitate in the form of the unreacted metallic oxide film 16 because the wiring formation film 15 is too thick for the predetermined metallic elements ⁇ diffused into the wiring formation film 15 to efficiently move to the surface of the wiring formation film 15 .
- the thickness of the wiring formation film 15 is reduced to the middle thereof through the CMP process.
- the wiring formation film 15 is scraped until its thickness from the surface of the self-formed barrier film 12 b on the cap layer 3 b falls in the range of 10 to 110 nm.
- a heat treatment for example, is formed at 200 to 400° C. for 5 to 60 minutes in an oxidation ambient atmosphere, thereby precipitating the unreacted metallic oxide film 16 on the surface of the wiring formation film 15 .
- the CMP is performed with the cap layer 3 b as a stopper to flatten the wiring formation film 15 until the cap layer 3 b is exposed, thereby forming the second wiring 17 , and the via 18 through which the first wiring 11 and the second wiring 17 are connected to each other.
- the self-formed barrier film 12 b on the cap layer 3 b is removed through the CMP process.
- the first barrier film 4 b is formed on the second wiring 17 and the cap layer 3 b. Moreover, while not illustrated in the figure, the insulating film and the like are formed as the upper layers, thereby forming the semiconductor device 1 .
- a third embodiment is different from the second embodiment in that the unreacted metallic oxide film 16 is precipitated after the CMP is performed for the wiring formation film 15 until the surface of the cap layer 3 b is exposed. It is noted that the same respects, such as the constitutions and the like of other portions, as those in the second embodiment are omitted here in their descriptions for the sake of simplicity.
- FIGS. 3A to 3D are respectively cross sectional views showing processes for fabricating a wiring structure in a semiconductor device according to the third embodiment.
- the CMP is performed with the cap layer 3 b as the stopper to flatten the wiring formation film 15 until the cap layer 3 b is exposed.
- the self-formed barrier film 12 b on the cap layer 3 b is removed through the CMP process.
- the heat treatment for example, is performed at 200 to 400° C. for 5 to 60 minutes in the oxidation ambient atmosphere, thereby precipitating the unreacted metallic oxide film 16 on the surface of the wiring formation film 15 .
- the self-formed barrier film 12 b contains therein the predetermined metallic elements ⁇ and oxygen constituting the unreacted metallic oxide film 16 , the reaction for formation of the unreacted metallic oxide film 16 progresses to the self-formed barrier film 12 b.
- a peripheral portion of the unreacted metallic oxide film 16 has a shape of extending downward along the cap layer 3 b.
- the reaction for formation of MnO x progresses to the inside of the self-formed barrier film 12 b because the self-formed barrier film 12 b contains therein Mn and O.
- the second wiring 17 having a rounded shape in its upper surface end portion, and the via 18 through which the first wiring 11 and the second wiring 17 are connected to each other are formed.
- the unreacted metallic oxide film 16 is removed by using an acid such as a hydrochloric acid.
- the first barrier film 4 b is formed on the second wiring 17 and the cap layer 3 b. Moreover, while not illustrated in the figure, the insulating film and the like are formed as the upper layers, thereby forming the semiconductor device 1 .
- the unreacted metallic oxide film 16 may not be removed because it is the insulating film.
- the first barrier film 4 b is formed on the unreacted metallic oxide film 16 .
- the second wiring 17 having the rounded shape in its upper surface end portion makes it possible to suppress concentration of an electric field on the upper surface end portion.
- the upper surface of the second wiring 17 is made different in height from that of the cap layer 3 b, thereby making it possible to reduce a leakage current.
- first wiring 11 can be formed by utilizing the same method as that for the second wiring 17 .
- FIG. 4 is a graph representing leakage current characteristics of the wiring structure in the semiconductor device fabricated by utilizing the method of the third embodiment.
- a lower curve represents the characteristics of the wiring having the rounded shape in its upper surface end portion fabricated by utilizing the method of the third embodiment
- an upper curve represents the characteristics of the conventional wiring having no rounded shape in its upper surface end portion.
- Each of the upper and lower curves represents a relationship between a magnitude of an electric field (plotted on an axis of ordinate in FIG. 4 ) occurring across the adjacent two wirings, and a magnitude of a leakage current (plotted on an axis of abscissa in FIG. 4 ).
- the conventional wiring having no rounded shape in its upper surface end portion shows the characteristics in which a breakdown is generated when the magnitude of the electric field exceeds about 3.8 MV/cm, so that the magnitude of the leakage current rises suddenly.
- the wiring having the rounded shape in its upper surface end portion shows the characteristics in which the magnitudes of the leakage currents are generally smaller than those in the conventional wiring structure, and also no breakdown is generated within this measurement range.
- a fourth embodiment is different from the third embodiment in that the unreacted metallic oxide film 16 is precipitated after the first barrier film 4 b is formed on the wiring formation film 15 . It is noted that the same respects, such as the constitutions and the like of other portions, as those in the third embodiment are omitted herein in their descriptions for the sake of simplicity.
- FIGS. 5A and 5B are respectively cross sectional views showing processes for fabricating a wiring structure in a semiconductor device according to the fourth embodiment.
- the first barrier film 4 b is formed on the wiring formation film 15 and the cap layer 3 b.
- the heat treatment for example, is performed at 200 to 400° C. for 5 to 60 minutes in the oxidation ambient atmosphere, thereby precipitating the unreacted metallic oxide film 16 on the surface of the wiring formation film 15 .
- the self-formed barrier film 12 b contains therein the predetermined metallic elements ⁇ and oxygen constituting the unreacted metallic oxide film 16 , the reaction for formation of the unreacted metallic oxide film 16 progresses to the self-formed barrier film 12 b.
- the peripheral portion of the unreacted metallic oxide film 16 has a shape of extending downward along the cap layer 3 .
- the insulating film and the like are formed as the upper layers, thereby forming the semiconductor device 1 .
- a fifth embodiment is different from the first or second embodiment in that the self-formed barrier film 12 is formed even on the upper surface of the second wiring 17 . It is noted that the same respects, such as the constitutions and the like of other portions, as those in the first or second embodiment are omitted here in their descriptions for the sake of simplicity.
- FIG. 6 is a cross sectional view showing a process for fabricating a wiring structure in a semiconductor device according to a fifth embodiment.
- a heat treatment for example, is performed at 200 to 400° C. for 5 to 60 minutes, preferably, in a reduction ambient atmosphere, which results in that a reaction occurs between the second wiring 17 and the first barrier film 4 b on the second wiring 17 , thereby forming the self-formed barrier film 12 b on the upper surface of the second wiring 17 .
- the self-formed barrier film 12 b is made of MnSi x O y
- the self-formed barrier film 12 b is formed on the upper surface of the second wiring 17 from Mn remaining in the second wiring 17 , and Si and O contained in the first barrier film 4 b.
- the insulating film and the like are formed as the upper layers, thereby forming the semiconductor device 1 .
- forming the self-formed barrier film 12 b even on the upper surface of the second wiring 17 makes it possible to further reduce the leakage current as compared with that in the first or second embodiment.
- first wiring 11 can be formed by utilizing the same method as that for the second wiring 17 .
- a sixth embodiment is different from the third embodiment in that the self-formed barrier film 12 b is formed even on the upper surface of the second wiring 17 . It is noted that the same respects, such as the constitutions and the like of other portions, as those in the third embodiment are omitted here in their descriptions for the sake of simplicity.
- FIG. 7 is a cross sectional view showing a process for fabricating a wiring structure in a semiconductor device according to the sixth embodiment.
- the heat treatment for example, is performed at 200 to 400° C. for 5 to 60 minutes, preferably, in the reduction ambient atmosphere, which results in that the reaction occurs between the second wiring 17 and the first barrier film 4 b on the second wiring 17 , thereby forming the self-formed barrier film 12 b on the upper surface of the second wiring 17 .
- the self-formed barrier film 12 b is made of MnSi x O y
- the self-formed barrier film 12 b is formed on the upper surface of the second wiring 17 from Mn remaining in the second wiring 17 , and Si and O contained in the first barrier film 4 b.
- the insulating film and the like are formed as the upper layers, thereby forming the semiconductor device 1 .
- forming the self-formed barrier film 12 b even on the upper surface of the second wiring 17 makes it possible to further reduce the leakage current as compared with that in the third embodiment.
- first wiring 11 can be formed by utilizing the same method as that for the second wiring 17 .
- a seventh embodiment is different from the first or second embodiment in that the self-formed barrier film 12 b is formed even on the upper surface of the second wiring 17 . It is noted that the same respects, such as the constitutions and the like of other portions, as those in the first or second embodiment are omitted here in their descriptions for the sake of simplicity.
- FIGS. 8A and 8B are respectively cross sectional views showing processes for fabricating a wiring structure in a semiconductor device according to the seventh embodiment.
- the upper surface of the second wiring 17 is exposed to each of a reducing gas and a silane gas.
- Si penetrates into only an uppermost portion of the upper surface of the second wiring 17 .
- the heat treatment for example, is performed at 200 to 400° C. for 5 to 60 minutes in the oxidation ambient atmosphere, thereby forming the self-formed barrier film 12 b on the upper surface of the second wiring 17 .
- the self-formed barrier film 12 b is made of MnSi x O y
- the self-formed barrier film 12 b is formed on the upper surface of the second wiring 17 from Mn and Si contained in the second wiring 17 , and O contained in the oxidation ambient atmosphere.
- the first barrier film 4 b is formed on the second wiring 17 and the cap layer 3 b. Moreover, while not illustrated in the figure, the insulating film and the like are formed as the upper layers, thereby forming the semiconductor device 1 .
- forming the self-formed barrier film 12 b even on the upper surface of the second wiring 17 makes it possible to further reduce the leakage current as compared with that in the first or second embodiment.
- first wiring 11 can be formed by utilizing the same method as that for the second wiring 17 .
- An eighth embodiment is different from the third embodiment in that the self-formed barrier film 12 b is formed even on the upper surface of the second wiring 17 . It is noted that the same respects, such as the constitutions and the like of other portions, as those in the third embodiment are omitted here in their descriptions for the sake of simplicity.
- FIGS. 9A and 9B are respectively cross sectional views showing processes for fabricating a wiring structure in a semiconductor device according to the eighth embodiment.
- the heat treatment for example, is performed at 200 to 400° C. for 5 to 60 minutes in the oxidation ambient atmosphere, thereby forming the self-formed barrier film 12 b on the upper surface of the second wiring 17 .
- the self-formed barrier film 12 b is made of MnSi x O y
- the self-formed barrier film 12 b is formed on the upper surface of the second wiring 17 from Mn and Si contained in the second wiring 17 , and O contained in the oxidation ambient atmosphere.
- the first barrier film 4 b is formed on the self-formed barrier film 12 b on the second wiring 17 , and the cap layer 3 b. Moreover, while not illustrated in the figure, the insulating film and the like are formed as the upper layers, thereby forming the semiconductor device.
- forming the self-formed barrier film 12 b even on the upper surface of the second wiring 17 makes it possible to further reduce the leakage current as compared with that in the third embodiment.
- first wiring 11 can be formed by utilizing the same method as that for the second wiring 17 .
- the present invention is not intended to be limited to the embodiments described above, and the various changes can be implemented by those skilled in the art without departing from the gist of the invention.
- the present invention can also be applied to any of wiring structures other than the dual damascene wiring structure as shown in each of the embodiments described above.
- the present invention may also be applied to a wiring structure in which wirings/vias covered with the self-formed barrier film are individually formed.
Abstract
A method of fabricating a semiconductor device according to an embodiment includes: forming a precursor film containing therein a predetermined metallic element on a surface of a recess portion formed in an insulating film on a semiconductor substrate; forming a wiring formation film on the precursor film; performing a heat treatment in an oxidation ambient atmosphere to cause the precursor film and the insulating film to react with each other, thereby forming a self-formed barrier film containing a compound, containing therein the predetermined metallic element and a constituent element of the insulating film, as a basic constituent in a boundary surface between the precursor film and the insulating film, and moving the predetermined metallic element unreacted into the wiring formation film through diffusion to cause the predetermined metallic element unreacted to react with oxygen contained in the oxidation ambient atmosphere on a surface of the wiring formation film, thereby precipitating an unreacted metallic oxide film including the predetermined metallic element; forming the same material as that of the wiring formation film on the wiring formation film after the unreacted metallic oxide film is removed; and flattening the wiring formation film until a portion of the insulating film located outside the recess portion is exposed.
Description
- This application is a divisional of and claims the benefit of priority from U.S. Ser. No. 11/956,868, filed Dec. 14, 2007, which claims the benefit of priority from Japanese Patent Application No. 2006-340506, filed on Dec. 18, 2006, the entire contents of each of which are incorporated herein by reference.
- A method of fabricating a semiconductor device having a wiring structure in which a barrier film for preventing diffusion of Cu is formed in a self-aligned manner between a wiring main body layer containing therein Cu as a basic constituent and an interlayer insulating film is known as a conventional method of fabricating a semiconductor device.
- A method of fabricating a semiconductor device according to one embodiment includes: forming a precursor film containing therein a predetermined metallic element on a surface of a recess portion formed in an insulating film on a semiconductor substrate; forming a wiring formation film on the precursor film; performing a heat treatment in an oxidation ambient atmosphere to cause the precursor film and the insulating film to react with each other, thereby forming a self-formed barrier film containing a compound, containing therein the predetermined metallic element and a constituent element of the insulating film, as a basic constituent in a boundary surface between the precursor film and the insulating film, and moving the predetermined metallic element unreacted into the wiring formation film through diffusion to cause the predetermined metallic element unreacted to react with oxygen contained in the oxidation ambient atmosphere on a surface of the wiring formation film, thereby precipitating an unreacted metallic oxide film including the predetermined metallic element; forming the same material as that of the wiring formation film on the wiring formation film after the unreacted metallic oxide film is removed; and flattening the wiring formation film until a portion of the insulating film located outside the recess portion is exposed.
- A method of fabricating a semiconductor device according to another embodiment includes: forming a precursor film containing therein a predetermined metallic element on a surface of a recess portion formed in an insulating film on a semiconductor substrate; forming a wiring formation film on the precursor film; performing a heat treatment to cause the precursor film and the insulating film to react with each other, thereby forming a self-formed barrier film containing a compound, containing therein the predetermined metallic element and a constituent element of the insulating film, as a basic constituent in a boundary surface between the precursor film and the insulating film, and diffusing the predetermined metallic element unreacted into the wiring formation film; reducing a thickness of the wiring formation film by removing a part of the wiring formation film after the self-formed barrier film is formed and the predetermined metallic element unreacted is diffused into the wiring formation film; performing a heat treatment in an oxidation ambient atmosphere, after the thickness of the wiring formation film is reduced, to cause the predetermined metallic element diffused into the wiring formation film to reactive with oxygen in the oxidation ambient atmosphere on a surface of the wiring formation film, thereby precipitating an unreacted metallic oxide film including the predetermined metallic element; and flattening the wiring formation film, until a portion of the insulating film located outside the recess portion is exposed, after the unreacted metallic oxide film is removed.
- A method of fabricating a semiconductor device according to still another embodiment includes: forming a precursor film containing therein a predetermined metallic element on a surface of a recess portion formed in an insulating film on a semiconductor substrate; forming a wiring formation film on the precursor film; performing a heat treatment to cause the precursor film and the insulating film to react with each other, thereby forming a self-formed barrier film containing a compound, containing therein the predetermined metallic element and a constituent element of the insulating film, as a basic constituent in a boundary surface between the precursor film and the insulating film, and diffusing the predetermined metallic element unreacted into the wiring formation film; flattening the wiring formation film, until a portion of the insulating film located outside the recess portion is exposed, after the self-formed barrier film is formed and the predetermined metallic element unreacted is diffused into the wiring formation film; and performing a heat treatment in an oxidation ambient atmosphere, after the wiring formation film is flattened, to cause the predetermined metallic element diffused into the wiring formation film to react with oxygen in the oxidation ambient temperature on a surface of the wiring formation film, causing the reaction to progress to an inside of the self-formed barrier film to precipitate an unreacted metallic oxide film including the predetermined metallic element on an upper surface of the wiring formation film and a side surface near the upper surface of the wiring formation film, and rounding an end portion of the upper surface of the wiring formation film.
-
FIGS. 1A to 1H are respectively cross sectional views showing processes for fabricating a wiring structure in a semiconductor device according to a first embodiment; -
FIGS. 2A to 2F are respectively cross sectional views showing processes for fabricating a wiring structure in a semiconductor device according to a second embodiment; -
FIGS. 3A to 3D are respectively cross sectional views showing processes for fabricating a wiring structure in a semiconductor device according to a third embodiment; -
FIG. 4 is a graph representing leakage current characteristics of the wiring structure in the semiconductor device fabricated by utilizing the method according to the third embodiment; -
FIGS. 5A and 5B are respectively cross sectional views showing processes for fabricating a wiring structure in a semiconductor device according to a fourth embodiment; -
FIG. 6 is a cross sectional views showing a process for fabricating a wiring structure in a semiconductor device according to a fifth embodiment; -
FIG. 7 is a cross sectional views showing a process for fabricating a wiring structure in a semiconductor device according to a sixth embodiment; -
FIGS. 8A and 8B are respectively cross sectional views showing processes for fabricating a wiring structure in a semiconductor device according to a seventh embodiment; and -
FIGS. 9A and 9B are respectively cross sectional views showing processes for fabricating a wiring structure in a semiconductor device according to an eighth embodiment. - In each of embodiments which will be described below, a description will now be given with respect to a method of fabricating a semiconductor device having a dual damascene wiring structure in which wirings and vias are covered with a self-formed barrier film.
- A wiring is made of a material containing therein Cu as a basic constituent (50 atomic % or more of the totality), and a self-formed barrier film is made of a material containing therein any one of αSixOy, αCxOy and αFxOy (x, y: real numbers), each containing therein a predetermined metallic element α, as a basic constituent. Here, the predetermined metallic element a is any one of Mn, V, Zn, Nb, Zr, Cr, Y, Tc and Re.
- In addition, a film containing therein the predetermined metallic element α is used as a precursor film for formation of the self-formed barrier film.
- Note that, it is preferable that the predetermined metallic element α is Mn, the self-formed barrier film is made of MnSixOy, and the precursor film is made of a CuMn alloy.
-
FIGS. 1A to 1H are respectively cross sectional views showing processes for fabricating a wiring structure in a semiconductor device according to a first embodiment. - Firstly, as shown in
FIG. 1A , afirst barrier film 4 a, a second interlayerinsulating film 5, asecond barrier film 6, an upper first interlayerinsulating film 2 b, and acap layer 3 b are laminated in order on the firstinterlayer insulating film 2 a and acap layer 3 a in which afirst wiring 11, having a side surface and a bottom surface covered with a self-formedbarrier film 12 a, is formed. - Here, each of the first
interlayer insulating films interlayer insulating film 2 b on thesecond barrier film 6, for example, has a thickness of 50 nm. - Each of the
cap layers - The
first barrier film 4 a can be formed of an inorganic insulating film which is made of SiCN, SiC or the like, and which, for example, has a thickness of 10 to 30 nm. It is noted that thefirst barrier film 4 a serves to prevent diffusion of Cu contained in thefirst wiring 11, and also functions as an etching stopper in a phase of formation of the wiring. - The second
interlayer insulating film 5 can be formed of an inorganic insulating film which is made of SiOC or the like, and which, for example, has a thickness of 50 nm. - The
second barrier film 6 can be formed of an inorganic insulating film which is made of SiOC or the like and which, for example, has a thickness of 10 nm. It is noted that thesecond barrier film 6 functions as an etching stopper in the phase of formation of the wiring. - Note that, when the self-formed
barrier film 12 b formed in a subsequent process is made of αSixOy, thefirst barrier film 4 a, the secondinterlayer insulating film 5, thesecond barrier film 6, the firstinterlayer insulating film 2 b, and thecap layer 3 b may be formed of insulating films each containing therein Si, respectively. In addition, when the self-formedbarrier film 12 b is made of either αCxOy or αFxOy, thefirst barrier film 4 a, the secondinterlayer insulating film 5, thesecond barrier film 6, the firstinterlayer insulating film 2 b, and thecap layer 3 b may be formed of insulating films each containing therein either C or F. - Next, as shown in
FIG. 1B , a wiring trench (recess portion) 13 for formation of asecond wiring 17 and a via 18 which will be described later by utilizing a suitable etching method. - Next, as shown in
FIG. 1C , aprecursor film 14 is formed by a sputtering method, a chemical vapor deposition (CVD) method or the like so as to cover portions of thefirst barrier film 4 a, the secondinterlayer insulating film 5, thesecond barrier film 6, the firstinterlayer insulating film 2 b, and thecap layer 3 b which are exposed from thewiring trench 13. - Here, the
precursor film 14, for example, is made of a CuMn alloy (having an Mn concentration of 4 to 10 atomic %) which has a thickness of 20 to 90 nm. - Next, as shown in
FIG. 1D , awiring formation film 15 is deposited on theprecursor film 14 by a suitable plating method using theprecursor film 14 as a seed layer, the CVD method or the like. - Here, the
wiring formation film 15, for example, is made of Cu which has a thickness from a surface of theprecursor film 14 on thecap layer 3 b falling in the range of 10 to 110 nm. - Next, as shown in
FIG. 1E , a heat treatment, for example, is performed at 200 to 400° C. for 5 to 60 minutes in an oxidation ambient atmosphere, which results in that theprecursor film 14 reacts with each of thefirst barrier film 4 a, the secondinterlayer insulating film 5, thesecond barrier film 6, the firstinterlayer insulating film 2 b, and thecap layer 3 b, so that the self-formedbarrier film 12 b is formed in a self-aligned manner. At this time, when a thickness, of thewiring formation film 15, from the surface of theprecursor film 14 on thecap layer 3 b is not smaller than 10 nm, cohesion of thewiring formation film 15 due to the heat treatment hardly occurs. - On the other hand, predetermined metallic elements α unreacted within the
precursor film 14 diffuse into and move within thewiring formation film 15, so that an unreactedmetallic oxide film 16, including predetermined metallic elements α, precipitates on the surface of thewiring formation film 15. At this time, when a thickness, of thewiring formation film 15, from the surface of theprecursor film 14 on thecap layer 3 b exceeds 110 nm, a precipitation of the unreacted predetermined metallic elements α may not progress and thus a large quantity of unreacted predetermined metallic element α may remain in thewiring formation film 15 because of an increase in distance of the movement of the predetermined metallic elements α to the surface of thewiring formation film 15. - When the
precursor film 14 is made of a CuMn alloy, and the self-formedbarrier film 12 b is made of MnSixOy, an MnSixOy film having a thickness of about 2 to about 10 nm is formed in the form of the self-formedbarrier film 12 b from Mn contained in theprecursor film 14, and Si and O contained in each of the secondinterlayer insulating film 5, thesecond barrier film 6, thecap layer 3 b and the like. It is noted that Cu contained in theprecursor film 14 diffuses into thewiring formation film 15. - In addition, unreacted Mn contained in the
precursor film 14 diffuses into and moves within thewiring formation film 15, so that the unreactedmetallic oxide film 16 precipitates in the form of an MnOx (x: a real number) film on the surface of thewiring formation film 15. In this case, about 0.04 atomic % Mn is contained in thewiring formation film 15 intended to become a Cu wiring. Thus, a specific resistance further increases in thewiring formation film 15 than in a wiring formation film containing therein no Mn by about 0.14 μΩ/cm. The increase in specific resistance hardly becomes a problem in actual use. It is noted that when about 0.05 atomic % or less Mn is contained in thewiring formation film 15, an increase in specific resistance becomes no problem. In addition thereto, it is possible to obtain the high reliability against the electromigration and the stress voids because Mn impedes the movement of Cu. - Next, as shown in
FIG. 1F , the unreactedmetallic oxide film 16 is removed by using an acid such as a hydrochloric acid, and thewiring formation film 15 is further formed so as to be stacked on the previouswiring formation film 15 by a suitable plating method, the CVD method or the like to have a thickness enough to permit chemical mechanical polishing (CMP) to be performed in a subsequent process, for example, to have up to the thickness of 0.8 to 1.5 μm. Note that, the thickness of the stackedwiring formation film 15 is preferably larger than that of the unreactedmetallic oxide film 16 thus removed. The reason for this is because if the thickness of the stackedwiring formation film 15 is permitted to be smaller than that of the unreactedmetallic oxide film 16, thewiring formation film 15 does not have the thickness enough to permit the CMP to be performed even after thewiring formation film 15 is stacked on the previouswiring formation film 15. - Next, as shown in
FIG. 1G , by performing the CMP with thecap layer 3 b as a stopper, thewiring formation film 15 is flattened until thecap layer 3 b is exposed, thereby forming asecond wiring 17, and a via 18 through which thefirst wiring 11 and thesecond wiring 17 are connected to each other. In addition, the self-formedbarrier film 12 b formed on thecap layer 3 b is removed through the CMP process. - Next, as shown in
FIG. 1H , thefirst barrier film 4 b is formed on thesecond wiring 17 and thecap layer 3 b. While not illustrated in the figure, an insulating film and the like are formed as upper layers, thereby forming asemiconductor device 1. - According to the first embodiment, the unreacted
metallic oxide film 16 is precipitated after thewiring formation film 15 is formed so that its thickness from the surface of theprecursor film 14 on thecap layer 3 b falls in the range of 10 to 110 nm, which results in that the quantity of unreacted predetermined metallic element α remaining in thewiring formation film 15 can be suppressed, and thus it is possible to obtain the high reliability against the electromigration and the stress voids without hardly increasing the specific resistance of thesecond wiring 17. - It is noted that the
first wiring 11 can be formed in the same manner as that for thesecond wiring 17. - A second embodiment is different from the first embodiment in that the unreacted
metallic oxide film 16 is precipitated after thewiring formation film 15 is flattened through the CMP process. Note that, the same respects, such as the constitutions and the like of other portions, as those in the first embodiment are omitted here in their descriptions for the sake of simplicity. -
FIGS. 2A to 2F are respectively cross sectional views showing processes for fabricating a wiring structure in a semiconductor device according to the second embodiment. - Firstly, there is performed up to the process for forming the
precursor film 14 as shown inFIG. 1C in the first embodiment. - Next, as shown in
FIG. 2A , thewiring formation film 15 is deposited on theprecursor film 14 by utilizing the suitable plating method, the CVD method or the like using theprecursor film 14 as a seed layer. Here, thewiring formation film 15 is formed to have a thickness enough to permit the CMP to be performed in the subsequent process, for example, to have a thickness from the surface of theprecursor film 14 on thecap layer 3 b falling in the range of 1 to 1.5 μm. - Next, as shown in
FIG. 2B , a heat treatment, for example, is performed at 200 to 400° C. for 5 to 60 minutes, preferably, in a reduction ambient atmosphere, which results in that theprecursor film 14 reacts with each of thefirst barrier film 4 a, the secondinterlayer insulating film 5, thesecond barrier film 6, the firstinterlayer insulating film 2 b, and thecap layer 3 b to turn into the self-formedbarrier film 12 b. It is noted that at this time point, the unreacted predetermined metallic elements α which are contained in theprecursor film 14 is in a state of diffusing into thewiring formation film 15, and thus does not yet precipitate in the form of the unreactedmetallic oxide film 16. Although the unreacted predetermined metallic elements α may be permitted to precipitate in the form of the unreactedmetallic oxide film 16, it is difficult for a sufficient quantity of metallic element α to precipitate in the form of the unreactedmetallic oxide film 16 because thewiring formation film 15 is too thick for the predetermined metallic elements α diffused into thewiring formation film 15 to efficiently move to the surface of thewiring formation film 15. - Next, as shown in
FIG. 2C , the thickness of thewiring formation film 15 is reduced to the middle thereof through the CMP process. For example, thewiring formation film 15 is scraped until its thickness from the surface of the self-formedbarrier film 12 b on thecap layer 3 b falls in the range of 10 to 110 nm. - Next, as shown in
FIG. 2D , a heat treatment, for example, is formed at 200 to 400° C. for 5 to 60 minutes in an oxidation ambient atmosphere, thereby precipitating the unreactedmetallic oxide film 16 on the surface of thewiring formation film 15. - Next, as shown in
FIG. 2E , after the unreactedmetallic oxide film 16 is removed by using an acid such as a hydrochloric acid, the CMP is performed with thecap layer 3 b as a stopper to flatten thewiring formation film 15 until thecap layer 3 b is exposed, thereby forming thesecond wiring 17, and the via 18 through which thefirst wiring 11 and thesecond wiring 17 are connected to each other. In addition, the self-formedbarrier film 12 b on thecap layer 3 b is removed through the CMP process. - Note that, at this time, by using an acidic CMP slurry, the removal of the unreacted
metallic oxide film 16, and the flattening of thewiring formation film 15 can be continuously performed through the CMP process. - Next, as shown in
FIG. 2F , thefirst barrier film 4 b is formed on thesecond wiring 17 and thecap layer 3 b. Moreover, while not illustrated in the figure, the insulating film and the like are formed as the upper layers, thereby forming thesemiconductor device 1. - According to the second embodiment, although the different fabricating method is utilized, the same effects as those of the first embodiment can be obtained.
- A third embodiment is different from the second embodiment in that the unreacted
metallic oxide film 16 is precipitated after the CMP is performed for thewiring formation film 15 until the surface of thecap layer 3 b is exposed. It is noted that the same respects, such as the constitutions and the like of other portions, as those in the second embodiment are omitted here in their descriptions for the sake of simplicity. -
FIGS. 3A to 3D are respectively cross sectional views showing processes for fabricating a wiring structure in a semiconductor device according to the third embodiment. - Firstly, there is performed up to the process for forming the self-formed
barrier film 12 to diffuse the unreacted predetermined metallic elements α into thewiring formation film 15 as shown inFIG. 2B in the second embodiment. - Next, as shown in
FIG. 3A , the CMP is performed with thecap layer 3 b as the stopper to flatten thewiring formation film 15 until thecap layer 3 b is exposed. In addition, the self-formedbarrier film 12 b on thecap layer 3 b is removed through the CMP process. - Next, as shown in
FIG. 3B , the heat treatment, for example, is performed at 200 to 400° C. for 5 to 60 minutes in the oxidation ambient atmosphere, thereby precipitating the unreactedmetallic oxide film 16 on the surface of thewiring formation film 15. At this time, since the self-formedbarrier film 12 b contains therein the predetermined metallic elements α and oxygen constituting the unreactedmetallic oxide film 16, the reaction for formation of the unreactedmetallic oxide film 16 progresses to the self-formedbarrier film 12 b. As a result, a peripheral portion of the unreactedmetallic oxide film 16 has a shape of extending downward along thecap layer 3 b. - When the unreacted
metallic oxide film 16 is made of MnOx, and the self-formedbarrier film 12 b is made of MnSixOy, the reaction for formation of MnOx progresses to the inside of the self-formedbarrier film 12 b because the self-formedbarrier film 12 b contains therein Mn and O. As a result, thesecond wiring 17 having a rounded shape in its upper surface end portion, and the via 18 through which thefirst wiring 11 and thesecond wiring 17 are connected to each other are formed. - Next, as shown in
FIG. 3C , the unreactedmetallic oxide film 16 is removed by using an acid such as a hydrochloric acid. - Next, as shown in
FIG. 3D , thefirst barrier film 4 b is formed on thesecond wiring 17 and thecap layer 3 b. Moreover, while not illustrated in the figure, the insulating film and the like are formed as the upper layers, thereby forming thesemiconductor device 1. - It is noted that the unreacted
metallic oxide film 16 may not be removed because it is the insulating film. In this case, thefirst barrier film 4 b is formed on the unreactedmetallic oxide film 16. - According to the third embodiment, formation of the
second wiring 17 having the rounded shape in its upper surface end portion makes it possible to suppress concentration of an electric field on the upper surface end portion. In addition, the upper surface of thesecond wiring 17 is made different in height from that of thecap layer 3 b, thereby making it possible to reduce a leakage current. - It is noted that the
first wiring 11 can be formed by utilizing the same method as that for thesecond wiring 17. -
FIG. 4 is a graph representing leakage current characteristics of the wiring structure in the semiconductor device fabricated by utilizing the method of the third embodiment. In the figure, a lower curve represents the characteristics of the wiring having the rounded shape in its upper surface end portion fabricated by utilizing the method of the third embodiment, while an upper curve represents the characteristics of the conventional wiring having no rounded shape in its upper surface end portion. Each of the upper and lower curves represents a relationship between a magnitude of an electric field (plotted on an axis of ordinate inFIG. 4 ) occurring across the adjacent two wirings, and a magnitude of a leakage current (plotted on an axis of abscissa inFIG. 4 ). - As apparent from
FIG. 4 , the conventional wiring having no rounded shape in its upper surface end portion shows the characteristics in which a breakdown is generated when the magnitude of the electric field exceeds about 3.8 MV/cm, so that the magnitude of the leakage current rises suddenly. On the other hand, the wiring having the rounded shape in its upper surface end portion shows the characteristics in which the magnitudes of the leakage currents are generally smaller than those in the conventional wiring structure, and also no breakdown is generated within this measurement range. - A fourth embodiment is different from the third embodiment in that the unreacted
metallic oxide film 16 is precipitated after thefirst barrier film 4 b is formed on thewiring formation film 15. It is noted that the same respects, such as the constitutions and the like of other portions, as those in the third embodiment are omitted herein in their descriptions for the sake of simplicity. -
FIGS. 5A and 5B are respectively cross sectional views showing processes for fabricating a wiring structure in a semiconductor device according to the fourth embodiment. - Firstly, there is performed up to the process for performing the CMP for the
wiring formation film 15 with thecap layer 3 b as the stopper as shown inFIG. 3A in the third embodiment. - Next, as shown in
FIG. 5A , thefirst barrier film 4 b is formed on thewiring formation film 15 and thecap layer 3 b. - Next, as shown in
FIG. 5B , the heat treatment, for example, is performed at 200 to 400° C. for 5 to 60 minutes in the oxidation ambient atmosphere, thereby precipitating the unreactedmetallic oxide film 16 on the surface of thewiring formation film 15. At this time, since the self-formedbarrier film 12 b contains therein the predetermined metallic elements α and oxygen constituting the unreactedmetallic oxide film 16, the reaction for formation of the unreactedmetallic oxide film 16 progresses to the self-formedbarrier film 12 b. As a result, the peripheral portion of the unreactedmetallic oxide film 16 has a shape of extending downward along the cap layer 3. Moreover, while not illustrated in the figure, the insulating film and the like are formed as the upper layers, thereby forming thesemiconductor device 1. - According to the fourth embodiment, although a different fabricating method is utilized, the same effects as those of the third embodiment can be obtained.
- A fifth embodiment is different from the first or second embodiment in that the self-formed
barrier film 12 is formed even on the upper surface of thesecond wiring 17. It is noted that the same respects, such as the constitutions and the like of other portions, as those in the first or second embodiment are omitted here in their descriptions for the sake of simplicity. -
FIG. 6 is a cross sectional view showing a process for fabricating a wiring structure in a semiconductor device according to a fifth embodiment. - Firstly, there is performed up to the process for forming the
first barrier film 4 b on thesecond wiring 17 and thecap layer 3 b as shown inFIG. 1H in the first embodiment or as shown inFIG. 2C in the second embodiment. However, in this embodiment, it is assumed that a quantity of predetermined metallic element α enough to permit the self-formedbarrier film 12 b to be formed on the upper surface of thesecond wiring 17 remains in thesecond wiring 17. - Next, as shown in
FIG. 6 , a heat treatment, for example, is performed at 200 to 400° C. for 5 to 60 minutes, preferably, in a reduction ambient atmosphere, which results in that a reaction occurs between thesecond wiring 17 and thefirst barrier film 4 b on thesecond wiring 17, thereby forming the self-formedbarrier film 12 b on the upper surface of thesecond wiring 17. - When the self-formed
barrier film 12 b is made of MnSixOy, the self-formedbarrier film 12 b is formed on the upper surface of thesecond wiring 17 from Mn remaining in thesecond wiring 17, and Si and O contained in thefirst barrier film 4 b. - Moreover, while not illustrated in the figure, the insulating film and the like are formed as the upper layers, thereby forming the
semiconductor device 1. - According to the fifth embodiment, forming the self-formed
barrier film 12 b even on the upper surface of thesecond wiring 17 makes it possible to further reduce the leakage current as compared with that in the first or second embodiment. - It is noted that the
first wiring 11 can be formed by utilizing the same method as that for thesecond wiring 17. - A sixth embodiment is different from the third embodiment in that the self-formed
barrier film 12 b is formed even on the upper surface of thesecond wiring 17. It is noted that the same respects, such as the constitutions and the like of other portions, as those in the third embodiment are omitted here in their descriptions for the sake of simplicity. -
FIG. 7 is a cross sectional view showing a process for fabricating a wiring structure in a semiconductor device according to the sixth embodiment. - Firstly, there is performed up to the process for forming the
first barrier film 4 b on thesecond wiring 17 and thecap layer 3 b as shown inFIG. 3D in the third embodiment. However, in this embodiment, it is assumed that the quantity of predetermined metallic element α enough to permit the self-formedbarrier film 12 b to be formed on the upper surface of thesecond wiring 17 remains in thesecond wiring 17. - Next, as shown in
FIG. 7 , the heat treatment, for example, is performed at 200 to 400° C. for 5 to 60 minutes, preferably, in the reduction ambient atmosphere, which results in that the reaction occurs between thesecond wiring 17 and thefirst barrier film 4 b on thesecond wiring 17, thereby forming the self-formedbarrier film 12 b on the upper surface of thesecond wiring 17. - When the self-formed
barrier film 12 b is made of MnSixOy, the self-formedbarrier film 12 b is formed on the upper surface of thesecond wiring 17 from Mn remaining in thesecond wiring 17, and Si and O contained in thefirst barrier film 4 b. - Moreover, while not illustrated in the figure, the insulating film and the like are formed as the upper layers, thereby forming the
semiconductor device 1. - According to the sixth embodiment, forming the self-formed
barrier film 12 b even on the upper surface of thesecond wiring 17 makes it possible to further reduce the leakage current as compared with that in the third embodiment. - It is noted that the
first wiring 11 can be formed by utilizing the same method as that for thesecond wiring 17. - A seventh embodiment is different from the first or second embodiment in that the self-formed
barrier film 12 b is formed even on the upper surface of thesecond wiring 17. It is noted that the same respects, such as the constitutions and the like of other portions, as those in the first or second embodiment are omitted here in their descriptions for the sake of simplicity. -
FIGS. 8A and 8B are respectively cross sectional views showing processes for fabricating a wiring structure in a semiconductor device according to the seventh embodiment. - Firstly, there is performed up to the process for performing the CMP with the
cap layer 3 b as the stopper, thereby flattening thewiring formation film 15 until thecap layer 3 b is exposed as shown inFIG. 1G in the first embodiment or as shown inFIG. 2E in the second embodiment. However, in this embodiment, it is assumed that the quantity of predetermined metallic element α enough to permit the self-formedbarrier film 12 b to be formed on the upper surface of thesecond wiring 17. - Next, as shown in
FIG. 8A , after plasma processing using ammonia or the like is executed under a reduced pressure to remove a copper oxide film (not shown) on the upper surface of thesecond wiring 17, the upper surface of thesecond wiring 17 is exposed to each of a reducing gas and a silane gas. As a result, Si penetrates into only an uppermost portion of the upper surface of thesecond wiring 17. Thus, the heat treatment, for example, is performed at 200 to 400° C. for 5 to 60 minutes in the oxidation ambient atmosphere, thereby forming the self-formedbarrier film 12 b on the upper surface of thesecond wiring 17. - When the self-formed
barrier film 12 b is made of MnSixOy, the self-formedbarrier film 12 b is formed on the upper surface of thesecond wiring 17 from Mn and Si contained in thesecond wiring 17, and O contained in the oxidation ambient atmosphere. - Next, as shown in
FIG. 8B , thefirst barrier film 4 b is formed on thesecond wiring 17 and thecap layer 3 b. Moreover, while not illustrated in the figure, the insulating film and the like are formed as the upper layers, thereby forming thesemiconductor device 1. - According to the seventh embodiment, forming the self-formed
barrier film 12 b even on the upper surface of thesecond wiring 17 makes it possible to further reduce the leakage current as compared with that in the first or second embodiment. - It is noted that the
first wiring 11 can be formed by utilizing the same method as that for thesecond wiring 17. - An eighth embodiment is different from the third embodiment in that the self-formed
barrier film 12 b is formed even on the upper surface of thesecond wiring 17. It is noted that the same respects, such as the constitutions and the like of other portions, as those in the third embodiment are omitted here in their descriptions for the sake of simplicity. -
FIGS. 9A and 9B are respectively cross sectional views showing processes for fabricating a wiring structure in a semiconductor device according to the eighth embodiment. - Firstly, there is performed up to the process for removing the unreacted
metallic oxide film 16 as shown inFIG. 3C in the third embodiment. However, in this embodiment, it is assumed that the quantity of predetermined metallic element a enough to permit the self-formedbarrier film 12 b to be formed on the upper surface of thesecond wiring 17 remains in thesecond wiring 17. - Next, as shown in
FIG. 9A , after the plasma processing using ammonia or the like is executed under the reduced pressure to remove the copper oxide film (not shown) on the upper surface of thesecond wiring 17, the upper surface of thesecond wiring 17 is exposed to each of the reducing gas and the silane gas. As a result, Si penetrates into only the uppermost portion of the upper surface of thesecond wiring 17. Thus, the heat treatment, for example, is performed at 200 to 400° C. for 5 to 60 minutes in the oxidation ambient atmosphere, thereby forming the self-formedbarrier film 12 b on the upper surface of thesecond wiring 17. - When the self-formed
barrier film 12 b is made of MnSixOy, the self-formedbarrier film 12 b is formed on the upper surface of thesecond wiring 17 from Mn and Si contained in thesecond wiring 17, and O contained in the oxidation ambient atmosphere. - Next, as shown in
FIG. 9B , thefirst barrier film 4 b is formed on the self-formedbarrier film 12 b on thesecond wiring 17, and thecap layer 3 b. Moreover, while not illustrated in the figure, the insulating film and the like are formed as the upper layers, thereby forming the semiconductor device. - According to the eighth embodiment, forming the self-formed
barrier film 12 b even on the upper surface of thesecond wiring 17 makes it possible to further reduce the leakage current as compared with that in the third embodiment. - It is noted that the
first wiring 11 can be formed by utilizing the same method as that for thesecond wiring 17. - It should be noted that the present invention is not intended to be limited to the embodiments described above, and the various changes can be implemented by those skilled in the art without departing from the gist of the invention. For example, the present invention can also be applied to any of wiring structures other than the dual damascene wiring structure as shown in each of the embodiments described above. For example, the present invention may also be applied to a wiring structure in which wirings/vias covered with the self-formed barrier film are individually formed.
- In addition, the constituent elements of the above-mentioned embodiments can be arbitrarily combined with one another without departing from the gist of the invention.
Claims (7)
1. A method of fabricating a semiconductor device, comprising:
forming a precursor film containing a predetermined metallic element on a surface of a recess portion formed in an insulating film on a semiconductor substrate;
forming a wiring formation film on the precursor film;
performing a heat treatment to cause the precursor film and the insulating film to react with each other, thereby forming a self-formed barrier film containing a compound which contains the predetermined metallic element and a constituent element of the insulating film, as a basic constituent in a boundary between the precursor film and the insulating film, and diffusing an unreacted predetermined metallic element into the wiring formation film;
reducing a thickness of the wiring formation film by removing a part of the wiring formation film after the self-formed barrier film is formed and the unreacted predetermined metallic element is diffused into the wiring formation film;
performing a heat treatment in an oxidation ambient atmosphere, after the thickness of the wiring formation film is reduced, to cause the predetermined metallic element diffused into the wiring formation film to react with oxygen in the oxidation ambient atmosphere, thereby precipitating an unreacted metallic oxide film including the predetermined metallic element to a surface of the wiring formation film; and
flattening the wiring formation film, until a portion of the insulating film located outside the recess portion is exposed, after the unreacted metallic oxide film is removed.
2. The method of fabricating a semiconductor device according to claim 1 , wherein the thickness of the wiring formation film is reduced so that the thickness from a top surface of a portion of the insulating film located outside the recess portion falls in a range of 10 to 110 nm.
3. The method of fabricating a semiconductor device according to claim 1 , wherein a thickness of the wiring formation film is reduced to at least a middle of the thickness through flattening processing.
4. The method of fabricating a semiconductor device according to claim 1 , wherein the predetermined metallic element is one of Mn, V, Zn, Nb, Zr, Cr, Y, Tc and Re.
5. The method of fabricating a semiconductor device according to claim 1 , wherein the wiring formation film is a Cu film, the precursor film is made of an alloy containing the predetermined metallic element and Cu, the insulating film contains Si, and the self-formed barrier film is made of an oxide containing the predetermined metallic element and Si.
6. The method of fabricating a semiconductor device according to claim 1 , further comprising:
forming a barrier film on the wiring formation film after the wiring formation film is flattened; and
performing a heat treatment to cause the barrier film and the wiring formation film to react with each other, thereby forming the self-formed barrier film containing the compound containing the predetermined metallic element and a constituent element of the barrier film as the basic constituent in the boundary between the barrier film and the wiring formation film.
7. The method of fabricating a semiconductor device according to claim 1 , further comprising:
exposing the wiring formation film to at least a silane gas after the wiring formation film is flattened; and
performing a heat treatment in an oxidation ambient atmosphere to cause the wiring formation film exposed to the silane gas to react with oxygen in the oxidation ambient atmosphere, thereby forming the self-formed barrier film containing the compound containing the predetermined metallic element and Si as the basic constituent on an upper surface of the wiring formation film.
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US12/983,700 US20110097890A1 (en) | 2006-12-18 | 2011-01-03 | Method of fabricating semiconductor device |
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JP2006340506A JP5010265B2 (en) | 2006-12-18 | 2006-12-18 | Manufacturing method of semiconductor device |
JP2006-340506 | 2006-12-18 | ||
US11/956,868 US7888253B2 (en) | 2006-12-18 | 2007-12-14 | Method of fabricating semiconductor device |
US12/983,700 US20110097890A1 (en) | 2006-12-18 | 2011-01-03 | Method of fabricating semiconductor device |
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US11/956,868 Division US7888253B2 (en) | 2006-12-18 | 2007-12-14 | Method of fabricating semiconductor device |
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US12/983,700 Abandoned US20110097890A1 (en) | 2006-12-18 | 2011-01-03 | Method of fabricating semiconductor device |
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Families Citing this family (19)
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US8102051B2 (en) * | 2007-06-22 | 2012-01-24 | Rohm Co., Ltd. | Semiconductor device having an electrode and method for manufacturing the same |
JP2010073736A (en) * | 2008-09-16 | 2010-04-02 | Rohm Co Ltd | Method of manufacturing semiconductor device |
JP2010080606A (en) * | 2008-09-25 | 2010-04-08 | Rohm Co Ltd | Method of manufacturing semiconductor apparatus |
JP2010040771A (en) * | 2008-08-05 | 2010-02-18 | Rohm Co Ltd | Method of manufacturing semiconductor device |
JP2010040772A (en) * | 2008-08-05 | 2010-02-18 | Rohm Co Ltd | Method of manufacturing semiconductor device |
JP5501586B2 (en) * | 2008-08-22 | 2014-05-21 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
US8258626B2 (en) | 2008-09-16 | 2012-09-04 | Advanced Interconnect Materials, Llc | Copper interconnection, method for forming copper interconnection structure, and semiconductor device |
US8168528B2 (en) * | 2009-06-18 | 2012-05-01 | Kabushiki Kaisha Toshiba | Restoration method using metal for better CD controllability and Cu filing |
JP5507909B2 (en) * | 2009-07-14 | 2014-05-28 | 東京エレクトロン株式会社 | Deposition method |
US8531033B2 (en) | 2009-09-07 | 2013-09-10 | Advanced Interconnect Materials, Llc | Contact plug structure, semiconductor device, and method for forming contact plug |
JP2011086837A (en) * | 2009-10-16 | 2011-04-28 | Tohoku Univ | Semiconductor device and method of forming the same |
JP2012253148A (en) * | 2011-06-01 | 2012-12-20 | Toshiba Corp | Semiconductor device and manufacturing method of the same |
US8492897B2 (en) | 2011-09-14 | 2013-07-23 | International Business Machines Corporation | Microstructure modification in copper interconnect structures |
US8916469B2 (en) * | 2013-03-12 | 2014-12-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating copper damascene |
US9343400B2 (en) * | 2013-03-13 | 2016-05-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dual damascene gap filling process |
US9224686B1 (en) * | 2014-09-10 | 2015-12-29 | International Business Machines Corporation | Single damascene interconnect structure |
KR20160116618A (en) * | 2015-03-30 | 2016-10-10 | 삼성전자주식회사 | A semiconductor device and method of manufacturing the semiconductor device |
US9842805B2 (en) | 2015-09-24 | 2017-12-12 | International Business Machines Corporation | Drive-in Mn before copper plating |
US11133216B2 (en) | 2018-06-01 | 2021-09-28 | International Business Machines Corporation | Interconnect structure |
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JP5010265B2 (en) | 2012-08-29 |
JP2008153472A (en) | 2008-07-03 |
US7888253B2 (en) | 2011-02-15 |
US20080146015A1 (en) | 2008-06-19 |
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