US20110103134A1

US20110103134A1 - Resistance random access memory having common source line

Info

Publication number: US20110103134A1
Application number: US13/004,251
Authority: US
Inventors: Hyung-Rok Oh; Sang-beom Kang; Joon-Min Park; Woo-Yeong Cho
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2007-01-23
Filing date: 2011-01-11
Publication date: 2011-05-05
Also published as: KR20080069336A; US7903448B2; KR100855585B1; US20080175036A1

Abstract

A method writes data to a resistance random access memory (RRAM) memory cell through first and second write paths, and includes; applying a positive source voltage to a selected source line, applying a word line drive voltage to a selected word line, and applying a voltage at least twice the level of the positive source voltage to a selected bit line via the first write path when writing data having the first state in the memory cell, and applying a ground voltage to the selected bit line via the second write path when writing data having the second state in the memory cell.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a divisional of application Ser. No. 11/964,142 filed on Dec. 26, 2007, which is incorporated herein by reference in its entirety. This application claims priority under 35 U.S.C. §119 to Korean Patent Application 10-2007-0006916 filed on Jan. 23, 2007, the entire contents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention
Embodiments of the invention relate to variable resistance semiconductor memory devices. More particularly, embodiments of the invention relate to a resistance random access memory (RRAM) having a common source line and an associated data access method.
2. Discussion of Related Art
Next generation nonvolatile memory devices are being developed for use in portable consumer products to provide high capacity and low power consumption. Next-generation memory devices include, for example, PRAMs (Phase change Random Access Memory) utilizing phase-change material that can be switched between two states, RRAMs(Resistance Random Access Memory) employing material having a variable resistance characteristic of complex metal oxides, and MRAMs (Magnetic Random Access Memory) having ferromagnetic material. A common characteristic of the various materials used to form next generation memory devices is that resistance values vary by the supplied current or voltage. In addition, the resistance value is maintained in these devices even when no current or voltage is supplied demonstrating the nonvolatile memory characteristic which obviates the need for refresh operations. In these devices, a memory cell is comprised of one switching device and one variable resistor. The variable resistor is connected between a bit line and the switching device. The switching device, which is constructed of an access transistor or diode, is typically coupled with the variable resistance and a word line.
A PRAM memory device may replace NOR flash memory typically utilized in mobile phones. In PRAMs, a variable resistor is formed of a chalcogenide alloy of germanium, antimony and tellurium (Ge—Sb—Te) called GST and the resistance of the material is changed by a change in temperature. When the variable resistor is formed of complex metal oxides disposed between top and bottom electrodes the device is most likely a RRAM. When a variable resistor is formed of an insulator disposed between top and bottom magnetic electrodes, the device may be an MRAM.
A data write operation in a PRAM is performed by applying voltage pulses having the same polarity with different amplitudes to a memory cell at different times. A phase change memory device produces a switch based on a setting and resetting temperature which causes the device to be sensitive to a change in neighboring temperature. On the other hand, in an RRAM device, material which has a characteristic resistance value is changed by the applied voltage or current to store information in a memory layer. Thus, two electrodes are provided with the memory layer and voltage or current is applied to the two electrodes. This simple structure reduces the size of the memory device.
FIG. 1 is a schematic diagram illustrating a conventional memory cell MC of an RRAM. Memory cell MC constitutes one cell having an access transistor AT and a resistive memory device SE. The resistive memory device SE may be formed of a complex metal oxide VR disposed between a top electrode TE and a bottom electrode BE. The complex metal oxide may be chrome doped SrZrO3 or a thin film of polycrystal PrCaMnO3 material. The gate of access transistor AT is connected to word line WL, its source is connected to source line SL, and its drain is connected to bottom electrode BE of resistive memory device SE. Bit line BL is connected to top electrode TE. When data of a first state is written to memory cell MC current is applied in a first direction D1. When data of a second state is written to the memory cell MC is applied in a second direction D2. The RRAM is also called a bi-directional RRAM in that writing data of a first and second state is performed in mutually opposite directions. The first direction D1 indicates a current path where a positive voltage applied from the bit line reaches source line SL via memory cell MC, and may be referred to as a first write path. The second direction D2 indicates a reverse current path (second write path) where a voltage applied from source line SL reaches bit line BL via memory cell MC. When writing data through the first write path, the resistive memory device SE has a high resistance value. When writing data through the second write path, the resistive memory device SE has a resistance value which is lower by hundreds or thousands of times as compared with the resistance value associated with the first write path.
Data can be read from memory cell MC via the use of a sense amplifier, coupled to bit line BL that senses current flowing through the bit line. The through-current varies depending on whether the memory cell is under a set state ‘1’ or under a reset state ‘0’. For example, the amount of through-current may be small because of a high resistance when the memory cell has a ‘set’ state and may be relatively large because of a low resistance when the memory cell is in a ‘reset’ state. Accordingly, the sense amplifier compares the through-current to the reference current to read data stored in the memory cell MC.
FIG. 2 illustrates a sectional view of a plurality of memory cells of FIG. 1 fabricated on a P substrate and its corresponding schematic circuit. A PCMO film 1 corresponds to VR and the platinum (Pt) layer forms the top electrode TE and bottom electrode BE. NMOS transistor 2, which is formed on a P-type substrate and whose gate is coupled to a word line, corresponds to access transistor AT. Fabrication details of the memory cells shown in FIG. 2 are disclosed in U.S. Pat. No. 7,057,922. The plurality of memory cells shown constitute a memory cell array having a matrix of rows and columns (as shown in FIGS. 3 and 4) to have a high density memory capacity.
FIGS. 3 and 4 illustrate conventional memory cell array configurations. The cell array of FIG. 3 (the details of which are disclosed in U.S. Pat. No. 7,045,840) includes a source line disposed in the direction of a word line. However, different source lines are correspondingly disposed for memory cells coupled with different word lines. The cell array of FIG. 4 (the details of which are disclosed in U.S. Pat. No. 7,016,222) includes a source line disposed in the direction of the bit line which is perpendicular to a word line. The memory cell arrays as illustrated in FIGS. 3 and 4 are RRAM type devices where the layout of word lines and bit lines occupy valuable chip area. By reducing the number of source lines in the RRAM device, the utilized chip area would correspondingly be reduced.
In a write operation of FIGS. 3 and 4, it is difficult to keep a source line potential and a bit line potential within a positive voltage level range. For example, when writing data 1, a ground voltage is applied to the source line and a positive write voltage is applied to the bit line. When writing data 0, a ground voltage is applied to the source line and a negative write voltage is applied to the bit line. When writing data 0, a negative voltage generated from a negative voltage generator must be applied to the selected bit line. This requires installing a negative voltage generator within the memory chip. Accordingly, there is a need for an advanced layout structure of a RRAM memory cell array and associated data access method.

SUMMARY OF THE INVENTION

Exemplary embodiments of the present invention are directed to a resistance random access memory (RRAM) and an associated data access method in which a write operation of writing data having a first state and a second state to a selected memory cell is performed through first and second write paths formed in mutually opposite directions. In an exemplary embodiment, the (RRAM) includes a plurality of word lines; a plurality of bit lines; a memory cell array having a plurality of memory cells which are disposed at the intersections of the word and bit lines to form a matrix of rows and columns and each have an access transistor and a resistive memory device; and a plurality of source lines each disposed between every two word lines and in the same direction as the word lines, and each connected to source terminals of corresponding access transistors having gate terminals connected to corresponding two word lines. In the memory device, when a positive voltage is applied to a selected source line, the corresponding access transistors may receive the positive voltage via the source terminals. In this manner, the use of common source lines reduces the occupied chip area.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic of a circuit illustrating a unit memory cell of an RRAM according to conventional art;

FIG. 2 illustrates a sectional view of a plurality of memory cells of FIG. 1 fabricated on a substrate and its corresponding equivalent circuit;

FIG. 3 illustrates a memory cell array according to an example of conventional art;

FIG. 4 illustrates a memory cell array according to another example of the conventional art;

FIG. 5 illustrates a memory cell array according to the present invention;

FIG. 6 is a timing diagram of applied drive voltages related to the operation of the memory cell array of FIG. 5; and

FIG. 7 is a block diagram illustrating a supply structure of source voltage applied to a memory cell block according to the present invention.

DESCRIPTION OF EMBODIMENTS

The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention, however, may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, like numbers refer to like elements throughout.
FIG. 5 illustrates a memory cell array 100 of bidirectional resistance random access memory. Bit lines BL_0 to BL_m are coupled to write driver and sense amplifier 200. Bit lines BL_0 to BL_m are disposed perpendicularly to word lines WL_0 to WL_n. Source lines SL_0 to SL(n−1) are each disposed between adjacent word lines WL_0 to WL_n. First and second write paths D1 and D2 are used when writing data of first and second states to a selected memory cell, for example, memory cell MC1 of memory array 100. Exemplary memory cell MC1 is comprised of access transistor AT₁and resistive memory device SE₁. The memory cell array 100 comprises a plurality of memory cells disposed in a matrix of rows and columns located at each intersection of word lines WL_0 to WL_n and corresponding bit lines BL_0 to BL_m. The source lines SL_0 to SL_(n−1) are disposed between the word lines in the same direction as the respective word line. For example, source line SL_0 is disposed between word lines WL_0 and WL_1 in the same direction as the word lines.
A first group of access transistors disposed above source line SL_0 have their respective source terminals coupled to source line SL_0 and their respective gate terminals coupled to word line WL_0. A second group of access transistors disposed below source line SL_0 have their respective gates coupled to adjacent word line WL_1 and their respective source terminals coupled in common to source line SL_0. Thus, the source terminals of the first and second group of access transistors are coupled to common source line SL_0. When a positive source voltage is applied through corresponding source line SL_0 in a write operating mode, the positive source voltage is applied to the source terminals of the first group of access transistors and the source terminals of the second group of access transistors. The source line shared structure of the access transistors reduces the number of source lines thereby reducing associated chip real estate occupied by the memory device. The source line potential and the bit line potential can be determined within a positive voltage level range by the operating conditions applied in the write operating mode. In writing data having different logic states to a memory cell sharing the same source line, the source line is configured to maintain a constant voltage which provides random write capability.
FIG. 6 illustrates a timing diagram of voltage waveforms each applied to a selected source line SL, word line WL and bit line BL in a read operating mode, write operating mode and standby operating mode. Time interval T1 indicates a read operating mode. Time interval T2 indicates a set operating mode with a time interval T3 designating a reset operating mode in a write operating mode. A time interval T4 denotes a standby operating mode. Time intervals T2 and T3 may correspond to program operating sections of a general nonvolatile semiconductor memory such as a flash memory. In a write operating mode, first write path D1 (shown in FIG. 5) is used to write data ‘1’ to a selected memory cell. As shown in time interval T2, a positive source voltage Vw is applied to the selected source line SL, a word line drive voltage Vw+Vth is applied to the selected word line WL, and voltage 2Vw which is about twice the positive source voltage is applied to selected bit line BL. Positive voltage Vw having a forward direction corresponding to direction D1 is applied to memory cell MC and a resistance value of the memory cell is changed to a high resistance. Consequently, when the write operation is obtained through first write path D1 by the applied voltage condition illustrated at time interval T2, data having a first state ‘1’ is written to the selected memory cell.
In the write operating mode, second write path D2 (shown in FIG. 5) is used to write data ‘0’ to a selected memory cell. In this case, as shown in the time interval T3, positive source voltage Vw is maintained in the selected source line SL, word line drive voltage Vw+Vth is applied to the selected word line WL, and ground voltage (i.e., 0V) is applied to the selected bit line BL. A negative voltage −Vw having a backward direction D2 is applied to memory cell MC and a resistance value of the memory cell is again changed to a low resistance. Consequently, when the write operation is obtained through the second write path D2 by the applied voltage condition as illustrated at time interval T3, data having a second state ‘0’ is written to the selected memory cell. Accordingly, in writing data ‘0’ the source line voltage and the word line voltage are maintained equally when writing data ‘1’ and the voltage applied to the bit line is determined by 2Vw. A negative voltage value is not applied to the other lines including the bit line obviating the need for a negative voltage generator installed in the memory chip. Additionally, as the source line voltage and the word line voltage are maintained equally when writing data ‘1’ and ‘0’, a random write operation to an optional memory cell can be performed.
In the standby operating mode shown at time interval T4, the voltage of source line SL, word line WL and bit line BL is maintained at ground (i.e., 0V.) In the read operating mode as shown at time interval T1, ground voltage is applied to the selected source line SL, word line drive voltage Vcc is applied to the selected word line WL, and clamping voltage VBL is applied to the selected bit line BL. A sense amplifier 200 connected to the selected bit line BL senses a through-current flowing through the bit line. When the selected memory cell is under a set state ‘1’, the through-current is smaller than the reference current because of the high resistance value of the memory cell and the read data is output as a logic ‘1’. Conversely, when the memory cell is in a reset state, more through-current flows because of the low resistance value of the memory cell and a logic ‘0’ is output as read data.
FIG. 7 is a block diagram illustrating a structure to supply greater source voltage to a memory cell block. Source line drivers 300 and 310 drive a source line voltage to cell block 100. A Y-path and bit line driver 220 is connected to the bit line of cell block 100 in a column direction. Power switch 400 supplies voltage Vw to source line driver 300. Power switch 410 supplies voltage Vw to source line driver 310. In a write operation, only the power switch (400 or 410) of a selected cell block is enabled and the source line voltage is applied to only the selected cell block. In this manner, the power line layout forming the network structure for cell block 100 solves the voltage supply delay and weakness problems experienced when voltage is supplied to an area of memory cell block 100 which is located far from the power source.
As described above, chip area occupation can be reduced by a source line sharing structure in a resistance random access memory. The source line potential and bit line potential can be determined within a positive voltage level range in a write operating mode. In addition, when writing data having different logic levels to a memory cell sharing a source line, the source line is maintained at a constant voltage to enable a random write mode to the memory device. This obviates the need for a negative voltage generator to produce a write operation current, thereby enabling a high speed write operation through a random write operation.
Although the present invention has been described in connection with the embodiment of the present invention illustrated in the accompanying drawings, it is not limited thereto. It will be apparent to those skilled in the art that various substitutions, modifications and changes may be made thereto without departing from the scope and spirit of the invention.

Claims

1. A method writing data having a first state and a second state to a selected memory cell of a resistance random access memory (RRAM) through first and second write paths formed in mutually opposite directions, the RRAM having a plurality of word lines, a plurality of bit lines, a memory cell array having a plurality of memory cells disposed in a matrix, each having an access transistor and a resistive memory device, and a plurality of source lines disposed between two word lines and extending in a same direction as the word lines, and being connected to a source terminal of a corresponding access transistor having gate terminals connected to corresponding two word lines, the method comprising:

applying a positive source voltage to a selected source line;

applying a word line drive voltage to a selected word line among the plurality of word lines; and

applying a voltage at least twice the level of the positive source voltage to a selected bit line among the plurality of bit lines via the first write path when writing data having the first state in the selected memory cell, and applying a ground voltage to the selected bit line via the second write path when writing data having the second state in the selected memory cell.

2. The method of claim 1, wherein when data having the first state has a logic level ‘1’ and data having the second state has a logic level ‘0’.

3. The method of claim 1, wherein the resistive memory device comprises top and bottom electrodes, and the data is written to the selected memory cell by changing a resistance value associated with the resistive memory device using a voltage pulse flowing through the top and bottom electrodes.

4. The method of claim 1, wherein the memory device comprises a plurality of the source lines defining a source line shared structure of a memory cell block of the memory cell array.

5. The method of claim 1, wherein the resistive memory device further comprises a chrome-doped SrZrO3 material disposed between a top and bottom electrodes.

6. The method of claim 1, wherein the resistive memory device further comprises a thin film of polycrystalline PrCaMnO3 material disposed between a top and bottom electrodes.