US20110134217A1

US20110134217A1 - Method and system for scaling 3d video

Info

Publication number: US20110134217A1
Application number: US12/963,014
Authority: US
Inventors: Darren Neuman; Jason Herrick; Qinghua Zhao; Christopher Payson
Original assignee: Broadcom Corp
Current assignee: Avago Technologies International Sales Pte Ltd
Priority date: 2009-12-08
Filing date: 2010-12-08
Publication date: 2011-06-09
Also published as: US20110134218A1; EP2462748A1; EP2462748A4; US9307223B2; CN102474632A; US20110134216A1; US20110134211A1; US9137513B2; WO2011072016A1; US20150341613A1; US8947503B2; US20110134212A1

Abstract

A method and system are provided in which an integrated circuit (IC) comprises multiple devices that may be selectively interconnected to route and process 3D video data. The IC may be operable to determine whether to scale the 3D video data before the 3D video data is captured to memory or after the captured 3D video data is retrieved from memory, and selectively interconnect one or more of the devices based on the determination. The selective interconnection may be based on input and output formats of the 3D video data, and on a scaling factor. The input format may be a left-and-right (L/R) format or an over-and-under (O/U) format. Similarly, the output format may be a L/R format or an O/U format. The selective interconnection may be based on input and output pixel rates of the 3D video data. Moreover, the selective interconnection may be determined on a picture-by-picture basis.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE

This application makes reference to, claims priority to, and claims the benefit of:
U.S. Provisional Patent Application Ser. No. 61/267,729 (Attorney Docket No. 20428US01) filed on Dec. 8, 2009;
U.S. Provisional Patent Application Ser. No. 61/296,851 (Attorney Docket No. 22866US01) filed on Jan. 20, 2010; and
U.S. Provisional Patent Application Ser. No. 61/330,456 (Attorney Docket No. 23028US01) filed on May 3, 2010.
This application also makes reference to:
U.S. Provisional Patent Application Ser. No. ______ (Attorney Docket No. 20428U502) filed on Dec. 8, 2010;
U.S. Provisional Patent Application Ser. No. ______ (Attorney Docket No. 23438U502) filed on Dec. 8, 2010;
U.S. Provisional Patent Application Ser. No. ______ (Attorney Docket No. 23439U502) filed on Dec. 8, 2010; and
U.S. Provisional Patent Application Ser. No. ______ (Attorney Docket No. 23440U502) filed on Dec. 8, 2010.
Each of the above referenced applications is hereby incorporated herein by reference in its entirety.

FIELD OF THE INVENTION

Certain embodiments of the invention relate to processing of three-dimensional (3D) video. More specifically, certain embodiments of the invention relate to a method and system for scaling 3D video.

BACKGROUND OF THE INVENTION

The availability and access to 3D video content continues to grow. Such growth has brought about challenges regarding the handling of 3D video content from different types of sources and/or the reproduction of 3D video content on different types of displays.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.

BRIEF SUMMARY OF THE INVENTION

A system and/or method for scaling 3D video, as set forth more completely in the claims.
Various advantages, aspects and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a block diagram that illustrates a system-on-chip that is operable to handle 3D video data scaling, in accordance with an embodiment of the invention.

FIGS. 2A-2E illustrate various input and output packing schemes for 3D video data, in accordance with embodiments of the invention.

FIGS. 3A-3C are block diagrams that illustrate a processing network that is operable to scale 3D video data, in accordance with embodiments of the invention.

FIGS. 4A and 4B illustrate format-related variables for left-and-right (L/R) format and over-and-under (O/U) format, respectively, in accordance with embodiments of the invention.

FIGS. 5A and 5B illustrate configurations of the processing network when scaling 3D video data from an L/R input format to an L/R output format, in accordance with embodiments of the invention.

FIGS. 6A and 6B illustrate configurations of the processing network when scaling 3D video data from an L/R input format to an O/U output format, in accordance with embodiments of the invention.

FIGS. 7A and 7B illustrate configurations of the processing network when scaling 3D video data from an O/U input format to an L/R output format, in accordance with embodiments of the invention.

FIGS. 8A and 8B illustrate configurations of the processing network when scaling 3D video data from an O/U input format to an O/U output format, in accordance with embodiments of the invention.

FIG. 9 is a diagram that illustrates an example of scaling on the capture side when the 3D video has a 1080p O/U input format and a 720p L/R output format, in accordance with an embodiment of the invention.

FIGS. 10A and 10B are block diagrams that illustrate the order in which additional video processing operations may be performed in a processing network configured for scaling 3D video data, in accordance with embodiments of the invention.

FIG. 11 is a flow chart that illustrates steps for scaling 3D video data in a configured processing network, in accordance with an embodiment of the invention.

FIG. 12 is a flow chart that illustrates steps for scaling 3D video data from multiple sources in a configured processing network, in accordance with an embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

Certain embodiments of the invention may be found in a method and system for scaling 3D video. Various embodiments of the invention relate to an integrated circuit (IC) comprising multiple devices that may be selectively interconnected to route and process 3D video data. The IC may be operable to determine whether to scale the 3D video data before the 3D video data is captured to memory or after the captured 3D video data is retrieved from the memory, and selectively interconnect one or more of the devices based on the determination. The selective interconnection may be based on input and output formats of the 3D video data, and on a scaling factor. The input format may be a left-and-right (L/R) format or an over-and-under (O/U) format. Similarly, the output format may be a L/R format or an O/U format. The selective interconnection may be based on input and output pixel rates of the 3D video data. Moreover, the selective interconnection may be determined on a picture-by-picture basis.
FIG. 1 is a block diagram that illustrates a system-on-chip (SoC) that is operable to handle 3D video data scaling, in accordance with an embodiment of the invention. Referring to FIG. 1, there is shown an SoC 100, a host processor module 120, and a memory module 130. The SoC 100 may comprise suitable logic, circuitry, code, and/or interfaces that may be operable to receive and/or process one or more signals that comprise video content, including 3D video content. Examples of signals comprising video content that may be received and processed by the SoC 100 include, but need not be limited to, composite, blanking, and sync (CVBS) signals, separate video (S-video) signals, high-definition multimedia interface (HDMI) signals, component signals, personal computer (PC) signals, source input format (SIF) signals, YCrCb, and red, green, blue (RGB) signals. Such signals may be received by the SoC 100 from one or more video sources communicatively coupled to the SoC 100.
The SoC 100 may generate one or more output signals that may be provided to one or more output devices for display, reproduction, and/or storage. For example, output signals from the SoC 100 may be provided to display devices such as cathode ray tubes (CRTs), liquid crystal displays (LCDs), plasma display panels (PDPs), thin film transistor LCDs (TFT-LCDs), plasma, light emitting diode (LED), Organic LED (OLED), or other flatscreen display technology. The characteristics of the output signals, such as pixel rate and/or resolution, for example, may be based on the type of output device to which those signals are to be provided.
The host processor module 120 may comprise suitable logic, circuitry, code, and/or interfaces that may be operable to control and/or configure the operation of the SoC 100. For example, parameters and/or other information, including but not limited to configuration data, may be provided to the SoC 100 by the host processor module 120 at various times during the operation of the SoC 100. The memory module 130 may comprise suitable logic, circuitry, code, and/or interfaces that may be operable to store information associated with the operation of the SoC 100. For example, the memory module 130 may store intermediate values that result during the processing of video data, including those values associated with 3D video data processing.
The SoC 100 may comprise an interface module 102, a video processor module 104, and a core processor module 106. The SoC 100 may be implemented as a single integrated circuit comprising the components listed above. The interface module 102 may comprise suitable logic, circuitry, code, and/or interfaces that may be operable to receive multiple signals that comprise video content. Similarly, the interface module 102 may be operable to communicate one or more signals comprising video content to output devices communicatively coupled to the SoC 100.
The video processor module 104 may comprise suitable logic, circuitry, code, and/or interfaces that may be operable to process video data associated with one or more signals received by the SoC 100. The video processor module 104 may be operable to support multiple video data formats, including multiple input formats and multiple output formats for 3D video data. The video processor module 104 may be operable to perform various types of operations on 3D video data, including but not limited to format conversion and/or scaling. In some embodiments, when the video content comprises audio data, the video processor module 104, and/or another module in the SoC 100, may be operable to handle the audio data.
The core processor module 106 may comprise suitable logic, circuitry, code, and/or interfaces that may be operable to control and/or configure the operation of the SoC 100. For example, the core processor module 106 may be operable to control and/or configure operations of the SoC 100 that are associated with processing video content, including but not limited to the processing of 3D video data. In this regard, the core processor 106 may be operable to determine and/or calculate parameters associated with the processing of 3D video data that may be utilized to configure and/or operate the video processor module 104. In some embodiments of the invention, the core processor module 106 may comprise memory (not shown) that may be utilized in connection with the operations performed by the SoC 100. For example, the core processor module 106 may comprise memory that may be utilized during 3D video data processing by the video processor module 104.
In operation, the SoC 100 may receive one or more signals comprising 3D video data through the interface module 102. When the 3D video data received in those signals is to be scaled, the video processor module 104 and/or the core processor module 106 may be utilized to determine whether to scale 3D video data in the video processor module 104 before the 3D video data is captured to memory through the video processor module 104 or after the captured 3D video data is retrieved from the memory through the video processor module 104. The memory into which the 3D video data is to be stored and from which it is to be subsequently retrieved may be a dynamic random access memory (DRAM) that may be part of the memory module 130 and/or of the core processor module 106, for example.
At least a portion of the video processor module 104 may be configured by the host processor module 120 and/or the core processor module 106 according to the determined order in which to scale the 3D video data. Such order may be based on an input format of the 3D video data, an output format of the 3D video data, and on a scaling factor. Moreover, the order in which to scale the 3D video data may be determined on a picture-by-picture basis. That is, the order in which to scale the 3D video data and the corresponding configuration of the video processor module 104 may be carried out for each picture in a video sequence that is received in the SoC. Once processed, the 3D video data may be communicated to one or more output devices by the SoC 100.
As indicated above, the SoC 100 may be operable handle 3D video data in multiple input formats and multiple output formats. The complexity of the SoC 100, however, may increase significantly the larger the number of input and output formats supported. An approach that may simplify the SoC 100 and that may enable support for a large number of formats is to convert an input format into one of a subset of formats supported by the SoC for processing and have the SoC 100 perform the processing of the 3D video data in that format. Once the processing is completed, the processed 3D video data may be converted to the appropriate output format if such conversion is necessary.
FIGS. 2A-2E illustrate various input and output packing schemes for 3D video data, in accordance with embodiments of the invention. Referring to FIG. 2A, there is shown a first packing scheme or first format 200 for 3D video data and a second packing scheme or second format 210 for 3D video data. Each of the first format 200 and the second format 210 illustrates the arrangement of the left eye content (L) and the right eye content (R) in a 3D video picture. In this regard, a 3D video picture may refer to a 3D video frame or a 3D video field in a video sequence, whichever is appropriate. The L and R in the first format 200 are arranged in a side-by-side arrangement, which is typically referred to as a left-and-right (L/R) format. The L and R in the second format 210 are arranged in a top-and-bottom arrangement, which is typically referred to as an over-and-under (O/U) format. Another arrangement, one not shown in FIG. 2A, may be one in which the L is in a first 3D video picture and the R is in a second 3D video picture. Such arrangement may be referred to as a sequential format because the 3D video pictures are processed sequentially.
Both the first format 200 and the second format 210 may be utilized by the SoC 100 described above to process 3D video data and may be referred to as native formats of the SoC 100. When 3D video data is received in one of the multiple input formats supported by the SoC 100, the SoC 100 may convert that input format to one of the first format 200 and the second format 210, if such conversion is necessary. The SoC 100 may then process the 3D video data in a native format. Once the 3D video data is processed, the SoC 100 may convert the processed 3D video data into one of the multiple output formats supported by the SoC 100, if such conversion is necessary. The SoC 100 may also be operable to process 3D video data in the sequential format, which is typically handled by the SoC 100 in a manner that is substantially similar to the handling of the second format 210.
Referring to FIG. 2B, there is shown a conversion mapping of certain input formats 202 a, 204 a, and 206 a supported by the SoC 100 to the first format 200. For example, an L/R input format 202 a may be converted to the first format 200, which is also an L/R format. In another example, a line interleaved input format 204 a may be converted to the first format 200. In yet another example, a checkerboard input format 206 a may be converted to the first format 200. In each of these scenarios, the SoC 100 may detect the type of input format associated with the 3D video data and may determine that the appropriate conversion of the detected input format is to the first format 200.
Referring to FIG. 2C, there is shown a conversion mapping of the first format 200 to certain output formats 202 b, 204 b, and 206 b supported by the SoC 100. For example, the first format 200 may be converted to an L/R output format 202 b. In another example, the first format 200 may be converted to a line interleaved output format 204 b. In yet another example, the first format 200 may be converted to a checkerboard output format 206 b. In each of these scenarios, the SoC 100 may determine the appropriate type of output format to which the first format 200 is to be converted.
Referring to FIG. 2D, there is shown a conversion mapping of certain input formats 212 a, 214 a, and 216 a supported by the SoC 100 to the second format 210. For example, an O/U input format 212 a may be converted to the second format 210, which is also an O/U format. In another example, an O/U ×2 input format 214 a may be converted to the second format 210. In yet another example, a multi-decode input format 216 a may be converted to the second format 210. In each of these scenarios, the SoC 100 may detect the type of input format associated with the 3D video data and may determine that the appropriate conversion of the detected input format is to the second format 210.
Referring to FIG. 2E, there is shown a conversion mapping of the second format 210 to certain output formats 212 b and 214 b supported by the SoC 100. For example, the second format 210 may be converted to an O/U output format 212 b. In another example, the second format 210 may be converted to an O/U x2 output format 214 b. In each of these scenarios, the SoC 100 may determine the appropriate type of output format to which the second format 210 is to be converted.
The conversion operations supported by the SoC 100 may also comprise converting from the first format 200 to the second format 210 and converting from the second format 210 to the first format 200. In this manner, 3D video data may be received in any one of multiple input formats, such as the input formats 202 a, 204 a, 206 a, 212 a, 214 a, and 216 a (FIGS. 2B and 2D). Accordingly, resulting processed 3D video data may be generated in any one of multiple output formats, such as the output formats 202 b, 204 b, 206 b, 212 b, and 214 b (FIGS. 2C and 2E).
The various input formats and output formats described above with respect to FIGS. 2A-2E are provided by way of illustration and not of limitation. The SoC 100 may support additional input formats that may be converted to a native format such as the first format 200, the second format 210, and the sequential format. Similarly, the SoC may support additional output formats to which a native format may be converted.
FIGS. 3A-3C are block diagrams that illustrate a processing network that is operable to scale 3D video data, in accordance with embodiments of the invention. Referring to FIG. 3A, there is shown a processing network 300 that may be part of the video processor module 104 in the SoC 100, for example. The processing network 300 may comprise suitable logic, circuitry, code, and/or interfaces that may be operable to route and process video data, including 3D video data. In this regard, the processing network 300 may comprise multiple devices, components, modules, blocks, circuits, or the like, that may be selectively interconnected to enable the routing and processing of video data. The various devices, components, modules, blocks, circuits, or the like in the processing network 300 may be dynamically configured and/or dynamically interconnected during the operation of the SoC 100 through one or more signals generated by the core processor module 106 and/or by the host processor module 120. In this regard, the configuration and/or the selective interconnection of various portions of the processing network 300 may be performed on a picture-by-picture basis when such an approach is appropriate to handle varying characteristics of the video data.
In the embodiment of the invention described in FIG. 3A, the processing network 300 may comprise an MPEG feeder (MFD) module 302, multiple video feeder (VFD) modules 304, an HDMI module 306, crossbar modules 310 a and 310 b, multiple scaler (SCL) modules 308, a motion-adaptive deinterlacer (MAD) module 312, a digital noise reduction (DNR) module 314, multiple capture (CAP) modules 320, and two compositor (CMP) modules 322. Each of the above-listed components may be operable to handle video data, including 3D video data. The references to a memory (not shown) in FIG. 3A may be associated with a DRAM utilized by the processing network 300 to handle storage of video data during various operations. Such DRAM may be part of the memory module 130 described above with respect to FIG. 1. In some instances, the DRAM may be part of memory embedded in the SoC 100. The references to a video encoder (not shown) in FIG. 3A may be associated with hardware and/or software in the SoC 100 that may be utilized after the processing network 300 to further process video data for communication to an output device, such as a display device, for example.
Each of the crossbar modules 310 a and 310 b may comprise multiple input ports and multiple output ports. The crossbar modules 310 a and 310 b may be configured such that any one of the input ports may be connected to one or more of the output ports. The crossbar modules 310 a and 310 b may enable pass-through connections 316 between one or more output ports of the crossbar module 310 a and corresponding input ports of the crossbar module 310 b. Moreover, the crossbar modules 310 a and 310 b may enable feedback connections 318 between one or more output ports of the crossbar module 310 b and corresponding input ports of the crossbar module 310 a. The configuration of the crossbar modules 310 a and/or 310 b may result in one or more processing paths being configured within the processing network 300 in accordance with the manner and/or order in which video data is to be processed.
The MFD module 302 may be operable to read video data from memory and provide such video data to the crossbar module 310 a. The video data read by the MFD module 302 may have been stored in memory after being generated by an MPEG encoder (not shown). Each VFD module 304 may be operable to read video data from memory and provide such video data to the crossbar module 310. The video data read by the VFD module 304 may have been stored in memory in connection with one or more operations and/or processes associated with the processing network 300. The HDMI module 306 may be operable to provide a live feed of high-definition video data to the crossbar module 310 a. The HDMI module 306 may comprise a buffer (not shown) that may enable the HDMI module 306 to receive the live feed at one data rate and provide the live feed to the crossbar module 310 a at another data rate.
Each SCL module 308 may be operable to scale video data received from the crossbar module 310 a and provide the scaled video data to the crossbar module 310 b. The MAD module 312 may be operable to perform motion-adaptive deinterlacing operations on interlaced video data received from the crossbar module 310 a, including operations related to inverse telecine (IT), and provide progressive video data to the crossbar module 310 b. The DNR module 314 may be operable to perform artifact reduction operations on video data received from the crossbar module 310 a, including block noise reduction and mosquito noise reduction, for example, and provide the noise-reduced video data to the crossbar module 310 b. In some embodiments of the invention, the operations performed by the DNR module 314 may be utilized before the operations of the MAD module 312 and/or the operations of the SCL module 308.
Each CAP module 320 may be operable to capture video data from the crossbar module 310 b and store the captured video data in memory. Each CMP module 322 may be operable to blend or combine video data received from the crossbar module 310 b with graphics data. For example, FIG. 3A shows one CMP module 322 being provided with a graphics feed Gfxa that is blended by the CMP module 322 with video data received from the crossbar module 310 b before the combination is communicated to a video encoder. Similarly, another CMP module 322 is provided with a graphics feed Gfxb that is blended by the CMP module 322 with video data received from the crossbar module 310 b before the combination is communicated to a video encoder.
Referring to FIG. 3B, there is shown the SCL module 308 in a first configuration that may be utilized when the 3D video data scaling comprises scaling down horizontally. In this configuration, the SCL module 308 may comprise a horizontal scaler (HSCL) module 330, which may be configured to operate first and handles the horizontal scaling (sx) of the video data, and a vertical scaler (VSCL) module 332, which may be configured to operate after the horizontal scaling and handles the vertical scaling (sy) of the video data. The overall scaling of the SCL module 308 in this configuration may be given by the product sx·sy. The input pixel rate of the SCL module 308 at node “in” is SCL_in, the output pixel rate of the HSCL module 330 at node “H” is SCL_H, and the output pixel rate of the VSCL module 332 at node “V” is SCL_V, which is the same as the output pixel rate of the SCL module 308 at node “out”, SCL_out.
Referring to FIG. 3C, there is shown the SCL module 308 in a second configuration that may be utilized when the 3D video data scaling comprises scaling up horizontally. In this configuration, the VSCL module 332 may be configured to operate first and the HSCL module 330 may be configured to operate after the VSCL module 332. The overall scaling of the SCL module 308 in this configuration may be given by the product sy·sx. The input pixel rate of the SCL module 308 at node “in” is SCL_in, the output pixel rate of the VSCL module 332 at node “V” is SCL_V, and the output pixel rate of the HSCL module 330 at node “H” is SCL_H, which is the same as the output pixel rate of the SCL module 308 at node “out”, SCL_out.
By configuring the processing network 300 and/or one or more of the SCL modules 308, the processing network 300 may be utilized to scale and/or process 3D video data received by the SoC 100 in any one of the multiple input formats supported by the SoC 100, such as those described above with respect to FIGS. 2B and 2D, for example. Similarly, the scaled and/or processed 3D video data generated by the configured processing network 300 and/or one or more SCL modules 308 may be converted, if necessary, to any one of the multiple output formats supported by the SoC 100, such as those described above with respect to FIGS. 2C and 2E, for example.
FIGS. 4A and 4B illustrate format-related variables for L/R format and O/U format, respectively, in accordance with embodiments of the invention. Referring to FIG. 4A, there is shown a 3D video data picture 400 that illustrates some of the variables associated with a side-by-side or left-and-right arrangement. FIG. 4B shows a 3D video data picture 410 that illustrates the same variables when associated with a top-and-bottom or over-and-under arrangement. For example, when the picture 400 or the picture 410 is associated with an input format, such as before the 3D video data is scaled and/or processed by the processing network 300, the variables may be described as follows: xtot=ixtot is the total width of the picture, ytot=iytot is the total height of the picture, xact=ixact is the active width of the picture, yact=iyact is the active height of the picture, x=ix is the width of the area of the picture that is to be cropped and displayed, and y=iy is the height of the area of the picture that is to be cropped and displayed.
When the picture 400 or the picture 410 is associated with an output format, such as after the 3D video data is scaled and/or processed by the processing network 300, the variables may be described as follows: xtot=oxtot is the total width of the picture, ytot=oytot is the total height of the picture, xact=oxact is the active width of the picture, yact=oyact is the active height of the picture, x=ox is the width of the area on the display that the input content is to be displayed, and y=oy is the height of the area on the display that the input content is to be displayed.
Based on the variables described in FIGS. 4A and 4B, a 3D video picture may be scaled up horizontally when ox>ix, may be scaled down horizontally when ox<ix, may be scaled up vertically when oy>iy, and may be scaled down vertically when oy<iy.
When 3D video data received by the SoC 100 is scaled utilizing the processing network 300, the order in which the scaling of the 3D video data occurs with respect to the operations provided by the CAP module 320 and the VFD module 304 may depend on the characteristics of the input format of the 3D video data, the output format of the 3D video data, and the scaling that is to take place. In this regard, there may be bandwidth considerations when determining the appropriate order in which to carry out the scaling of the 3D video data, and consequently, the appropriate configuration of the processing network 300. Below are provided various scenarios that describe the selection of the order or positioning of the scaling operation in a sequence of operations that may be performed on 3D video data by the processing network 300.
FIGS. 5A and 5B illustrate configurations of the processing network 300 when scaling 3D video data from an L/R input format to an L/R output format, in accordance with embodiments of the invention. Referring to FIG. 5A, there is shown a first configuration 500 of the processing network 300 that may be utilized when an L/R input format and an L/R output format are being considered and the 3D video data scaling operation is determined to occur before the capture operation. The first configuration 500 may refer to a particular interconnection and/or operation of several of the modules in the processing network 300. For example, in the first configuration 500, the 3D video data may be provided to one of the SCL modules 308 from the MFD module 302 or from the HDMI module 306 by the appropriate configuration of the crossbar module 310 a. The output of the SCL module 308 may be provided to one of the CAP modules 320 by the appropriate configuration of the crossbar module 310 b. The scaled 3D video data may be captured by the CAP module 320 and may be stored in a memory 502. The memory 502 may be a DRAM memory, for example. One of the VFD modules 304 may retrieve the scaled and captured 3D video data from the memory 502 and may provide the retrieved 3D video data to one of the CMP modules 322 through the pass-through connections 316 between the crossbar modules 310 a and 310 b. The CMP module 322 may subsequently communicate the 3D video data to a video encoder.
In the first configuration 500, the pixel rate at node “A”, p_rate_A, is the same as the input pixel rate of the SCL module 308, SCL_in. The output pixel rate of the SCL module 308 is SCL_out=SCL_in·sx·sy=p_rate_A·sx·sy. Moreover, the pixel rate at node “C”, p_rate_C, is associated with the output characteristics of the 3D video data.
With respect to the CAP module 320 in the first configuration 500, the real time scheduling, cap_rts₁, is based on the number of requests for a line of data, n_req, and a time available for all requests, t_n_reqs. With L and R captured separately, these variables may be determined as follows:
$\begin{matrix} n_req = ⌈ \frac{ox}{N_{C}} ⌉, & (1) \\ \begin{matrix} t_n_req = \frac{ox}{S C L_{out}} \\ = \frac{ox}{{p_rate}_{A} \cdot sx \cdot sy} \\ = \frac{ix}{{p_rate}_{A}} \cdot \frac{1}{sy}, \end{matrix} & (2) \\ {cap_rts}_{1} = \frac{n_req}{t_n_req} = (\frac{ix}{{p_rate}_{A}} \cdot \frac{1}{sy}) / ⌈ \frac{ox}{N_{C}} ⌉, & (3) \end{matrix}$
where ox is the width of the area on the display that the input content is to be displayed as indicated above with respect to FIGS. 4A and 4B, and N_cis the burst size of the CAP module 320 in number of pixels.
With respect to the VFD module 304 in the first configuration 500, the real time scheduling, vfd_rts₁, is based on the number of requests for a line of data, n_req, and a time available for all requests, t n_reqs. With L and R captured separately, these variables may be determined as follows:
$\begin{matrix} n_req = ⌈ \frac{ox}{N_{V}} ⌉, & (4) \\ t_n_req = \frac{ox}{{p_rate}_{C}}, & (5) \\ {vfd_rts}_{1} = \frac{n_req}{t_n_req} = \frac{ox}{{p_rate}_{C}} / ⌈ \frac{ox}{N_{V}} ⌉, & (6) \end{matrix}$
where N_Vis the burst size of the VFD module 304 in number of pixels.
Referring to FIG. 5B, there is shown a second configuration 510 of the processing network 300 that may be utilized when an L/R input format and an L/R output format are being considered and the 3D video data scaling operation is determined to occur after the captured 3D video data is retrieved from memory. The second configuration 510 may refer to a particular interconnection and/or operation of several of the modules in the processing network 300. For example, in the second configuration 510, the 3D video data may be provided to one of the CAP modules 320 from the MFD module 302 or from the HDMI module 306 through the pass-through connections 316 between the crossbar modules 310 a and 310 b. The 3D video data may be captured by the CAP module 320 and may be stored in the memory 502. One of the VFD modules 304 may retrieve the captured 3D video data from the memory 502 and may provide the retrieved 3D video data to one of the SCL modules 308 by the appropriate configuration of the crossbar module 310 a. The output of the SCL module 308 may be provided to one of the CMP modules 322 by the appropriate configuration of the crossbar module 310 b. The CMP module 322 may subsequently communicate the 3D video data to a video encoder.
In the second configuration 510, the pixel rate at node “C”, p_rate_C, may be the same as the output pixel rate of the SCL module 308, SCL_out. The input pixel rate of the SCL module 308 may be SCL_in=SCL_out/(sx·sy)=p_rate_C/(sx·sy). Moreover, the pixel rate at node “A”, p_rate_A, may be associated with the input characteristics of the 3D video data.
With respect to the CAP module 320 in the second configuration 510, the real time scheduling, cap_rts₂, is based on the number of requests for a line of data, nreq, and a time available for all requests, t n_reqs. With L and R captured separately, these variables may be determined as follows:
$\begin{matrix} n_req = ⌈ \frac{ix}{N_{C}} ⌉, & (7) \\ t_n_req = \frac{ix}{{p_rate}_{A}}, & (8) \\ {cap_rts}_{2} = \frac{t_n_req}{n_req} = \frac{ix}{{p_rate}_{A}} / ⌈ \frac{ix}{N_{C}} ⌉, & (9) \end{matrix}$
where ix is the width of the area of the picture that is to be cropped and displayed as indicated above with respect to FIGS. 4A and 4B.
With respect to the VFD module 304 in the second configuration 510, the real time scheduling, vfd_rts₂, is based on the number of requests for a line of data, n_req, and a time available for all requests, t_n_reqs. With L and R captured separately, these variables may be determined as follows:
$\begin{matrix} n_req = ⌈ \frac{ix}{N_{V}} ⌉, & (10) \\ t_n_req = \frac{ix}{S C L_{i n}} = \frac{ix}{{p_rate}_{C} / (sx \cdot sy)} = \frac{ox \cdot sy}{{p_rate}_{C}}, & (11) \\ {vfd_rts}_{2} = \frac{t_n_req}{n_req} = \frac{ox}{{p_rate}_{C}} \cdot sy / ⌈ \frac{ix}{N_{V}} ⌉ . & (12) \end{matrix}$
A decision or selection as to whether to perform the scaling operation before capture, as in the first configuration 500, or after the captured data is retrieved from memory, as in the second configuration 510, may be based on the bandwidths associated with both scenarios. For the case when the burst size of the CAP module 320 and the burst size of the VFD module 304 are the same (i.e., N_c=N_v=N), the bandwidth calculations may be determined as follows:
$\begin{matrix} BW 1 = {cap_rts}_{1} + {vfd_rts}_{1} = (\frac{ix}{{p_rate}_{A}} \cdot \frac{1}{sy} + \frac{ox}{{p_rate}_{C}}) / ⌈ \frac{ox}{N} ⌉, & (13) \\ BW 2 = {cap_rts}_{2} + {vfd_rts}_{2} = (\frac{ix}{{p_rate}_{A}} + \frac{ox}{{p_rate}_{C}} \cdot sy) / ⌈ \frac{ix}{N} ⌉, & (14) \\ λ = \frac{BW 2}{BW 1} = \frac{⌈ ox / N ⌉}{⌈ ix / N ⌉} \cdot sy, & (15) \end{matrix}$
where BW1 is the bandwidth associated with the first configuration 500, BW2 is the bandwidth associated with the second configuration 510, and λ is the ratio of the two bandwidths. When λ<1, the SCL module 308 is to be positioned before the CAP module 320, as in the first configuration 500, and when λ>1, the SCL module 308 is to be positioned after the VFD module 304, as in the second configuration 510.
FIGS. 6A and 6B illustrate configurations of the processing network 300 when scaling 3D video data from an L/R input format to an O/U output format, in accordance with embodiments of the invention. Referring to FIG. 6A, there is shown a third configuration 600 of the processing network 300 that may be utilized when an L/R input format and an O/U output format are being considered and the 3D video data scaling operation is determined to occur before the capture operation. The third configuration 600 may refer to a particular interconnection and/or operation of several of the modules in the processing network 300. In the third configuration 600, the arrangement of the processing network 300 may be similar to that of the first configuration 500 in FIG. 5A. That is, the 3D video data may be provided to one of the SCL modules 308 from the MFD module 302 or from the HDMI module 306 by the appropriate configuration of the crossbar module 310 a. The output of the SCL module 308 may be provided to one of the CAP modules 320 by the appropriate configuration of the crossbar module 310 b. The scaled 3D video data may be captured by the CAP module 320 and may be stored in the memory 502. One of the VFD modules 304 may retrieve the scaled and captured 3D video data from the memory 502 and may provide the retrieved 3D video data to one of the CMP modules 322 through the pass-through connections 316 between the crossbar modules 310 a and 310 b. The CMP module 322 may subsequently communicate the 3D video data to a video encoder.
With respect to the CAP module 320 in the third configuration 600, the real time scheduling, cap_rts₃, may be determined as follows:
$\begin{matrix} {cap_rts}_{3} = (\frac{ix}{{p_rate}_{A}} \cdot \frac{1}{sy}) / ⌈ \frac{ox}{N_{C}} ⌉ . & (16) \end{matrix}$
With respect to the VFD module 304 in the third configuration 600, the real time scheduling, vfd_rts₃, may be determined as follows:
$\begin{matrix} {vfd_rts}_{3} = \frac{ox}{{p_rate}_{D}} / ⌈ \frac{ox}{N_{V}} ⌉, & (17) \end{matrix}$
where the pixel rate at node “D”, p_rate_D, may be associated with the output characteristics of the 3D video data.
Referring to FIG. 6B, there is shown a fourth configuration 610 of the processing network 300 that may be utilized when an L/R input format and an O/U output format are being considered and the 3D video data scaling operation is determined to occur after the captured 3D video data is retrieved from memory. The fourth configuration 610 may refer to a particular interconnection and/or operation of several of the modules in the processing network 300. In the fourth configuration 610, the arrangement of the processing network 300 may be similar to that of the second configuration 510 in FIG. 5B. That is, the 3D video data may be provided to one of the CAP modules 320 from the MFD module 302 or from the HDMI module 306 through the pass-through connections 316 between the crossbar modules 310 a and 310 b. The 3D video data may be captured by the CAP module 320 and may be stored in the memory 502. One of the VFD modules 304 may retrieve the captured 3D video data from the memory 502 and may provide the retrieved 3D video data to one of the SCL modules 308 by the appropriate configuration of the crossbar module 310 a. The output of the SCL module 308 may be provided to one of the CMP modules 322 by the appropriate configuration of the crossbar module 310 b. The CMP module 322 may subsequently communicate the 3D video data to a video encoder.
With respect to the CAP module 320 in the fourth configuration 610, the real time scheduling, cap_rts₄, may be determined as follows:
$\begin{matrix} {cap_rts}_{4} = \frac{ix}{{p_rate}_{A}} / ⌈ \frac{ix}{N_{C}} ⌉, & (18) \end{matrix}$
With respect to the VFD module 304 in the fourth configuration 610, the real time scheduling, vfd_rts₄, may be determined as follows:
$\begin{matrix} {vfd_rts}_{4} = \frac{ox}{{p_rate}_{D}} \cdot sy / ⌈ \frac{ix}{N_{V}} ⌉, & (19) \end{matrix}$
where the pixel rate at node “D”, p_rate_D, may be the same as the output pixel rate of the SCL module 308, SCL_out.
A decision or selection as to whether to perform the scaling operation before capture, as in the third configuration 600, or after the captured data is retrieved from memory, as in the fourth configuration 610, may be based on the bandwidths associated with both scenarios. For the case when the burst size of the CAP module 320 and the burst size of the VFD module 304 are the same (i.e., N_C=N_V=N), the following ratio may be determined:
$\begin{matrix} λ = \frac{BW 2}{BW 1} = \frac{⌈ ox / N ⌉}{⌈ ix / N ⌉} \cdot sy . & (22) \end{matrix}$
where BW1 is the bandwidth associated with the third configuration 600, BW2 is the bandwidth associated with the fourth configuration 610, and λ is the ratio of the two bandwidths. When λ<1, the SCL module 308 is to be positioned before the CAP module 320, as in the third configuration 600, and when λ>1, the SCL module 308 is to be positioned after the VFD module 304, as in the fourth configuration 610.
FIGS. 7A and 7B illustrate configurations of the processing network 300 when scaling 3D video data from an O/U input format to an L/R output format, in accordance with embodiments of the invention. Referring to FIG. 7A, there is shown a fifth configuration 700 of the processing network 300 that may be utilized when an O/U input format and an L/R output format are being considered and the 3D video data scaling operation is determined to occur before the capture operation. The fifth configuration 700 may refer to a particular interconnection and/or operation of several of the modules in the processing network 300. In this configuration, the arrangement of the processing network 300 may be similar to that of the first configuration 500 in FIG. 5A.
With respect to the CAP module 320 in the fifth configuration 700, the real time scheduling, cap may be determined as follows:
$\begin{matrix} {cap_rts}_{5} = (\frac{ix}{{p_rate}_{B}} \cdot \frac{1}{sy}) / ⌈ \frac{ox}{N_{C}} ⌉, & (23) \end{matrix}$
where the pixel rate at node “B”, p_rate_B, may be the same as the input pixel rate of the SCL module 308, SCL_in.
With respect to the VFD module 304 in the fifth configuration 700, the real time scheduling, vfd_rts₅, may be determined as follows:
$\begin{matrix} {vfd_rts}_{5} = \frac{ox}{{p_rate}_{C}} / ⌈ \frac{ox}{N_{V}} ⌉ . & (24) \end{matrix}$
Referring to FIG. 7B, there is shown a sixth configuration 710 of the processing network 300 that may be utilized when an O/U input format and an L/R output format are being considered and the 3D video data scaling operation is determined to occur after the captured 3D video data is retrieved from memory. The sixth configuration 710 may refer to a particular interconnection and/or operation of several of the modules in the processing network 300. In this configuration, the arrangement of the processing network 300 may be similar to that of the second configuration 510 in FIG. 5B.
With respect to the CAP module 320 in the sixth configuration 710, the real time scheduling, cap_rts_s, may be determined as follows:
$\begin{matrix} {cap_rts}_{6} = \frac{ix}{{p_rate}_{B}} / ⌈ \frac{ix}{N_{C}} ⌉, & (25) \end{matrix}$
where the pixel rate at node “B”, p_rate_B, may be associated with the input characteristics of the 3D video data.
With respect to the VFD module 304 in the sixth configuration 710, the real time scheduling, vfd_rts_s, may be determined as follows:
$\begin{matrix} {vfd_rts}_{6} = \frac{ox}{{p_rate}_{C}} \cdot sy / ⌈ \frac{ix}{N_{V}} ⌉ . & (26) \end{matrix}$
A decision or selection as to whether to perform the scaling operation before capture, as in the fifth configuration 700, or after the captured data is retrieved from memory, as in the sixth configuration 710, may be based on the bandwidths associated with both scenarios. For the case when the burst size of the CAP module 320 and the burst size of the VFD module 304 are the same (i.e., N_c=N_v=N), the following ratio may be determined:
$\begin{matrix} λ = \frac{BW 2}{BW 1} = \frac{⌈ ox / N ⌉}{⌈ ix / N ⌉} \cdot sy, & (27) \end{matrix}$
where BW1 is the bandwidth associated with the fifth configuration 700, BW2 is the bandwidth associated with the sixth configuration 710, and λ is the ratio of the two bandwidths. When λ<1, the SCL module 308 is to be positioned before the CAP module 320, as in the fifth configuration 700, and when λ>1, the SCL module 308 is to be positioned after the VFD module 304, as in the sixth configuration 710.
FIGS. 8A and 8B illustrate configurations of the processing network 300 when scaling 3D video data from an O/U input format to an O/U output format, in accordance with embodiments of the invention. Referring to FIG. 8A, there is shown a seventh configuration 800 of the processing network 300 that may be utilized when an O/U input format and an O/U output format are being considered and the 3D video data scaling operation is determined to occur before the capture operation. The seventh configuration 800 may refer to a particular interconnection and/or operation of several of the modules in the processing network 300. In this configuration, the arrangement of the processing network 300 may be similar to that of the first configuration 500 in FIG. 5A.
With respect to the CAP module 320 in the seventh configuration 800, the real time scheduling, cap may be determined as follows:
$\begin{matrix} {cap_rts}_{7} = (\frac{ix}{{p_rate}_{B}} \cdot \frac{1}{sy}) / ⌈ \frac{ox}{N_{C}} ⌉ . & (28) \end{matrix}$
With respect to the VFD module 304 in the seventh configuration 800, the real time scheduling, vfd_rts₇, may be determined as follows:
$\begin{matrix} {vfd_rts}_{7} = \frac{ox}{{p_rate}_{D}} / ⌈ \frac{ox}{N_{V}} ⌉ . & (29) \end{matrix}$
Referring to FIG. 8B, there is shown an eighth configuration 810 of the processing network 300 that may be utilized when an O/U input format and an O/U output format are being considered and the 3D video data scaling operation is determined to occur after the captured 3D video data is retrieved from memory. The eighth configuration 810 may refer to a particular interconnection and/or operation of several of the modules in the processing network 300. In this configuration, the arrangement of the processing network 300 may be similar to that of the second configuration 510 in FIG. 5B.
With respect to the CAP module 320 in the eighth configuration 810, the real time scheduling, cap may be determined as follows:
$\begin{matrix} {cap_rts}_{8} = \frac{ix}{{p_rate}_{B}} / ⌈ \frac{ix}{N_{C}} ⌉ . & (30) \end{matrix}$
With respect to the VFD module 304 in the eighth configuration 810, the real time scheduling, vfd_rts_s, may be determined as follows:
$\begin{matrix} {vfd_rts}_{8} = \frac{ox}{{p_rate}_{D}} \cdot sy / ⌈ \frac{ix}{N_{V}} ⌉ . & (31) \end{matrix}$
A decision or selection as to whether to perform the scaling operation before capture, as in the seventh configuration 800, or after the captured data is retrieved from memory, as in the eighth configuration 810, may be based on the bandwidths associated with both scenarios. For the case when the burst size of the CAP module 320 and the burst size of the VFD module 304 are the same (i.e., N_c=N_v=N), the following ratio may be determined:
$\begin{matrix} λ = \frac{BW 2}{BW 1} = \frac{⌈ ox / N ⌉}{⌈ ix / N ⌉} \cdot sy, & (32) \end{matrix}$
where BW1 is the bandwidth associated with the seventh configuration 800, BW2 is the bandwidth associated with the eighth configuration 810, and λ is the ratio of the two bandwidths. When λ<1, the SCL module 308 is to be positioned before the CAP module 320, as in the seventh configuration 800, and when λ>1, the SCL module 308 is to be positioned after the VFD module 304, as in the eighth configuration 810.
FIG. 9 is a diagram that illustrates an example of scaling on the capture side when the 3D video has a 1080 progressive (1080p) O/U input format and a 720p L/R output format, in accordance with an embodiment of the invention. Referring to FIG. 9, the example shown corresponds to the fifth configuration 700 described above with respect to FIG. 7A. In this example, an input picture 900, which is formatted as 1080p O/U 3D video data, is provided to the processing network 300 for scaling and/or processing. The input picture 900 is scaled by a scaling operation 910 that is performed by, for example, one of the SCL modules 308 shown in FIG. 3A. A scaled picture 920 is then captured to memory by a capture operation 930 performed by, for example, one of the CAP modules 320 shown in FIG. 3A. The captured picture is retrieved from memory through a capture retrieval operation 940 performed by, for example, one of the VFD modules 304 shown in FIG. 3A. The retrieval of the captured picture, that is, the manner in which the 3D video data is read from the memory, is performed such that an output picture 950 is generated having a 720p L/R format.
FIGS. 10A and 10B are block diagrams that illustrate the order in which additional video processing operations may be performed in the processing network 300 when configured for scaling 3D video data, in accordance with embodiments of the invention. Referring to FIG. 10A, there is shown a ninth configuration 1000 of the processing network 300 in which the location of the SCL module 308 is before the CAP module 320. The ninth configuration 1000 may refer to a particular interconnection and/or operation of several of the modules in the processing network 300. In this configuration, additional processing cores or operations may be performed on the 3D video data. For example, a first core (P1) module 1002 may be positioned before the SCL module 308, while a second core (P2) module 1004 may be positioned after the SCL module 308. Moreover, a third core (P3) module 1006 may be positioned after the VFD module 304. The various core modules described herein may refer to processing modules in the processing network 300 such as the MAD module 312 and/or the DNR module 314. Other modules not shown in FIG. 3A, but that may be included in the processing network 300, may also be utilized as core modules in the ninth configuration 1000.
Referring to FIG. 10B, there is shown a tenth configuration 1010 of the processing network 300 in which the location of the SCL module 308 is after the VFD module 304. The tenth configuration 1010 may refer to a particular interconnection and/or operation of several of the modules in the processing network 300. In this configuration, additional processing cores or operations may be performed on the 3D video data. For example, the P1 module 1002 may be positioned before the CAP module 320. The P2 module 1004 may be positioned after the VFD module 304 and before the SCL module 308. Moreover, the P3 module 1006 may be positioned after the SCL module 308. As indicated above, the various core modules described herein may refer to processing modules in the processing network 300 such as the MAD module 312 and/or the DNR module 314. Other modules not shown in FIG. 3A, but that may be included in the processing network 300, may also be utilized as core modules in the tenth configuration 1010.
FIG. 11 is a flow chart that illustrates steps for scaling 3D video data in the configured processing network 300, in accordance with an embodiment of the invention. Referring to FIG. 11, there is shown a flow chart 1100 in which, at step 1110, the video processor module 104 in the SoC 100 may receive 3D video data from a source of such data. At step 1120, the video processor module 104 and/or the host processor module 120 may determine whether to scale the 3D video data received before capture to memory through the video processor module 104 or after capture to memory and subsequent retrieval from memory through the video processor module 104.
At step 1130, the video processor module 104 and/or the host processor module 120 may configure a portion of the video processor module 104 comprising a processing network, such as the processing network 300 shown in FIG. 3A. The configuration may be based on the order or positioning determined in step 1120 regarding the scaling of the 3D video data. At step 1140, the 3D video data may be scaled by the configured processing network in the video processor module 104.
FIG. 12 is a flow chart that illustrates steps for scaling 3D video data from multiple sources in the configured processing network 300, in accordance with an embodiment of the invention. Referring to FIG. 12, there is shown a flow chart 1200 in which, at step 1210, the video processor module 104 in the SoC 100 may receive 3D video data from multiple sources of such data. At step 1220, the video processor module 104 and/or the host processor module 120 may determine, for each of the sources, whether to scale the 3D video data received before capture to memory through the video processor module 104 or after capture to memory and subsequent retrieval from memory through the video processor module 104.
At step 1230, the video processor module 104 and/or the host processor module 120 may configure a portion of the video processor module 104 comprising a processing network, such as the processing network 300 shown in FIG. 3A. The configuration may be based on the order or positioning determined in step 1220 regarding the scaling of the 3D video data for each of the sources. In this regard, the processing network may be configured to have multiple paths for processing the 3D video data from the various sources of such data. At step 1240, the 3D video data from each source may be scaled by the configured processing network in the video processor module 104.
Various embodiments of the invention relate to an integrated circuit, such as the SoC 100 described above with respect to FIG. 1, for example, which may be operable to selectively route and process 3D video data. For example, the processing network 300 described above with respect to FIG. 3A may be utilized in the SoC 100 to route and process 3D video data. The integrated circuit may comprise multiple devices, such as the various modules in the processing network 300, for example, which may be operable to be selectively interconnected to enable the routing and the processing of 3D video data. The integrated circuit may be operable to determine whether to scale the 3D video data before the 3D video data is captured to memory or after the captured 3D video data is retrieved from the memory. Moreover, the integrated circuit may be operable to selectively interconnect one or more of the multiple devices based on the determination.
The integrated circuit may be operable to determine the selective interconnection of the one or more of devices based on an input format of the 3D video data, an output format of the 3D video data, and a scaling factor. The input format of the 3D video data may be a L/R input format or an O/U input format and the output format of the 3D video data may be a L/R output format or an O/U output format. The integrated circuit may be operable to determine the selective interconnection of the one or more devices based on an input pixel rate of the 3D video data and on an output pixel rate of the 3D video data. The integrated circuit may be operable to determine the selective interconnection of the one or more devices on a picture-by-picture basis.
The selectively interconnected devices in the integrated circuit may be operable to horizontally scale the 3D video data and to vertically scale the 3D video data. Moreover, the selectively interconnected devices in the integrated circuit may be operable to perform one or more operations on the 3D video data before the 3D video data is scaled, after the 3D video data is scale, or both.
In another embodiment of the invention, a non-transitory machine and/or computer readable storage and/or medium may be provided, having stored thereon a machine code and/or a computer program having at least one code section executable by a machine and/or a computer, thereby causing the machine and/or computer to perform the steps as described herein for scaling 3D video.
Accordingly, the present invention may be realized in hardware, software, or a combination of hardware and software. The present invention may be realized in a centralized fashion in at least one computer system or in a distributed fashion where different elements may be spread across several interconnected computer systems. Any kind of computer system or other apparatus adapted for carrying out the methods described herein is suited. A typical combination of hardware and software may be a general-purpose computer system with a computer program that, when being loaded and executed, controls the computer system such that it carries out the methods described herein.
The present invention may also be embedded in a computer program product, which comprises all the features enabling the implementation of the methods described herein, and which when loaded in a computer system is able to carry out these methods. Computer program in the present context means any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following: a) conversion to another language, code or notation; b) reproduction in a different material form.
While the present invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present invention without departing from its scope. Therefore, it is intended that the present invention not be limited to the particular embodiment disclosed, but that the present invention will include all embodiments falling within the scope of the appended claims.

Claims

1. A method, comprising:

in an integrated circuit operable to selectively route and process 3D video data, the integrated circuit comprising a plurality of devices that are operable to be selectively interconnected to enable the routing and the processing:

determining whether to scale the 3D video data before the 3D video data is captured to memory or after the captured 3D video data is retrieved from the memory; and

selectively interconnecting one or more of the plurality of devices based on the determination.

2. The method of claim 1, wherein the selective interconnection of the one or more of the plurality of devices in the integrated circuit is determined based on an input format of the 3D video data, an output format of the 3D video data, and a scaling factor.

3. The method of claim 2, wherein the input format of the 3D video data is a left-and-right input format and the output format of the 3D video data is a left-and-right output format.

4. The method of claim 2, wherein the input format of the 3D video data is a left-and-right input format and the output format of the 3D video data is an over-and-under output format.

5. The method of claim 2, wherein the input format of the 3D video data is an over-and-under input format and the output format of the 3D video data is a left-and-right output format.

6. The method of claim 2, wherein the input format of the 3D video data is an over-and-under input format and the output format of the 3D video data is an over-and-under output format.

7. The method of claim 1, wherein the selective interconnection of the one or more of the plurality of devices in the integrated circuit is determined based on an input pixel rate of the 3D video data and on an output pixel rate of the 3D video data.

8. The method of claim 1, wherein the selective interconnection of the one or more of the plurality of devices in the integrated circuit is determined on a picture-by-picture basis.

9. The method of claim 1, comprising scaling the 3D video data in the selectively interconnected one or more of the plurality of devices in the integrated circuit, the scaling comprising a horizontal scaling and a vertical scaling.

10. The method of claim 1, comprising performing one or more operations in the selectively interconnected one or more of the plurality of devices in the integrated circuit, the one or more operations being performed before the 3D video data is scaled, after the 3D video data is scaled, or both.

11. A system, comprising:

an integrated circuit operable to selectively route and process 3D video data, the integrated circuit comprising a plurality of devices that are operable to be selectively interconnected to enable the routing and the processing;

the integrated circuit being operable to determine whether to scale the 3D video data before the 3D video data is captured to memory or after the captured 3D video data is retrieved from the memory; and

the integrated circuit being operable to selectively interconnect one or more of the plurality of devices based on the determination.

12. The system of claim 11, wherein the integrated circuit is operable to determine the selective interconnection of the one or more of the plurality of devices based on an input format of the 3D video data, an output format of the 3D video data, and a scaling factor.

13. The system of claim 12, wherein the input format of the 3D video data is a left-and-right input format and the output format of the 3D video data is a left-and-right output format.

14. The system of claim 12, wherein the input format of the 3D video data is a left-and-right input format and the output format of the 3D video data is an over-and-under output format.

15. The system of claim 12, wherein the input format of the 3D video data is an over-and-under input format and the output format of the 3D video data is a left-and-right output format.

16. The system of claim 12, wherein the input format of the 3D video data is an over-and-under input format and the output format of the 3D video data is an over-and-under output format.

17. The system of claim 11, wherein the integrated circuit is operable to determine the selective interconnection of the one or more of the plurality of devices based on an input pixel rate of the 3D video data and on an output pixel rate of the 3D video data.

18. The system of claim 11, wherein the integrated circuit is operable to determine the selective interconnection of the one or more of the plurality of devices on a picture-by-picture basis.

19. The system of claim 11, wherein the selectively interconnected one or more of the plurality of devices are operable to horizontally scale the 3D video data and to vertically scale the 3D video data.

20. The system of claim 19, wherein the selectively interconnected one or more of the plurality of devices are operable to perform one or more operations on the 3D video data before the 3D video data is scaled, after the 3D video data is scaled, or both.