US20110147859A1 - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the same Download PDFInfo
- Publication number
- US20110147859A1 US20110147859A1 US12/968,470 US96847010A US2011147859A1 US 20110147859 A1 US20110147859 A1 US 20110147859A1 US 96847010 A US96847010 A US 96847010A US 2011147859 A1 US2011147859 A1 US 2011147859A1
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- substrate
- semiconductor device
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L2924/12036—PN diode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16235—Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
Definitions
- the present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the present invention relates to a semiconductor device having a cap substrate bonded to a base substrate made of silicon for protecting various elements formed in a surface layer of the base substrate, and a method of manufacturing the same.
- a cap substrate to a base substrate for protecting various element formed in a surface layer of the base substrate.
- an electrical connection for electrically connecting the base substrate and an external part is necessary.
- a large through hole is required in the cap substrate to conduct wire bonding. That is, an area necessary for making the electrical connection is likely to increase.
- a leading electrode that extends from the base substrate to the surface of the cap substrate and allows the electrical connection at the end can be employed.
- the cap substrate made of silicon is divided into partial regions by an insulating and separating trench, and a specific region of the partial regions, which connects to an insulated and separated base semiconductor region of the base substrate, is used as a leading conductive region.
- the upper end of the specific region is electrically connected to the external part by the wire bonding, soldering or the like.
- a semiconductor device having such an electrical connection structure is, for example, described in Japanese Patent Application Publications No. JP2008-229833A (Publication 1, corresponding to US2008/0290490A1) and No. JP2008-256495 (Publication 2).
- FIG. 30 shows an example of the semiconductor device described in Publication 1.
- a semiconductor device 91 shown in FIG. 30 has a semiconductor base substrate B 2 and a conductive cap substrate C 2 bonded to the base substrate B 2 .
- the base substrate B 2 is a SOI (Silicon On Insulator) substrate in which an embedded oxide film 20 is interposed between a SOI layer 21 and a support substrate 22 .
- Insulated and separated multiple base semiconductor regions Bs are formed in a surface layer of the base substrate B 2 .
- the base semiconductor regions Bs are provided by the SOI layer 21 , and are insulated and separated from adjacencies by a trench 23 that reaches the embedded oxide film 20 .
- Projections T 1 are formed above the base semiconductor regions Bs.
- the projections T 1 are provided by a conductive film 50 , which is made of poly crystal silicone, metal or the like.
- the semiconductor device 91 includes a mechanical quantity sensor element for measuring a mechanical quantity, such as acceleration and angular velocity, using an inertia force.
- the mechanical quantity sensor element is constructed of the multiple base semiconductor regions Bs.
- the base semiconductor regions Bs include at least two base semiconductor regions Bs 1 and two base semiconductor regions Bs 2 .
- the base semiconductor regions Bs 1 constitute a movable semiconductor region.
- the base semiconductor regions Bs 1 are formed by performing sacrifice layer etching on a part of the embedded oxide film 20 .
- the base semiconductor regions Bs 1 as the movable semiconductor region include a movable electrode Em, which is formed to be displaceable.
- the base semiconductor regions Bs 2 constitute a fixed semiconductor region including a fixed electrode Es opposed to the movable electrode Em.
- the two base semiconductor region Bs 1 and the two base semiconductor region Bs 2 each form a continuous and integrated region on a plane.
- a capacitance is created between opposed surfaces of the movable electrode Em and the fixed electrode Es.
- the capacitance changes in accordance with a change in the distance between the movable electrode Em and the fixed electrode Es.
- the applied mechanical quantity is detected by measuring the change in capacitance.
- the cap substrate C 2 is provided by a single crystal silicon substrate 30 on which multiple cap conductive regions Ce as partial regions are formed.
- the cap conductive regions Ce are divided by an insulating and separating trench 31 that passes through the single crystal silicon substrate 30 .
- the cap substrate C 2 has a surface protection layer 33 made of silicon oxide (SiO 2 ) or the like, and electrode pads 34 made of aluminum (Al) or the like.
- the cap substrate C 2 is bonded to the projections T 1 formed on the base semiconductor regions Bs, and a bonding surface D 1 is formed therebetween.
- the bonding surface D 1 has a loop shape in a predetermined region R 1 of the base substrate B 2 .
- a space sealed in a highly vacuum condition is provided between the surface of the predetermined region R 1 and the surface of the cap substrate C 2 by bonding the base substrate B 2 and the cap substrate C 2 .
- specific cap conductive regions Ce 1 , Ce 2 are electrically connected to the specific base semiconductor regions Bs 1 , Bs 2 , respectively, to serve as leading conductive regions.
- the leading conductive regions Ce 1 , Ce 2 are respectively connected to the movable semiconductor region Bs 1 and the fixed semiconductor region Bs 2 , respectively.
- FIG. 31 shows an example of a semiconductor device described in Publication 2.
- a semiconductor device 92 of FIG. 31 has a semiconductor mechanical quantity sensor element for detecting a mechanical quantity, such as acceleration and angular velocity, similar to the semiconductor device 91 of FIG. 30 .
- the semiconductor device 92 has a base substrate B 3 provided by a Sal substrate.
- the SOI substrate includes a support substrate 11 made of silicon semiconductor and a poly silicon layer 12 disposed on the support substrate 11 through an oxide film 13 . Sensing portions Se are formed by the poly silicon layer 12 disposed on the support substrate 11 .
- the sensing portions Se include a movable electrode and a fixed electrode.
- the movable electrode and the fixed electrode are provided by a beam structure, which is generally used in conventional acceleration sensors and angular velocity sensors. As the movable electrode is displaced in accordance with the applied acceleration or angular velocity, the capacitance between the movable electrode and the fixed electrode is changed. A voltage signal indicative of the change in capacitance is produced.
- a cap C 3 is fixed to the base substrate B 3 to surround the sensing portions Se.
- the cap C 3 is bonded to the poly silicon layer 12 through an adhesive layer Ds made of a resin adhesive or the like.
- the cap C 3 is provided with penetrating electrodes Ke.
- the cap C 3 is made of silicon semiconductor in which impurities, such as phosphorous (P) and boron (B), are preferably doped so as to have electrical conductivity.
- the penetrating electrodes Ke pass through the cap C 3 in a direction in which a thickness of the cap C 3 is measured.
- the penetrating electrodes Ke serve to lead electrical signals from the sensing portions Se, which are located under the cap C 3 , to the upper surface of the cap C 3 .
- the penetrating electrodes Ke are constituted as portions of the cap C 3 having the electrical conductivity.
- the cap C 3 is formed with grooves 15 , which are referred to as air isolations, on peripheries of the penetrating electrodes Ke.
- the grooves 15 surround the penetrating electrodes Ke, and pass through the cap C 3 in the direction in which the thickness of the cap C 3 is measured.
- the penetrating electrodes Ke and portions of the cap C 3 on the peripheries of the penetrating electrodes Ke are insulated by means of the grooves 15 . That is, the grooves 15 serve as electrically insulating portions to electrically insulate the penetrating electrodes Ke from the peripheral portions thereof in the cap C 3 .
- the penetrating electrodes Ke are in contact with the poly silicon layer 12 through connecting electrodes 51 , which are made of aluminum, Al—Si or the like, to make electrical connection with the sensing portions Se.
- the cap substrate C 2 serves as a sealing cap for protecting the mechanical quantity sensor element formed in the predetermined region R 1 of the surface layer of the base substrate B 2 .
- the cap conductive regions Ce 1 , Ce 2 of the cap substrate C 2 which are electrically connected to the base semiconductor regions Bs 1 , Bs 2 of the base substrate B 2 , serve as leading conductive regions.
- the insulating and separating trench 31 exist on the peripheries of the leading conductive regions Ce 1 , Ce 2 to isolate the leading conductive regions Ce 1 , Ce 2 from the peripheral cap conductive regions. Therefore, parasitic capacitance is produced due to the insulating and separating trench 31 being an electric substance, and is likely to affect performance of the semiconductor device 91 .
- the penetrating electrodes Ke are electrically insulated from the peripheral portions in the cap C 3 by the grooves 15 as the air isolations. Therefore, the electric permittivity at the grooves 15 is smaller than that at the trench 31 of the semiconductor device 91 in which the electric substance is embedded. That is, the semiconductor device 92 of FIG. 31 is less apt to generate the parasitic capacitance, as compared with the semiconductor device 91 of FIG. 30 .
- the semiconductor device 91 employs the cap substrate C 2 made of single crystal silicon.
- the semiconductor device 92 employs the cap substrate C 3 made of silicon semiconductor.
- silicon is less expensive than other substrate materials, and a trench is easily formed in a silicon substrate.
- silicon has a relatively large specific resistance. Therefore, the leading conductive regions Ce 1 , Ce 2 and the penetrating electrodes Ke are likely to increase resistance, and hence the applicable range of such semiconductor devices may be restricted.
- a semiconductor device includes a base substrate, a cap substrate and a leading electrode for allowing an electrical connection between the base substrate and an external device.
- the base substrate is made of silicon and has a plurality of base semiconductor regions in a predetermined portion of a surface layer thereof.
- the cap substrate is bonded to the predetermined portion of the surface layer of the base substrate.
- the leading electrode includes a metal part. The leading electrode passes through the cap substrate. A first end of the leading electrode is connected to one of the plurality of base semiconductor regions. A second end of the leading electrode is located adjacent to a surface of the cap substrate, the surface being opposite to a bonding surface at which the base substrate and the cap substrate are bonded, to allow the electrical connection with an external part. Further, a groove is formed between the leading electrode and the cap substrate.
- the leading electrode has the metal part having conductivity higher than that of silicon. Hence, the resistance at the leading electrode can be reduced, as compared with a conventional semiconductor device. Further, the groove is formed between the leading electrode and the cap substrate. That is, because the leading electrode has an air isolation structure, the conventional insulating and separating trench for forming the leading conductive region is not employed. Therefore, parasitic capacitance will not be easily created. In addition, stress due to a thermal expansion difference between the metal part and the cap substrate is reduced.
- a method of manufacturing a semiconductor device includes: forming a base substrate made of silicon; forming a cap substrate; bonding the cap substrate to a predetermined portion of the base substrate; and forming a leading electrode including a metal part.
- the base substrate has a plurality of base semiconductor regions in the predetermined portion of a surface layer thereof, and the plurality of base semiconductor regions is insulated and separated from each other.
- the leading electrode passes through the cap substrate.
- the leading electrode has a first end connected to one of the plurality of base semiconductor regions and a second end located adjacent to a surface of the cap substrate.
- the leading electrode defines a groove between an outer surface thereof and the cap substrate.
- FIG. 1A is a schematic cross-sectional view of a part of a semiconductor device as an example according to an embodiment of the present invention
- FIG. 1B is a schematic cross-sectional view taken along a line IB-IB in FIG. 1A ;
- FIG. 2 is a perspective view of a base substrate of the semiconductor device shown in FIGS. 1A and 1B ;
- FIGS. 3A to 3C are schematic cross-sectional views for showing a process of forming the base substrate shown in FIG. 2 ;
- FIGS. 4A to 4C are schematic cross-sectional views for showing a process of forming a cap substrate of the semiconductor device shown in FIGS. 1A and 1B ;
- FIGS. 5A to 5D are schematic cross-sectional views for showing a process of manufacturing the semiconductor device using the base substrate and the cap substrate formed by the processes shown in FIGS. 3A to 3C and 4 A to 4 C;
- FIG. 6A is a schematic cross-sectional view of a leading electrode thereof as a modification of a leading electrode of the semiconductor device shown in FIGS. 1A and 1B .
- FIG. 6B is a schematic cross-sectional view of a leading electrode as another modification of the leading electrode of the semiconductor device shown in FIGS. 1A and 1B .
- FIGS. 7A to 7D and 8 A to 8 D are schematic cross-sectional views for showing a process of forming the leading electrodes shown in FIGS. 6A and 6B ;
- FIG. 9A is a schematic cross-sectional view of a part of a semiconductor device as a modification of the semiconductor device shown in FIGS. 1A and 1B ;
- FIG. 9B is a schematic cross-sectional view taken along a line IXB-IXB in FIG. 9A ;
- FIG. 10A is a schematic cross-sectional view of a leading electrode as a modification of a leading electrode of the semiconductor device shown in FIGS. 9A and 9B ;
- FIG. 10B is a schematic cross-sectional view of a leading electrode as a modification of the leading electrode of the semiconductor device shown in FIGS. 9A and 9B ;
- FIGS. 11A to 11D are schematic cross-sectional views for showing a process of forming the leading electrode shown in FIG. 10B ;
- FIG. 12A is a schematic cross-sectional view of a leading electrode as further another modification of the leading electrode of the semiconductor device shown in FIGS. 9A and 9B ;
- FIG. 12B is a schematic cross-sectional view taken along a line XIIA-XIIA in FIG. 12A ;
- FIG. 13A is a schematic cross-sectional view of a leading electrode as yet another modification of the leading electrode of the semiconductor device shown in FIGS. 9A and 9B ;
- FIG. 13B is a schematic cross-sectional view of a leading electrode as still another modification of the leading electrode of the semiconductor device shown in FIGS. 9A and 9B ;
- FIG. 14A is a schematic cross-sectional view of a part of a semiconductor device as a modification of the semiconductor device shown in FIGS. 9A and 9B ;
- FIG. 14B is a schematic cross-sectional view of a part of a semiconductor device as another modification of the semiconductor device shown in FIGS. 9A and 9B ;
- FIG. 14C is a schematic cross-sectional view of a leading electrode as a modification of a leading electrode of the semiconductor device shown in FIG. 14B ;
- FIGS. 15A to 15C are schematic cross-sectional views for showing a process of manufacturing the semiconductor device shown in FIG. 14A ;
- FIGS. 16A to 16D , 17 A to 17 D and 18 A to 18 C are schematic cross-sectional views for showing a process of forming the leading electrodes shown in FIGS. 14B and 14C ;
- FIG. 19A is a schematic cross-sectional view of a part of a semiconductor device as a modification of the semiconductor device shown in FIGS. 1A and 1B ;
- FIG. 19B is a schematic cross-sectional view of a part of a semiconductor device as another modification of the semiconductor device shown in FIG. 14B ;
- FIGS. 20A and 20B are schematic cross-sectional views for showing a process of forming a leading electrode of the semiconductor device shown in FIG. 19A ;
- FIGS. 21A to 21D are schematic cross-sectional views for showing a process of forming a leading electrode of the semiconductor device shown in FIG. 19B ;
- FIG. 22 is a schematic cross-sectional view of a part of a semiconductor device as further another modification of the semiconductor device shown in FIGS. 1A and 1B ;
- FIG. 23 is a schematic cross-sectional view of a part of a semiconductor device as an example of another use of the semiconductor device shown in FIGS. 1A and 18 ;
- FIG. 24 is a schematic cross-sectional view of a part of a semiconductor device as an example of the semiconductor device according to the embodiment.
- FIGS. 25A to 25D and 26 A to 26 C are schematic cross-sectional views for showing a process of manufacturing the semiconductor device shown in FIG. 24
- FIG. 27 is a schematic cross-sectional view of a part of a semiconductor device as an example of the semiconductor device according to the embodiment.
- FIGS. 28A to 28D and 29 A to 29 D are schematic cross-sectional views for showing a process of manufacturing the semiconductor device shown in FIG. 27 ;
- FIG. 30 is a schematic cross-sectional view of a part of a semiconductor device of a prior art.
- FIG. 31 is a schematic cross-sectional view of a part of a semiconductor device of another prior art.
- FIG. 1A is a schematic plan view of a part of a semiconductor device 100 as an example of the semiconductor device according to an embodiment.
- FIG. 1B is a schematic cross-sectional view taken along a line IB-IB in FIG. 1A .
- FIG. 1A is also a cross-section taken along a line IA-IA in FIG. 1B .
- FIG. 2 is a perspective view of a base substrate of the semiconductor device 100 shown in FIGS. 1A and 1B .
- FIGS. 1A , 1 B and 2 like parts which correspond to parts of the semiconductor devices 91 , 92 of FIGS. 30 and 31 , are designated with like reference characters.
- the semiconductor device 100 has a base substrate B 4 made of silicon and a cap substrate C 4 made of silicon.
- the base substrate B 4 and the cap substrate C 4 are bonded to each other at a bonding surface D 1 .
- the semiconductor device 100 includes a mechanical quantity sensor element using an inertia force.
- a sensing portion Se for detecting mechanical quantity such as acceleration and angular velocity is formed in a predetermined region R 1 of the base substrate B 4 .
- the cap substrate C 4 is formed with a recess 32 b .
- the cap substrate C 4 is bonded to the base substrate B 4 to oppose the predetermined region R 1 where the sensing portion Se is formed.
- the cap substrate C 4 seals a space defined by the recess 32 b and a trench 23 of the base substrate B 4 .
- the base substrate B 4 is a SOI (Silicon On Insulator) substrate having an embedded oxide film 20 , a SOI layer 21 and a support substrate 22 .
- the embedded oxide film 20 is disposed between the SOI layer 21 and the support substrate 22 .
- the base substrate B 4 has multiple base semiconductor regions Bs including base semiconductor regions Bs 1 , Bs 2 in a surface layer thereof.
- the base semiconductor regions Bs are provided by the SOI layer 21 .
- the base semiconductor regions Bs are insulated and separated from each other by the trench 23 that reaches the embedded oxide film 20 .
- the sensing portion Se includes a mechanical quantity sensor element for measuring acceleration or angular velocity.
- the mechanical quantity sensor element is constructed of some of the base semiconductor regions Bs.
- the base semiconductor region Bs 1 is a movable semiconductor region including a movable electrode Em.
- the movable electrode Em is formed by performing sacrifice layer etching on a part of the embedded oxide film 20 .
- the movable electrode Em is displaceable.
- the base semiconductor region Bs 2 is a fixed semiconductor region including a fixed electrode Es that is opposed to the movable electrode Em.
- capacitance is created between the opposed surfaces of the movable electrode Em and the fixed electrode Es.
- the movable electrode Em is displaced in a direction perpendicular to the opposed surfaces.
- the capacitance changes in accordance with a change in a distance between the opposed surfaces of the movable electrode Em and the fixed electrode Es.
- the change in capacitance is measured to detect the applied mechanical quantity. It is noted that, in the base substrate B 4 , other elements and circuits may be formed in regions other than the predetermined region R 1 .
- the cap substrate C 4 includes a single crystal silicon 30 , which can be precisely processed at a relatively low cost.
- the recess 32 b is formed at a position corresponding to the sensing portion Se of the base substrate B 4 .
- An insulating layer 32 a is formed on a lower surface of the single crystal silicon substrate 30 bonded to the base substrate B 4 .
- the insulating layer 32 a is, for example, made of silicon oxide (SiO 2 ).
- the base substrate B 4 and the cap substrate C 4 are bonded to each other through the bonding surface D 1 .
- the cap substrate is generally employed to protect various elements formed in a surface layer of a base substrate.
- the semiconductor device having the cap substrate as a method of forming an electrical connection between the various elements formed in the surface layer of the base substrate and external parts, it may be possible to directly connect a bonding wire to a surface of, the base substrate by a wire bonding technique through a through hole formed in the cap substrate.
- the through hole of the cap substrate needs to be large enough to allow the wire bonding.
- an area for making the electrical connection is likely to increase.
- a semiconductor device having a cap substrate needs a leading electrode that extends from the surface of a base substrate to an upper surface of the cap substrate to allow the electrical connection with an external part at an upper end thereof.
- the semiconductor device 100 has a leading electrode De 1 that extends from the surface of the base substrate B 4 to an upper surface of the cap substrate C 4 for facilitating an electrical connection between the mechanical quantity sensor element of the base substrate B 4 and the external part.
- the leading electrode De 1 includes a metal part 40 made of metal such as aluminum (Al), copper (Cu), chrome (Cr) tungsten (W), and platinum (Pt).
- a lower end of the leading electrode De 1 is connected to a predetermined base semiconductor region Bs.
- the leading electrode De 1 extends from the predetermined base semiconductor region Bs to the upper surface of the cap substrate C 4 , while passing through the cap substrate C 4 .
- “extending to the upper surface of the cap substrate C 4 ” means that an upper end of the leading electrode De 1 is located adjacent to the upper surface of the cap substrate C 4 .
- the upper end of the leading electrode De 1 is located at the same height as or higher than the upper surface of the cap substrate C 4 .
- a groove 35 is formed on a periphery of the leading electrode De 1 .
- the groove 35 is formed between an outer surface of the leading electrode De 1 and the cap substrate C 4 .
- the leading electrode De 1 is separated from the cap substrate C 4 by the groove 35 .
- FIG. 1B shows a condition where a bonding wire 60 is connected to the upper end of the leading electrode De 1 .
- the silicon cap substrate C 2 is divided into partial regions Ce through the insulating and separating trench 31 , and predetermined conductive regions Ce 1 , Ce 2 of the partial regions Ce, which connect to the insulated and separated base semiconductor region Bs, are used as the leading conductive regions to make electrical connections at the upper end thereof with the external parts by wire bonding, soldering or the like.
- the penetrating electrodes Ke which are provided by portions of the silicon cap substrate C 3 and separated through the grooves 15 , are used to make electrical connections at the upper end thereof with the external parts by the wire bonding, soldering or the like.
- the leading electrode De 1 is provided by the metal part 40 , which has high electric conductivity.
- the metal part 40 connects to the predetermined base semiconductor region Bs, that is, at a bonding portion Des shown by a dashed line in FIG. 2 .
- the metal part 40 passes through the cap substrate C 4 , and the upper end of the metal part 40 is located higher than the upper surface of the cap substrate C 4 . Therefore, the resistance of the leading electrode De 1 is smaller than the resistance of the conductive regions Ce 1 , Ce 2 and the penetrating electrodes Ke of the semiconductor devices 91 , 92 , which utilize portions of the silicone cap substrates C 2 , C 3 . Accordingly, the applicable range of the semiconductor device 100 increases.
- the groove 35 is provided between the leading electrode De 1 and the cap substrate C 4 . That is, the leading electrode De 1 has a so-called air isolation structure.
- the cap substrate C 4 of the semiconductor device 100 does not have the insulating and separating trench 31 for forming the partial regions Ce as the semiconductor device 91 .
- parasitic capacitance will not be easily formed due to the electric substance such as the insulating and separating trench 31 . Further, since the groove 35 is formed around the leading substrate de 1 , stress due to a thermal expansion difference between the leading electrode De 1 and the cap substrate C 4 can be reduced.
- the groove 15 is formed around the penetrating electrode Ke, the parasitic capacitance will not be easily formed.
- the groove 15 reaches the base substrate B 3 .
- the insulating layer 32 a is formed under the groove 35 , and thus the groove 35 does not reach the base substrate B 4 .
- the groove 15 passing through the cap substrate C 3 and reaching the base substrate B 3 is preferable as in the semiconductor device 92 of FIG. 31 .
- the insulating layer 32 a is positioned at the bottom of the groove 35 . That is, the insulating layer 32 a is exists around the base of the leading electrode De 1 . Therefore, the insulating layer 32 a serves as a support portion to increase the strength of the leading electrode De 1 , which is particularly required during the wire bonding or soldering the upper end of the leading electrode De 1 .
- the upper end of the leading electrode De 1 is located higher than the upper surface of the cap substrate C 4 .
- the upper end of the leading electrode De 1 is at the same height as or lower than the upper surface of the cap substrate C 4 . Therefore, the wire bonding and the soldering are easily conducted at the upper end of the leading electrode De 1 .
- the resistance of the leading electrode De 1 is reduced and the parasitic capacitance will not be easily formed around the leading electrode De 1 .
- the cap substrate C 4 is provided by the single crystal silicon substrate 30 , which is easily processed at a relatively low cost. Further, since the leading electrode De 1 is constructed of the metal part 40 , the cap substrate C 4 can be provided by a poly crystal substrate, an intrinsic silicon substrate in which glass and impurities are not doped, or other similar insulating substrates, in place of the single crystal silicon substrate.
- FIGS. 3A-3C are schematic cross-sectional views for showing a process of forming the base substrate B 4 .
- a SOI substrate B 4 a including the embedded oxide film 20 between the SOI layer 21 and the support substrate 22 is prepared.
- the SOI substrate B 4 a is formed by a substrate bonding technique, for example.
- the embedded oxide film 20 is a silicon oxide (SiO 2 ) film
- the support substrate 22 is a single crystal silicon substrate having a specific resistance in a range of 0.001 to 1 ⁇ cm, for example.
- the SOI layer 21 is used for forming various elements.
- the SOI layer 21 is a single crystal silicon layer containing N+ type impurities such as arsenic (As) and phosphorous (P) with a specific resistance of 0.001 to 1 ⁇ cm and a thickness of 1 to 50 ⁇ m.
- the SOI layer 21 has a thickness of 10 to 20 ⁇ m, and the SOI layer 21 and the support substrate 22 are formed by bonding N+ type single crystal substrates containing impurities at high concentrations.
- the concentration of impurities of the SOI layer 21 is as high as possible, that is, the specific resistance of the SOI layer 21 is as small as possible.
- the SOI layer 21 contains the N+ type impurities.
- all the impurities can be P+ type impurities, such as born (B).
- a mask pattern (not shown) of such as a photoresist and an oxide film is formed on the SOI layer 21 .
- a trench 23 that has substantially perpendicular walls and reaches the oxide film 20 is formed by photolithography and deep-etching techniques.
- the SOI layer 21 is divided to form the multiple base semiconductor regions Bs, which are insulated and separated from adjacencies, in a surface layer of the SOI substrate B 4 a.
- the embedded oxide film 20 is partly removed through the trench 23 by an etching technique with hydrogen fluoride (HF) gas.
- HF hydrogen fluoride
- the base substrate B 4 for the semiconductor device 100 is formed.
- FIGS. 4A to 4C are schematic cross-sectional views for showing a process of forming the cap substrate C 4 .
- the single crystal silicon substrate 30 is prepared.
- a mask pattern (not shown) of such as a photoresist or an oxide film is formed on a lower surface of the silicon substrate 30 .
- the recess 32 b is formed by photolithography and etching techniques.
- the insulating layer 32 a of the silicon oxide (SiO 2 ) is formed on the lower surface of the silicon substrate 30 by a thermal oxidation technique. In this way, the cap substrate C 4 for the semiconductor device 100 is formed.
- FIGS. 5A to 5D are schematic cross-sectional views for showing process of manufacturing the semiconductor device 100 using the base substrate B 4 and the cap substrate C 4 respectively formed by the processes shown in FIGS. 3A to 3C and FIGS. 4A to 4D .
- the base substrate B 4 and the cap substrate C 4 are bonded to each other.
- the cap substrate C 4 is positioned relative to the base substrate B 4 such that the cap substrate C 4 is opposed to the predetermined region R 1 where the mechanical quantity sensor element has been formed, and is laid on the base substrate B 4 .
- the lower surface of the cap substrate C 4 is bonded to the upper surface of the base substrate B 4 .
- the cap substrate C 4 and the base substrate B 4 are bonded using an arbitrary adhesive.
- the cap substrate C 4 and the base substrate B 4 are securely bonded at the bonding surface D 1 , and the space defined by the recess 32 b and the trench 23 is fully sealed.
- the leading electrode De 1 is formed, as shown in FIGS. 5B to 5D .
- a trench 41 is formed at a predetermined position of the cap substrate C 4 .
- the trench 41 is formed to reach the predetermined base semiconductor region Bs of the base substrate B 4 .
- the metal part 40 is embedded in the trench 41 , and then an upper surface of the cap substrate C 4 is etched so that the upper end of the metal part 40 becomes higher than the upper surface of the cap substrate C 4 .
- FIG. 5D a portion of the silicon substrate 30 around the trench 41 in which the metal part 40 is embedded is etched to form the groove 35 around the trench 41 .
- the leading electrode De 1 is formed, and the semiconductor device 100 is manufactured. It is noted that, in an actual manufacturing process, the base substrate B 4 and the cap substrate C 4 are prepared in the condition of wafers, and the finished semiconductor devices 100 are produced by cutting the wafers into multiple chips after the process of FIGS. 5A to 5D .
- FIG. 6A is a schematic cross-sectional view of the leading electrode De 1 and the neighboring structure thereof as a modification.
- FIG. 6B is a schematic cross-sectional view of the leading electrode De 1 and the neighboring structure thereof as another modification.
- an insulating layer 42 is formed at the bottom portion of the groove 35 a .
- the insulating layer 42 is separate from the insulating layer 32 a , and has a thickness greater than a thickness of the insulating layer 32 a .
- strength of the leading electrode De 1 required for forming the electrical connection to the external part, that is, for conducting the wire bonding and the soldering can be increased, as compared with a structure shown in FIG. 1B .
- a groove 35 b is formed around the leading electrode De 1 .
- the groove 35 b reaches the base substrate B 4 , similar to the structure around the penetrating electrode Ke of the semiconductor device 92 shown in FIG. 31 .
- parasitic capacitance due to the leading electrode De 1 can be further reduced, as compared with the structures shown in FIGS. 1B and 6A .
- FIGS. 7A to 7D and 8 A to 8 D are schematic cross-sectional views for showing a process of forming the structures shown in FIGS. 6A and 6B .
- the process shown in FIGS. 7A to 7D and 8 A to 8 D is performed after the base substrate B 4 and the cap substrate C 4 are bonded in the manner shown in FIGS. 5A and 5B .
- a silicon nitride (Si 3 N 4 ) film 30 a is formed on the single crystal silicon substrate 30 of the cap substrate C 4 by a low pressure chemical vapor deposition (LPCVD) technique or a plasma chemical vapor deposition (CVD) technique.
- LPCVD low pressure chemical vapor deposition
- CVD plasma chemical vapor deposition
- the silicon nitride film 30 a can be formed on the single crystal silicon substrate 30 before the cap substrate C 4 is bonded to the base substrate B 4 .
- a mask pattern (not shown) of a photoresist is formed on the silicon nitride film 30 a , and then a trench 41 a is formed at a predetermined position of the cap substrate C 4 by etching from the top of the silicon nitride film 30 a .
- the trench 41 a is formed to reach the predetermined base semiconductor region Bs.
- a silicon oxide film 42 a is deposited on an entire surface, that is, on the silicon nitride film 30 a and walls of the trench 42 a by a plasma CVD technique.
- FIG. 7D the silicon oxide film 42 a formed on the silicon nitride film 30 a and the bottom wall of the trench 41 a is removed.
- the silicon oxide film 42 a on the side wall of the trench 41 a remains.
- a metal layer 40 a which is for example made of aluminum (Al), is deposited on an entire surface, that is, on the silicon nitride film 30 a and inside of the trench 41 a .
- the trench 41 a is filled with the metal layer 40 a.
- the metal layer 40 a on the silicon nitride film 30 a is removed by an etchback technique.
- the metal layer 40 a inside of the trench 41 a remains to form the metal part 40 of the leading electrode De 1 of FIGS. 6A and 6B .
- the groove 35 a is formed by removing the silicon oxide film 42 a formed on the side wall of the trench 41 a .
- the silicon oxide film 42 a remains at a lower portion of the groove 35 a .
- the insulating layer 42 shown in FIG. 6A is formed.
- leading electrode De 1 and its neighboring portion shown in FIG. 6A are formed.
- the leading electrode De 1 and its neighboring portion shown in FIG. 6B are formed by entirely removing the silicon oxide film 42 a from the side walls of the trench 41 a , as shown in FIG. 8D .
- trench forming step for forming the trench 41 a in the cap substrate C 4 to reach the predetermined base semiconductor region Bs is performed.
- the meal layer 40 a is embedded in the trench 41 a to form the metal part 40 of the leading electrode De 1 .
- the groove 35 a , 35 b is formed at portions of the trench 41 a.
- FIG. 9A is a schematic plan view of a part of a semiconductor device 110 as a modification of the semiconductor device 100 shown in FIGS. 1A and 1B .
- FIG. 9B is a schematic cross-sectional view taken along a line IXB-IXB in FIG. 9A .
- FIG. 9A is also a schematic cross-sectional view taken along a line IXA-IXA in FIG. 9B .
- like parts are denoted by like reference characters as those of the semiconductor device 100 shown in FIGS. 1A and 1B .
- the semiconductor device 110 has the same base substrate B 4 as that of the semiconductor device 100 of FIGS. 1A and 1B .
- a leading electrode De 2 and its neighboring structure are different from the leading electrode De 1 and its neighboring structure of the cap substrate C 4 of the semiconductor device 100
- the leading electrode De 1 of the semiconductor device 100 is constructed of only the metal part 40 . Further, although the groove 35 is formed between the cap substrate C 4 and the leading electrode De 1 , the cap substrate C 4 is constructed of a single member, that is, the silicon substrate 30 .
- a groove 36 is formed in the single crystal silicon substrate 30 to divide the single crystal silicon substrate 30 into a portion surrounding the leading electrode De 2 and its peripheral portion. That is, the cap substrate C 5 is divided into multiple partial regions Cs by the grooves 36 . The partial regions Cs are insulated and separated by the grooves 36 .
- the leading electrode De 2 is constructed of a predetermined partial region Cs 1 and the metal part 40 formed in the predetermined partial region Cs 1 .
- the leading electrode De 2 of the semiconductor device 110 has the metal part 40 that contacts the base semiconductor region Bs and extends to the upper surface of the cap substrate C 5 .
- the resistance of the leading electrode De 2 is reduced, as compared with that in the semiconductor devices 91 , 92 of FIGS. 30 , 31 . With this, the applicable range increases.
- the groove 36 is formed between the leading electrode De 2 and the cap substrate C 5 , similar to the semiconductor device 100 of FIGS. 1A and 1B Therefore the parasitic capacitance will not be easily formed on a periphery of the leading electrode De 2 .
- the leading electrode De 2 of the semiconductor device 110 is different from the leading electrode De 1 of the semiconductor device 100 since the leading electrode De 2 includes the predetermined partial region Cs 1 as an element in addition to the metal part 40 .
- the predetermined partial region Cs 1 is formed around the metal part 40 , but is insulated and separated from the adjacent partial portion Cs by the groove 36 .
- the resistance can be reduced by the metal part 40 as the element of the leading electrode De 2 . Furthermore, because the predetermined partial region Cs 1 around the metal part 40 serves as a support part, strength of the leading electrode De 2 required at the time of wire bonding and soldering can be increased.
- IC circuits can be formed in other partial regions Csa, Csb of the partial regions Cs, as shown in FIG. 9A .
- FIGS. 10A and 10B are schematic cross-sectional views of the leading electrode De 2 and the neighboring portion thereof as modifications of the structure shown in FIGS. 9A and 9B .
- a groove 36 a is formed to pass through the cap substrate C 5 and reach the base substrate B 4 , similar to the groove 35 b shown in FIG. 6B . Therefore, in the structure shown in FIG. 10A parasitic capacitance due to the leading electrode De 2 is further reduced, as compared with the structure shown in FIGS. 9A and 9B .
- the silicon nitride film 30 a remains, which has been formed at the beginning of the forming of the leading electrode De 2 as shown in FIG. 7A , on the single crystal silicon substrate 30 . Further, the upper end of the metal part 40 is on the same height as the upper surface of the silicon nitride film 30 a . That is, the silicon nitride film 30 a is formed above the predetermined partial region Cs 1 formed around the metal part 40 , and the upper surface of the silicon nitride film 30 is coplanar with the upper surface of the metal part 40 .
- the silicon nitride film 30 a serves as a support portion, strength of the leading electrode De 2 required at the time of wire bonding and soldering is increased, as compared with that of the leading electrode shown in FIG. 10A .
- FIGS. 11A to 11D are schematic cross-sectional views for showing a process of forming the leading electrode De 2 and its neighboring structure shown in FIG. 10B .
- the process begins from the similar condition shown in FIG. 7A after the base substrate B 4 and the cap substrate C 5 are bonded.
- a mask pattern (not shown) of a photoresist is formed on the silicon nitride film 30 a , and then a trench 41 a is formed at a predetermined position of the cap substrate C 5 by etching from the top of the silicon nitride film 30 a .
- the trench 41 a is formed to reach the predetermined base semiconductor region Bs.
- the metal layer 40 a is deposited on an entire surface, that is, over the silicon nitride film 30 a and inside of the trench 41 a .
- the trench 41 b is filled with the metal layer 40 a.
- the metal layer 40 a above the silicon nitride film 30 a is removed by an etchback technique.
- the metal layer 40 a inside of the trench 41 b remains to form the metal part 40 of the leading electrode De 2 shown in FIG. 10B .
- a mask pattern (not shown) of a photoresist is formed on the silicon nitride film 30 a , and the groove 36 a is formed by etching from the top of the mask pattern.
- leading electrode De 2 and its neighboring structure shown in FIG. 10B are formed. It is noted that the leading electrode De 2 and its neighboring structure shown in FIG. 10A are formed by removing the silicon nitride film 30 a after the step shown in FIG. 11D . It is also noted that the leading electrode De 2 and its neighboring structure shown in FIG. 9B are formed by forming the groove 36 a while remaining the insulating layer 32 a at the bottom of the groove 36 a in the step of FIG. 11D and further removing the silicon nitride film 30 a after the step of FIG. 11D .
- FIG. 12A is a plan view of the leading electrode De 2 and the neighboring structure thereof as further another modification of the structure shown in FIGS. 9A and 9B .
- FIG. 12B is a schematic cross-sectional view taken along a line XIIB-XIIB in FIG. 12A .
- FIG. 12A is also across-section taken along a line XIIA-XIIA in FIG. 12B .
- a cap substrate C 10 shown in FIGS. 12A and 12B includes an insulating substrate 30 z made of intrinsic silicon in which impurities are not doped. That is, the cap substrate C 10 is different from the cap substrate C 5 of FIGS. 9A , 9 B, 10 A and 10 B, which includes the single crystal silicon substrate 30 in which the impurities are doped.
- a groove 36 b having a substantially C-shape is formed around the metal part 40 of the leading electrode De 2 .
- a portion of the substrate 30 z formed around the metal, part 40 is connected to an adjacent portion of the substrate 30 z , that is, on a periphery of the groove 36 b through an opening of the C-shape of the groove 36 b.
- FIGS. 13A and 13B are schematic cross-sectional views of a leading electrode De 3 and a neighboring structure thereof as still other modifications of the structure shown in FIGS. 9A and 9B .
- the leading electrodes De 3 shown in FIGS. 13A and 13B are provided by subdividing the leading electrodes De 2 of FIGS. 10A and 10B , respectively. That is, the metal part 40 is constructed of multiple portions in a predetermined partial region Cs 2 , which is one of the partial regions Cs and separated and insulated from a peripheral partial region Cs by the groove 36 a.
- the silicon nitride film 30 a formed above the single crystal silicon substrate 30 during the manufacturing process is removed.
- the silicon nitride film 30 a remains on the single crystal silicon substrate 30 .
- the bonding wire 60 and the solder can be embedded between the divided portions of the metal part 40 , which protrude higher than the upper surface of the partial region Cs 2 . Therefore, reliability of connection improves.
- FIG. 14A is a schematic cross-sectional view of a part of a semiconductor device 111 as a modification of the semiconductor device 110 shown in FIGS. 9A and 9B .
- FIG. 14B is a schematic cross-sectional view of a part of a semiconductor device 112 as another modification of the semiconductor device 110 shown in FIGS. 9A and 9B .
- FIG. 14C is a schematic cross-sectional view of a leading electrode De 5 and its neighboring structure as a modification of a leading electrode De 5 and its neighboring structure of the semiconductor device 112 shown in FIG. 14B .
- the base substrates B 4 of the semiconductor devices 111 , 112 are the same as the base substrates B 4 of the semiconductor devices 100 , 110 of FIGS. 1A , 1 B, 9 A and 9 B.
- the semiconductor devices 111 , 112 have cap substrates C 7 , C 8 and leading electrodes De 4 , De 5 , which have different structures from the cap substrates C 5 and the leading electrode De 2 of the semiconductor device 110 of FIGS. 9A and 9B .
- the leading electrode De 2 of the semiconductor device 110 is constructed of the predetermined partial region Cs 1 and the metal part 40 formed at the center of the partial region Cs 1 .
- the leading electrode De 4 of the semiconductor device 111 is constructed of a predetermined partial region Cs 3 , which is one of the partial regions Cs, and the metal part 40 that covers a side wall and an upper surface of the partial region Cs 3 .
- the metal part 40 covers the upper surface of the partial region Cs 4 , connecting area between the metal part 40 and the bonding wire or the solder is increased, as compared with the leading electrode De 2 of the semiconductor device 110 shown in FIGS. 9A and 9B in which the metal part 40 does not cover the upper surface of the partial region Cs 1 . Therefore, the electrical connection further improves.
- the leading electrode De 5 of the semiconductor device 112 is constructed of the predetermined partial region Cs 4 and the metal part 40 covering a lower surface of the partial region Cs 4 in addition to the side wall and the upper surface of the partial region Cs 4 .
- the connection between the leading electrode De 5 and the predetermined base semiconductor region Bs of the base substrate B 4 further improves, as compared with the connection between the leading electrode De 4 and the predetermined base semiconductor region Bs of the semiconductor device 111 shown in FIG. 14A .
- the metal part 40 of the leading electrode De 4 of the semiconductor device 111 connects to the base semiconductor region Bs and extends to the same height as or higher than the upper surface of the cap substrate C 7 .
- the metal part 40 of the leading electrode De 5 of the semiconductor device 112 connects to the base semiconductor region Bs and extends to the same height as or higher than the upper surface of the cap substrate C 8 .
- resistance of the leading electrodes De 4 , De 5 is reduced, as compared with that of the semiconductor devices 91 , 92 of FIGS. 30 and 31 . Therefore, the applicable ranges of the semiconductor devices 111 , 112 increase.
- a groove 37 a is formed between the leading electrode De 4 and the cap substrate C 7 . Therefore parasitic capacitance will not be easily formed on a periphery of the leading electrode De 4 .
- a groove 37 b is formed between the leading electrode De 5 and the cap substrate C 8 . Therefore, parasitic capacitance will not be easily formed on a periphery of the leading electrode De 5 .
- a groove 37 c is formed around the leading electrode De 5 , and an insulating layer 43 , which is separate from the insulating layer 32 a of the cap substrate C 8 , is formed at the bottom portion of the groove 37 c . Therefore, strength of the leading electrode De 5 of FIG. 140 required at the time of wire bonding and soldering is increased, as compared with that of the leading electrode De 5 of FIG. 14B .
- FIGS. 15A to 15C are schematic cross-sectional views for showing a process of forming the semiconductor device 111 of FIG. 14A .
- the groove 37 a is formed at a predetermined position of the cap substrate C 7 to reach the insulating layer 32 a .
- the single crystal silicon substrate 30 is divided into the partial regions Cs including a partial region Cs 3 .
- the insulating layer 32 a at the bottom portion of the groove 37 a is further etched to form a trench 41 c reaching the predetermined base semiconductor region Bs of the base substrate B 4 .
- the metal part 40 is formed successively inside the trench 41 c , on the side wall of the partial region Cs 3 , and on an upper surface of the partial region Cs 3 .
- the leading electrode De 4 is formed, and thus the semiconductor device 111 of FIG. 14A is manufactured.
- FIGS. 16A to 16D , 17 A to 17 D and 18 A to 180 are schematic cross-sectional views for showing a process of forming the leading electrodes De 5 and neighboring structures thereof shown in FIGS. 14B and 14C .
- the process of forming the leading electrode De 5 of the semiconductor device 112 shown in FIG. 14B is different from the processes of forming the leading electrodes De 1 to De 4 .
- To form the leading electrode De 5 of the semiconductor device 112 shown in FIG. 14B necessary structures are formed in the cap substrate C 8 before the base substrate B 4 and the cap substrate C 8 are bonded to each other.
- the single crystal silicon substrate 30 is prepared.
- a mask pattern (not shown) of a photoresist is formed on the single crystal silicon substrate 30 , and then a trench 41 d is formed by etching from the top.
- a metal layer 40 b made of such as aluminum (Al) is deposited entirely over the single crystal silicon substrate 30 including the trench 41 d.
- a silicon oxide (SiO 2 ) film 43 a is deposited entirely over the metal layer 40 b by a plasma CVD technique.
- the silicon oxide film 43 a is removed by an etchback technique so that the metal layer 40 b on the surface of the single crystal silicon substrate 30 exposes, and only, the silicon oxide film 43 a inside of the trench 41 d remains.
- a predetermined mask pattern (not shown) is formed, and the metal layer 40 b is partly removed by an etching technique.
- the single crystal silicon substrate 30 is turned upside down, and then is grinded from the top so that the silicon oxide film 43 a embedded inside of the trenches 41 d is exposed. In this way, the single crystal silicon substrate 30 is divided to form the insulated and separated multiple partial regions Cs including a partial region Cs 4 .
- a metal layer 40 c made of such as aluminum (Al) is deposited entirely over the single crystal silicon substrate 30 .
- a predetermined mask pattern (not shown) is, formed on the metal layer 40 c , and then the metal layer 40 c is partly removed by etching.
- the metal part 40 that covers the side wall, the upper surface and the lower surface of the partial region Cs 4 is formed.
- the cap substrate C 8 before being bonded is formed.
- the base substrate B 4 and the cap substrate C 8 which have been formed beforehand, are bonded to each other.
- the trench 37 c is formed by etching the silicon oxide film 43 a from the top.
- the silicon oxide film 43 a remains at the bottom of the trench 37 c to provide the insulating layer 43 .
- the leading electrode De 5 and its neighboring structure shown in FIG. 14C are formed.
- the groove 37 b is formed as shown in FIG. 18C .
- the leading electrode De 5 and its neighboring structure shown in FIG. 14B are formed.
- the leading electrode forming process can be partly conducted during the cap substrate forming process. That is, the leading electrode De 5 can be formed in a condition of being connected to the cap substrate C 8 while the cap substrate C 8 is formed. Then, the lower surface of the leading electrode De 5 is connected to the predetermined base semiconductor region Bs while the cap substrate C 8 is bonded to the base substrate B 4 . Thereafter, the grooves 37 b , 37 c are formed.
- FIG. 19A is a schematic cross-sectional view of a part of a semiconductor device 113 as a modification of the semiconductor device 100 shown in FIGS. 1A and 1B .
- FIG. 19B is a schematic cross-sectional view of a part of a semiconductor device 114 as a modification of the semiconductor device 112 shown in FIG. 14B .
- a leading electrode De 6 has an upper surface to which the electrical connection is formed such as by the wire bonding and the soldering.
- the upper surface has an area greater than that of a lower surface, which is connected to the base semiconductor region Bs to form the bonding portion Des.
- a leading electrode De 7 of the semiconductor device 114 shown in FIG. 19B has an upper surface with an area greater than a lower surface thereof.
- FIGS. 20A and 20B are schematic cross-sectional views for showing a process of forming the leading electrode De 6 and its neighboring structure of the semiconductor device 113 shown in FIG. 19A .
- the process begins from the condition shown in FIG. 8A .
- the metal layer 40 a formed on the silicon nitride film 30 a is etched in a predetermined pattern so that the metal part 40 having the upper surface with the greater area than its lower surface is formed.
- the silicon oxide film 42 a on the side wall of the trench 41 a and the silicon nitride film 30 a on the single crystal silicon substrate 30 are removed in a predetermined order to form the groove 35 b.
- leading electrode De 6 and its neighboring structure of the semiconductor device 113 shown in FIG. 19A are formed.
- FIGS. 21A to 21D are schematic cross-sectional views for showing a process of forming the leading electrode De 7 and its neighboring structure of the semiconductor device 114 shown in FIG. 19B .
- the process begins from the condition shown in FIG. 17B .
- the metal layer 40 c made of such as aluminum (Al) is deposited over an entire surface of the single crystal silicon substrate 30 with a thickness greater than a thickness of the metal layer 40 c of FIG. 17C
- the metal layer 40 c is etched in a predetermined pattern.
- the metal part 40 having the upper surface with the greater area than that of the lower surface is formed.
- FIG. 21D the silicon oxide film 43 a is fully removed by an etching technique to form the groove 37 b.
- leading electrode De 1 and its neighboring structure of the semiconductor device 114 shown in FIG. 19B is formed.
- FIG. 22 is a schematic cross-sectional view of a part of a semiconductor device 115 as further another modification of the semiconductor device 100 shown in FIGS. 1A and 1B .
- the semiconductor device 115 shown in FIG. 22 has an integrated circuit (IC circuit) 101 on a partial region Csc of the single crystal silicon substrate 30 in addition to the structure of the semiconductor device 100 shown in FIG. 1B .
- the partial region Csc is one of the partial regions Cs of the cap substrate C 4 , and seals the sensing portion Se of the base substrate B 4 .
- the integrated circuit can be formed in the predetermined partial region of the cap substrate, which is insulated and separated.
- FIG. 23 is a schematic cross-sectional view of a part of the semiconductor device 100 for showing another applicable example.
- the upper end of the leading electrode De 1 is exemplarily connected to the wire bonding 60 to be electrically connected to an external part.
- the semiconductor device 100 is mounted to a separate single crystal silicon substrate 70 having an integrated circuit (IC circuit) IC 2 by a flip-chip technique.
- the end surfaces of the metal parts 40 constructing the leading electrodes De 1 are electrically connected to pad electrodes 71 formed on the single crystal silicon substrate 70 by solders 61 . In this way, the electrical connections of the end surfaces of the leading electrodes De 1 to the external parts can be formed by either the wire bonding or the soldering.
- FIG. 24 is a schematic cross-sectional view of a part of a semiconductor device 120 as an example of the semiconductor device according to the embodiment.
- the semiconductor device 120 has two base substrates B 5 , B 6 and a cap substrate C 9 .
- the base substrates B 5 , B 6 are bonded on opposite sides of the cap substrate C 9 .
- the base substrate B 5 is provided with an angular velocity sensor element (a gyro sensor element).
- the base substrate B 6 is provided with an acceleration sensor element.
- the base substrate B 5 and the second substrate B 6 are electrically connected to each other through leading electrodes De 8 formed in the cap substrate C 9 .
- the semiconductor device 120 carries the angular velocity sensor element and the acceleration sensor element, it is configured compact and wiring resistance of the semiconductor device 120 is reduced.
- the cap substrate C 9 has a groove 38 formed to divide the single crystal silicon substrate 30 . That is, the cap substrate C 9 is divided into multiple partial regions Cs, which are insulated and separated from each other, by the groove 38 .
- the leading electrode De 8 is constructed of the predetermined partial region Cs 5 of the partial regions Cs and the metal part 40 formed around the partial region Cs 5 .
- the metal part 40 is formed on the side wall of the partial region Cs 5 .
- the metal part 40 connects to the base semiconductor region Bs and extends to the upper surface of the cap substrate C 9 .
- both the end surfaces of the metal part 40 are on the same heights as the opposite surfaces of the cap substrate C 9 and connect to the base semiconductor regions Bs of the base substrates 85 , B 6 .
- FIGS. 25A to 25D and FIGS. 26A to 26C are schematic cross-sectional views for showing a process of manufacturing the semiconductor device 120 shown in FIG. 24 .
- the base substrate B 5 having the angular velocity sensor element is formed.
- a primary cap substrate C 9 a having a primary leading electrode De 8 a which will be the leading electrode De 8 , is formed.
- a primary groove 38 a is formed in the single crystal silicon substrate 30 of the primary cap substrate C 9 a , and further a metal layer 40 d is formed inside of the primary groove 38 a.
- the primary cap substrate C 9 a shown in FIG. 25B is bonded to the base substrate B 5 shown in FIG. 25A .
- the primary cap substrate C 9 a and the base substrate B 5 are bonded to each other by a silicon direct bonding technique, which is conducted at a low temperature in a vacuum state.
- the primary cap substrate C 9 a is grinded from the top to a position where the primary groove 38 a penetrates through the primary cap substrate C 9 a .
- the groove 38 of the semiconductor device 120 is formed.
- the cap substrate C 9 is provided by the primary cap substrate C 9 a , which is divided into the multiple partial regions Ce by the groove 38 , and the metal part 40 as the element of the leading electrode De 8 is provided by the metal layer 40 d.
- FIG. 26B the primary base substrate B 6 a , which has been formed to have the acceleration sensor element as shown in FIG. 26A , is turned upside down and bonded to the cap substrate C 9 .
- FIG. 26C wiring processing for making electrical connections is conducted in the primary base substrate B 6 a , and thus the base substrate B 6 is finished.
- the semiconductor device 120 shown in FIG. 24 is manufactured.
- the primary groove 38 a is formed in the primary cap substrate C 9 a in the cap substrate forming step.
- the metal layer 40 d is formed on the side wall of the primary groove 38 a , as a part of the leading electrode forming step, to form a primary leading electrode De 8 a .
- the base substrate B 5 and the primary cap substrate C 9 a are bonded in such a manner that the opening of the primary groove 38 a is opposed to the upper surface of the base substrate B 5 . After the substrate bonding step, as shown in FIG.
- the primary cap substrate C 9 a is grinded from the top, that is, from a side opposite to the base substrate B 5 , to make the cap substrate C 9 .
- the primary leading electrode De 8 a and the primary groove 38 a respectively, become the leading electrode De 8 and the groove 38 .
- the metal layer 40 d formed on the side wall of the primary groove 38 a becomes the metal part 40 of the leading electrode De 8 .
- the cap substrate C 4 to C 10 is bonded to the base substrate B 4 to B 6 to protect the base substrate B 4 to B 6 .
- the leading electrode De 1 to De 8 for making the electrical connection with the external part at the end thereof is formed such that the resistance of the leading electrode De 1 to De 8 is reduced and the parasitic capacitance around the leading electrode De 1 to De 8 will not be easily formed.
- the above-described semiconductor devices 110 , 110 to 114 and 120 as examples of the semiconductor device according to the embodiment each has the mechanical quantity sensor element for detecting acceleration and/or angular velocity.
- the semiconductor device according to the embodiment can have pressure sensor element, micro electro mechanical system (MEMS) resonator, infrared radiation sensor element, or any other semiconductor sensor element.
- MEMS micro electro mechanical system
- FIG. 27 is a schematic cross-sectional view of a semiconductor device 130 having a pressure sensor element PS as an example of the semiconductor device according to the embodiment.
- a pressure sensor element PS as an example of the semiconductor device according to the embodiment.
- the semiconductor device 130 has a base substrate B 7 .
- the base substrate B 7 includes a single crystal silicon substrate 25 .
- the thin single crystal silicon layer 24 having different conductivity types is formed at an upper surface layer of the single crystal silicon substrate 25 .
- a deep, groove 26 is formed at a predetermined region R 2 of the base substrate B 7 .
- the groove 26 extends from a bottom surface to an upper surface of the single crystal silicon substrate 25 , and a membrane Me is formed above the groove 26 .
- the single crystal silicon layer 24 has multiple impurity diffused regions (base semiconductor regions) Bd, which are insulated and separated from adjacencies by PN-junction separation, in the predetermined region R 2 .
- the membrane Me also has impurity diffused regions Bd 1 , Bd 2 .
- the impurity diffused regions Bd 1 , Bd 2 serve as a pressure sensor element PS. That is, in the semiconductor device 130 , the membrane Me displaces in accordance with pressure applied through the groove 26 . Thus, a change in resistance of the impurity diffused regions Bd 1 , Bd 2 in accordance with the displacement is measured to detect the applied pressure.
- a cap substrate C 11 is bonded to the base substrate B 7 made of silicon at the bonding surface D 1 and a sealed space is formed above the membrane Me.
- the semiconductor device 130 has a leading electrode De 9 constructed of the metal part 40 .
- a lower end of the leading electrode De 9 connects to an impurity diffused region (base semiconductor region) Bd 3 of the base substrate B 7 .
- the leading electrode De 9 extends from the upper surface of the base substrate B 7 to the upper surface of the cap substrate C 4 through the groove 35 of the cap substrate C 11 .
- an upper end of the metal part 40 is located higher than the upper surface of the cap substrate C 11 .
- the bonding wire 60 is connected to an upper end of the leading electrode De 9 .
- FIGS. 28A to 28D and FIGS. 29A to 29D are schematic cross-sectional views for showing a process of manufacturing the semiconductor device 130 shown in FIG. 27 .
- the base substrate 87 is formed. Specifically, the thin single crystal silicon layer 24 having the different conductivity types is formed at the upper surface layer of the single crystal silicon substrate 25 .
- FIG. 18B structures such as the impurity diffused regions (base semiconductor regions) Bd, Bd 1 to Bd 3 as shown in FIG. 27 , except the groove 26 , are formed in the predetermined region R 2 of the single crystal silicon layer 24 .
- the cap substrate C 11 is formed.
- the insulating layer 32 a and the recess 32 b are formed on the lower surface of the single crystal silicon substrate 30 , in the similar manner as the cap substrate forming process shown in FIGS. 4A to 4C .
- the base substrate B 7 formed in the step shown in FIG. 28B and the cap substrate C 11 formed in the step shown in FIG. 28C are positioned relative to each other and bonded to each other.
- a trench 44 is formed at a predetermined position of the cap substrate C 11 to reach the impurity diffused region Bd 3 of the base substrate B 7 .
- the metal part 40 is embedded in the trench 44 , and then the upper surface of the cap substrate C 11 , that is, the upper surface of the single crystal silicon substrate 30 is etched such that the upper end of the metal part 40 is located higher than the upper surface of the cap substrate C 11 .
- FIG. 29C a peripheral portion of the trench 44 in which the metal part 44 has been embedded is etched to form the groove 35 .
- FIG. 29D the bonded base substrate B 7 and cap substrate C 11 is turned upside down, and the groove 26 is formed from a back side, that is, from the top in FIG. 29D .
- the membrane Me as a thin membrane portion, is formed. Accordingly, the pressure sensor element PS is formed.
- the semiconductor device 130 shown in FIG. 27 has the leading electrode De 9 constructed of the metal part 40 , and the groove 35 is formed between the metal part 40 and the cap substrate C 11 .
- the upper end of the leading electrode De 9 allows the electrical connection with the external part. Therefore, resistance of the leading electrode De 9 is reduced, and parasitic capacitance will not be easily formed around the leading electrode De 9 .
- the semiconductor device according to the embodiment can be implemented by combining the above described exemplary semiconductor devices in various ways. Also, as an example of the semiconductor device according to the embodiment, a semiconductor device having a chip in which the mechanical quantity sensor elements, such as the acceleration sensor element and the angular velocity sensor element as shown in FIG. 1 and the pressure sensor element PS as shown in FIG. 27 are formed and the leading electrode constructed of the metal part separated from the cap substrate by the groove is applicable.
- the mechanical quantity sensor elements such as the acceleration sensor element and the angular velocity sensor element as shown in FIG. 1 and the pressure sensor element PS as shown in FIG. 27 are formed and the leading electrode constructed of the metal part separated from the cap substrate by the groove is applicable.
Abstract
A semiconductor device includes a base substrate made of silicon, a cap substrate and a leading electrode having a metal part. The base substrate has base semiconductor regions being insulated and separated from each other at a predetermined portion of a surface layer thereof. The cap substrate is bonded to the predetermined portion of the surface layer of the base substrate. The leading electrode has a first end connected to one of the plurality of base semiconductor regions of the base substrate and extends through the cap substrate such that a second end of the leading electrode is located adjacent to a surface of the cap substrate for allowing an electrical connection with an external part, the surface being opposite to a bonding surface at which the base substrate and the cap substrate are bonded. The leading electrode defines a groove between an outer surface thereof and the cap substrate.
Description
- This application is based on Japanese Patent Applications No. 2009-286874 filed on Dec. 17, 2009 and No. 2010-251092 filed on Nov. 9, 2010, the disclosure of which are incorporated herein by reference.
- The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the present invention relates to a semiconductor device having a cap substrate bonded to a base substrate made of silicon for protecting various elements formed in a surface layer of the base substrate, and a method of manufacturing the same.
- In a semiconductor device, it is known to bond a cap substrate to a base substrate for protecting various element formed in a surface layer of the base substrate.
- In such a semiconductor device, an electrical connection for electrically connecting the base substrate and an external part is necessary. For example, it is known to make a bonding wire directly on the surface of the base substrate through a through hole formed in the cap substrate. In such a method, however, a large through hole is required in the cap substrate to conduct wire bonding. That is, an area necessary for making the electrical connection is likely to increase.
- In order to ease the electrical connection between the element and the external part by the wire bonding, soldering or the like in a small area, a leading electrode that extends from the base substrate to the surface of the cap substrate and allows the electrical connection at the end can be employed.
- It has been known to use a portion of the cap substrate as the leading electrode. For example, the cap substrate made of silicon is divided into partial regions by an insulating and separating trench, and a specific region of the partial regions, which connects to an insulated and separated base semiconductor region of the base substrate, is used as a leading conductive region. The upper end of the specific region is electrically connected to the external part by the wire bonding, soldering or the like.
- A semiconductor device having such an electrical connection structure is, for example, described in Japanese Patent Application Publications No. JP2008-229833A (
Publication 1, corresponding to US2008/0290490A1) and No. JP2008-256495 (Publication 2). -
FIG. 30 shows an example of the semiconductor device described inPublication 1. Asemiconductor device 91 shown inFIG. 30 has a semiconductor base substrate B2 and a conductive cap substrate C2 bonded to the base substrate B2. - The base substrate B2 is a SOI (Silicon On Insulator) substrate in which an embedded
oxide film 20 is interposed between aSOI layer 21 and asupport substrate 22. Insulated and separated multiple base semiconductor regions Bs are formed in a surface layer of the base substrate B2. The base semiconductor regions Bs are provided by theSOI layer 21, and are insulated and separated from adjacencies by atrench 23 that reaches the embeddedoxide film 20. Projections T1 are formed above the base semiconductor regions Bs. The projections T1 are provided by aconductive film 50, which is made of poly crystal silicone, metal or the like. - The
semiconductor device 91 includes a mechanical quantity sensor element for measuring a mechanical quantity, such as acceleration and angular velocity, using an inertia force. The mechanical quantity sensor element is constructed of the multiple base semiconductor regions Bs. Specifically, the base semiconductor regions Bs include at least two base semiconductor regions Bs1 and two base semiconductor regions Bs2. - The base semiconductor regions Bs1 constitute a movable semiconductor region. The base semiconductor regions Bs1 are formed by performing sacrifice layer etching on a part of the embedded
oxide film 20. The base semiconductor regions Bs1 as the movable semiconductor region include a movable electrode Em, which is formed to be displaceable. - The base semiconductor regions Bs2 constitute a fixed semiconductor region including a fixed electrode Es opposed to the movable electrode Em. The two base semiconductor region Bs1 and the two base semiconductor region Bs2 each form a continuous and integrated region on a plane.
- In the
semiconductor device 91, a capacitance is created between opposed surfaces of the movable electrode Em and the fixed electrode Es. As the movable electrode Em is displaced in a direction perpendicular to the opposed surfaces in accordance with the applied mechanical quantity, the capacitance changes in accordance with a change in the distance between the movable electrode Em and the fixed electrode Es. Thus, the applied mechanical quantity is detected by measuring the change in capacitance. - The cap substrate C2 is provided by a single
crystal silicon substrate 30 on which multiple cap conductive regions Ce as partial regions are formed. The cap conductive regions Ce are divided by an insulating and separatingtrench 31 that passes through the singlecrystal silicon substrate 30. The cap substrate C2 has asurface protection layer 33 made of silicon oxide (SiO2) or the like, andelectrode pads 34 made of aluminum (Al) or the like. - The cap substrate C2 is bonded to the projections T1 formed on the base semiconductor regions Bs, and a bonding surface D1 is formed therebetween. The bonding surface D1 has a loop shape in a predetermined region R1 of the base substrate B2. Thus, a space sealed in a highly vacuum condition is provided between the surface of the predetermined region R1 and the surface of the cap substrate C2 by bonding the base substrate B2 and the cap substrate C2.
- Also, as the base substrate B2 and the cap substrate C2 are bonded, specific cap conductive regions Ce1, Ce2 are electrically connected to the specific base semiconductor regions Bs1, Bs2, respectively, to serve as leading conductive regions. In other words, the leading conductive regions Ce1, Ce2 are respectively connected to the movable semiconductor region Bs1 and the fixed semiconductor region Bs2, respectively.
-
FIG. 31 shows an example of a semiconductor device described in Publication 2. Asemiconductor device 92 ofFIG. 31 has a semiconductor mechanical quantity sensor element for detecting a mechanical quantity, such as acceleration and angular velocity, similar to thesemiconductor device 91 ofFIG. 30 . - The
semiconductor device 92 has a base substrate B3 provided by a Sal substrate. The SOI substrate includes asupport substrate 11 made of silicon semiconductor and apoly silicon layer 12 disposed on thesupport substrate 11 through anoxide film 13. Sensing portions Se are formed by thepoly silicon layer 12 disposed on thesupport substrate 11. - Similar to the
semiconductor device 91 ofFIG. 30 , the sensing portions Se include a movable electrode and a fixed electrode. The movable electrode and the fixed electrode are provided by a beam structure, which is generally used in conventional acceleration sensors and angular velocity sensors. As the movable electrode is displaced in accordance with the applied acceleration or angular velocity, the capacitance between the movable electrode and the fixed electrode is changed. A voltage signal indicative of the change in capacitance is produced. - Further, a cap C3 is fixed to the base substrate B3 to surround the sensing portions Se. The cap C3 is bonded to the
poly silicon layer 12 through an adhesive layer Ds made of a resin adhesive or the like. The cap C3 is provided with penetrating electrodes Ke. The cap C3 is made of silicon semiconductor in which impurities, such as phosphorous (P) and boron (B), are preferably doped so as to have electrical conductivity. - The penetrating electrodes Ke pass through the cap C3 in a direction in which a thickness of the cap C3 is measured. The penetrating electrodes Ke serve to lead electrical signals from the sensing portions Se, which are located under the cap C3, to the upper surface of the cap C3. The penetrating electrodes Ke are constituted as portions of the cap C3 having the electrical conductivity.
- Further, the cap C3 is formed with
grooves 15, which are referred to as air isolations, on peripheries of the penetrating electrodes Ke. Thegrooves 15 surround the penetrating electrodes Ke, and pass through the cap C3 in the direction in which the thickness of the cap C3 is measured. - Thus, the penetrating electrodes Ke and portions of the cap C3 on the peripheries of the penetrating electrodes Ke are insulated by means of the
grooves 15. That is, thegrooves 15 serve as electrically insulating portions to electrically insulate the penetrating electrodes Ke from the peripheral portions thereof in the cap C3. The penetrating electrodes Ke are in contact with thepoly silicon layer 12 through connectingelectrodes 51, which are made of aluminum, Al—Si or the like, to make electrical connection with the sensing portions Se. - In the
semiconductor device 91 ofFIG. 30 , the cap substrate C2 serves as a sealing cap for protecting the mechanical quantity sensor element formed in the predetermined region R1 of the surface layer of the base substrate B2. The cap conductive regions Ce1, Ce2 of the cap substrate C2, which are electrically connected to the base semiconductor regions Bs1, Bs2 of the base substrate B2, serve as leading conductive regions. - In such a structure, however, the insulating and separating
trench 31 exist on the peripheries of the leading conductive regions Ce1, Ce2 to isolate the leading conductive regions Ce1, Ce2 from the peripheral cap conductive regions. Therefore, parasitic capacitance is produced due to the insulating and separatingtrench 31 being an electric substance, and is likely to affect performance of thesemiconductor device 91. - In the
semiconductor device 92 ofFIG. 31 , on the other hand, the penetrating electrodes Ke are electrically insulated from the peripheral portions in the cap C3 by thegrooves 15 as the air isolations. Therefore, the electric permittivity at thegrooves 15 is smaller than that at thetrench 31 of thesemiconductor device 91 in which the electric substance is embedded. That is, thesemiconductor device 92 ofFIG. 31 is less apt to generate the parasitic capacitance, as compared with thesemiconductor device 91 ofFIG. 30 . - The
semiconductor device 91 employs the cap substrate C2 made of single crystal silicon. Thesemiconductor device 92 employs the cap substrate C3 made of silicon semiconductor. In general, silicon is less expensive than other substrate materials, and a trench is easily formed in a silicon substrate. However, silicon has a relatively large specific resistance. Therefore, the leading conductive regions Ce1, Ce2 and the penetrating electrodes Ke are likely to increase resistance, and hence the applicable range of such semiconductor devices may be restricted. - It is an object of the present invention to provide a semiconductor device having a base substrate and a cap substrate bonded to the base substrate for protesting the base substrate, in which a leading electrode for allowing an electrical connection between the base substrate and an external part has a structure capable of reducing resistance, and the leading electrode and a neighboring portion thereof have a structure capable of reducing occurrence of parasitic capacitance, and a method of manufacturing the semiconductor device.
- According to an aspect of the present invention, a semiconductor device includes a base substrate, a cap substrate and a leading electrode for allowing an electrical connection between the base substrate and an external device. The base substrate is made of silicon and has a plurality of base semiconductor regions in a predetermined portion of a surface layer thereof. The cap substrate is bonded to the predetermined portion of the surface layer of the base substrate. The leading electrode includes a metal part. The leading electrode passes through the cap substrate. A first end of the leading electrode is connected to one of the plurality of base semiconductor regions. A second end of the leading electrode is located adjacent to a surface of the cap substrate, the surface being opposite to a bonding surface at which the base substrate and the cap substrate are bonded, to allow the electrical connection with an external part. Further, a groove is formed between the leading electrode and the cap substrate.
- The leading electrode has the metal part having conductivity higher than that of silicon. Hence, the resistance at the leading electrode can be reduced, as compared with a conventional semiconductor device. Further, the groove is formed between the leading electrode and the cap substrate. That is, because the leading electrode has an air isolation structure, the conventional insulating and separating trench for forming the leading conductive region is not employed. Therefore, parasitic capacitance will not be easily created. In addition, stress due to a thermal expansion difference between the metal part and the cap substrate is reduced.
- According to a second aspect of the present invention, a method of manufacturing a semiconductor device includes: forming a base substrate made of silicon; forming a cap substrate; bonding the cap substrate to a predetermined portion of the base substrate; and forming a leading electrode including a metal part. The base substrate has a plurality of base semiconductor regions in the predetermined portion of a surface layer thereof, and the plurality of base semiconductor regions is insulated and separated from each other. The leading electrode passes through the cap substrate. The leading electrode has a first end connected to one of the plurality of base semiconductor regions and a second end located adjacent to a surface of the cap substrate. The leading electrode defines a groove between an outer surface thereof and the cap substrate.
- In the semiconductor device manufactured by the above method similar effects as described in the above are achieved.
- Other objects, features and advantages of the present invention will become more apparent from the following detailed description made with reference to the accompanying drawings, in which like parts are designated by like reference characters and in which:
-
FIG. 1A is a schematic cross-sectional view of a part of a semiconductor device as an example according to an embodiment of the present invention; -
FIG. 1B is a schematic cross-sectional view taken along a line IB-IB inFIG. 1A ; -
FIG. 2 is a perspective view of a base substrate of the semiconductor device shown inFIGS. 1A and 1B ; -
FIGS. 3A to 3C are schematic cross-sectional views for showing a process of forming the base substrate shown inFIG. 2 ; -
FIGS. 4A to 4C are schematic cross-sectional views for showing a process of forming a cap substrate of the semiconductor device shown inFIGS. 1A and 1B ; -
FIGS. 5A to 5D are schematic cross-sectional views for showing a process of manufacturing the semiconductor device using the base substrate and the cap substrate formed by the processes shown inFIGS. 3A to 3C and 4A to 4C; -
FIG. 6A is a schematic cross-sectional view of a leading electrode thereof as a modification of a leading electrode of the semiconductor device shown inFIGS. 1A and 1B . -
FIG. 6B is a schematic cross-sectional view of a leading electrode as another modification of the leading electrode of the semiconductor device shown inFIGS. 1A and 1B . -
FIGS. 7A to 7D and 8A to 8D are schematic cross-sectional views for showing a process of forming the leading electrodes shown inFIGS. 6A and 6B ; -
FIG. 9A is a schematic cross-sectional view of a part of a semiconductor device as a modification of the semiconductor device shown inFIGS. 1A and 1B ; -
FIG. 9B is a schematic cross-sectional view taken along a line IXB-IXB inFIG. 9A ; -
FIG. 10A is a schematic cross-sectional view of a leading electrode as a modification of a leading electrode of the semiconductor device shown inFIGS. 9A and 9B ; -
FIG. 10B is a schematic cross-sectional view of a leading electrode as a modification of the leading electrode of the semiconductor device shown inFIGS. 9A and 9B ; -
FIGS. 11A to 11D are schematic cross-sectional views for showing a process of forming the leading electrode shown inFIG. 10B ; -
FIG. 12A is a schematic cross-sectional view of a leading electrode as further another modification of the leading electrode of the semiconductor device shown inFIGS. 9A and 9B ; -
FIG. 12B is a schematic cross-sectional view taken along a line XIIA-XIIA inFIG. 12A ; -
FIG. 13A is a schematic cross-sectional view of a leading electrode as yet another modification of the leading electrode of the semiconductor device shown inFIGS. 9A and 9B ; -
FIG. 13B is a schematic cross-sectional view of a leading electrode as still another modification of the leading electrode of the semiconductor device shown inFIGS. 9A and 9B ; -
FIG. 14A is a schematic cross-sectional view of a part of a semiconductor device as a modification of the semiconductor device shown inFIGS. 9A and 9B ; -
FIG. 14B is a schematic cross-sectional view of a part of a semiconductor device as another modification of the semiconductor device shown inFIGS. 9A and 9B ; -
FIG. 14C is a schematic cross-sectional view of a leading electrode as a modification of a leading electrode of the semiconductor device shown inFIG. 14B ; -
FIGS. 15A to 15C are schematic cross-sectional views for showing a process of manufacturing the semiconductor device shown inFIG. 14A ; -
FIGS. 16A to 16D , 17A to 17D and 18A to 18C are schematic cross-sectional views for showing a process of forming the leading electrodes shown inFIGS. 14B and 14C ; -
FIG. 19A is a schematic cross-sectional view of a part of a semiconductor device as a modification of the semiconductor device shown inFIGS. 1A and 1B ; -
FIG. 19B is a schematic cross-sectional view of a part of a semiconductor device as another modification of the semiconductor device shown inFIG. 14B ; -
FIGS. 20A and 20B are schematic cross-sectional views for showing a process of forming a leading electrode of the semiconductor device shown inFIG. 19A ; -
FIGS. 21A to 21D are schematic cross-sectional views for showing a process of forming a leading electrode of the semiconductor device shown inFIG. 19B ; -
FIG. 22 is a schematic cross-sectional view of a part of a semiconductor device as further another modification of the semiconductor device shown inFIGS. 1A and 1B ; -
FIG. 23 is a schematic cross-sectional view of a part of a semiconductor device as an example of another use of the semiconductor device shown inFIGS. 1A and 18 ; -
FIG. 24 is a schematic cross-sectional view of a part of a semiconductor device as an example of the semiconductor device according to the embodiment; -
FIGS. 25A to 25D and 26A to 26C are schematic cross-sectional views for showing a process of manufacturing the semiconductor device shown inFIG. 24 -
FIG. 27 is a schematic cross-sectional view of a part of a semiconductor device as an example of the semiconductor device according to the embodiment; -
FIGS. 28A to 28D and 29A to 29D are schematic cross-sectional views for showing a process of manufacturing the semiconductor device shown inFIG. 27 ; -
FIG. 30 is a schematic cross-sectional view of a part of a semiconductor device of a prior art; and -
FIG. 31 is a schematic cross-sectional view of a part of a semiconductor device of another prior art. -
FIG. 1A is a schematic plan view of a part of asemiconductor device 100 as an example of the semiconductor device according to an embodiment.FIG. 1B is a schematic cross-sectional view taken along a line IB-IB inFIG. 1A .FIG. 1A is also a cross-section taken along a line IA-IA inFIG. 1B .FIG. 2 is a perspective view of a base substrate of thesemiconductor device 100 shown inFIGS. 1A and 1B . - In
FIGS. 1A , 1B and 2 like parts which correspond to parts of thesemiconductor devices FIGS. 30 and 31 , are designated with like reference characters. - Referring to
FIGS. 1A and 1B , thesemiconductor device 100 has a base substrate B4 made of silicon and a cap substrate C4 made of silicon. The base substrate B4 and the cap substrate C4 are bonded to each other at a bonding surface D1. - The
semiconductor device 100 includes a mechanical quantity sensor element using an inertia force. A sensing portion Se for detecting mechanical quantity such as acceleration and angular velocity is formed in a predetermined region R1 of the base substrate B4. - The cap substrate C4 is formed with a
recess 32 b. The cap substrate C4 is bonded to the base substrate B4 to oppose the predetermined region R1 where the sensing portion Se is formed. Thus, the cap substrate C4 seals a space defined by therecess 32 b and atrench 23 of the base substrate B4. - The base substrate B4 is a SOI (Silicon On Insulator) substrate having an embedded
oxide film 20, aSOI layer 21 and asupport substrate 22. The embeddedoxide film 20 is disposed between theSOI layer 21 and thesupport substrate 22. The base substrate B4 has multiple base semiconductor regions Bs including base semiconductor regions Bs1, Bs2 in a surface layer thereof. The base semiconductor regions Bs are provided by theSOI layer 21. The base semiconductor regions Bs are insulated and separated from each other by thetrench 23 that reaches the embeddedoxide film 20. - The sensing portion Se includes a mechanical quantity sensor element for measuring acceleration or angular velocity. The mechanical quantity sensor element is constructed of some of the base semiconductor regions Bs.
- The base semiconductor region Bs1 is a movable semiconductor region including a movable electrode Em. The movable electrode Em is formed by performing sacrifice layer etching on a part of the embedded
oxide film 20. The movable electrode Em is displaceable. The base semiconductor region Bs2 is a fixed semiconductor region including a fixed electrode Es that is opposed to the movable electrode Em. - In the
semiconductor device 100, capacitance is created between the opposed surfaces of the movable electrode Em and the fixed electrode Es. As the mechanical quantity is applied to the movable electrode Em, the movable electrode Em is displaced in a direction perpendicular to the opposed surfaces. The capacitance changes in accordance with a change in a distance between the opposed surfaces of the movable electrode Em and the fixed electrode Es. The change in capacitance is measured to detect the applied mechanical quantity. It is noted that, in the base substrate B4, other elements and circuits may be formed in regions other than the predetermined region R1. - The cap substrate C4 includes a
single crystal silicon 30, which can be precisely processed at a relatively low cost. In the cap substrate C4, therecess 32 b is formed at a position corresponding to the sensing portion Se of the base substrate B4. An insulatinglayer 32 a is formed on a lower surface of the singlecrystal silicon substrate 30 bonded to the base substrate B4. The insulatinglayer 32 a is, for example, made of silicon oxide (SiO2). - In the
semiconductor device 100, as described above, the base substrate B4 and the cap substrate C4 are bonded to each other through the bonding surface D1. In a semiconductor device having a cap substrate as thesemiconductor device 100, the cap substrate is generally employed to protect various elements formed in a surface layer of a base substrate. - In the semiconductor device having the cap substrate, as a method of forming an electrical connection between the various elements formed in the surface layer of the base substrate and external parts, it may be possible to directly connect a bonding wire to a surface of, the base substrate by a wire bonding technique through a through hole formed in the cap substrate.
- In such a method, however, the through hole of the cap substrate needs to be large enough to allow the wire bonding. Thus, an area for making the electrical connection is likely to increase.
- In order to ease the electrical connection with a small area, a semiconductor device having a cap substrate needs a leading electrode that extends from the surface of a base substrate to an upper surface of the cap substrate to allow the electrical connection with an external part at an upper end thereof.
- The
semiconductor device 100 has a leading electrode De1 that extends from the surface of the base substrate B4 to an upper surface of the cap substrate C4 for facilitating an electrical connection between the mechanical quantity sensor element of the base substrate B4 and the external part. - The leading electrode De1 includes a
metal part 40 made of metal such as aluminum (Al), copper (Cu), chrome (Cr) tungsten (W), and platinum (Pt). A lower end of the leading electrode De1 is connected to a predetermined base semiconductor region Bs. The leading electrode De1 extends from the predetermined base semiconductor region Bs to the upper surface of the cap substrate C4, while passing through the cap substrate C4. Here, “extending to the upper surface of the cap substrate C4” means that an upper end of the leading electrode De1 is located adjacent to the upper surface of the cap substrate C4. For example, the upper end of the leading electrode De1 is located at the same height as or higher than the upper surface of the cap substrate C4. - A
groove 35 is formed on a periphery of the leading electrode De1. In other words, thegroove 35 is formed between an outer surface of the leading electrode De1 and the cap substrate C4. The leading electrode De1 is separated from the cap substrate C4 by thegroove 35.FIG. 1B shows a condition where abonding wire 60 is connected to the upper end of the leading electrode De1. - In the
semiconductor device 91 ofFIG. 30 , the silicon cap substrate C2 is divided into partial regions Ce through the insulating and separatingtrench 31, and predetermined conductive regions Ce1, Ce2 of the partial regions Ce, which connect to the insulated and separated base semiconductor region Bs, are used as the leading conductive regions to make electrical connections at the upper end thereof with the external parts by wire bonding, soldering or the like. - In the
semiconductor device 92 ofFIG. 31 , the penetrating electrodes Ke, which are provided by portions of the silicon cap substrate C3 and separated through thegrooves 15, are used to make electrical connections at the upper end thereof with the external parts by the wire bonding, soldering or the like. - In such structures, however, since the resistance of the silicon conductive regions and the silicon penetrating electrodes Ke is large, the applicable ranges of the semiconductor devices are likely to be restricted.
- In the
semiconductor device 100, on the other hand, the leading electrode De1 is provided by themetal part 40, which has high electric conductivity. Themetal part 40 connects to the predetermined base semiconductor region Bs, that is, at a bonding portion Des shown by a dashed line inFIG. 2 . Themetal part 40 passes through the cap substrate C4, and the upper end of themetal part 40 is located higher than the upper surface of the cap substrate C4. Therefore, the resistance of the leading electrode De1 is smaller than the resistance of the conductive regions Ce1, Ce2 and the penetrating electrodes Ke of thesemiconductor devices semiconductor device 100 increases. - Further, the
groove 35 is provided between the leading electrode De1 and the cap substrate C4. That is, the leading electrode De1 has a so-called air isolation structure. The cap substrate C4 of thesemiconductor device 100 does not have the insulating and separatingtrench 31 for forming the partial regions Ce as thesemiconductor device 91. - In the
semiconductor device 100, therefore, parasitic capacitance will not be easily formed due to the electric substance such as the insulating and separatingtrench 31. Further, since thegroove 35 is formed around the leading substrate de1, stress due to a thermal expansion difference between the leading electrode De1 and the cap substrate C4 can be reduced. - In the
semiconductor device 92 ofFIG. 31 , since thegroove 15 is formed around the penetrating electrode Ke, the parasitic capacitance will not be easily formed. In thesemiconductor device 92 ofFIG. 31 , thegroove 15 reaches the base substrate B3. In thesemiconductor device 100 ofFIGS. 1A and 1B , on the other hand, the insulatinglayer 32 a is formed under thegroove 35, and thus thegroove 35 does not reach the base substrate B4. - In view of reducing the parasitic capacitance, the
groove 15 passing through the cap substrate C3 and reaching the base substrate B3 is preferable as in thesemiconductor device 92 ofFIG. 31 . Thus, it may be possible to form thegroove 35 to reach the base substrate B4 in thesemiconductor device 100. - In the
semiconductor device 100, however, the insulatinglayer 32 a is positioned at the bottom of thegroove 35. That is, the insulatinglayer 32 a is exists around the base of the leading electrode De1. Therefore, the insulatinglayer 32 a serves as a support portion to increase the strength of the leading electrode De1, which is particularly required during the wire bonding or soldering the upper end of the leading electrode De1. - In the example shown in
FIG. 1B , the upper end of the leading electrode De1 is located higher than the upper surface of the cap substrate C4. As compared with a case where the upper end of the leading electrode De1 is at the same height as or lower than the upper surface of the cap substrate C4, interference with peripheral portions is reduced. Therefore, the wire bonding and the soldering are easily conducted at the upper end of the leading electrode De1. - Accordingly, in the
semiconductor device 100, the resistance of the leading electrode De1 is reduced and the parasitic capacitance will not be easily formed around the leading electrode De1. - As described above, the cap substrate C4 is provided by the single
crystal silicon substrate 30, which is easily processed at a relatively low cost. Further, since the leading electrode De1 is constructed of themetal part 40, the cap substrate C4 can be provided by a poly crystal substrate, an intrinsic silicon substrate in which glass and impurities are not doped, or other similar insulating substrates, in place of the single crystal silicon substrate. - Next, a method of manufacturing the
semiconductor device 100 will be described. -
FIGS. 3A-3C are schematic cross-sectional views for showing a process of forming the base substrate B4. - In
FIG. 3A , a SOI substrate B4 a including the embeddedoxide film 20 between theSOI layer 21 and thesupport substrate 22 is prepared. The SOI substrate B4 a is formed by a substrate bonding technique, for example. The embeddedoxide film 20 is a silicon oxide (SiO2) film, and thesupport substrate 22 is a single crystal silicon substrate having a specific resistance in a range of 0.001 to 1 Ωcm, for example. - The
SOI layer 21 is used for forming various elements. TheSOI layer 21 is a single crystal silicon layer containing N+ type impurities such as arsenic (As) and phosphorous (P) with a specific resistance of 0.001 to 1 Ωcm and a thickness of 1 to 50 μm. For example, theSOI layer 21 has a thickness of 10 to 20 μm, and theSOI layer 21 and thesupport substrate 22 are formed by bonding N+ type single crystal substrates containing impurities at high concentrations. - In the case where the base semiconductor regions Bs are partly used as the movable semiconductor region Bs1 including the movable electrode Em and the fixed semiconductor region Bs2 including the fixed electrode Es, it is preferable that the concentration of impurities of the
SOI layer 21 is as high as possible, that is, the specific resistance of theSOI layer 21 is as small as possible. In the above-described example, theSOI layer 21 contains the N+ type impurities. As another example, all the impurities can be P+ type impurities, such as born (B). - In
FIG. 3B , a mask pattern (not shown) of such as a photoresist and an oxide film is formed on theSOI layer 21. Atrench 23 that has substantially perpendicular walls and reaches theoxide film 20 is formed by photolithography and deep-etching techniques. By thetrench 23, theSOI layer 21 is divided to form the multiple base semiconductor regions Bs, which are insulated and separated from adjacencies, in a surface layer of the SOI substrate B4 a. - In
FIG. 3C , after the mask pattern is removed from theSOI layer 21, the embeddedoxide film 20 is partly removed through thetrench 23 by an etching technique with hydrogen fluoride (HF) gas. Thus, the movable semiconductor region Bs1 including the movable electrode Em, the fixed semiconductor region Bs2 including the fixed electrode Es, and the like are formed. In this case, the portions of theoxide film 20 under the movable electrode Em and the fixed electrode Es are thoroughly removed, as shown inFIG. 3C . - In this way, the base substrate B4 for the
semiconductor device 100 is formed. -
FIGS. 4A to 4C are schematic cross-sectional views for showing a process of forming the cap substrate C4. - In
FIG. 4A , the singlecrystal silicon substrate 30 is prepared. InFIG. 4B , a mask pattern (not shown) of such as a photoresist or an oxide film is formed on a lower surface of thesilicon substrate 30. Then, therecess 32 b is formed by photolithography and etching techniques. - In
FIG. 4C , the insulatinglayer 32 a of the silicon oxide (SiO2) is formed on the lower surface of thesilicon substrate 30 by a thermal oxidation technique. In this way, the cap substrate C4 for thesemiconductor device 100 is formed. -
FIGS. 5A to 5D are schematic cross-sectional views for showing process of manufacturing thesemiconductor device 100 using the base substrate B4 and the cap substrate C4 respectively formed by the processes shown inFIGS. 3A to 3C andFIGS. 4A to 4D . - As shown in
FIGS. 5A and 5B , the base substrate B4 and the cap substrate C4 are bonded to each other. - Specifically, in
FIG. 5A , the cap substrate C4 is positioned relative to the base substrate B4 such that the cap substrate C4 is opposed to the predetermined region R1 where the mechanical quantity sensor element has been formed, and is laid on the base substrate B4. - In
FIG. 5B , the lower surface of the cap substrate C4 is bonded to the upper surface of the base substrate B4. Here, the cap substrate C4 and the base substrate B4 are bonded using an arbitrary adhesive. Thus, the cap substrate C4 and the base substrate B4 are securely bonded at the bonding surface D1, and the space defined by therecess 32 b and thetrench 23 is fully sealed. - Next, the leading electrode De1 is formed, as shown in
FIGS. 5B to 5D . - First, as shown in
FIG. 5B , atrench 41 is formed at a predetermined position of the cap substrate C4. In this case, thetrench 41 is formed to reach the predetermined base semiconductor region Bs of the base substrate B4. - In
FIG. 5C , themetal part 40 is embedded in thetrench 41, and then an upper surface of the cap substrate C4 is etched so that the upper end of themetal part 40 becomes higher than the upper surface of the cap substrate C4. - In
FIG. 5D , a portion of thesilicon substrate 30 around thetrench 41 in which themetal part 40 is embedded is etched to form thegroove 35 around thetrench 41. - In this way, the leading electrode De1 is formed, and the
semiconductor device 100 is manufactured. It is noted that, in an actual manufacturing process, the base substrate B4 and the cap substrate C4 are prepared in the condition of wafers, and thefinished semiconductor devices 100 are produced by cutting the wafers into multiple chips after the process ofFIGS. 5A to 5D . - Next, modifications of the leading electrode De1 and a neighboring structure thereof will be described in detail.
-
FIG. 6A is a schematic cross-sectional view of the leading electrode De1 and the neighboring structure thereof as a modification.FIG. 6B is a schematic cross-sectional view of the leading electrode De1 and the neighboring structure thereof as another modification. - In the modification shown in
FIG. 6A , an insulatinglayer 42 is formed at the bottom portion of thegroove 35 a. The insulatinglayer 42 is separate from the insulatinglayer 32 a, and has a thickness greater than a thickness of the insulatinglayer 32 a. In this case, therefore, strength of the leading electrode De1 required for forming the electrical connection to the external part, that is, for conducting the wire bonding and the soldering, can be increased, as compared with a structure shown inFIG. 1B . - In the modification shown in
FIG. 5B , agroove 35 b is formed around the leading electrode De1. Thegroove 35 b reaches the base substrate B4, similar to the structure around the penetrating electrode Ke of thesemiconductor device 92 shown inFIG. 31 . In this case, therefore, parasitic capacitance due to the leading electrode De1 can be further reduced, as compared with the structures shown inFIGS. 1B and 6A . -
FIGS. 7A to 7D and 8A to 8D are schematic cross-sectional views for showing a process of forming the structures shown inFIGS. 6A and 6B . The process shown inFIGS. 7A to 7D and 8A to 8D is performed after the base substrate B4 and the cap substrate C4 are bonded in the manner shown inFIGS. 5A and 5B . - In
FIG. 7A , a silicon nitride (Si3N4)film 30 a is formed on the singlecrystal silicon substrate 30 of the cap substrate C4 by a low pressure chemical vapor deposition (LPCVD) technique or a plasma chemical vapor deposition (CVD) technique. Thesilicon nitride film 30 a can be formed on the singlecrystal silicon substrate 30 before the cap substrate C4 is bonded to the base substrate B4. - In
FIG. 7B , a mask pattern (not shown) of a photoresist is formed on thesilicon nitride film 30 a, and then atrench 41 a is formed at a predetermined position of the cap substrate C4 by etching from the top of thesilicon nitride film 30 a. Thetrench 41 a is formed to reach the predetermined base semiconductor region Bs. - In
FIG. 7C , asilicon oxide film 42 a is deposited on an entire surface, that is, on thesilicon nitride film 30 a and walls of thetrench 42 a by a plasma CVD technique. - In
FIG. 7D , thesilicon oxide film 42 a formed on thesilicon nitride film 30 a and the bottom wall of thetrench 41 a is removed. Thus, thesilicon oxide film 42 a on the side wall of thetrench 41 a remains. - Next, in
FIG. 8A , ametal layer 40 a, which is for example made of aluminum (Al), is deposited on an entire surface, that is, on thesilicon nitride film 30 a and inside of thetrench 41 a. Thetrench 41 a is filled with themetal layer 40 a. - In
FIG. 8B , themetal layer 40 a on thesilicon nitride film 30 a is removed by an etchback technique. Thus, themetal layer 40 a inside of thetrench 41 a remains to form themetal part 40 of the leading electrode De1 ofFIGS. 6A and 6B . - In
FIG. 8C , thegroove 35 a is formed by removing thesilicon oxide film 42 a formed on the side wall of thetrench 41 a. Thesilicon oxide film 42 a remains at a lower portion of thegroove 35 a. Thus, the insulatinglayer 42 shown inFIG. 6A is formed. - In this way, the leading electrode De1 and its neighboring portion shown in
FIG. 6A are formed. - The leading electrode De1 and its neighboring portion shown in
FIG. 6B are formed by entirely removing thesilicon oxide film 42 a from the side walls of thetrench 41 a, as shown inFIG. 8D . - As described in the above, after a bonding step shown in
FIG. 7A , trench forming step for forming thetrench 41 a in the cap substrate C4 to reach the predetermined base semiconductor region Bs is performed. In a subsequent leading electrode forming step, themeal layer 40 a is embedded in thetrench 41 a to form themetal part 40 of the leading electrode De1. Then, thegroove trench 41 a. -
FIG. 9A is a schematic plan view of a part of asemiconductor device 110 as a modification of thesemiconductor device 100 shown inFIGS. 1A and 1B .FIG. 9B is a schematic cross-sectional view taken along a line IXB-IXB inFIG. 9A .FIG. 9A is also a schematic cross-sectional view taken along a line IXA-IXA inFIG. 9B . In thesemiconductor device 110 shown inFIGS. 9A and 9B , like parts are denoted by like reference characters as those of thesemiconductor device 100 shown inFIGS. 1A and 1B . - As shown in
FIGS. 9A and 9B , thesemiconductor device 110 has the same base substrate B4 as that of thesemiconductor device 100 ofFIGS. 1A and 1B . With regard to a cap substrate C5 of thesemiconductor device 110, a leading electrode De2 and its neighboring structure are different from the leading electrode De1 and its neighboring structure of the cap substrate C4 of thesemiconductor device 100 - The leading electrode De1 of the
semiconductor device 100 is constructed of only themetal part 40. Further, although thegroove 35 is formed between the cap substrate C4 and the leading electrode De1, the cap substrate C4 is constructed of a single member, that is, thesilicon substrate 30. - With regard to the cap substrate C5 of the
semiconductor device 110, on the other hand, agroove 36 is formed in the singlecrystal silicon substrate 30 to divide the singlecrystal silicon substrate 30 into a portion surrounding the leading electrode De2 and its peripheral portion. That is, the cap substrate C5 is divided into multiple partial regions Cs by thegrooves 36. The partial regions Cs are insulated and separated by thegrooves 36. The leading electrode De2 is constructed of a predetermined partial region Cs1 and themetal part 40 formed in the predetermined partial region Cs1. - Similar to the
semiconductor device 100 ofFIGS. 1A and 1B , the leading electrode De2 of thesemiconductor device 110 has themetal part 40 that contacts the base semiconductor region Bs and extends to the upper surface of the cap substrate C5. As such, the resistance of the leading electrode De2 is reduced, as compared with that in thesemiconductor devices FIGS. 30 , 31. With this, the applicable range increases. - The
groove 36 is formed between the leading electrode De2 and the cap substrate C5, similar to thesemiconductor device 100 ofFIGS. 1A and 1B Therefore the parasitic capacitance will not be easily formed on a periphery of the leading electrode De2. - The leading electrode De2 of the
semiconductor device 110 is different from the leading electrode De1 of thesemiconductor device 100 since the leading electrode De2 includes the predetermined partial region Cs1 as an element in addition to themetal part 40. The predetermined partial region Cs1 is formed around themetal part 40, but is insulated and separated from the adjacent partial portion Cs by thegroove 36. - In the
semiconductor device 110, therefore, the resistance can be reduced by themetal part 40 as the element of the leading electrode De2. Furthermore, because the predetermined partial region Cs1 around themetal part 40 serves as a support part, strength of the leading electrode De2 required at the time of wire bonding and soldering can be increased. - In the case where the cap substrate C5 is divided into multiple partial regions Cs, which are insulated and separated from each other, as the
semiconductor device 110, integrated circuits (IC circuits) can be formed in other partial regions Csa, Csb of the partial regions Cs, as shown inFIG. 9A . -
FIGS. 10A and 10B are schematic cross-sectional views of the leading electrode De2 and the neighboring portion thereof as modifications of the structure shown inFIGS. 9A and 9B . - In the modification shown in
FIG. 10A , agroove 36 a is formed to pass through the cap substrate C5 and reach the base substrate B4, similar to thegroove 35 b shown inFIG. 6B . Therefore, in the structure shown inFIG. 10A parasitic capacitance due to the leading electrode De2 is further reduced, as compared with the structure shown inFIGS. 9A and 9B . - In the modification shown in
FIG. 10B , thesilicon nitride film 30 a remains, which has been formed at the beginning of the forming of the leading electrode De2 as shown inFIG. 7A , on the singlecrystal silicon substrate 30. Further, the upper end of themetal part 40 is on the same height as the upper surface of thesilicon nitride film 30 a. That is, thesilicon nitride film 30 a is formed above the predetermined partial region Cs1 formed around themetal part 40, and the upper surface of thesilicon nitride film 30 is coplanar with the upper surface of themetal part 40. - In such a structure, because the
silicon nitride film 30 a serves as a support portion, strength of the leading electrode De2 required at the time of wire bonding and soldering is increased, as compared with that of the leading electrode shown inFIG. 10A . -
FIGS. 11A to 11D are schematic cross-sectional views for showing a process of forming the leading electrode De2 and its neighboring structure shown inFIG. 10B . - The process begins from the similar condition shown in
FIG. 7A after the base substrate B4 and the cap substrate C5 are bonded. As shown inFIG. 11A , a mask pattern (not shown) of a photoresist is formed on thesilicon nitride film 30 a, and then atrench 41 a is formed at a predetermined position of the cap substrate C5 by etching from the top of thesilicon nitride film 30 a. Thetrench 41 a is formed to reach the predetermined base semiconductor region Bs. - In
FIG. 11B themetal layer 40 a is deposited on an entire surface, that is, over thesilicon nitride film 30 a and inside of thetrench 41 a. Thus, thetrench 41 b is filled with themetal layer 40 a. - In
FIG. 11C , themetal layer 40 a above thesilicon nitride film 30 a is removed by an etchback technique. Themetal layer 40 a inside of thetrench 41 b remains to form themetal part 40 of the leading electrode De2 shown inFIG. 10B . - In
FIG. 11D , a mask pattern (not shown) of a photoresist is formed on thesilicon nitride film 30 a, and thegroove 36 a is formed by etching from the top of the mask pattern. - In this way, the leading electrode De2 and its neighboring structure shown in
FIG. 10B are formed. It is noted that the leading electrode De2 and its neighboring structure shown inFIG. 10A are formed by removing thesilicon nitride film 30 a after the step shown inFIG. 11D . It is also noted that the leading electrode De2 and its neighboring structure shown inFIG. 9B are formed by forming thegroove 36 a while remaining the insulatinglayer 32 a at the bottom of thegroove 36 a in the step ofFIG. 11D and further removing thesilicon nitride film 30 a after the step ofFIG. 11D . -
FIG. 12A is a plan view of the leading electrode De2 and the neighboring structure thereof as further another modification of the structure shown inFIGS. 9A and 9B .FIG. 12B is a schematic cross-sectional view taken along a line XIIB-XIIB inFIG. 12A .FIG. 12A is also across-section taken along a line XIIA-XIIA inFIG. 12B . - A cap substrate C10 shown in
FIGS. 12A and 12B includes an insulatingsubstrate 30 z made of intrinsic silicon in which impurities are not doped. That is, the cap substrate C10 is different from the cap substrate C5 ofFIGS. 9A , 9B, 10A and 10B, which includes the singlecrystal silicon substrate 30 in which the impurities are doped. - Further, as shown in
FIG. 12A , agroove 36 b having a substantially C-shape is formed around themetal part 40 of the leading electrode De2. A portion of thesubstrate 30 z formed around the metal,part 40 is connected to an adjacent portion of thesubstrate 30 z, that is, on a periphery of thegroove 36 b through an opening of the C-shape of thegroove 36 b. - Therefore, in the structure shown in
FIGS. 12A and 12B , strength of the leading electrode De2 required at the time of wire bonding and soldering is further increased, as compared with the structures shown inFIGS. 9A , 9B and 10A. Since thesubstrate 30 z has an insulating property, themetal part 40 of the leading electrode De2 is electrically insulated from a peripheral portion. -
FIGS. 13A and 13B are schematic cross-sectional views of a leading electrode De3 and a neighboring structure thereof as still other modifications of the structure shown inFIGS. 9A and 9B . - The leading electrodes De3 shown in
FIGS. 13A and 13B are provided by subdividing the leading electrodes De2 ofFIGS. 10A and 10B , respectively. That is, themetal part 40 is constructed of multiple portions in a predetermined partial region Cs2, which is one of the partial regions Cs and separated and insulated from a peripheral partial region Cs by thegroove 36 a. - In the structure shown in
FIG. 13A , thesilicon nitride film 30 a formed above the singlecrystal silicon substrate 30 during the manufacturing process is removed. In the structure shown inFIG. 13B , thesilicon nitride film 30 a remains on the singlecrystal silicon substrate 30. - In the structures shown in
FIGS. 13A and 13B , stress due to a thermal expansion difference between themetal part 40 and the partial region Cs2 made of silicon is further reduced, as compared with the structures shown inFIGS. 10A and 10B . - In the structure shown in
FIG. 13A , at the time of wire bonding or soldering, thebonding wire 60 and the solder can be embedded between the divided portions of themetal part 40, which protrude higher than the upper surface of the partial region Cs2. Therefore, reliability of connection improves. -
FIG. 14A is a schematic cross-sectional view of a part of asemiconductor device 111 as a modification of thesemiconductor device 110 shown inFIGS. 9A and 9B .FIG. 14B is a schematic cross-sectional view of a part of asemiconductor device 112 as another modification of thesemiconductor device 110 shown inFIGS. 9A and 9B .FIG. 14C is a schematic cross-sectional view of a leading electrode De5 and its neighboring structure as a modification of a leading electrode De5 and its neighboring structure of thesemiconductor device 112 shown inFIG. 14B . - The base substrates B4 of the
semiconductor devices semiconductor devices FIGS. 1A , 1B, 9A and 9B. Thesemiconductor devices semiconductor device 110 ofFIGS. 9A and 9B . - The leading electrode De2 of the
semiconductor device 110 is constructed of the predetermined partial region Cs1 and themetal part 40 formed at the center of the partial region Cs1. On the other hand, the leading electrode De4 of thesemiconductor device 111 is constructed of a predetermined partial region Cs3, which is one of the partial regions Cs, and themetal part 40 that covers a side wall and an upper surface of the partial region Cs3. - That is, in the leading electrode De4 of the
semiconductor device 111, since themetal part 40 covers the upper surface of the partial region Cs4, connecting area between themetal part 40 and the bonding wire or the solder is increased, as compared with the leading electrode De2 of thesemiconductor device 110 shown inFIGS. 9A and 9B in which themetal part 40 does not cover the upper surface of the partial region Cs1. Therefore, the electrical connection further improves. - The leading electrode De5 of the
semiconductor device 112 is constructed of the predetermined partial region Cs4 and themetal part 40 covering a lower surface of the partial region Cs4 in addition to the side wall and the upper surface of the partial region Cs4. In this case, the connection between the leading electrode De5 and the predetermined base semiconductor region Bs of the base substrate B4 further improves, as compared with the connection between the leading electrode De4 and the predetermined base semiconductor region Bs of thesemiconductor device 111 shown inFIG. 14A . - The
metal part 40 of the leading electrode De4 of thesemiconductor device 111 connects to the base semiconductor region Bs and extends to the same height as or higher than the upper surface of the cap substrate C7. Similarly, themetal part 40 of the leading electrode De5 of thesemiconductor device 112 connects to the base semiconductor region Bs and extends to the same height as or higher than the upper surface of the cap substrate C8. As such, in thesemiconductor devices semiconductor devices FIGS. 30 and 31 . Therefore, the applicable ranges of thesemiconductor devices - In addition, in the
semiconductor device 111 ofFIG. 14A , agroove 37 a is formed between the leading electrode De4 and the cap substrate C7. Therefore parasitic capacitance will not be easily formed on a periphery of the leading electrode De4. - Likewise in the
semiconductor device 112 ofFIG. 14B , agroove 37 b is formed between the leading electrode De5 and the cap substrate C8. Therefore, parasitic capacitance will not be easily formed on a periphery of the leading electrode De5. - In the leading electrode De5 and the neighboring structure thereof shown in
FIG. 14C , agroove 37 c is formed around the leading electrode De5, and an insulatinglayer 43, which is separate from the insulatinglayer 32 a of the cap substrate C8, is formed at the bottom portion of thegroove 37 c. Therefore, strength of the leading electrode De5 ofFIG. 140 required at the time of wire bonding and soldering is increased, as compared with that of the leading electrode De5 ofFIG. 14B . -
FIGS. 15A to 15C are schematic cross-sectional views for showing a process of forming thesemiconductor device 111 ofFIG. 14A . - In
FIG. 15A , after the base substrate B4 and the cap substrate C7 are bonded to each other in a similar manner as shown inFIGS. 5A and 5B , thegroove 37 a is formed at a predetermined position of the cap substrate C7 to reach the insulatinglayer 32 a. Thus, the singlecrystal silicon substrate 30 is divided into the partial regions Cs including a partial region Cs3. - In
FIG. 15B , the insulatinglayer 32 a at the bottom portion of thegroove 37 a is further etched to form atrench 41 c reaching the predetermined base semiconductor region Bs of the base substrate B4. - In
FIG. 15C , themetal part 40 is formed successively inside thetrench 41 c, on the side wall of the partial region Cs3, and on an upper surface of the partial region Cs3. - In this way, the leading electrode De4 is formed, and thus the
semiconductor device 111 ofFIG. 14A is manufactured. -
FIGS. 16A to 16D , 17A to 17D and 18A to 180 are schematic cross-sectional views for showing a process of forming the leading electrodes De5 and neighboring structures thereof shown inFIGS. 14B and 14C . - The process of forming the leading electrode De5 of the
semiconductor device 112 shown inFIG. 14B is different from the processes of forming the leading electrodes De1 to De4. To form the leading electrode De5 of thesemiconductor device 112 shown inFIG. 14B necessary structures are formed in the cap substrate C8 before the base substrate B4 and the cap substrate C8 are bonded to each other. - In
FIG. 16A , the singlecrystal silicon substrate 30 is prepared. A mask pattern (not shown) of a photoresist is formed on the singlecrystal silicon substrate 30, and then atrench 41 d is formed by etching from the top. - In
FIG. 16B , ametal layer 40 b made of such as aluminum (Al) is deposited entirely over the singlecrystal silicon substrate 30 including thetrench 41 d. - In
FIG. 16C , a silicon oxide (SiO2)film 43 a is deposited entirely over themetal layer 40 b by a plasma CVD technique. - In
FIG. 16D , thesilicon oxide film 43 a is removed by an etchback technique so that themetal layer 40 b on the surface of the singlecrystal silicon substrate 30 exposes, and only, thesilicon oxide film 43 a inside of thetrench 41 d remains. - Next, in
FIG. 17A , a predetermined mask pattern (not shown) is formed, and themetal layer 40 b is partly removed by an etching technique. - In
FIG. 17B , the singlecrystal silicon substrate 30 is turned upside down, and then is grinded from the top so that thesilicon oxide film 43 a embedded inside of thetrenches 41 d is exposed. In this way, the singlecrystal silicon substrate 30 is divided to form the insulated and separated multiple partial regions Cs including a partial region Cs4. - In
FIG. 17C , ametal layer 40 c made of such as aluminum (Al) is deposited entirely over the singlecrystal silicon substrate 30. - In
FIG. 17D , a predetermined mask pattern (not shown) is, formed on themetal layer 40 c, and then themetal layer 40 c is partly removed by etching. Thus, themetal part 40 that covers the side wall, the upper surface and the lower surface of the partial region Cs4 is formed. - By the above steps, the cap substrate C8 before being bonded is formed.
- Next, in
FIG. 18A , the base substrate B4 and the cap substrate C8, which have been formed beforehand, are bonded to each other. - In
FIG. 18B , thetrench 37 c is formed by etching thesilicon oxide film 43 a from the top. Thesilicon oxide film 43 a remains at the bottom of thetrench 37 c to provide the insulatinglayer 43. - By the above steps, the leading electrode De5 and its neighboring structure shown in
FIG. 14C are formed. - If the
silicon oxide film 43 a is fully removed by the etching, thegroove 37 b is formed as shown inFIG. 18C . Thus, the leading electrode De5 and its neighboring structure shown inFIG. 14B are formed. - As described in the above, the leading electrode forming process can be partly conducted during the cap substrate forming process. That is, the leading electrode De5 can be formed in a condition of being connected to the cap substrate C8 while the cap substrate C8 is formed. Then, the lower surface of the leading electrode De5 is connected to the predetermined base semiconductor region Bs while the cap substrate C8 is bonded to the base substrate B4. Thereafter, the
grooves -
FIG. 19A is a schematic cross-sectional view of a part of asemiconductor device 113 as a modification of thesemiconductor device 100 shown inFIGS. 1A and 1B .FIG. 19B is a schematic cross-sectional view of a part of asemiconductor device 114 as a modification of thesemiconductor device 112 shown inFIG. 14B . - In the
semiconductor device 113 shown inFIG. 19A , a leading electrode De6 has an upper surface to which the electrical connection is formed such as by the wire bonding and the soldering. The upper surface has an area greater than that of a lower surface, which is connected to the base semiconductor region Bs to form the bonding portion Des. Similarly, a leading electrode De7 of thesemiconductor device 114 shown inFIG. 19B has an upper surface with an area greater than a lower surface thereof. - In such cases, a pad area increases, as compared with a case where the upper surface of a leading electrode has an area smaller than or the same as an area of the lower surface thereof. Therefore, the wire bonding and the soldering to the upper surface of the leading electrodes De6, De7 are easily conducted.
-
FIGS. 20A and 20B are schematic cross-sectional views for showing a process of forming the leading electrode De6 and its neighboring structure of thesemiconductor device 113 shown inFIG. 19A . - As shown in
FIG. 20A , the process begins from the condition shown inFIG. 8A . InFIG. 20A , themetal layer 40 a formed on thesilicon nitride film 30 a is etched in a predetermined pattern so that themetal part 40 having the upper surface with the greater area than its lower surface is formed. - In
FIG. 20B , thesilicon oxide film 42 a on the side wall of thetrench 41 a and thesilicon nitride film 30 a on the singlecrystal silicon substrate 30 are removed in a predetermined order to form thegroove 35 b. - In this way, the leading electrode De6 and its neighboring structure of the
semiconductor device 113 shown inFIG. 19A are formed. -
FIGS. 21A to 21D are schematic cross-sectional views for showing a process of forming the leading electrode De7 and its neighboring structure of thesemiconductor device 114 shown inFIG. 19B . - As shown in
FIG. 21A , the process begins from the condition shown inFIG. 17B . InFIG. 21A , themetal layer 40 c made of such as aluminum (Al) is deposited over an entire surface of the singlecrystal silicon substrate 30 with a thickness greater than a thickness of themetal layer 40 c ofFIG. 17C - In
FIG. 21B , themetal layer 40 c is etched in a predetermined pattern. Thus, themetal part 40 having the upper surface with the greater area than that of the lower surface is formed. - In
FIG. 21C , the base substrate B4 and the cap substrate C8, which have been prepared beforehand are bonded to each other. - In
FIG. 21D thesilicon oxide film 43 a is fully removed by an etching technique to form thegroove 37 b. - In this way, the leading electrode De1 and its neighboring structure of the
semiconductor device 114 shown inFIG. 19B is formed. -
FIG. 22 is a schematic cross-sectional view of a part of asemiconductor device 115 as further another modification of thesemiconductor device 100 shown inFIGS. 1A and 1B . - The
semiconductor device 115 shown inFIG. 22 has an integrated circuit (IC circuit) 101 on a partial region Csc of the singlecrystal silicon substrate 30 in addition to the structure of thesemiconductor device 100 shown inFIG. 1B . The partial region Csc is one of the partial regions Cs of the cap substrate C4, and seals the sensing portion Se of the base substrate B4. In the case where the single crystal silicon substrate is used for the cap substrate, in this way, the integrated circuit can be formed in the predetermined partial region of the cap substrate, which is insulated and separated. -
FIG. 23 is a schematic cross-sectional view of a part of thesemiconductor device 100 for showing another applicable example. - In the example shown in
FIG. 1B , the upper end of the leading electrode De1 is exemplarily connected to thewire bonding 60 to be electrically connected to an external part. In the example shown inFIG. 23 , on the other hand, thesemiconductor device 100 is mounted to a separate singlecrystal silicon substrate 70 having an integrated circuit (IC circuit) IC2 by a flip-chip technique. The end surfaces of themetal parts 40 constructing the leading electrodes De1 are electrically connected to padelectrodes 71 formed on the singlecrystal silicon substrate 70 bysolders 61. In this way, the electrical connections of the end surfaces of the leading electrodes De1 to the external parts can be formed by either the wire bonding or the soldering. -
FIG. 24 is a schematic cross-sectional view of a part of asemiconductor device 120 as an example of the semiconductor device according to the embodiment. Thesemiconductor device 120 has two base substrates B5, B6 and a cap substrate C9. The base substrates B5, B6 are bonded on opposite sides of the cap substrate C9. - For example, the base substrate B5 is provided with an angular velocity sensor element (a gyro sensor element). The base substrate B6 is provided with an acceleration sensor element.
- In the
semiconductor device 120 shown inFIG. 24 , the base substrate B5 and the second substrate B6 are electrically connected to each other through leading electrodes De8 formed in the cap substrate C9. Although thesemiconductor device 120 carries the angular velocity sensor element and the acceleration sensor element, it is configured compact and wiring resistance of thesemiconductor device 120 is reduced. - The cap substrate C9 has a
groove 38 formed to divide the singlecrystal silicon substrate 30. That is, the cap substrate C9 is divided into multiple partial regions Cs, which are insulated and separated from each other, by thegroove 38. The leading electrode De8 is constructed of the predetermined partial region Cs5 of the partial regions Cs and themetal part 40 formed around the partial region Cs5. For example, themetal part 40 is formed on the side wall of the partial region Cs5. - The
metal part 40 connects to the base semiconductor region Bs and extends to the upper surface of the cap substrate C9. For example, both the end surfaces of themetal part 40 are on the same heights as the opposite surfaces of the cap substrate C9 and connect to the base semiconductor regions Bs of the base substrates 85, B6. - Also in such a case, resistance of the leading electrode De8 is reduced, and thus the applicable range, of the
semiconductor device 120 increases. Further, thegroove 38 is formed between the leading electrode De8 and the cap substrate C9. Thus, parasitic capacitance will not be easily formed on a periphery of the leading electrode De8. -
FIGS. 25A to 25D andFIGS. 26A to 26C are schematic cross-sectional views for showing a process of manufacturing thesemiconductor device 120 shown inFIG. 24 . - In
FIG. 25A , the base substrate B5 having the angular velocity sensor element is formed. - In
FIG. 25B , a primary cap substrate C9 a having a primary leading electrode De8 a, which will be the leading electrode De8, is formed. For example, aprimary groove 38 a is formed in the singlecrystal silicon substrate 30 of the primary cap substrate C9 a, and further ametal layer 40 d is formed inside of theprimary groove 38 a. - In
FIG. 25C , the primary cap substrate C9 a shown inFIG. 25B is bonded to the base substrate B5 shown inFIG. 25A . For example, the primary cap substrate C9 a and the base substrate B5 are bonded to each other by a silicon direct bonding technique, which is conducted at a low temperature in a vacuum state. - In
FIG. 25D , the primary cap substrate C9 a is grinded from the top to a position where theprimary groove 38 a penetrates through the primary cap substrate C9 a. In this way, thegroove 38 of thesemiconductor device 120 is formed. The cap substrate C9 is provided by the primary cap substrate C9 a, which is divided into the multiple partial regions Ce by thegroove 38, and themetal part 40 as the element of the leading electrode De8 is provided by themetal layer 40 d. - Next, in
FIG. 26B , the primary base substrate B6 a, which has been formed to have the acceleration sensor element as shown inFIG. 26A , is turned upside down and bonded to the cap substrate C9. - Then, in
FIG. 26C , wiring processing for making electrical connections is conducted in the primary base substrate B6 a, and thus the base substrate B6 is finished. - In this way, the
semiconductor device 120 shown inFIG. 24 is manufactured. - As described in the above, the
primary groove 38 a is formed in the primary cap substrate C9 a in the cap substrate forming step. Then, themetal layer 40 d is formed on the side wall of theprimary groove 38 a, as a part of the leading electrode forming step, to form a primary leading electrode De8 a. In a substrate bonding step shown inFIG. 25C , the base substrate B5 and the primary cap substrate C9 a are bonded in such a manner that the opening of theprimary groove 38 a is opposed to the upper surface of the base substrate B5. After the substrate bonding step, as shown inFIG. 25D , the primary cap substrate C9 a is grinded from the top, that is, from a side opposite to the base substrate B5, to make the cap substrate C9. Thus, the primary leading electrode De8 a and theprimary groove 38 a, respectively, become the leading electrode De8 and thegroove 38. Themetal layer 40 d formed on the side wall of theprimary groove 38 a becomes themetal part 40 of the leading electrode De8. - In each of the above-described
semiconductor devices - The above-described
semiconductor devices -
FIG. 27 is a schematic cross-sectional view of asemiconductor device 130 having a pressure sensor element PS as an example of the semiconductor device according to the embodiment. InFIG. 27 , parts similar to the preceding parts are denoted with like reference characters. - The
semiconductor device 130 has a base substrate B7. The base substrate B7 includes a singlecrystal silicon substrate 25. The thin singlecrystal silicon layer 24 having different conductivity types is formed at an upper surface layer of the singlecrystal silicon substrate 25. A deep,groove 26 is formed at a predetermined region R2 of the base substrate B7. Thegroove 26 extends from a bottom surface to an upper surface of the singlecrystal silicon substrate 25, and a membrane Me is formed above thegroove 26. The singlecrystal silicon layer 24 has multiple impurity diffused regions (base semiconductor regions) Bd, which are insulated and separated from adjacencies by PN-junction separation, in the predetermined region R2. - The membrane Me also has impurity diffused regions Bd1, Bd2. The impurity diffused regions Bd1, Bd2 serve as a pressure sensor element PS. That is, in the
semiconductor device 130, the membrane Me displaces in accordance with pressure applied through thegroove 26. Thus, a change in resistance of the impurity diffused regions Bd1, Bd2 in accordance with the displacement is measured to detect the applied pressure. - Also in the
semiconductor device 130, a cap substrate C11 is bonded to the base substrate B7 made of silicon at the bonding surface D1 and a sealed space is formed above the membrane Me. Thesemiconductor device 130 has a leading electrode De9 constructed of themetal part 40. A lower end of the leading electrode De9 connects to an impurity diffused region (base semiconductor region) Bd3 of the base substrate B7. The leading electrode De9 extends from the upper surface of the base substrate B7 to the upper surface of the cap substrate C4 through thegroove 35 of the cap substrate C11. For example, an upper end of themetal part 40 is located higher than the upper surface of the cap substrate C11. Thebonding wire 60 is connected to an upper end of the leading electrode De9. -
FIGS. 28A to 28D andFIGS. 29A to 29D are schematic cross-sectional views for showing a process of manufacturing thesemiconductor device 130 shown inFIG. 27 . - In
FIG. 28A , the base substrate 87 is formed. Specifically, the thin singlecrystal silicon layer 24 having the different conductivity types is formed at the upper surface layer of the singlecrystal silicon substrate 25. - In
FIG. 18B , structures such as the impurity diffused regions (base semiconductor regions) Bd, Bd1 to Bd3 as shown inFIG. 27 , except thegroove 26, are formed in the predetermined region R2 of the singlecrystal silicon layer 24. - In
FIG. 28C , the cap substrate C11 is formed. For example, the insulatinglayer 32 a and therecess 32 b are formed on the lower surface of the singlecrystal silicon substrate 30, in the similar manner as the cap substrate forming process shown inFIGS. 4A to 4C . - In
FIG. 28D , the base substrate B7 formed in the step shown inFIG. 28B and the cap substrate C11 formed in the step shown inFIG. 28C are positioned relative to each other and bonded to each other. - Next, in
FIG. 29A , atrench 44 is formed at a predetermined position of the cap substrate C11 to reach the impurity diffused region Bd3 of the base substrate B7. - In
FIG. 29B , themetal part 40 is embedded in thetrench 44, and then the upper surface of the cap substrate C11, that is, the upper surface of the singlecrystal silicon substrate 30 is etched such that the upper end of themetal part 40 is located higher than the upper surface of the cap substrate C11. - In
FIG. 29C , a peripheral portion of thetrench 44 in which themetal part 44 has been embedded is etched to form thegroove 35. - In
FIG. 29D , the bonded base substrate B7 and cap substrate C11 is turned upside down, and thegroove 26 is formed from a back side, that is, from the top inFIG. 29D . Thus, the membrane Me, as a thin membrane portion, is formed. Accordingly, the pressure sensor element PS is formed. - In this way, the
semiconductor device 130 shown inFIG. 27 is manufactured. - Similar to the
semiconductor device 100 shown inFIGS. 1A and 1B , thesemiconductor device 130 shown inFIG. 27 has the leading electrode De9 constructed of themetal part 40, and thegroove 35 is formed between themetal part 40 and the cap substrate C11. The upper end of the leading electrode De9 allows the electrical connection with the external part. Therefore, resistance of the leading electrode De9 is reduced, and parasitic capacitance will not be easily formed around the leading electrode De9. - The semiconductor device according to the embodiment can be implemented by combining the above described exemplary semiconductor devices in various ways. Also, as an example of the semiconductor device according to the embodiment, a semiconductor device having a chip in which the mechanical quantity sensor elements, such as the acceleration sensor element and the angular velocity sensor element as shown in
FIG. 1 and the pressure sensor element PS as shown inFIG. 27 are formed and the leading electrode constructed of the metal part separated from the cap substrate by the groove is applicable. - Additional advantages and modifications will readily occur to those skilled in the art. The invention in its broader term is therefore not limited to the specific details, representative apparatus, and illustrative examples shown and described.
Claims (19)
1. A semiconductor device comprising:
a base substrate made of silicon, the base substrate having a plurality of base semiconductor regions in a predetermined portion of a surface layer thereof, the plurality of base semiconductor regions being insulated and separated from each other;
a cap substrate bonded to the predetermined portion of the surface layer of the base substrate; and
a leading electrode including a metal part, the leading electrode passing through the cap substrate, the leading electrode having a first end connected to one of the plurality of base semiconductor regions of the base substrate and a second end located adjacent to a surface of the cap substrate for allowing an electrical connection with an external part, the surface being opposite to a bonding surface at which the base substrate and the cap substrate are bonded, wherein the leading electrode defines a groove between an outer surface thereof and the cap substrate.
2. The semiconductor device according to claim 1 , wherein the cap substrate is made of silicon.
3. The semiconductor device according to claim 2 , wherein
the cap substrate has a plurality of partial regions insulated and separated from each other,
the leading electrode is constructed of the metal part and one of the plurality of partial regions, and
the metal part is disposed around the one of the plurality of partial regions.
4. The semiconductor device according to claim 3 , wherein
the metal part is disposed to cover an end surface of the one of the partial regions, the end surface being adjacent to the second end of the leading electrode.
5. The semiconductor device according to claim 1 , wherein the cap substrate is made of single crystal silicon.
6. The semiconductor device according to claim 5 , wherein
the cap substrate includes a plurality of partial regions insulated and separated from each other, and
one of the plurality of partial regions is provided with an integrated circuit.
7. The semiconductor device according to claim 1 , wherein
the second end of the leading electrode is located further from the bonding surface than the surface of the cap substrate.
8. The semiconductor device according to claim 7 , wherein the second end of the leading electrode has an area greater than an area of the first end.
9. The semiconductor device according to claim 1 , further comprising an insulating layer at a bottom portion of the groove to avoid the groove reaching the base substrate.
10. The semiconductor device according to claim 1 , wherein
the cap substrate is bonded to the predetermined portion of the base substrate such that a sealed space is provided between the cap substrate and the predetermined region of the base substrate.
11. The semiconductor device according to claim 1 , wherein
the base substrate includes a SOI substrate having an embedded oxide film and a SOI layer along the embedded oxide film,
the plurality of base semiconductor regions is provided by the SOI layer and is insulated and separated from each other through a trench formed in the SOI layer, the trench reaching the embedded oxide film.
12. The semiconductor device according to claim 1 , wherein
at least one of the plurality of base semiconductor regions provides a fixed semiconductor region including a fixed electrode,
at least another one of the plurality of base semiconductor regions provides a movable semiconductor region including a movable electrode opposed to the fixed electrode and displaceable relative to the fixed electrode, the movable electrode is formed by conducting a sacrifice layer etching at a portion of the embedded oxide film,
the leading electrode is connected to each of the fixed semiconductor region and the movable semiconductor region,
the fixed semiconductor region and the movable semiconductor region constitute a mechanical quantity sensor element for detecting a mechanical quantity applied thereto, the mechanical quantity being detected based on a change in capacitance between the fixed electrode and the movable electrode in accordance with a change in distance between the fixed electrode and the movable electrode due to the movable electrode being displaced relative to the fixed electrode by the mechanical quantity.
13. The semiconductor device according to claim 12 , wherein
the mechanical quantity includes one of acceleration and angular velocity.
14. The semiconductor device according to claim 1 , wherein
the base substrate includes a single crystal silicon substrate,
the plurality of base semiconductor regions include impurity diffused regions that are insulated and separated by PN-junction separation.
15. The semiconductor device according to claim 14 , wherein
the single crystal silicon substrate has a membrane at a surface portion thereof,
at least one of the impurity diffused regions is disposed in the membrane and constitutes a pressure sensor element for detecting a pressure applied to the membrane based on a change in resistance of the impurity diffused region in accordance with displacement of the membrane by the pressure.
16. A method of manufacturing a semiconductor device, comprising:
forming a base substrate made of silicon, wherein the base substrate has a plurality of base semiconductor regions in a predetermined portion of a surface layer thereof, the plurality of base semiconductor regions is insulated and separated from each other;
forming a cap substrate;
bonding the cap substrate to the predetermined portion of the base substrate; and
forming a leading electrode including a metal part, wherein the leading electrode passes through the cap substrate, the leading electrode has a first end connected to one of the plurality of base semiconductor regions and a second end located adjacent to, a surface of the cap substrate, and the leading electrode defines a groove between an outer surface thereof and the cap substrate.
17. The method according to claim 16 , further comprising:
forming a trench in the cap substrate to reach the one of the plurality of base semiconductor regions after the bonding, wherein
the forming of the leading electrode includes embedding a metal for providing the metal part in the trench and forming the groove on a periphery of the trench.
18. The method according to claim 16 , wherein
the forming of the leading electrode is partly conducted in the forming of the cap substrate so that the leading electrode is formed in condition of being connected to the cap substrate,
the bonding includes connecting the first end of the leading electrode to the one of the plurality of base semiconductor regions, and
the remainder of the forming of the leading electrode is performed after the bonding.
19. The method according to, claim 16 , wherein
the forming of the cap substrate includes forming a primary groove in a primary cap substrate,
the forming of the cap substrate further includes forming a primary leading electrode, as a part of the forming of the leading electrode, by applying a metal on a side wall of the primary groove, and
the bonding includes connecting the primary cap substrate to the base substrate such that an opening of the primary groove is opposed to the base substrate,
the method further comprising:
grinding a surface of the primary cap substrate, the surface being opposite to a bonding surface at which the primary cap substrate and the base substrate are bonded, so that the cap substrate is provided by the primary cap substrate, and the leading electrode and the groove are respectively provided by the primary leading electrode and the primary groove.
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Also Published As
Publication number | Publication date |
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JP5115618B2 (en) | 2013-01-09 |
JP2011146687A (en) | 2011-07-28 |
US8941229B2 (en) | 2015-01-27 |
US20140048922A1 (en) | 2014-02-20 |
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