US20110186978A1 - Stack package - Google Patents
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- Publication number
- US20110186978A1 US20110186978A1 US12/794,324 US79432410A US2011186978A1 US 20110186978 A1 US20110186978 A1 US 20110186978A1 US 79432410 A US79432410 A US 79432410A US 2011186978 A1 US2011186978 A1 US 2011186978A1
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- United States
- Prior art keywords
- pads
- semiconductor chip
- electrodes
- disposed
- connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 claims abstract description 234
- 239000003990 capacitor Substances 0.000 claims abstract description 95
- 239000003989 dielectric material Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims description 57
- 239000008393 encapsulating agent Substances 0.000 claims description 12
- 238000007789 sealing Methods 0.000 claims description 9
- 229910000679 solder Inorganic materials 0.000 description 11
- 238000000034 method Methods 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 229920006336 epoxy molding compound Polymers 0.000 description 4
- 238000013500 data storage Methods 0.000 description 3
- 230000001603 reducing effect Effects 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
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Definitions
- the present invention relates generally to a stack package, to and more particularly, to a stack package in which a capacitor is embedded to reduce power noise.
- a semiconductor package having a semiconductor chip capable of storing and/or processing a huge amount of data within a short period has been developed.
- stack a package in which a plurality of semiconductor chips are stacked, increases data storage capacity. Further, a stack package is known, in which a memory semiconductor chip and a system semiconductor chip are stacked to increase a data storage capacity and also to improve a data processing speed.
- One exemplary method of decreasing the inductance component at the package level includes a decoupling capacitor disposed between a power pad and a ground pad.
- Such a capacitor is often formed on the surface of a semiconductor chip, or formed as an embedded capacitor, which is embedded in a substrate.
- Embodiments of the present invention include a stack package in which a capacitor for reducing power noise is reliably embedded at a reduced cost.
- embodiments of the present invention include a stack package which can realize a capacitor of a large capacity.
- embodiments of the present invention include a stack package which can prevent the volume of the package from increasing and accomplish the simplification of manufacturing processes.
- a stack package comprises a first semiconductor chip having a first surface on which first pads and second pads are disposed and a second surface which faces away from the first surface; a second semiconductor chip having a third surface which faces the first surface of the first semiconductor chip and on which third pads and fourth pads electrically connected with the second pads are disposed, and a fourth surface which faces away from the third surface; and capacitors interposed between the first semiconductor chip and the second semiconductor chip, and having first electrodes which are electrically connected with the first pads of the first semiconductor chip, second electrodes which are electrically is connected with the third pads of the second semiconductor chip, and dielectrics which are interposed between the first electrodes and the second electrodes.
- the stack package may further comprise first connection members electrically connecting the second pads of the first semiconductor chip and the fourth pads of the second semiconductor chip.
- the first pads may comprise power pads and the third pads may comprise ground pads, or the first pads may comprise ground pads and the third pads may comprise power pads.
- the first electrodes of the capacitors may be electrically connected with the first pads of the first semiconductor chip by the medium of second connection members, and the second electrodes of the capacitors may be electrically connected with the third pads of the second semiconductor chip by the medium of third connection members.
- the first electrodes and the second electrodes of the capacitors may be disposed to directly contact the first surface of the first semiconductor chip including the first pads and the third surface of the second semiconductor chip including the third pads, respectively.
- the first electrodes and the second electrodes of the capacitors may have a plate-like shape.
- the first electrode of each capacitor may include a first is plate part and a plurality of first projecting parts which are formed on the first plate part to extend toward the second electrode, and the second electrode of each capacitor may include a second plate part and a plurality of second projecting parts which are formed on the second plate part to be placed between the first projecting parts.
- Each capacitor including the first electrode, the second electrode and the dielectric may have an area that is less than that of each of the first and second semiconductor chips.
- the dielectrics of the capacitors may be disposed only between the first electrodes and the second electrodes.
- the dielectrics of the capacitors may be disposed in a space between the first semiconductor chip and the second semiconductor chip, including spaces between the first electrodes and the second electrodes.
- Each of the capacitors may have an area that is the same as that of each of the first and second semiconductor chips and may be defined with an opening through which a connection part between the second pad of the first semiconductor chip and the fourth pad of the second semiconductor chip passes.
- the stack package may further comprise first redistribution lines disposed on the third surface of the second semiconductor chip such that one ends thereof are electrically connected with the third pads and the other ends thereof extend to a first edge of the third surface; and second redistribution lines disposed on the third is surface of the second semiconductor chip such that one ends thereof are electrically connected with the fourth pads and the other ends thereof extend to a second edge of the third surface which is opposite the first edge.
- the stack package may further comprise a substrate having a fifth surface to which the fourth surface of the second semiconductor chip is attached and on which first connection pads connected with the first redistribution lines and second connection pads connected with the second redistribution lines are disposed, and a sixth surface which faces away from the fifth surface and on which third connection pads are disposed; connection members connecting the other ends of the first redistribution lines with the first connection pads and the other ends of the second redistribution lines with the second connection pads; an encapsulant sealing the fifth surface of the substrate including the first and second semiconductor chips and the connection members; and external mounting members attached to the third connection members of the substrate.
- the stack package may further comprise through-electrodes formed in the second semiconductor chip to pass through the third and fourth surfaces of the second semiconductor chip, and connected with the third pads and the fourth pads.
- the stack package may further comprise a substrate having a fifth surface to which the fourth surface of the second is semiconductor chip is attached and on which first connection pads and second connection pads connected with the through-electrodes are disposed, and a sixth surface which faces away from the fifth surface and on which third connection pads are disposed; an encapsulant sealing the fifth surface of the substrate including the first and second semiconductor chips; and external mounting members attached to the third connection pads of the substrate.
- a stack package comprises a first semiconductor chip having a first surface on which first pads and second pads are disposed and a second surface which faces away from the first surface; a second semiconductor chip having a third surface which faces the first surface of the first semiconductor chip and on which third pads and fourth pads electrically connected with the second pads are disposed, and a fourth surface which faces away from the third surface; connection members electrically connecting the first pads with the third pads and the second pads with the fourth pads; a substrate having a fifth surface to which the fourth surface of the second semiconductor chip is attached and on which first connection pads and second connection pads are disposed, and a sixth surface which faces away from the fifth surface and on which third connection pads are disposed; capacitors having first electrodes which are electrically connected with the third pads, second electrodes which are connected with the first connection pads, and dielectrics interposed between the first electrodes and second electrodes; and connection members connecting the fourth pads of the second semiconductor chip with the second connection pads of the substrate.
- the stack package may further comprise first redistribution lines disposed on the third surface of the second semiconductor chip such that one ends thereof are electrically connected with the third pads and the other ends thereof extend to a first edge of the third surface, to be connected with the first electrodes of the capacitors; and second redistribution lines disposed on the third surface of the second semiconductor chip such that one ends thereof are electrically connected with the fourth pads and the other ends thereof extend to a second edge of the third surface which is opposite the first edge, to be connected with the second connection pads of the substrate.
- the stack package may further comprise an encapsulant sealing the fifth surface of the substrate including the first and second semiconductor chips and the capacitors; and external mounting members attached to the third connection members of the substrate.
- a stack package comprises a first semiconductor chip having a first surface on which first pads and second pads are disposed and a second surface which faces away from the first surface; a second is semiconductor chip having a third surface which faces the first surface of the first semiconductor chip and on which third pads and fourth pads electrically connected with the second pads are disposed, and a fourth surface which faces away from the third surface; first redistribution lines disposed on the third surface of the second semiconductor chip, and having one ends which are connected with the first pads and the third pads and the other ends which extend to a first side surface meeting the third surface; second redistribution lines disposed on the third surface of the second semiconductor chip, and having one ends which are connected with the second pads and the fourth pads and the other ends which extend to a second side surface facing away from the first side surface; a substrate having a fifth surface to which the fourth surface of the second semiconductor chip is attached and on which first connection pads and second connection pads are disposed, and a sixth surface which faces away from the fifth surface and on which third connection pads
- the first and second redistribution lines may directly contact the first and third pads and the second and fourth pads, and may be electrically insulated from the first and second semiconductor chips.
- FIGS. 1 and 2 are cross-sectional views showing a stack package in accordance with an embodiment of the present invention.
- FIGS. 3 through 7 are cross-sectional views showing a capacitor of the stack package in accordance with an embodiment of the present invention.
- FIG. 8 is a cross-sectional view showing a stack package in accordance with an embodiment of the present invention.
- FIG. 9 is a cross-sectional view showing a stack package in accordance with an embodiment of the present invention.
- FIG. 10 is a cross-sectional view showing a stack package in accordance with an embodiment of the present invention.
- the capacitors can be relatively simply formed, costs can be saved, and reliability can be secured.
- capacitors of a large capacity advantageous to the reduction of power noise can be easily realized.
- the capacitors are disposed between the upper semiconductor chip and the lower semiconductor chip, the volume of the entire stack package is not unnecessarily increased.
- FIGS. 1 and 2 are cross-sectional views showing a stack package in accordance with an embodiment of the present invention.
- a stack package 100 in accordance with an embodiment of the present invention includes a first semiconductor chip 110 , a second semiconductor chip 120 , and capacitors 130 connected to the first semiconductor chip 110 and the second semiconductor chip 120 .
- the first semiconductor chip 110 has a first surface S 1 on which first pads 112 and second pads 114 are disposed and a second surface S 2 which faces away from the first surface S 1 .
- the second semiconductor chip 120 has a third surface S 3 on which third pads 122 and fourth pads 124 are disposed and a fourth surface S 4 which faces away from the third surface S 3 .
- the first semiconductor chip 110 and the second semiconductor chip 120 are oppositely positioned. That is, for example, the first semiconductor chip 110 is positioned above the second semiconductor chip 120 , and the first surface S 1 of the first semiconductor 110 faces the third surface S 3 of the second semiconductor chip 120 .
- the first pads 112 of the first semiconductor chip 110 are power pads
- the third pads 122 of the second semiconductor chip 120 which correspond to the first pads 112 of the first semiconductor chip 110
- the first pads 112 of the first semiconductor chip 110 may be ground pads
- the third pads 122 of the second semiconductor chip 120 which correspond to the first pads 112 of the first semiconductor chip 110
- Both the second pads 114 of the first semiconductor chip 110 and the fourth pads 124 of the second semiconductor chip 120 are signal pads.
- each of the first semiconductor chip 110 and the second is semiconductor chip 120 has therein a circuit unit, which includes a data storage section for storing data and a data processing section for processing data.
- the third pads 122 of the second semiconductor chip 120 can be disposed at positions which face the first pads 112 of the first semiconductor chip 110 as shown in FIG. 1 .
- the third pads 122 of the second semiconductor chip 120 can be disposed at positions which do not face the first pads 112 of the first semiconductor chip 110 .
- the second pads 114 of the first semiconductor chip 110 and the corresponding fourth pads 124 of the second semiconductor chip 120 are electrically connected with each other through first connection members 142 .
- the first connection members 142 may comprise an electrically conductive material, for example, solders or bumps.
- Each capacitor 130 includes a first electrode 132 electrically connected with the first pad 112 of the first semiconductor chip 110 , a second electrode 134 electrically connected with the third pad 122 of the second semiconductor chip 120 , and a dielectric 136 interposed between the first electrode 132 and the second electrode 134 .
- the first electrode 132 is electrically connected with the first pad 112 of the first semiconductor chip 110 through a second is connection member 144
- the second electrode 134 is electrically connected with the third pad 122 of the second semiconductor chip 120 through a third connection member 146 .
- the second and third connection members 144 and 146 may comprise an electrically conductive material, for example solders or bumps.
- a surface of the capacitor 130 has an area that is less than an area of the surfaces S 1 , S 3 of the first and second semiconductor chips 110 and 120 , respectively.
- a surface of the capacitor 130 can have an area as great as the area of each of the surfaces S 1 , S 3 first and second semiconductor chips 110 and 120 , respectively, in order to secure an increased capacity.
- the capacitor 130 has an opening v through which a connection part between the second pad 114 of the first semiconductor chip 110 and the fourth pad 124 of the second semiconductor chip 120 passes.
- the first electrode 132 , the second electrode 134 and the dielectric 136 of the capacitor 130 are formed so as to have defined therein the opening v through which the first connection member 142 connecting the second pad 114 of the first semiconductor chip 110 and the fourth pad 124 of the second semiconductor chip 120 passes.
- the first electrode 132 and the second electrode 134 of the capacitor 130 are connected with the first pad 112 of the first semiconductor chip 110 and the third pad 122 of the second semiconductor chip 120 through the second connection member 144 and the third connection member 146 , respectively.
- the first electrode 132 and the second electrode 134 of the capacitor 130 can be formed so as to directly contact the first surface S 1 of the first semiconductor chip 110 including the first pad 112 and the third surface S 3 of the second semiconductor chip 120 including the third pad 122 , respectively.
- a surface of the capacitor 130 which includes the first electrode 132 and the second electrode 134 formed to directly contact the first surface S 1 of the first semiconductor chip 110 and the third surface S 3 of the second semiconductor chip 120 , can have an area that is less than the area of surfaces S 1 and S 3 of the first and second semiconductor chips 110 and 120 , respectively, as shown in FIG. 4 , or can have an area that is the same as the area of the surfaces S 1 and S 3 of the first and second semiconductor chips 110 and 120 , respectively, as shown in FIG. 5 , in order to secure an increased capacity.
- the capacitor 130 has an opening v through which the first connection member 142 connecting the second pad 114 of the first semiconductor chip 110 and the fourth pad 124 of the second semiconductor chip 120 passes.
- each of the first electrode 132 and the second electrode 134 of the capacitor 130 is formed to have a plate-like shape as shown in FIGS. 1 through 5 .
- the first electrode 132 can be formed to have a first plate part 132 a and a plurality of first projecting parts 132 b formed on the first plate part 132 a so as to project toward the second electrode 134
- the second electrode 134 can be formed to have a second plate part 134 a and a plurality of second projecting parts 134 b formed on the second plate part 134 a so as to be respectively placed between the first projecting parts 132 b.
- a surface of the capacitor 130 which includes the first electrode 132 having the first plate part 132 a and the first projecting parts 132 b and the second electrode 134 having the second plate part 134 a and the second projecting parts 134 b , can be formed to have an area that is less than the area of each of the surfaces S 1 and S 3 of the first and second semiconductor chips 110 and 120 , respectively, as shown in FIG. 6 , or can be formed to have an area that is the same as the area of each of the surfaces S 1 and S 3 of the first and second semiconductor chips 110 and 120 , as shown in FIG. 7 .
- the capacitor 130 has an opening v through which the first connection member 142 connecting the second pad 114 of the first semiconductor chip 110 and the fourth pad 124 of the second semiconductor chip 120 passes.
- the space between the first semiconductor chip 110 and the second semiconductor chip 120 is filled with the dielectric 136 of the capacitor 130 , therefore it is not necessary to fill a separate underfill in the space between the first semiconductor chip 110 and the second semiconductor chip 120 , and an underfill omission effect can be achieved.
- the third pads 122 of the second semiconductor chip 120 are disposed on the third surface S 3 of the second semiconductor chip 120 in such a way as to respectively face the first pads 112 of the first semiconductor chip 110 , it is conceivable that the third pads 122 of the second semiconductor chip 120 can be disposed on the third surface S 3 of the second semiconductor chip 120 at positions which do not face the first pads 112 of the first semiconductor chip 110 . In this case, it can be understood that the shape of the capacitors 130 is changed accordingly.
- the stack package 100 can include first redistribution lines 126 and second redistribution lines 128 which are formed on the third surface S 3 of the second semiconductor chip 120 .
- Each first redistribution line 126 is disposed on the third surface S 3 of the second semiconductor chip 120 such that one end thereof is electrically connected with the third pad 122 and the second end thereof extends to an edge of the third surface S 3 .
- Each second redistribution line 128 is disposed on the third surface S 3 of the second semiconductor chip 120 such that one end thereof is electrically connected with the fourth pad 124 and the second end thereof extends to a second edge of the third surface S 3 which is opposite the first edge.
- the first and second redistribution lines 126 and 128 facilitate easy electrical connection with a substrate, which will be described below.
- the stack package 100 as shown in FIG. 2 can further includes a substrate 160 having an upper surface on which the second semiconductor chip 120 is attached, connection members 172 and 174 which connect the redistribution lines 126 and 128 with the substrate 160 , and an encapsulant 180 sealing the first and second semiconductor chips 110 and 120 and the connection members 172 and 174 , and external mounting members 190 which are attached to the substrate 160 .
- the substrate 160 has a fifth surface S 5 to which the fourth surface S 4 of the second semiconductor chip 120 is attached and on which first connection pads 162 and second connection pads 164 are disposed, and a sixth surface S 6 which faces away from the fifth surface S 5 and on which third connection pads 166 are disposed.
- the substrate 160 may comprise a printed circuit board.
- the first connection pads 162 are disposed on portions of the fifth surface S 5 of the substrate 160 which are adjacent to the second of the first redistribution lines 126 , and are electrically connected with the first redistribution lines 126 through the first connection members 172 .
- the second connection pads 164 are disposed on portions of the fifth surface S 5 of the substrate 160 which at the second ends of the second redistribution lines 128 , and are electrically connected with the second redistribution lines 128 through the second connection members 174 .
- the first connection members 172 and the second connection members 174 preferably comprise conductive wires, or may comprise a conductive ink or a pattern film.
- the encapsulant 180 preferably comprises an epoxy molding compound (EMC), or may comprise other insulation materials.
- EMC epoxy molding compound
- the external mounting members 190 preferably comprise solder balls, or may comprise conductive pins or a solder paste.
- the stack package according to an embodiment has a structure in which the capacitors are connected to the power pads of the first semiconductor chip and the grounds pads of the second semiconductor chip, the capacitors are can be easily formed, and the reliability of the capacitors can be improved.
- the stack package has a structure in which the capacitors are disposed between the first semiconductor chip and the second semiconductor chip, the volume of the package is not unnecessarily increased, and a separate process for mounting capacitors is not needed.
- the capacitors can have a large capacity since sectional shape of the capacitor electrodes can be optionally changed as described above, and accordingly, power noise reducing effect can be improved.
- FIG. 8 is a cross-sectional view showing an exemplary stack package.
- the same reference numerals will be used to refer to the same component elements as those shown in FIG. 2 , and the detailed descriptions of the same component elements will be omitted herein.
- a stack package 200 includes first and second through-electrodes 152 and 154 formed within a second semiconductor chip 120 .
- the first and second through-electrodes 152 and 154 are formed so as to pass through a third surface S 3 and a fourth surface S 4 of the second semiconductor chip 120 and be connected with third pads 122 and fourth pads 124 , respectively.
- the first and second through-electrodes 152 and 154 are electrically insulated from the body of the second semiconductor chip 120 .
- the stack package 200 as shown in FIG. 8 further includes a substrate 160 and connection members 162 and 164 .
- the positions of the connection members 162 and 164 are changed when compared to those of the first embodiment.
- the substrate 160 may comprise a printed circuit board.
- the substrate 160 has a fifth surface S 5 to which the fourth surface S 4 of the second semiconductor chip 120 is attached and on which first connection pads 162 and second connection pads 164 are disposed, and a sixth surface S 6 which faces away from the fifth surface S 5 and on which third connection pads 166 are disposed.
- the first connection pads 162 and the second connection pads 164 are respectively connected with the first through-electrodes 152 and the second through-electrodes 154 , as will be described below in detail.
- the stack package 200 as shown in FIG. 8 further includes an encapsulant 180 sealing the fifth surface S 5 of the substrate 160 and the first and second semiconductor chip 110 and 120 , and includes external mounting members 190 , which are attached to the third connection pads 166 of the substrate 160 .
- the external mounting members 190 preferably comprise solder balls, or may comprise conductive pins or a solder paste.
- the stack package 200 as shown in FIG. 8 further includes capacitors 130 constructed so as to be connected with the first and second semiconductor chips 110 and 120 .
- Each capacitor 130 includes a first electrode 132 electrically connected with each first pad 112 of the first semiconductor chip 110 through a second connection member 144 , a second electrode 134 electrically connected with each third pad 122 of the second semiconductor chip 120 through a third connection member 146 , and a dielectric 136 interposed between the first electrode 132 and the second electrode 134 .
- a surface of the capacitor 130 has an area that is less than the area of each of the surfaces S 1 and S 3 of the first and second semiconductor chips 110 and 120 , respectively, it can be envisaged that a surface of the capacitor 130 can have an area that is the same as the area of each of the surfaces S 1 and S 3 of the first and second semiconductor chips 110 and 120 , respectively, as shown in FIG. 3 , so as to secure a large capacity.
- the capacitor 130 has an opening v through which the first connection member 142 connecting the second pad 114 of the first semiconductor chip 110 and the fourth pad 124 of the second semiconductor chip 120 passes.
- first and second electrodes 132 and 134 of the capacitor 130 are formed to be respectively connected with the first pad 112 of the first semiconductor chip 110 and the third pad 122 of the second semiconductor chip 120 through the second and third connection members 144 and 146 , it can be contemplated that the first electrode 132 and the second electrode 134 of the capacitor 130 can be formed in such a way as to directly contact the first surface S 1 of the first semiconductor chip 110 including the first pad 112 and the third surface S 3 of the second semiconductor chip 120 including the third pad 122 , respectively, as shown in FIGS. 4 and 5 .
- each of the first and second electrodes 132 and 134 of the capacitor 130 has a plate-like shape
- the first electrode 132 can be formed to have a first plate part and first projecting parts and the second electrode 134 can be formed to have a second plate part and second projecting parts as shown in FIGS. 6 and 7 , in order to secure a large capacity.
- the capacitor 130 which includes the first electrode 132 having the first plate part and the first projecting parts, the second electrode 134 having the second plate part and the second projecting parts, and the dielectric 136 interposed between the first electrode 132 and the second electrode 134 , can be formed such that an area of a surface of the capacitor 130 is less than that of each of the surfaces S 1 and S 3 of the first and second semiconductor chips 110 and 120 , respectively, as shown in FIG. 6 , or can be formed such that an area of a surface of the capacitor 130 is the same as that of each of the first and second semiconductor chips 110 and 120 , as shown in FIG. 7 .
- FIG. 9 is a cross-sectional view showing an exemplary stack package.
- the same reference numerals will be used to refer to the same component elements as those shown in FIG. 2 , and the detailed descriptions of the same component elements will be omitted herein.
- a stack package 300 includes capacitors 130 which are formed between a second semiconductor chip 120 and a substrate 160 .
- each capacitor 130 includes a first electrode 132 which is connected to a third pad 122 of a second semiconductor chip 120 , a second electrode 134 which is connected to a first connection pad 162 of a substrate 160 , and a dielectric 136 which is interposed between the first electrode 132 and the second electrode 134 .
- the first electrode 132 is connected with the second of a first redistribution line 126 formed on a third surface S 3 of the second semiconductor chip 120 , where one end of the first redistribution line 126 is connected with the third pad 122 and the second end extending to the first edge of the third surface S 3 . Therefore, it can be understood that the first electrode 132 is electrically connected with the third pad 122 of the second semiconductor chip 120 through the first redistribution line 126 .
- the dielectric 136 of the capacitor 130 is not limited to the shape as shown in FIG. 8 and can be formed to have various shapes according to different manufacturing processes.
- a second pad 114 disposed on a first surface S 1 of a first semiconductor chip 110 and a fourth pad 124 disposed on the third surface S 3 of the second semiconductor chip 120 are electrically connected with each other through a first connection member 142
- a first pad 112 disposed on the first surface S 1 of the first semiconductor chip 110 and the third pad 122 disposed on the third surface S 3 of the second semiconductor chip 120 are electrically connected with each other through a fourth connection member 148 .
- the first and fourth connection members 142 and 148 may comprise, for example, a conductive material such as solders or bumps.
- a second redistribution line 128 is formed on the third surface S 3 of the second semiconductor chip 120 such that one end thereof is electrically connected with the fourth pad 124 and a second end extends to the second edge of the third surface S 3 which is opposite the first edge.
- the second of the second redistribution line 128 is connected with a second connection pad 164 which is disposed on a fifth surface S 5 of the substrate 160 , through a connection member 176 .
- the fifth surface S 5 of the substrate 160 , the first and second semiconductor chips 110 and 120 , and the capacitors 130 are sealed by an encapsulant 180 such as an EMC.
- External mounting members 190 such as solder balls are attached to third connection pads 166 disposed on a sixth surface S 6 of the substrate 160 facing away from the fifth surface S 5 .
- FIG. 10 is a cross-sectional view illustrating an exemplary stack package.
- the same reference numerals will be used to refer to the same component elements as those shown in FIG. 2 , and the detailed descriptions of the same component elements will be omitted herein.
- a stack package 400 includes first and second semiconductor chips 110 and 120 which are oppositely positioned, a substrate 160 to which a fourth surface S 4 of the second semiconductor chip 120 is attached, and capacitors 130 which are formed between the second semiconductor chip 120 and the substrate 160 .
- the stack package 400 further includes first redistribution lines 126 and second redistribution lines 128 which are interposed between the first semiconductor chip 110 and the second semiconductor chip 120 .
- Each first redistribution line 126 is formed on a third surface S 3 of the second semiconductor chip 120 such that a first end thereof is connected with a first pad 112 of the first semiconductor chip 110 and a third pad 122 of the second semiconductor chip 120 and a second end thereof extends to a first side surface adjoining the third surface S 3 .
- Each second redistribution line 128 is formed on the third surface S 3 of the second semiconductor chip 120 such that a first end thereof is connected with a second pad 114 of the first semiconductor chip 110 and a fourth pad 124 of the second semiconductor chip 120 and a second end thereof extends to a second side surface adjoining the third surface S 3 and facing away from the first side surface.
- the first and second redistribution lines 126 and 128 are disposed to directly contact both a first surface S 1 of the first semiconductor chip 110 , including first pads 112 , and the third surface S 3 of the second semiconductor chip 120 , including third pads 122 , and the first surface S 1 of the first semiconductor chip 110 , including second pads 114 , and the third surface S 3 of the second semiconductor chip 120 , including fourth pads 124 , respectively.
- the first and second redistribution lines 126 and 128 are electrically insulated from the bodies of the first and second semiconductor chips 110 and 120 .
- the substrate 160 has a fifth surface S 5 to which the fourth surface S 4 of the second semiconductor chip 120 is attached and on which first and second connection pads 162 and 164 are disposed, and a sixth surface S 6 facing away from the fifth surface S 5 on which third connection pads 166 are disposed.
- the first connection pads 162 are disposed on portions of the fifth surface S 5 of the substrate 160 adjacent to the first side surface of the second semiconductor chip 120
- the second connection pads 164 are disposed on portions of the fifth surface S 5 of the substrate 160 adjacent to the second side surface of the second semiconductor chip 120 .
- Each capacitor 130 includes a first electrode 132 connected with the third pad 122 of the second semiconductor chip 120 , a second electrode 134 connected with the first connection pad 162 of the substrate 160 , and a dielectric 136 interposed between the first electrode 132 and the second electrode 134 .
- the first electrode 132 is formed to be connected with the second end of the first redistribution line 126 which has the first end thereof connected with the third pad 122 of the second semiconductor chip 120 and the second end thereof disposed on the first side surface of the second semiconductor chip 120 . Therefore, it can be understood that the first electrode 132 is electrically connected with the third pad 122 of the second semiconductor chip 120 through the first redistribution line 126 .
- the dielectric 136 of the capacitor 130 can be formed to have various shapes in addition to the shape shown in the drawing.
- the stack package 400 further includes connection members 178 connecting the second ends of the second redistribution lines 128 disposed on the second side surface with second connection pads 164 of the substrate 160 , external mounting members 190 attached to third connection pads 166 disposed on the sixth surface S 6 of the substrate 160 , and an encapsulant 180 sealing the fifth surface S 5 of the substrate 160 , the first and second semiconductor chips 110 and 120 , and the capacitors 130 .
- the connection members 178 can comprise a conductive material such as solders, and the encapsulant 180 can comprise, for example, an EMC.
- the external mounting members 190 preferably comprise solder balls, or can comprise conductive pins or a solder paste.
- the first connection pads 162 of the substrate 160 to which the second is electrodes 134 of the capacitors 130 are connected, comprise power pads
- the first connection pads 162 of the substrate 160 to which the second electrodes 134 of the capacitors 130 are connected, comprise ground pads
- the first and third pads 112 and 122 of the first and second semiconductor chips 110 and 120 which are connected to the first electrodes 132 of the capacitors 130 through the first redistribution lines 126 , comprise ground pads.
- the stack package according to the present invention provides advantages in that, since the stack package has a structure in which decoupling capacitors are disposed between power pads and ground pads at a package level, power noise can be effectively reduced through the reduction of an inductance component, and accordingly, a desired data processing speed can be maintained.
Abstract
A stack package includes a first semiconductor chip first pads and second pads disposed thereon and a second semiconductor chip having third pads and fourth pads electrically connected with the second pads disposed thereon. Capacitors are interposed between the first semiconductor chip and the second semiconductor chip, and include first electrodes electrically connected with the first pads to of the first semiconductor chip, second electrodes electrically connected with the third pads of the second semiconductor chip, and dielectrics interposed between the first electrodes and the second electrodes.
Description
- The present application claims priority to Korean patent application number 10-2010-0010105 filed on Feb. 3, 2010, which is incorporated herein by reference in its entirety.
- The present invention relates generally to a stack package, to and more particularly, to a stack package in which a capacitor is embedded to reduce power noise.
- A semiconductor package having a semiconductor chip capable of storing and/or processing a huge amount of data within a short period has been developed.
- It is known that stack a package, in which a plurality of semiconductor chips are stacked, increases data storage capacity. Further, a stack package is known, in which a memory semiconductor chip and a system semiconductor chip are stacked to increase a data storage capacity and also to improve a data processing speed.
- In order to maintain a data processing speed at a high level, it is necessary to minimize power noise that is generated at an operating frequency of a semiconductor chip.
- In general, reduction of power noise at a package level is effectively accomplished by decreasing an inductance component. One exemplary method of decreasing the inductance component at the package level, includes a decoupling capacitor disposed between a power pad and a ground pad.
- Such a capacitor is often formed on the surface of a semiconductor chip, or formed as an embedded capacitor, which is embedded in a substrate.
- Known methods of forming such a capacitor are costly and are unreliable.
- Further, according to the known methods, it is difficult to realize a capacitor having a large capacity, and therefore such capacitors have limitations in reducing power noise.
- In addition, in the case of mounting the capacitor on the substrate, a problem is caused in that the volume of a package increases and a separate mounting process is needed.
- Embodiments of the present invention include a stack package in which a capacitor for reducing power noise is reliably embedded at a reduced cost.
- Also, embodiments of the present invention include a stack package which can realize a capacitor of a large capacity.
- Further, embodiments of the present invention include a stack package which can prevent the volume of the package from increasing and accomplish the simplification of manufacturing processes.
- In one embodiment of the present invention, a stack package comprises a first semiconductor chip having a first surface on which first pads and second pads are disposed and a second surface which faces away from the first surface; a second semiconductor chip having a third surface which faces the first surface of the first semiconductor chip and on which third pads and fourth pads electrically connected with the second pads are disposed, and a fourth surface which faces away from the third surface; and capacitors interposed between the first semiconductor chip and the second semiconductor chip, and having first electrodes which are electrically connected with the first pads of the first semiconductor chip, second electrodes which are electrically is connected with the third pads of the second semiconductor chip, and dielectrics which are interposed between the first electrodes and the second electrodes.
- The stack package may further comprise first connection members electrically connecting the second pads of the first semiconductor chip and the fourth pads of the second semiconductor chip.
- The first pads may comprise power pads and the third pads may comprise ground pads, or the first pads may comprise ground pads and the third pads may comprise power pads.
- The first electrodes of the capacitors may be electrically connected with the first pads of the first semiconductor chip by the medium of second connection members, and the second electrodes of the capacitors may be electrically connected with the third pads of the second semiconductor chip by the medium of third connection members.
- The first electrodes and the second electrodes of the capacitors may be disposed to directly contact the first surface of the first semiconductor chip including the first pads and the third surface of the second semiconductor chip including the third pads, respectively.
- The first electrodes and the second electrodes of the capacitors may have a plate-like shape.
- The first electrode of each capacitor may include a first is plate part and a plurality of first projecting parts which are formed on the first plate part to extend toward the second electrode, and the second electrode of each capacitor may include a second plate part and a plurality of second projecting parts which are formed on the second plate part to be placed between the first projecting parts.
- Each capacitor including the first electrode, the second electrode and the dielectric may have an area that is less than that of each of the first and second semiconductor chips.
- The dielectrics of the capacitors may be disposed only between the first electrodes and the second electrodes.
- The dielectrics of the capacitors may be disposed in a space between the first semiconductor chip and the second semiconductor chip, including spaces between the first electrodes and the second electrodes.
- Each of the capacitors may have an area that is the same as that of each of the first and second semiconductor chips and may be defined with an opening through which a connection part between the second pad of the first semiconductor chip and the fourth pad of the second semiconductor chip passes.
- The stack package may further comprise first redistribution lines disposed on the third surface of the second semiconductor chip such that one ends thereof are electrically connected with the third pads and the other ends thereof extend to a first edge of the third surface; and second redistribution lines disposed on the third is surface of the second semiconductor chip such that one ends thereof are electrically connected with the fourth pads and the other ends thereof extend to a second edge of the third surface which is opposite the first edge.
- The stack package may further comprise a substrate having a fifth surface to which the fourth surface of the second semiconductor chip is attached and on which first connection pads connected with the first redistribution lines and second connection pads connected with the second redistribution lines are disposed, and a sixth surface which faces away from the fifth surface and on which third connection pads are disposed; connection members connecting the other ends of the first redistribution lines with the first connection pads and the other ends of the second redistribution lines with the second connection pads; an encapsulant sealing the fifth surface of the substrate including the first and second semiconductor chips and the connection members; and external mounting members attached to the third connection members of the substrate.
- The stack package may further comprise through-electrodes formed in the second semiconductor chip to pass through the third and fourth surfaces of the second semiconductor chip, and connected with the third pads and the fourth pads.
- The stack package may further comprise a substrate having a fifth surface to which the fourth surface of the second is semiconductor chip is attached and on which first connection pads and second connection pads connected with the through-electrodes are disposed, and a sixth surface which faces away from the fifth surface and on which third connection pads are disposed; an encapsulant sealing the fifth surface of the substrate including the first and second semiconductor chips; and external mounting members attached to the third connection pads of the substrate.
- According to another embodiment of the present invention, a stack package comprises a first semiconductor chip having a first surface on which first pads and second pads are disposed and a second surface which faces away from the first surface; a second semiconductor chip having a third surface which faces the first surface of the first semiconductor chip and on which third pads and fourth pads electrically connected with the second pads are disposed, and a fourth surface which faces away from the third surface; connection members electrically connecting the first pads with the third pads and the second pads with the fourth pads; a substrate having a fifth surface to which the fourth surface of the second semiconductor chip is attached and on which first connection pads and second connection pads are disposed, and a sixth surface which faces away from the fifth surface and on which third connection pads are disposed; capacitors having first electrodes which are electrically connected with the third pads, second electrodes which are connected with the first connection pads, and dielectrics interposed between the first electrodes and second electrodes; and connection members connecting the fourth pads of the second semiconductor chip with the second connection pads of the substrate.
- The stack package may further comprise first redistribution lines disposed on the third surface of the second semiconductor chip such that one ends thereof are electrically connected with the third pads and the other ends thereof extend to a first edge of the third surface, to be connected with the first electrodes of the capacitors; and second redistribution lines disposed on the third surface of the second semiconductor chip such that one ends thereof are electrically connected with the fourth pads and the other ends thereof extend to a second edge of the third surface which is opposite the first edge, to be connected with the second connection pads of the substrate.
- The stack package may further comprise an encapsulant sealing the fifth surface of the substrate including the first and second semiconductor chips and the capacitors; and external mounting members attached to the third connection members of the substrate.
- According to another embodiment of the present invention, a stack package comprises a first semiconductor chip having a first surface on which first pads and second pads are disposed and a second surface which faces away from the first surface; a second is semiconductor chip having a third surface which faces the first surface of the first semiconductor chip and on which third pads and fourth pads electrically connected with the second pads are disposed, and a fourth surface which faces away from the third surface; first redistribution lines disposed on the third surface of the second semiconductor chip, and having one ends which are connected with the first pads and the third pads and the other ends which extend to a first side surface meeting the third surface; second redistribution lines disposed on the third surface of the second semiconductor chip, and having one ends which are connected with the second pads and the fourth pads and the other ends which extend to a second side surface facing away from the first side surface; a substrate having a fifth surface to which the fourth surface of the second semiconductor chip is attached and on which first connection pads and second connection pads are disposed, and a sixth surface which faces away from the fifth surface and on which third connection pads are disposed; capacitors having first electrodes which are connected with the other ends of the first redistribution lines extending to the first side surface of the second semiconductor chip, second electrodes which are connected with the first connection pads, and dielectrics which are interposed between the first electrodes and the second electrodes; and connection members connecting the other ends of the second redistribution lines and the second connection pads of the substrate.
- The first and second redistribution lines may directly contact the first and third pads and the second and fourth pads, and may be electrically insulated from the first and second semiconductor chips.
-
FIGS. 1 and 2 are cross-sectional views showing a stack package in accordance with an embodiment of the present invention. -
FIGS. 3 through 7 are cross-sectional views showing a capacitor of the stack package in accordance with an embodiment of the present invention. -
FIG. 8 is a cross-sectional view showing a stack package in accordance with an embodiment of the present invention. -
FIG. 9 is a cross-sectional view showing a stack package in accordance with an embodiment of the present invention. -
FIG. 10 is a cross-sectional view showing a stack package in accordance with an embodiment of the present invention. - In the present invention, when realizing a stack package of a chip-on-chip structure, power pads and ground pads of an upper semiconductor chip and a lower semiconductor chip are connected by capacitors.
- Therefore, according to embodiments of the present invention, even though the capacitors are embedded, the capacitors can be relatively simply formed, costs can be saved, and reliability can be secured.
- Also, in the present invention, by freely adjusting the area of the electrodes of the capacitors, capacitors of a large capacity advantageous to the reduction of power noise can be easily realized.
- Further, in the present invention, because the capacitors are disposed between the upper semiconductor chip and the lower semiconductor chip, the volume of the entire stack package is not unnecessarily increased.
- Hereafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings.
- It is to be understood herein that the drawings are not necessarily to scale and in some instances proportions may have been exaggerated in order to more clearly depict certain features of the invention.
-
FIGS. 1 and 2 are cross-sectional views showing a stack package in accordance with an embodiment of the present invention. - Referring to
FIG. 1 , astack package 100 in accordance with an embodiment of the present invention includes afirst semiconductor chip 110, asecond semiconductor chip 120, andcapacitors 130 connected to thefirst semiconductor chip 110 and thesecond semiconductor chip 120. - The
first semiconductor chip 110 has a first surface S1 on whichfirst pads 112 andsecond pads 114 are disposed and a second surface S2 which faces away from the first surface S1. Thesecond semiconductor chip 120 has a third surface S3 on whichthird pads 122 andfourth pads 124 are disposed and a fourth surface S4 which faces away from the third surface S3. As shown inFIG. 1 , thefirst semiconductor chip 110 and thesecond semiconductor chip 120 are oppositely positioned. That is, for example, thefirst semiconductor chip 110 is positioned above thesecond semiconductor chip 120, and the first surface S1 of thefirst semiconductor 110 faces the third surface S3 of thesecond semiconductor chip 120. - For example, the
first pads 112 of thefirst semiconductor chip 110 are power pads, and thethird pads 122 of thesecond semiconductor chip 120, which correspond to thefirst pads 112 of thefirst semiconductor chip 110, are ground pads. Alternatively, thefirst pads 112 of thefirst semiconductor chip 110 may be ground pads, and thethird pads 122 of thesecond semiconductor chip 120, which correspond to thefirst pads 112 of thefirst semiconductor chip 110, may be power pads. Both thesecond pads 114 of thefirst semiconductor chip 110 and thefourth pads 124 of thesecond semiconductor chip 120 are signal pads. - It should be understood, that while not shown in a drawing, each of the
first semiconductor chip 110 and the second issemiconductor chip 120 has therein a circuit unit, which includes a data storage section for storing data and a data processing section for processing data. - The
third pads 122 of thesecond semiconductor chip 120 can be disposed at positions which face thefirst pads 112 of thefirst semiconductor chip 110 as shown inFIG. 1 . Of course, while not shown in a drawing, it is conceivable that thethird pads 122 of thesecond semiconductor chip 120 can be disposed at positions which do not face thefirst pads 112 of thefirst semiconductor chip 110. - The
second pads 114 of thefirst semiconductor chip 110 and the correspondingfourth pads 124 of thesecond semiconductor chip 120 are electrically connected with each other throughfirst connection members 142. Thefirst connection members 142 may comprise an electrically conductive material, for example, solders or bumps. - Each
capacitor 130 includes afirst electrode 132 electrically connected with thefirst pad 112 of thefirst semiconductor chip 110, asecond electrode 134 electrically connected with thethird pad 122 of thesecond semiconductor chip 120, and a dielectric 136 interposed between thefirst electrode 132 and thesecond electrode 134. - The
first electrode 132 is electrically connected with thefirst pad 112 of thefirst semiconductor chip 110 through a second isconnection member 144, and thesecond electrode 134 is electrically connected with thethird pad 122 of thesecond semiconductor chip 120 through athird connection member 146. The second andthird connection members - In the embodiment, a surface of the
capacitor 130 has an area that is less than an area of the surfaces S1, S3 of the first andsecond semiconductor chips - However, as shown in
FIG. 3 , a surface of thecapacitor 130 can have an area as great as the area of each of the surfaces S1, S3 first andsecond semiconductor chips FIG. 3 , thecapacitor 130 has an opening v through which a connection part between thesecond pad 114 of thefirst semiconductor chip 110 and thefourth pad 124 of thesecond semiconductor chip 120 passes. In detail, thefirst electrode 132, thesecond electrode 134 and the dielectric 136 of thecapacitor 130 are formed so as to have defined therein the opening v through which thefirst connection member 142 connecting thesecond pad 114 of thefirst semiconductor chip 110 and thefourth pad 124 of thesecond semiconductor chip 120 passes. - In the embodiment shown in
FIG. 3 , thefirst electrode 132 and thesecond electrode 134 of thecapacitor 130 are connected with thefirst pad 112 of thefirst semiconductor chip 110 and thethird pad 122 of thesecond semiconductor chip 120 through thesecond connection member 144 and thethird connection member 146, respectively. - As shown in
FIG. 4 , thefirst electrode 132 and thesecond electrode 134 of thecapacitor 130 can be formed so as to directly contact the first surface S1 of thefirst semiconductor chip 110 including thefirst pad 112 and the third surface S3 of thesecond semiconductor chip 120 including thethird pad 122, respectively. - As shown in
FIG. 4 , a surface of thecapacitor 130, which includes thefirst electrode 132 and thesecond electrode 134 formed to directly contact the first surface S1 of thefirst semiconductor chip 110 and the third surface S3 of thesecond semiconductor chip 120, can have an area that is less than the area of surfaces S1 and S3 of the first andsecond semiconductor chips FIG. 4 , or can have an area that is the same as the area of the surfaces S1 and S3 of the first andsecond semiconductor chips FIG. 5 , in order to secure an increased capacity. In the latter case as shown inFIG. 5 , thecapacitor 130 has an opening v through which thefirst connection member 142 connecting thesecond pad 114 of thefirst semiconductor chip 110 and thefourth pad 124 of thesecond semiconductor chip 120 passes. - In addition, in the embodiment, each of the
first electrode 132 and thesecond electrode 134 of thecapacitor 130 is formed to have a plate-like shape as shown inFIGS. 1 through 5 . - As shown in
FIG. 6 , in order to secure an increased capacity, thefirst electrode 132 can be formed to have afirst plate part 132 a and a plurality of first projectingparts 132 b formed on thefirst plate part 132 a so as to project toward thesecond electrode 134, and thesecond electrode 134 can be formed to have asecond plate part 134 a and a plurality of second projectingparts 134 b formed on thesecond plate part 134 a so as to be respectively placed between the first projectingparts 132 b. - A surface of the
capacitor 130, which includes thefirst electrode 132 having thefirst plate part 132 a and the first projectingparts 132 b and thesecond electrode 134 having thesecond plate part 134 a and the second projectingparts 134 b, can be formed to have an area that is less than the area of each of the surfaces S1 and S3 of the first andsecond semiconductor chips FIG. 6 , or can be formed to have an area that is the same as the area of each of the surfaces S1 and S3 of the first andsecond semiconductor chips FIG. 7 . In the latter case, thecapacitor 130 has an opening v through which thefirst connection member 142 connecting thesecond pad 114 of thefirst semiconductor chip 110 and thefourth pad 124 of thesecond semiconductor chip 120 passes. - In the case of the stack package structures shown in
FIGS. 6 and 7 , the space between thefirst semiconductor chip 110 and thesecond semiconductor chip 120 is filled with the dielectric 136 of thecapacitor 130, therefore it is not necessary to fill a separate underfill in the space between thefirst semiconductor chip 110 and thesecond semiconductor chip 120, and an underfill omission effect can be achieved. - In addition, while it is illustrated and described in the embodiment that the
third pads 122 of thesecond semiconductor chip 120 are disposed on the third surface S3 of thesecond semiconductor chip 120 in such a way as to respectively face thefirst pads 112 of thefirst semiconductor chip 110, it is conceivable that thethird pads 122 of thesecond semiconductor chip 120 can be disposed on the third surface S3 of thesecond semiconductor chip 120 at positions which do not face thefirst pads 112 of thefirst semiconductor chip 110. In this case, it can be understood that the shape of thecapacitors 130 is changed accordingly. - Referring to
FIG. 2 , thestack package 100 can includefirst redistribution lines 126 andsecond redistribution lines 128 which are formed on the third surface S3 of thesecond semiconductor chip 120. Eachfirst redistribution line 126 is disposed on the third surface S3 of thesecond semiconductor chip 120 such that one end thereof is electrically connected with thethird pad 122 and the second end thereof extends to an edge of the third surface S3. Eachsecond redistribution line 128 is disposed on the third surface S3 of thesecond semiconductor chip 120 such that one end thereof is electrically connected with thefourth pad 124 and the second end thereof extends to a second edge of the third surface S3 which is opposite the first edge. The first andsecond redistribution lines - The
stack package 100 as shown inFIG. 2 , can further includes asubstrate 160 having an upper surface on which thesecond semiconductor chip 120 is attached,connection members redistribution lines substrate 160, and anencapsulant 180 sealing the first andsecond semiconductor chips connection members members 190 which are attached to thesubstrate 160. - The
substrate 160 has a fifth surface S5 to which the fourth surface S4 of thesecond semiconductor chip 120 is attached and on whichfirst connection pads 162 andsecond connection pads 164 are disposed, and a sixth surface S6 which faces away from the fifth surface S5 and on whichthird connection pads 166 are disposed. For example, thesubstrate 160 may comprise a printed circuit board. - The
first connection pads 162 are disposed on portions of the fifth surface S5 of thesubstrate 160 which are adjacent to the second of thefirst redistribution lines 126, and are electrically connected with thefirst redistribution lines 126 through thefirst connection members 172. Thesecond connection pads 164 are disposed on portions of the fifth surface S5 of thesubstrate 160 which at the second ends of thesecond redistribution lines 128, and are electrically connected with thesecond redistribution lines 128 through thesecond connection members 174. - The
first connection members 172 and thesecond connection members 174 preferably comprise conductive wires, or may comprise a conductive ink or a pattern film. Theencapsulant 180 preferably comprises an epoxy molding compound (EMC), or may comprise other insulation materials. The external mountingmembers 190 preferably comprise solder balls, or may comprise conductive pins or a solder paste. - Since the stack package according to an embodiment has a structure in which the capacitors are connected to the power pads of the first semiconductor chip and the grounds pads of the second semiconductor chip, the capacitors are can be easily formed, and the reliability of the capacitors can be improved.
- Also, since the stack package has a structure in which the capacitors are disposed between the first semiconductor chip and the second semiconductor chip, the volume of the package is not unnecessarily increased, and a separate process for mounting capacitors is not needed.
- Further, the capacitors can have a large capacity since sectional shape of the capacitor electrodes can be optionally changed as described above, and accordingly, power noise reducing effect can be improved.
-
FIG. 8 is a cross-sectional view showing an exemplary stack package. The same reference numerals will be used to refer to the same component elements as those shown inFIG. 2 , and the detailed descriptions of the same component elements will be omitted herein. - Referring to
FIG. 8 , astack package 200 includes first and second through-electrodes second semiconductor chip 120. The first and second through-electrodes second semiconductor chip 120 and be connected withthird pads 122 andfourth pads 124, respectively. Preferably, the first and second through-electrodes second semiconductor chip 120. - The
stack package 200 as shown inFIG. 8 further includes asubstrate 160 andconnection members connection members substrate 160 may comprise a printed circuit board. Thesubstrate 160 has a fifth surface S5 to which the fourth surface S4 of thesecond semiconductor chip 120 is attached and on whichfirst connection pads 162 andsecond connection pads 164 are disposed, and a sixth surface S6 which faces away from the fifth surface S5 and on whichthird connection pads 166 are disposed. Thefirst connection pads 162 and thesecond connection pads 164 are respectively connected with the first through-electrodes 152 and the second through-electrodes 154, as will be described below in detail. - The
stack package 200 as shown inFIG. 8 further includes anencapsulant 180 sealing the fifth surface S5 of thesubstrate 160 and the first andsecond semiconductor chip members 190, which are attached to thethird connection pads 166 of thesubstrate 160. The external mountingmembers 190 preferably comprise solder balls, or may comprise conductive pins or a solder paste. - The
stack package 200 as shown inFIG. 8 further includescapacitors 130 constructed so as to be connected with the first andsecond semiconductor chips capacitor 130 includes afirst electrode 132 electrically connected with eachfirst pad 112 of thefirst semiconductor chip 110 through asecond connection member 144, asecond electrode 134 electrically connected with eachthird pad 122 of thesecond semiconductor chip 120 through athird connection member 146, and a dielectric 136 interposed between thefirst electrode 132 and thesecond electrode 134. - While it is shown
FIG. 8 in that a surface of thecapacitor 130 has an area that is less than the area of each of the surfaces S1 and S3 of the first andsecond semiconductor chips capacitor 130 can have an area that is the same as the area of each of the surfaces S1 and S3 of the first andsecond semiconductor chips FIG. 3 , so as to secure a large capacity. In this case, thecapacitor 130 has an opening v through which thefirst connection member 142 connecting thesecond pad 114 of thefirst semiconductor chip 110 and thefourth pad 124 of thesecond semiconductor chip 120 passes. - Also, while it is shown in
FIG. 8 that the first andsecond electrodes capacitor 130 are formed to be respectively connected with thefirst pad 112 of thefirst semiconductor chip 110 and thethird pad 122 of thesecond semiconductor chip 120 through the second andthird connection members first electrode 132 and thesecond electrode 134 of thecapacitor 130 can be formed in such a way as to directly contact the first surface S1 of thefirst semiconductor chip 110 including thefirst pad 112 and the third surface S3 of thesecond semiconductor chip 120 including thethird pad 122, respectively, as shown inFIGS. 4 and 5 . - Moreover, while it is shown in
FIG. 8 that each of the first andsecond electrodes capacitor 130 has a plate-like shape, it is conceivable that thefirst electrode 132 can be formed to have a first plate part and first projecting parts and thesecond electrode 134 can be formed to have a second plate part and second projecting parts as shown inFIGS. 6 and 7 , in order to secure a large capacity. - Here, the
capacitor 130, which includes thefirst electrode 132 having the first plate part and the first projecting parts, thesecond electrode 134 having the second plate part and the second projecting parts, and the dielectric 136 interposed between thefirst electrode 132 and thesecond electrode 134, can be formed such that an area of a surface of thecapacitor 130 is less than that of each of the surfaces S1 and S3 of the first andsecond semiconductor chips FIG. 6 , or can be formed such that an area of a surface of thecapacitor 130 is the same as that of each of the first andsecond semiconductor chips FIG. 7 . -
FIG. 9 is a cross-sectional view showing an exemplary stack package. The same reference numerals will be used to refer to the same component elements as those shown inFIG. 2 , and the detailed descriptions of the same component elements will be omitted herein. - Referring to
FIG. 9 , astack package 300 includescapacitors 130 which are formed between asecond semiconductor chip 120 and asubstrate 160. In detail, eachcapacitor 130 includes afirst electrode 132 which is connected to athird pad 122 of asecond semiconductor chip 120, asecond electrode 134 which is connected to afirst connection pad 162 of asubstrate 160, and a dielectric 136 which is interposed between thefirst electrode 132 and thesecond electrode 134. - The
first electrode 132 is connected with the second of afirst redistribution line 126 formed on a third surface S3 of thesecond semiconductor chip 120, where one end of thefirst redistribution line 126 is connected with thethird pad 122 and the second end extending to the first edge of the third surface S3. Therefore, it can be understood that thefirst electrode 132 is electrically connected with thethird pad 122 of thesecond semiconductor chip 120 through thefirst redistribution line 126. - The dielectric 136 of the
capacitor 130 is not limited to the shape as shown inFIG. 8 and can be formed to have various shapes according to different manufacturing processes. - In the
stack package 300, asecond pad 114 disposed on a first surface S1 of afirst semiconductor chip 110 and afourth pad 124 disposed on the third surface S3 of thesecond semiconductor chip 120 are electrically connected with each other through afirst connection member 142, and afirst pad 112 disposed on the first surface S1 of thefirst semiconductor chip 110 and thethird pad 122 disposed on the third surface S3 of thesecond semiconductor chip 120 are electrically connected with each other through afourth connection member 148. The first andfourth connection members - In the
stack package 300, asecond redistribution line 128 is formed on the third surface S3 of thesecond semiconductor chip 120 such that one end thereof is electrically connected with thefourth pad 124 and a second end extends to the second edge of the third surface S3 which is opposite the first edge. The second of thesecond redistribution line 128 is connected with asecond connection pad 164 which is disposed on a fifth surface S5 of thesubstrate 160, through aconnection member 176. - Further, in the
stack package 300, the fifth surface S5 of thesubstrate 160, the first andsecond semiconductor chips capacitors 130 are sealed by anencapsulant 180 such as an EMC. External mountingmembers 190 such as solder balls are attached tothird connection pads 166 disposed on a sixth surface S6 of thesubstrate 160 facing away from the fifth surface S5. -
FIG. 10 is a cross-sectional view illustrating an exemplary stack package. The same reference numerals will be used to refer to the same component elements as those shown inFIG. 2 , and the detailed descriptions of the same component elements will be omitted herein. - Referring to
FIG. 10 , astack package 400 includes first andsecond semiconductor chips substrate 160 to which a fourth surface S4 of thesecond semiconductor chip 120 is attached, andcapacitors 130 which are formed between thesecond semiconductor chip 120 and thesubstrate 160. - The
stack package 400 further includesfirst redistribution lines 126 andsecond redistribution lines 128 which are interposed between thefirst semiconductor chip 110 and thesecond semiconductor chip 120. - Each
first redistribution line 126 is formed on a third surface S3 of thesecond semiconductor chip 120 such that a first end thereof is connected with afirst pad 112 of thefirst semiconductor chip 110 and athird pad 122 of thesecond semiconductor chip 120 and a second end thereof extends to a first side surface adjoining the third surface S3. Eachsecond redistribution line 128 is formed on the third surface S3 of thesecond semiconductor chip 120 such that a first end thereof is connected with asecond pad 114 of thefirst semiconductor chip 110 and afourth pad 124 of thesecond semiconductor chip 120 and a second end thereof extends to a second side surface adjoining the third surface S3 and facing away from the first side surface. The first andsecond redistribution lines first semiconductor chip 110, includingfirst pads 112, and the third surface S3 of thesecond semiconductor chip 120, includingthird pads 122, and the first surface S1 of thefirst semiconductor chip 110, includingsecond pads 114, and the third surface S3 of thesecond semiconductor chip 120, includingfourth pads 124, respectively. The first andsecond redistribution lines second semiconductor chips - The
substrate 160 has a fifth surface S5 to which the fourth surface S4 of thesecond semiconductor chip 120 is attached and on which first andsecond connection pads third connection pads 166 are disposed. Thefirst connection pads 162 are disposed on portions of the fifth surface S5 of thesubstrate 160 adjacent to the first side surface of thesecond semiconductor chip 120, and thesecond connection pads 164 are disposed on portions of the fifth surface S5 of thesubstrate 160 adjacent to the second side surface of thesecond semiconductor chip 120. - Each
capacitor 130 includes afirst electrode 132 connected with thethird pad 122 of thesecond semiconductor chip 120, asecond electrode 134 connected with thefirst connection pad 162 of thesubstrate 160, and a dielectric 136 interposed between thefirst electrode 132 and thesecond electrode 134. In detail, thefirst electrode 132 is formed to be connected with the second end of thefirst redistribution line 126 which has the first end thereof connected with thethird pad 122 of thesecond semiconductor chip 120 and the second end thereof disposed on the first side surface of thesecond semiconductor chip 120. Therefore, it can be understood that thefirst electrode 132 is electrically connected with thethird pad 122 of thesecond semiconductor chip 120 through thefirst redistribution line 126. - The dielectric 136 of the
capacitor 130 can be formed to have various shapes in addition to the shape shown in the drawing. - The
stack package 400 further includesconnection members 178 connecting the second ends of thesecond redistribution lines 128 disposed on the second side surface withsecond connection pads 164 of thesubstrate 160, external mountingmembers 190 attached tothird connection pads 166 disposed on the sixth surface S6 of thesubstrate 160, and anencapsulant 180 sealing the fifth surface S5 of thesubstrate 160, the first andsecond semiconductor chips capacitors 130. Theconnection members 178 can comprise a conductive material such as solders, and theencapsulant 180 can comprise, for example, an EMC. The external mountingmembers 190 preferably comprise solder balls, or can comprise conductive pins or a solder paste. - In the
stack package 400, in the case where thefirst connection pads 162 of thesubstrate 160, to which the second iselectrodes 134 of thecapacitors 130 are connected, comprise power pads, the first andthird pads second semiconductor chips first electrodes 132 of thecapacitors 130 through thefirst redistribution lines 126, comprise power pads. Alternatively, in the case where thefirst connection pads 162 of thesubstrate 160, to which thesecond electrodes 134 of thecapacitors 130 are connected, comprise ground pads, the first andthird pads second semiconductor chips first electrodes 132 of thecapacitors 130 through thefirst redistribution lines 126, comprise ground pads. - As is apparent from the above description, the stack package according to the present invention provides advantages in that, since the stack package has a structure in which decoupling capacitors are disposed between power pads and ground pads at a package level, power noise can be effectively reduced through the reduction of an inductance component, and accordingly, a desired data processing speed can be maintained.
- Although specific embodiments of the present invention to have been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and the spirit of the invention as disclosed in the accompanying claims.
Claims (20)
1. A stack package comprising:
a first semiconductor chip including a first surface having first pads and second pads disposed thereon, and a second surface facing away from the first surface;
a second semiconductor chip including a third surface having third pads and fourth pads disposed thereon, and a fourth surface facing away from the third surface, wherein the third surface of the second semiconductor chip faces the first surface of the first semiconductor chip and the fourth pads are electrically connected with the second pads; and
capacitors interposed between the first semiconductor chip and the second semiconductor chip, and having first electrodes electrically connected with the first pads of the first semiconductor chip, second electrodes electrically connected with the third pads of the second semiconductor chip, and dielectrics interposed between the first electrodes and the second electrodes.
2. The stack package according to claim 1 , further comprising:
first connection members electrically connecting the second pads of the first semiconductor chip and the fourth pads of the second semiconductor chip.
3. The stack package according to claim 1 , wherein the first pads comprise power pads and the third pads comprise ground pads, or the first pads comprise ground pads and the third pads comprise power pads.
4. The stack package according to claim 1 , wherein the first electrodes of the capacitors are electrically connected with the first pads of the first semiconductor chip through second connection members, and the second electrodes of the capacitors are electrically connected with the third pads of the second semiconductor chip through third connection members.
5. The stack package according to claim 1 , wherein the first electrodes and the second electrodes of the capacitors directly contact the first surface of the first semiconductor chip having the first pads disposed thereon and the third surface of the second semiconductor chip having the third pads disposed thereon, respectively.
6. The stack package according to claim 1 , wherein the first electrodes and the second electrodes of the capacitors have a shape of a plate.
7. The stack package according to claim 1 , wherein the first electrode of each capacitor includes a first plate part having a plurality of first projecting parts formed thereon extending toward the second electrode, and the second electrode of each capacitor includes a second plate part having a plurality of second projecting parts formed thereon so as to extend toward the first electrode between the first projecting parts.
8. The stack package according to claim 1 , wherein an area of a surface of each capacitor is less than an area of each of the first surface of the first semiconductor chip and an area of the third surface of the second semiconductor chip.
9. The stack package according to claim 8 , wherein the dielectrics of the capacitors are disposed only between the first electrodes and the second electrodes.
10. The stack package according to claim 8 , wherein the dielectrics of the capacitors are disposed in a space between the first semiconductor chip and the second semiconductor chip, including spaces between the first electrodes and the second electrodes.
11. The stack package according to claim 1 , wherein an area of a surface of each of the capacitors is the substantially equal to an area of each of the first surface of the first semiconductor chip and an area of the third surface of the second semiconductor chips, and an opening is defined in each of the capacitors through which a connection part connecting the second pad of the first semiconductor chip and the fourth pad of the second semiconductor chip passes.
12. The stack package according to claim 1 , further comprising:
first redistribution lines disposed on the third surface of the second semiconductor chip including first ends electrically connected with the third pads and second ends extending to an edge of the third surface; and
second redistribution lines disposed on the third surface of the second semiconductor chip including first ends electrically connected with the fourth pads and the second ends extending to a second edge of the third surface opposite the first edge.
13. The stack package according to claim 12 , further comprising:
a substrate having a fifth surface attached to the fourth surface of the second semiconductor chip and having disposed thereon first connection pads connected with the first redistribution lines and second connection pads connected with the second redistribution lines, and a sixth surface facing away from the fifth surface and having third connection pads disposed thereon;
connection members connecting the second ends of the first redistribution lines with the first connection pads and the second ends of the second redistribution lines with the second connection pads;
an encapsulant sealing the fifth surface of the substrate, the first and second semiconductor chips, and the connection members; and
external mounting members attached to the third connection members of the substrate.
14. The stack package according to claim 1 , further comprising:
through-electrodes formed in the second semiconductor chip passing through the third and fourth surfaces of the second semiconductor chip, and connected with the third pads and the fourth pads.
15. The stack package according to claim 14 , further comprising:
a substrate having a fifth surface attached to the fourth surface of the second semiconductor chip and having disposed thereon first connection pads and second connection pads connected with the through-electrodes, and a sixth surface facing away from the fifth surface having third connection pads disposed thereon;
an encapsulant sealing the fifth surface of the substrate and the first and second semiconductor chips; and
external mounting members attached to the third connection pads of the substrate.
16. A stack package comprising:
a first semiconductor chip including a first surface having first pads and second pads disposed thereon, and a second surface facing away from the first surface;
a second semiconductor chip including a third surface having third pads and fourth pads disposed thereon, and a fourth surface which facing away from the third surface, wherein the third surface of the second semiconductor chip faces the first surface of the first semiconductor chip and the fourth pads are electrically connected with the second pads;
connection members electrically connecting the first pads with the third pads and the second pads with the fourth pads;
a substrate including a fifth surface attached to the fourth surface of the second semiconductor chip and having disposed thereon first connection pads and second connection pads, and a sixth surface facing away from the fifth surface and having third connection pads disposed thereon;
capacitors including first electrodes electrically connected with the third pads, second electrodes electrically connected with the first connection pads, and dielectrics interposed between the first electrodes and second electrodes; and
connection members connecting the fourth pads of the second semiconductor chip with the second connection pads of the substrate.
17. The stack package according to claim 16 , further comprising:
first redistribution lines disposed on the third surface of the second semiconductor chip having first ends electrically connected with the third pads and second ends extending to a first edge of the third surface electrically connected with the first electrodes of the capacitors; and
second redistribution lines disposed on the third surface of the second semiconductor chip having first ends electrically connected with the fourth pads and second ends extending to a second edge of the third surface opposite the first edge, the second ends electrically connected with the second connection pads of the substrate.
18. The stack package according to claim 16 , further comprising:
an encapsulant sealing the fifth surface of the substrate, the first and second semiconductor chips, and the capacitors; and
external mounting members attached to the third connection members of the substrate.
19. A stack package comprising:
a first semiconductor chip including a first surface having first pads and second pads disposed thereon, and a second surface facing away from the first surface;
a second semiconductor chip including a third surface having third pads and fourth pads disposed thereon, and a fourth surface which facing away from the third surface, wherein the third surface of the second semiconductor chip faces the first surface of the first semiconductor chip and the fourth pads are electrically connected with the second pads;
first redistribution lines disposed on the third surface of the second semiconductor chip having first ends connected with the first pads and the third pads, and second ends extending to a first side surface adjoining the third surface;
second redistribution lines disposed on the third surface of the second semiconductor chip having first ends connected with the second pads and the fourth pads, and second ends extending to a second side surface adjoining the third surface, the second side surface facing away from the first side surface;
a substrate including a fifth surface attached to the fourth surface of the second semiconductor chip having first connection pads and second connection pads disposed thereon, and a sixth surface facing away from the fifth surface having third connection pads disposed thereon;
capacitors including first electrodes connected with the second ends of the first redistribution lines extending to the first side surface of the second semiconductor chip, second electrodes connected with the first connection pads, and dielectrics interposed between the first electrodes and the second electrodes; and
connection members connecting the second ends of the second redistribution lines and the second connection pads of the substrate.
20. The stack package according to claim 19 , wherein the first redistribution lines directly contact the first pads and third pads and the second redistribution lines directly contact the second pads and fourth pads, and the first and second redistribution lines are electrically insulated from the first and second semiconductor chips.
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US13/687,024 US20130087887A1 (en) | 2010-02-03 | 2012-11-28 | Stack package |
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KR1020100010105A KR101046394B1 (en) | 2010-02-03 | 2010-02-03 | Stack package |
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US13/687,056 Expired - Fee Related US8680652B2 (en) | 2010-02-03 | 2012-11-28 | Stack package |
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US13/687,056 Expired - Fee Related US8680652B2 (en) | 2010-02-03 | 2012-11-28 | Stack package |
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US20110114377A1 (en) * | 2008-06-03 | 2011-05-19 | Jean Brun | Stacked electronic device and method of making such an electronic device |
US20110180913A1 (en) * | 2010-01-27 | 2011-07-28 | Shiann-Ming Liou | Method of stacking flip-chip on wire-bonded chip |
US20120205798A1 (en) * | 2011-02-15 | 2012-08-16 | Hynix Semiconductor Inc. | Semiconductor package and method for manufacturing the same |
US20140183611A1 (en) * | 2012-12-28 | 2014-07-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method to integrate different function devices fabricated by different process technologies |
US8907451B2 (en) * | 2012-12-21 | 2014-12-09 | SK Hynix Inc. | Semiconductor chip and semiconductor apparatus with embedded capacitor |
US20150204926A1 (en) * | 2014-01-22 | 2015-07-23 | Kabushiki Kaisha Toshiba | Semiconductor device and system |
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Also Published As
Publication number | Publication date |
---|---|
KR101046394B1 (en) | 2011-07-05 |
US20130087887A1 (en) | 2013-04-11 |
US8680652B2 (en) | 2014-03-25 |
US20130082352A1 (en) | 2013-04-04 |
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