US20120140564A1 - Non-volatile one-time-programmable and multiple-time programmable memory configuration circuit - Google Patents
Non-volatile one-time-programmable and multiple-time programmable memory configuration circuit Download PDFInfo
- Publication number
- US20120140564A1 US20120140564A1 US13/362,687 US201213362687A US2012140564A1 US 20120140564 A1 US20120140564 A1 US 20120140564A1 US 201213362687 A US201213362687 A US 201213362687A US 2012140564 A1 US2012140564 A1 US 2012140564A1
- Authority
- US
- United States
- Prior art keywords
- otp
- volatile
- pull
- floating gate
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015654 memory Effects 0.000 title claims description 19
- 230000008878 coupling Effects 0.000 claims abstract description 30
- 238000010168 coupling process Methods 0.000 claims abstract description 30
- 238000005859 coupling reaction Methods 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims description 7
- 239000007943 implant Substances 0.000 claims description 6
- 230000006870 function Effects 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 102000004129 N-Type Calcium Channels Human genes 0.000 claims 15
- 108090000699 N-Type Calcium Channels Proteins 0.000 claims 15
- 108091006146 Channels Proteins 0.000 claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 238000003491 array Methods 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 13
- 238000002347 injection Methods 0.000 description 10
- 239000007924 injection Substances 0.000 description 10
- 230000008569 process Effects 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 7
- 230000008901 benefit Effects 0.000 description 6
- 239000002784 hot electron Substances 0.000 description 5
- 230000005641 tunneling Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000007246 mechanism Effects 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005265 energy consumption Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000036039 immunity Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003472 neutralizing effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0002—Multistate logic
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
- H01L29/7885—Hot carrier injection from the channel
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/02—Structural aspects of erasable programmable read-only memories
- G11C2216/10—Floating gate memory cells with a single polysilicon layer
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
- G11C2216/26—Floating gate memory which is adapted to be one-time programmable [OTP], e.g. containing multiple OTP blocks permitting limited update ability
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
Definitions
- the present invention relates to non-volatile configuration circuits which can be programmed one time, or multiple times in some instances.
- the invention has particular applicability to applications where is it desirable to customize electronic circuits, including programmable logic devices, field programmable gate arrays, etc.
- FPGAs Field Programmable Gate Arrays
- FPGAs are well-known circuits used in a variety of electronic devices/computing systems. FPGAs offer the ability to update their functionality in the field, which is a substantial advantage over fixed ASIC type devices. FPGAs contain reconfigurable interconnects that allow predefined logic blocks to be wired together.
- an SRAM is used to configure the functions of the logic blocks and the routing of the interconnections.
- Recent implementations use a form of non-volatile memory to perform this function. These devices, however, are not optimal, however, as they require additional processing step to embed them within a logic circuit.
- OTP time programmable
- MTP multi-time programmable
- OTP one time programmable
- MTP multiple time programmable
- a unique aspect of the device is that the floating gate of the memory cell structure is electrically coupled strongly through one of the S/ 0 junctions of the transistor, whereas traditional single poly nonvolatile memory cells require either an additional interconnect layer to couple to the floating gate, or the floating gate has coupling to any of the existing electrical signals.
- Another key feature is that it is implemented with an NMOS device structure, whereas the traditional single-poly OTP is commonly implemented with a PMOS device structure. This means that the device can be formed at the same time as other n-channel devices on a wafer.
- an NMOS device structure behaves similar to an EPROM device, i.e., the device is programmed into a non-conducting state from a conducting state.
- the most commonly used PMOS OTP device is programmed from a non-conducting state into a conducting state). This can eliminate the need of an additional masking step that is commonly associated with a PMOS OTP device in order to make sure that PMOS device is in a non-conducting state coming out of the manufacturing fab.
- an NMOS device's programming mechanism with channel hot electrons injection is self-limiting, unlike that case of a PMOS with channel hot electron programming, the amount of energy consumption during programming is self-limited for this invention.
- NMOS OTP implementation is disclosed by U.S. Pat. No. 6,920,067, incorporated by reference herein.
- the device in this reference is programmed with channel hot-hole-injection.
- the disclosure teaches that the device is programmed into conducting state, after the channel hot hole injection.
- NMOS device will conduct a channel current to initiate the hot hole injection only when the floating gate potential is sufficient to turn on the device, or when the threshold voltage is always low initially to allow channel current conduction.
- the only way to ensure either scenario is to introduce an additional process step to modify the turn on characteristics of the NMOS. Now assuming the channel is conducting initially and hot holes are injected, the holes injected on the floating gate will make the device more conductive. So the device basically goes from a conductive state (in order to initiate channel current for hot hole injection) to a highly conductive state.
- An object of the present invention is to overcome the aforementioned limitations of the prior art.
- FIG. 1 is a top down view of a preferred embodiment of a non-volatile memory cell of the present invention
- FIG. 2 is a side cross section view of the preferred non-volatile memory cell
- FIG. 3 is an electrical diagram illustrating the electrical relationship of the structures of the preferred non-volatile memory cell
- FIG. 4 depicts a prior art non-volatile memory cell which uses a floating gate for an OTP application
- FIG. 5 is an electrical diagram showing a preferred embodiment of a latch circuit and/or configuration circuit constructed with the NV memory cells of the present invention.
- FIG. 6A is a top down view of the preferred non-volatile configuration circuit of the present invention.
- FIG. 68 is a flow diagram showing preferred operations used to manufacture the non-volatile configuration circuit of the present invention.
- the present disclosure concerns a new type of non-volatile configuration circuit (preferably single poly) that can be operated either as an OTP (one time programmable) or as preferred device structure is fully compatible with advanced CMOS logic process, and would require, at the worst case, very minimal additional steps to implement.
- OTP one time programmable
- a unique aspect of the present device is that the floating gate of the memory cell structure is electrically coupled strongly through a variable number of S/D junctions of the transistor, whereas traditional single poly nonvolatile memory cells require either an additional interconnect layer to couple to the floating gate, or the floating gate has virtually none or minimal electrical coupling to any of the existing electrical signals.
- the coupling ratio can be more specific and precise. That is, by exactly controlling the coupling ratio (through areal means) the amount of charge, and thus the final programmed Vt, are directly proportional to the product of the coupling ratio and the drain voltage. It can be more precisely controlled such that the coupling ratio is dictated or designed by the desired programming threshold level (Vt) of the memory cell. This allows for a design that evolves easily into a multi-level version of an OTP since different coupling ratios yield different programmed Vt.
- FIG. 1 illustrates the top view of the layout of a preferred structure used in the present invention.
- FIG. 2 illustrates a representative cross-sectional view of the device structure. It will be understood that these drawings are not intended to be set out to scale, and some aspects of the device have been omitted for clarity.
- the device includes a typical NMOS transistor 100 which is modified so that the gate (poly in a preferred embodiment) 110 of the device is not electrically connected to a voltage source.
- a drain 120 of the device is bent around and is preferably joined by an N-type well 130 that typically already exists in a conventional advanced CMOS process.
- the N-Well 130 can be replaced with an n-type diffusion layer introduced so as to be beneath the poly floating gate.
- a conventional source region 125 is also utilized.
- the floating gate poly 110 is extended beyond a typical transistor channel region 135 and includes an overlap region 140 which overlaps an active region extending from the drain junction.
- the active region portion 141 that is surrounded by the N-Well region serves as an effective capacitive coupling to the floating gate. Thus any voltage applied to the drain junction will be effectively coupled onto the floating gate.
- the floating gate can effectively acquire and have a high percentage of the value of the drain voltage.
- a key advantage of the preferred embodiment is that it is formed from same layers conventionally used to make active n-channel devices in a CMOS process.
- the poly (or metal as the case may be) gate layer is not interconnected with such other formed active devices or coupled to a gate signal.
- the other implants for the source/drain are also part of a CMOS conventional process.
- the invention can be integrated without any additional processing costs, because the only alteration is to an existing mask for each relevant layer of the wafer being processed.
- this device structure is to make the drain-to-gate coupling capacitor area on the sidewall of a trench. This will greatly reduce the area of the drain-to-gate coupling capacitor. This reduction in cell area may come at the expense of significantly increase the manufacturing process complexity. However, again, in applications where the invention is integrated with certain types of DRAM architectures (especially embedded types), it is possible to incorporate the conventional processing steps for such memories to avoid additional processing costs. Other techniques for coupling a voltage to the floating gate and achieving a desired coupling ratio will be apparent to those skilled in the art.
- floating gate is shown as a single polysilicon layer, it will be appreciated by skilled artisans that other materials could be used as well. In some applications for example it may be possible to exploit the formation of other structures/devices which while part of other main underlying logic/memory structures, can be exploited for purposes of making a floating gate of some kind
- floating gates can typically be formed of a number of different materials, including through techniques in which impurities are implanted/diffused into a dielectric/insulating layer.
- the preferred embodiment depicts the NVM cell as part of a conventional lateral-planar FET structure on a substrate
- other geometries/architectures can be used, including non-planar structures.
- the invention could be used in SOl substrates, in thin film structures, at other levels of the device than the substrate, in multi-gate (FINFET type) orientations, and in vertical/non-planar configurations. In such latter instances the floating gate would be embedded and oriented vertically with respect to the substrate.
- the non-volatile device structure preferably has the physical features of a conventional 1 / 0 transistor implemented in an advanced CMOS logic process. At present, such 1 / 0 transistor is nominally operated at 3.3V but it will be understood that this value will change with successive generations of manufacturing.
- This type of 1 / 0 transistor typically has a threshold voltage of 0.5V to 0.7V, with a typical electrical gate oxide thickness of 70A.
- a drain coupling to floating gate ratio of 0.90 and a read drain voltage of 1.0V applied to the device, the floating gate will effectively be coupled with a voltage of about 0.90V. This is sufficient to turn on the un-programmed NMOS device 100 , and a channel current can be detected by typical means of sense circuitry to identify the state of the device.
- the particular coupling ratio, read voltage, etc. will vary from application to application and can be configured based on desired device operating characteristics.
- the device is originally in an unprogrammed state, which in the preferred embodiment is characterized by a low resistance coupling between the source and drain through channel region 135 .
- the preferred embodiment is shown in the form of a symmetric cell/channel, it will be understood that the invention could be used in non-symmetric forms such as shown in the aforementioned 20080186722 publication.
- the device To program the device into a programmed state, the device must be shut off by reducing carriers in the channel region, and increasing the threshold voltage. To do this a drain voltage of 6.0V can be applied and this will effectively couple a voltage of about 5.4V to the floating gate. This bias condition will placed the device into a channel hot electron injection regime. The electrons injected into the floating gate effectively increase the threshold voltage of the device. When a subsequent read voltage of 1.0V is applied again on the drain, the device does not conduct current due to its high threshold voltage, and this second state of the device is thus determined. As with the read characteristics, it will be understood to those skilled in the art that the particular coupling ratio, program voltage, etc., will vary from application to application and can be configured based on desired device operating characteristics.
- the prior art referred to above is primarily a one time programmable device, since there is no disclosed mechanism for removing the charge on the floating gate.
- some embodiments of the present invention can be made to be capable of multiple-time-programming.
- an erase operation can be introduced to remove or neutralize the electrons that have been injected into the floating gate.
- the mechanism for removing or neutralizing electrons is preferably through band-band tunneling hot hole injection from the other non-coupling junction 125 of the device.
- the preferred bias condition would be as followed: the non-coupling junction (source junction) is biased with 6V to cause the junction to initiate band-band tunneling current.
- the band-band tunneling current causes hot holes to be injected into the floating gate and neutralize the electrons that are stored on the floating gate.
- it is (re)programmed from a non-conducting, or even a low conducting state, into a conducting state.
- the device is then able to conduct channel current when a subsequent read voltage is applied to the coupling junction during the read operation. It will be understood that programming from a low conducting state to a conducting state may have a limited operating sense window.
- the coupling junction can be supplied with a negative voltage so that the floating gate is made more negative to cause higher band-band tunneling current across the source junction.
- additional protection can be implemented to ensure the OTP and MTP device have sufficient immunity against the loss of charge stored on the floating gate.
- the device can be configured into a paired latch 500—as shown in FIG. 5 —where the data and its complement are stored into the latch, thus effectively doubling the margin in the stored data.
- a top device 510 couples a node 530 to a first voltage reference (Vee) while a second bottom device 520 couples the node to a second voltage reference (Vss).
- Vee first voltage reference
- Vss second voltage reference
- the top device 510 is programmed into a non-conductive state, thus ensuring that node 530 is pulled down by bottom device 520 to Vss, representing a first logical data value (0).
- the bottom device 520 is programmed into a non-conductive state, thus ensuring that node 530 is pulled up by top device 510 to Vee, representing a second logical data value (1).
- Another useful advantage of the present preferred embodiment is that it is implemented with an NMOS device structure, whereas most traditional single-poly OTPs are commonly implemented with a PMOS device structure. This means that the device can be formed at the same time as other n-channel devices on a wafer.
- Another advantage of an NMOS device structure in this invention is that it behaves similar to an EPROM device, i.e., the device is programmed into a non-conducting state from a conducting state.
- This aspect of the invention thus can eliminate the need of an additional masking step that is commonly associated with a PMOS OTP device in order to make sure that PMOS device is in a non-conducting state coming out of the manufacturing fab.
- an NMOS device's programming mechanism with channel hot electrons injection is self-limiting, unlike that case of a PMOS with channel hot electron programming, the amount of energy consumption during programming is self-limited for this invention.
- the particular configuration of the floating gate is not critical. All that is required is that it be structurally and electrically configured to control channel conduction and also be capacitively coupled to an electrical source of charge carriers.
- the particular geometry can be varied in accordance with any desired layout or mask. In some instances it may be desirable to implement the floating gate as a multi-level structure for example.
- capacitive coupling is a function of the materials used, the invention allows for significant flexibility as the composition of the floating gate can also be varied as desired to accommodate and be integrated into a particular process.
- An array of cells constructed in accordance with the present teachings could include different shapes and sizes of floating gates so that cells having threshold cells could be created.
- two of the OTP/MTP cells can be arranged in a manner such it can serve as a configuration storage circuit 500 in a programmable logic device or FPGA application.
- an output 530 of the cell/circuit 500 has to be either Vee (logical high) or Vss (logical low), in order to drive a subsequent CMOS gate (not shown) inside an FPGA's logic block
- a single OTP/MTP cell preferably outputs either a fixed amount of read current or very little read current, depending on the programming state of the cell.
- two of such cells would have to be connected together in an inverter fashion to output either Vee or Vss.
- FIG. 5 illustrates the circuit connection in order to implement an FPGA configuration bit. It is basically two cells with a first device 510 serving as a pull-up transistor and the other one 520 serving as a pull-down transistor in an “inverter” or “voltage divider” configuration.
- the top and bottom OTP/MTP cells can be programmed or erased by program logic circuit (not shown) into exactly the opposite state of each other, to render output 530 into a particular desired logical value/state—i.e., as either Vee or Vss.
- the top OTP/MTP cell 510 is set to be conducting while the bottom OTP/MTP cell 520 is programmed into a non-conducting state. This way, the output node 530 tracks Vee—minus a threshould voltage which can be set to near zero via a channel implant adjustment as discussed below.
- the top OTP/MTP cell 510 is programmed into a non-conducting state while the bottom OTP cell 520 is programmed to a conducting state to discharge the output node 530 to Vss or ground.
- two OTP/MTP devices can be used as a configuration bit in an FPGA logic block, or any other programmable device.
- FIG. 6A shows a layout for the configuration circuit 500 .
- a pair of floating gates 610 , 610 ′ are coupled to a first drain region 620 and second drain region 620 ′ respectively.
- the drains 620 , 620 ′ are similarly bent around and are preferably joined by an N-type well 630 that typically already exists in a conventional advanced CMOS process.
- the N-Well 630 can be replaced with an n-type diffusion layer introduced so as to be beneath the poly floating gates.
- a conventional source region 625 is also utilized.
- the floating gate poly 610 / 610 ′ is extended beyond typical transistor channel regions 635 / 635 ′ and includes overlap regions 640 / 640 ′ which overlap active regions extending from the drain junctions.
- the active region portions 641 / 641 ′ that are surrounded by the N-Well region serve as an effective capacitive coupling to the pair of floating gates. Thus any voltage applied to the drain junctions will be effectively coupled onto the respective floating gates.
- Output 650 drives a configuration value (1 or 0) to a subsequent CMOS gate (not shown).
- a configuration circuit can be constructed of two OTP/MTP cells.
- the output 650 of the configuration circuit 600 can be altered as desired to reflect a new configuration value. So a second logical value can be set in the circuit 600 for in-system re-programmability.
- FIG. 68 A flowchart of a fabrication process used to make an integrated logic/NVM configuration circuit is shown in FIG. 68 .
- the configuration circuit 600 is manufactured using only the nominal processing steps otherwise required to make other logic circuits within a programmable logic device. The only differences are expressly shown to be as follows: a) any OTP/MTP devices are masked and not given an implant for adjusting an 1 / 0 device threshold voltage; b) if desired, an optional mask/implant can be introduced to compensate for the threshold voltage loss noted above. In other words, if the configuration circuit output 650 must equal Vee (i.e, no threshold drop), then this process step can compensate for such drop and afford a full swing output.
- Vee i.e, no threshold drop
Abstract
Description
- The present application is a continuation of U.S. Pat. No. 12/650,238, filed on Dec. 30, 2009, which claims the benefit of the filing date of U.S. Provisional Application No. 61/141,618, filed on Dec. 30, 2008, the disclosures of which is hereby incorporated herein by reference. The application is further related to U.S. application Ser. Nos. 12/264,029, 12/264,060, and 12/264,076, all filed on Nov. 3, 2008 which are hereby incorporated herein by reference.
- The present invention relates to non-volatile configuration circuits which can be programmed one time, or multiple times in some instances. The invention has particular applicability to applications where is it desirable to customize electronic circuits, including programmable logic devices, field programmable gate arrays, etc.
- Field Programmable Gate Arrays (FPGAs) are well-known circuits used in a variety of electronic devices/computing systems. FPGAs offer the ability to update their functionality in the field, which is a substantial advantage over fixed ASIC type devices. FPGAs contain reconfigurable interconnects that allow predefined logic blocks to be wired together.
- Typically an SRAM is used to configure the functions of the logic blocks and the routing of the interconnections. Recent implementations, however, use a form of non-volatile memory to perform this function. These devices, however, are not optimal, however, as they require additional processing step to embed them within a logic circuit.
- One time programmable (OTP) and multi-time programmable (MTP) memories have been recently introduced for beneficial use in a number of applications where customization is required for both digital and analog designs. These applications include data encryption, reference trimming, manufacturing 10, security 10, and many other applications. Incorporating OTP and MTP memories nonetheless also typically comes at the expense of some additional processing steps.
- A new form of OTP is disclosed in the aforementioned U.S. application Ser. No. 12/264029 and which is incorporated by reference herein. In that disclosure, a new type of single-poly non-volatile memory device structure can be operated either as an OTP (one time programmable) or as an MTP (multiple time programmable) memory cell is disclosed. The device structure is fully compatible with advanced CMOS logic process, and would require, at the worst case, very minimal additional steps to implement. A unique aspect of the device is that the floating gate of the memory cell structure is electrically coupled strongly through one of the S/0 junctions of the transistor, whereas traditional single poly nonvolatile memory cells require either an additional interconnect layer to couple to the floating gate, or the floating gate has coupling to any of the existing electrical signals.
- Another key feature is that it is implemented with an NMOS device structure, whereas the traditional single-poly OTP is commonly implemented with a PMOS device structure. This means that the device can be formed at the same time as other n-channel devices on a wafer.
- Another advantage of an NMOS device structure is that it behaves similar to an EPROM device, i.e., the device is programmed into a non-conducting state from a conducting state. (The most commonly used PMOS OTP device is programmed from a non-conducting state into a conducting state). This can eliminate the need of an additional masking step that is commonly associated with a PMOS OTP device in order to make sure that PMOS device is in a non-conducting state coming out of the manufacturing fab. In addition, since an NMOS device's programming mechanism with channel hot electrons injection is self-limiting, unlike that case of a PMOS with channel hot electron programming, the amount of energy consumption during programming is self-limited for this invention.
- Another NMOS OTP implementation is disclosed by U.S. Pat. No. 6,920,067, incorporated by reference herein. The device in this reference is programmed with channel hot-hole-injection. The disclosure teaches that the device is programmed into conducting state, after the channel hot hole injection. However, it is unclear whether the device actually works in the way the inventors claim.
- That is, it is not apparent that the channel current will be initiated to induce hot-hole-injection since the state of the floating gate is unknown and there is no available means to couple a voltage unto the floating gate. An NMOS device will conduct a channel current to initiate the hot hole injection only when the floating gate potential is sufficient to turn on the device, or when the threshold voltage is always low initially to allow channel current conduction. The only way to ensure either scenario is to introduce an additional process step to modify the turn on characteristics of the NMOS. Now assuming the channel is conducting initially and hot holes are injected, the holes injected on the floating gate will make the device more conductive. So the device basically goes from a conductive state (in order to initiate channel current for hot hole injection) to a highly conductive state.
- This is not a very optimal behavior for a memory device.
- Another prior art device described in U.S. publication no. 2008/0186772 (incorporated by reference herein) shows a slightly different approach to the problem of providing a programming voltage to a floating gate embodiment of an OTP device. In this design, shown in
FIG. 4 , the drain border length L1 is increased relative to the source side length L1 to increase a coupling ratio to the eraseablefloating gate 416. By increasing the coupling ratio, the amount of channel current is increased; therefore the charge injection into the floating gate will also increase. The drawbacks of this cell, however, include the fact that the cell andchannel 412 must be asymmetric, and the coupling is only controlled using the length dimension of the active regions. Because of these limitations, it also does not appear to be extendable to a multi-level architecture. Moreover, it apparently is only implemented as a p-channel device. - Accordingly there is clearly a long-felt need for an embedded programmable configuration circuit which is capable of addressing these deficiencies in the prior art.
- An object of the present invention, therefore, is to overcome the aforementioned limitations of the prior art.
- It will be understood from the Detailed Description that the inventions can be implemented in a multitude of different embodiments. Furthermore, it will be readily appreciated by skilled artisans that such different embodiments will likely include only one or more of the aforementioned objects of the present inventions.
- Thus, the absence of one or more of such characteristics in any particular embodiment should not be construed as limiting the scope of the present inventions. While described in the context of a non-volatile memory array, it will be apparent to those skilled in the art that the present teachings could be used in any number of applications.
-
FIG. 1 is a top down view of a preferred embodiment of a non-volatile memory cell of the present invention; -
FIG. 2 is a side cross section view of the preferred non-volatile memory cell; -
FIG. 3 is an electrical diagram illustrating the electrical relationship of the structures of the preferred non-volatile memory cell; -
FIG. 4 depicts a prior art non-volatile memory cell which uses a floating gate for an OTP application; -
FIG. 5 is an electrical diagram showing a preferred embodiment of a latch circuit and/or configuration circuit constructed with the NV memory cells of the present invention. -
FIG. 6A is a top down view of the preferred non-volatile configuration circuit of the present invention; -
FIG. 68 is a flow diagram showing preferred operations used to manufacture the non-volatile configuration circuit of the present invention. - The present disclosure concerns a new type of non-volatile configuration circuit (preferably single poly) that can be operated either as an OTP (one time programmable) or as preferred device structure is fully compatible with advanced CMOS logic process, and would require, at the worst case, very minimal additional steps to implement.
- A unique aspect of the present device is that the floating gate of the memory cell structure is electrically coupled strongly through a variable number of S/D junctions of the transistor, whereas traditional single poly nonvolatile memory cells require either an additional interconnect layer to couple to the floating gate, or the floating gate has virtually none or minimal electrical coupling to any of the existing electrical signals. Moreover, unlike the 2008/0186772 reference, the coupling ratio can be more specific and precise. That is, by exactly controlling the coupling ratio (through areal means) the amount of charge, and thus the final programmed Vt, are directly proportional to the product of the coupling ratio and the drain voltage. It can be more precisely controlled such that the coupling ratio is dictated or designed by the desired programming threshold level (Vt) of the memory cell. This allows for a design that evolves easily into a multi-level version of an OTP since different coupling ratios yield different programmed Vt.
-
FIG. 1 illustrates the top view of the layout of a preferred structure used in the present invention.FIG. 2 illustrates a representative cross-sectional view of the device structure. It will be understood that these drawings are not intended to be set out to scale, and some aspects of the device have been omitted for clarity. - The device includes a
typical NMOS transistor 100 which is modified so that the gate (poly in a preferred embodiment) 110 of the device is not electrically connected to a voltage source. Adrain 120 of the device is bent around and is preferably joined by an N-type well 130 that typically already exists in a conventional advanced CMOS process. As an alternative, the N-Well 130 can be replaced with an n-type diffusion layer introduced so as to be beneath the poly floating gate. Aconventional source region 125 is also utilized. - The floating
gate poly 110 is extended beyond a typicaltransistor channel region 135 and includes anoverlap region 140 which overlaps an active region extending from the drain junction. Theactive region portion 141 that is surrounded by the N-Well region serves as an effective capacitive coupling to the floating gate. Thus any voltage applied to the drain junction will be effectively coupled onto the floating gate. - As seen in the electrical diagram of
FIG. 3 , if the coupling ratio of the drain to the floating gate is sufficiently high—which is determined by the ratio of the area of the gate channel region and the area of the Poly extension overlapping the drain extension region—the floating gate can effectively acquire and have a high percentage of the value of the drain voltage. - A key advantage of the preferred embodiment, as seen in
FIGS. 1 and 2 , is that it is formed from same layers conventionally used to make active n-channel devices in a CMOS process. The only difference is that the poly (or metal as the case may be) gate layer is not interconnected with such other formed active devices or coupled to a gate signal. The other implants for the source/drain are also part of a CMOS conventional process. Thus, in most applications the invention can be integrated without any additional processing costs, because the only alteration is to an existing mask for each relevant layer of the wafer being processed. - One other optional variation of this device structure is to make the drain-to-gate coupling capacitor area on the sidewall of a trench. This will greatly reduce the area of the drain-to-gate coupling capacitor. This reduction in cell area may come at the expense of significantly increase the manufacturing process complexity. However, again, in applications where the invention is integrated with certain types of DRAM architectures (especially embedded types), it is possible to incorporate the conventional processing steps for such memories to avoid additional processing costs. Other techniques for coupling a voltage to the floating gate and achieving a desired coupling ratio will be apparent to those skilled in the art.
- While the floating gate is shown as a single polysilicon layer, it will be appreciated by skilled artisans that other materials could be used as well. In some applications for example it may be possible to exploit the formation of other structures/devices which while part of other main underlying logic/memory structures, can be exploited for purposes of making a floating gate of some kind
- In this respect it should be noted that floating gates can typically be formed of a number of different materials, including through techniques in which impurities are implanted/diffused into a dielectric/insulating layer.
- Moreover while the preferred embodiment depicts the NVM cell as part of a conventional lateral-planar FET structure on a substrate, it will be apparent to those skilled in the art that other geometries/architectures can be used, including non-planar structures. Thus the invention could be used in SOl substrates, in thin film structures, at other levels of the device than the substrate, in multi-gate (FINFET type) orientations, and in vertical/non-planar configurations. In such latter instances the floating gate would be embedded and oriented vertically with respect to the substrate.
- The preferred operation of
device 100 will be described. The non-volatile device structure preferably has the physical features of a conventional 1/0 transistor implemented in an advanced CMOS logic process. At present, such 1/0 transistor is nominally operated at 3.3V but it will be understood that this value will change with successive generations of manufacturing. - This type of 1/0 transistor typically has a threshold voltage of 0.5V to 0.7V, with a typical electrical gate oxide thickness of 70A. With a drain coupling to floating gate ratio of 0.90, and a read drain voltage of 1.0V applied to the device, the floating gate will effectively be coupled with a voltage of about 0.90V. This is sufficient to turn on the
un-programmed NMOS device 100, and a channel current can be detected by typical means of sense circuitry to identify the state of the device. It will be understood to those skilled in the art that the particular coupling ratio, read voltage, etc., will vary from application to application and can be configured based on desired device operating characteristics. - The device is originally in an unprogrammed state, which in the preferred embodiment is characterized by a low resistance coupling between the source and drain through
channel region 135. This means that thechannel region 135 can be substantially uniform and current flow is reliable. While the preferred embodiment is shown in the form of a symmetric cell/channel, it will be understood that the invention could be used in non-symmetric forms such as shown in the aforementioned 20080186722 publication. - To program the device into a programmed state, the device must be shut off by reducing carriers in the channel region, and increasing the threshold voltage. To do this a drain voltage of 6.0V can be applied and this will effectively couple a voltage of about 5.4V to the floating gate. This bias condition will placed the device into a channel hot electron injection regime. The electrons injected into the floating gate effectively increase the threshold voltage of the device. When a subsequent read voltage of 1.0V is applied again on the drain, the device does not conduct current due to its high threshold voltage, and this second state of the device is thus determined. As with the read characteristics, it will be understood to those skilled in the art that the particular coupling ratio, program voltage, etc., will vary from application to application and can be configured based on desired device operating characteristics.
- The prior art referred to above is primarily a one time programmable device, since there is no disclosed mechanism for removing the charge on the floating gate. In contrast, some embodiments of the present invention can be made to be capable of multiple-time-programming.
- To do this, an erase operation can be introduced to remove or neutralize the electrons that have been injected into the floating gate. The mechanism for removing or neutralizing electrons is preferably through band-band tunneling hot hole injection from the other
non-coupling junction 125 of the device. The preferred bias condition would be as followed: the non-coupling junction (source junction) is biased with 6V to cause the junction to initiate band-band tunneling current. The band-band tunneling current causes hot holes to be injected into the floating gate and neutralize the electrons that are stored on the floating gate. Thus it is (re)programmed from a non-conducting, or even a low conducting state, into a conducting state. The device is then able to conduct channel current when a subsequent read voltage is applied to the coupling junction during the read operation. It will be understood that programming from a low conducting state to a conducting state may have a limited operating sense window. - As an additional optional operation, to facilitate erase operation and enhance band-band tunneling current, the coupling junction can be supplied with a negative voltage so that the floating gate is made more negative to cause higher band-band tunneling current across the source junction.
- Thus the operating characteristics are preferably as follows:
-
OPERATION Drain Source Substrate Program 6.0 V OV OV Read 1.0 V OV OV Erase Float or −Vee 6.0 V OV - In some embodiments, additional protection can be implemented to ensure the OTP and MTP device have sufficient immunity against the loss of charge stored on the floating gate. To do this, the device can be configured into a paired
latch 500—as shown in FIG. 5—where the data and its complement are stored into the latch, thus effectively doubling the margin in the stored data. As seen therein, atop device 510 couples anode 530 to a first voltage reference (Vee) while a second bottom device 520 couples the node to a second voltage reference (Vss). By placing charge on the top device floating gate, thetop device 510 is programmed into a non-conductive state, thus ensuring thatnode 530 is pulled down by bottom device 520 to Vss, representing a first logical data value (0). Similarly, by placing charge on the bottom device floating gate, the bottom device 520 is programmed into a non-conductive state, thus ensuring thatnode 530 is pulled up bytop device 510 to Vee, representing a second logical data value (1). - Another useful advantage of the present preferred embodiment is that it is implemented with an NMOS device structure, whereas most traditional single-poly OTPs are commonly implemented with a PMOS device structure. This means that the device can be formed at the same time as other n-channel devices on a wafer. Another advantage of an NMOS device structure in this invention is that it behaves similar to an EPROM device, i.e., the device is programmed into a non-conducting state from a conducting state. In contrast, the prior art 20080186722 type device—and other commonly used PMOS OTP devices—are programmed from a non-conducting state into a conducting state.
- This aspect of the invention thus can eliminate the need of an additional masking step that is commonly associated with a PMOS OTP device in order to make sure that PMOS device is in a non-conducting state coming out of the manufacturing fab.
- In addition, since an NMOS device's programming mechanism with channel hot electrons injection is self-limiting, unlike that case of a PMOS with channel hot electron programming, the amount of energy consumption during programming is self-limited for this invention.
- As seen in the present description therefore, the particular configuration of the floating gate is not critical. All that is required is that it be structurally and electrically configured to control channel conduction and also be capacitively coupled to an electrical source of charge carriers. The particular geometry can be varied in accordance with any desired layout or mask. In some instances it may be desirable to implement the floating gate as a multi-level structure for example. Moreover, since capacitive coupling is a function of the materials used, the invention allows for significant flexibility as the composition of the floating gate can also be varied as desired to accommodate and be integrated into a particular process. An array of cells constructed in accordance with the present teachings could include different shapes and sizes of floating gates so that cells having threshold cells could be created.
- Configuration Circuit for Programmable Logi
- As shown in
FIG. 5 , two of the OTP/MTP cells can be arranged in a manner such it can serve as aconfiguration storage circuit 500 in a programmable logic device or FPGA application. To serve as an FPGA configuration bit, anoutput 530 of the cell/circuit 500 has to be either Vee (logical high) or Vss (logical low), in order to drive a subsequent CMOS gate (not shown) inside an FPGA's logic block - As noted above, a single OTP/MTP cell preferably outputs either a fixed amount of read current or very little read current, depending on the programming state of the cell. Thus two of such cells would have to be connected together in an inverter fashion to output either Vee or Vss.
-
FIG. 5 illustrates the circuit connection in order to implement an FPGA configuration bit. It is basically two cells with afirst device 510 serving as a pull-up transistor and the other one 520 serving as a pull-down transistor in an “inverter” or “voltage divider” configuration. The top and bottom OTP/MTP cells can be programmed or erased by program logic circuit (not shown) into exactly the opposite state of each other, to renderoutput 530 into a particular desired logical value/state—i.e., as either Vee or Vss. - For passing the Vee voltage (high logic value) at
output node 530, the top OTP/MTP cell 510 is set to be conducting while the bottom OTP/MTP cell 520 is programmed into a non-conducting state. This way, theoutput node 530 tracks Vee—minus a threshould voltage which can be set to near zero via a channel implant adjustment as discussed below. - For rendering Vss (low logic value) at the
output node 530, the top OTP/MTP cell 510 is programmed into a non-conducting state while the bottom OTP cell 520 is programmed to a conducting state to discharge theoutput node 530 to Vss or ground. In this fashion, two OTP/MTP devices can be used as a configuration bit in an FPGA logic block, or any other programmable device. -
FIG. 6A shows a layout for theconfiguration circuit 500. A pair of floatinggates first drain region 620 andsecond drain region 620′ respectively. Thedrains conventional source region 625 is also utilized. - The floating
gate poly 610/610′ is extended beyond typicaltransistor channel regions 635/635′ and includesoverlap regions 640/640′ which overlap active regions extending from the drain junctions. Theactive region portions 641/641′ that are surrounded by the N-Well region serve as an effective capacitive coupling to the pair of floating gates. Thus any voltage applied to the drain junctions will be effectively coupled onto the respective floating gates. -
Output 650 drives a configuration value (1 or 0) to a subsequent CMOS gate (not shown). Thus a configuration circuit can be constructed of two OTP/MTP cells. - Because the two devices can be erased and re-programmed, the
output 650 of the configuration circuit 600 can be altered as desired to reflect a new configuration value. So a second logical value can be set in the circuit 600 for in-system re-programmability. - A flowchart of a fabrication process used to make an integrated logic/NVM configuration circuit is shown in
FIG. 68 . As seen therein, the configuration circuit 600 is manufactured using only the nominal processing steps otherwise required to make other logic circuits within a programmable logic device. The only differences are expressly shown to be as follows: a) any OTP/MTP devices are masked and not given an implant for adjusting an 1/0 device threshold voltage; b) if desired, an optional mask/implant can be introduced to compensate for the threshold voltage loss noted above. In other words, if theconfiguration circuit output 650 must equal Vee (i.e, no threshold drop), then this process step can compensate for such drop and afford a full swing output. - The above descriptions are intended as merely illustrative embodiments of the proposed inventions. It is understood that the protection afforded the present invention also comprehends and extends to embodiments different from those above, but which fall within the scope of the present claims.
Claims (16)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/362,687 US8582342B2 (en) | 2008-12-30 | 2012-01-31 | Non-volatile one-time-programmable and multiple-time programmable memory configuration circuit |
US13/734,500 US8705263B2 (en) | 2008-12-30 | 2013-01-04 | Non-volatile one-time-programmable and multiple-time programmable memory configuration circuit |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14161808P | 2008-12-30 | 2008-12-30 | |
US12/650,238 US8203861B2 (en) | 2008-12-30 | 2009-12-30 | Non-volatile one-time—programmable and multiple-time programmable memory configuration circuit |
US13/362,687 US8582342B2 (en) | 2008-12-30 | 2012-01-31 | Non-volatile one-time-programmable and multiple-time programmable memory configuration circuit |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/650,238 Continuation US8203861B2 (en) | 2008-12-30 | 2009-12-30 | Non-volatile one-time—programmable and multiple-time programmable memory configuration circuit |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/734,500 Continuation US8705263B2 (en) | 2008-12-30 | 2013-01-04 | Non-volatile one-time-programmable and multiple-time programmable memory configuration circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
US20120140564A1 true US20120140564A1 (en) | 2012-06-07 |
US8582342B2 US8582342B2 (en) | 2013-11-12 |
Family
ID=42284758
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/650,238 Expired - Fee Related US8203861B2 (en) | 2008-12-30 | 2009-12-30 | Non-volatile one-time—programmable and multiple-time programmable memory configuration circuit |
US13/362,687 Active US8582342B2 (en) | 2008-12-30 | 2012-01-31 | Non-volatile one-time-programmable and multiple-time programmable memory configuration circuit |
US13/734,500 Active US8705263B2 (en) | 2008-12-30 | 2013-01-04 | Non-volatile one-time-programmable and multiple-time programmable memory configuration circuit |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/650,238 Expired - Fee Related US8203861B2 (en) | 2008-12-30 | 2009-12-30 | Non-volatile one-time—programmable and multiple-time programmable memory configuration circuit |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/734,500 Active US8705263B2 (en) | 2008-12-30 | 2013-01-04 | Non-volatile one-time-programmable and multiple-time programmable memory configuration circuit |
Country Status (1)
Country | Link |
---|---|
US (3) | US8203861B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090124054A1 (en) * | 2007-11-14 | 2009-05-14 | Liu David K Y | Method of making integrated circuit embedded with non-volatile programmable memory having variable coupling |
US20130120023A1 (en) * | 2008-12-30 | 2013-05-16 | Invensas Corporation | Non-volatile one-time-programmable and multiple-time programmable memory configuration circuit |
US9449709B1 (en) * | 2015-09-23 | 2016-09-20 | Qualcomm Incorporated | Volatile memory and one-time program (OTP) compatible memory cell and programming method |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2012134239A2 (en) | 2011-03-31 | 2012-10-04 | 한양대학교 산학협력단 | Apparatus and method for generating a digital value |
US9230814B2 (en) | 2011-10-28 | 2016-01-05 | Invensas Corporation | Non-volatile memory devices having vertical drain to gate capacitive coupling |
US8873302B2 (en) | 2011-10-28 | 2014-10-28 | Invensas Corporation | Common doped region with separate gate control for a logic compatible non-volatile memory cell |
US8942034B2 (en) | 2013-02-05 | 2015-01-27 | Qualcomm Incorporated | System and method of programming a memory cell |
DE102014009640B4 (en) | 2014-06-26 | 2022-06-23 | Elmos Semiconductor Se | Transistor or memory cell transistor with floating gate without separate control gate |
KR102169634B1 (en) | 2014-09-30 | 2020-10-23 | 삼성전자주식회사 | Nonvolatile memory device |
US10127993B2 (en) | 2015-07-29 | 2018-11-13 | National Chiao Tung University | Dielectric fuse memory circuit and operation method thereof |
US9953727B1 (en) | 2017-02-10 | 2018-04-24 | Globalfoundries Inc. | Circuit and method for detecting time dependent dielectric breakdown (TDDB) shorts and signal-margin testing |
US10797063B2 (en) * | 2018-01-10 | 2020-10-06 | Ememory Technology Inc. | Single-poly nonvolatile memory unit |
CN115581068A (en) * | 2021-07-06 | 2023-01-06 | 成都锐成芯微科技股份有限公司 | Anti-fuse type one-time programming nonvolatile memory unit and memory thereof |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7729864B2 (en) * | 2003-05-30 | 2010-06-01 | Merck Sharp & Dohme Corp. | Computer systems and methods for identifying surrogate markers |
US7852656B2 (en) * | 2007-02-16 | 2010-12-14 | Magnachip Semiconductor Ltd. | One-time programmable cell and memory device having the same |
Family Cites Families (61)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4087795A (en) * | 1974-09-20 | 1978-05-02 | Siemens Aktiengesellschaft | Memory field effect storage device |
US4328565A (en) * | 1980-04-07 | 1982-05-04 | Eliyahou Harari | Non-volatile eprom with increased efficiency |
IT1209227B (en) * | 1980-06-04 | 1989-07-16 | Sgs Microelettronica Spa | ELECTRICALLY ALTERABLE FLOATING 'GATE' MEMORY CELL. |
US4532611A (en) * | 1982-11-01 | 1985-07-30 | Motorola, Inc. | Redundant memory circuit |
US4870304A (en) * | 1987-12-08 | 1989-09-26 | Cypress Semiconductor Corporation | Fast EPROM programmable logic array cell |
JPH07120720B2 (en) * | 1987-12-17 | 1995-12-20 | 三菱電機株式会社 | Nonvolatile semiconductor memory device |
DE4121053C2 (en) * | 1991-06-26 | 1995-10-19 | Eurosil Electronic Gmbh | Memory cell with floating gate transistor |
JP3522788B2 (en) * | 1992-10-29 | 2004-04-26 | 株式会社ルネサステクノロジ | Semiconductor integrated circuit device |
EP0595775B1 (en) * | 1992-10-29 | 1999-07-28 | STMicroelectronics S.r.l. | Method of evaluating the dielectric layer of nonvolatile EPROM, EEPROM and flash-EEPROM memories |
US5410268A (en) * | 1993-09-08 | 1995-04-25 | Advanced Micro Devices, Inc. | Latching zero-power sense amplifier with cascode |
JP3073645B2 (en) * | 1993-12-27 | 2000-08-07 | 株式会社東芝 | Nonvolatile semiconductor memory device and method of operating the same |
US5598367A (en) | 1995-06-07 | 1997-01-28 | International Business Machines Corporation | Trench EPROM |
US6461916B1 (en) * | 1997-03-28 | 2002-10-08 | Hitachi, Ltd. | Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making the device |
JP3481817B2 (en) * | 1997-04-07 | 2003-12-22 | 株式会社東芝 | Semiconductor storage device |
US5914898A (en) * | 1997-08-05 | 1999-06-22 | Micron Technology, Inc. | Memory device and system with leakage blocking circuitry |
EP0926260A3 (en) * | 1997-12-12 | 2001-04-11 | Matsushita Electric Industrial Co., Ltd. | Using antibody - antigen interaction for formation of a patterened metal film |
AU1960301A (en) * | 1999-09-13 | 2001-04-17 | Advanced Technology Materials, Inc. | A single chip embedded microcontroller having multiple non-volatile erasable proms sharing a single high voltage generator |
US6407963B1 (en) * | 1999-10-19 | 2002-06-18 | Hitachi, Ltd. | Semiconductor memory device of DDR configuration having improvement in glitch immunity |
US6577531B2 (en) * | 2000-04-27 | 2003-06-10 | Semiconductor Energy Laboratory Co., Ltd. | Nonvolatile memory and semiconductor device |
US6400603B1 (en) * | 2000-05-03 | 2002-06-04 | Advanced Technology Materials, Inc. | Electronically-eraseable programmable read-only memory having reduced-page-size program and erase |
JP2001358313A (en) | 2000-06-14 | 2001-12-26 | Hitachi Ltd | Semiconductor device |
US6631087B2 (en) * | 2000-06-23 | 2003-10-07 | Gennum Corporation | Low voltage single poly deep sub-micron flash eeprom |
TW477065B (en) * | 2001-01-30 | 2002-02-21 | Ememory Technology Inc | Manufacturing method of flash memory cell structure with dynamic-like write-in/erasing through channel and its operating method |
US6441443B1 (en) * | 2001-02-13 | 2002-08-27 | Ememory Technology Inc. | Embedded type flash memory structure and method for operating the same |
JP4170604B2 (en) * | 2001-04-18 | 2008-10-22 | 株式会社東芝 | Nonvolatile semiconductor memory |
US6731541B2 (en) * | 2001-05-09 | 2004-05-04 | Gennum Corporation | Low voltage single poly deep sub-micron flash EEPROM |
US6489202B1 (en) * | 2001-05-29 | 2002-12-03 | Ememory Technology, Inc. | Structure of an embedded channel write-erase flash memory cell and fabricating method thereof |
JP2003197765A (en) * | 2001-12-28 | 2003-07-11 | Texas Instr Japan Ltd | Semiconductor device and its manufacturing method |
US6678190B2 (en) * | 2002-01-25 | 2004-01-13 | Ememory Technology Inc. | Single poly embedded eprom |
KR100442090B1 (en) * | 2002-03-28 | 2004-07-27 | 삼성전자주식회사 | Non-volatile memory cells having a split gate structure and methods of fabricating the same |
JP4557950B2 (en) | 2002-05-10 | 2010-10-06 | 株式会社東芝 | Nonvolatile semiconductor memory device |
US7064978B2 (en) | 2002-07-05 | 2006-06-20 | Aplus Flash Technology, Inc. | Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout |
WO2004015764A2 (en) * | 2002-08-08 | 2004-02-19 | Leedy Glenn J | Vertical system integration |
US6920067B2 (en) * | 2002-12-25 | 2005-07-19 | Ememory Technology Inc. | Integrated circuit embedded with single-poly non-volatile memory |
US6914825B2 (en) * | 2003-04-03 | 2005-07-05 | Ememory Technology Inc. | Semiconductor memory device having improved data retention |
US6989562B2 (en) * | 2003-04-04 | 2006-01-24 | Catalyst Semiconductor, Inc. | Non-volatile memory integrated circuit |
JP2005038894A (en) | 2003-07-15 | 2005-02-10 | Sony Corp | Nonvolatile semiconductor memory apparatus and its operating method |
JP2005057106A (en) | 2003-08-06 | 2005-03-03 | Sony Corp | Non volatile semiconductor memory device and its charge injecting method |
US7046549B2 (en) * | 2003-12-31 | 2006-05-16 | Solid State System Co., Ltd. | Nonvolatile memory structure |
JP2005236139A (en) * | 2004-02-20 | 2005-09-02 | Matsushita Electric Ind Co Ltd | Non-volatile semiconductor memory apparatus and its driving method and method for manufacturing the same |
JP2006093707A (en) * | 2004-09-22 | 2006-04-06 | Samsung Electronics Co Ltd | Semiconductor device and manufacturing method therefor |
US7256439B2 (en) * | 2005-01-21 | 2007-08-14 | International Business Machines Corporation | Trench capacitor array having well contacting merged plate |
US7471570B2 (en) * | 2005-09-19 | 2008-12-30 | Texas Instruments Incorporated | Embedded EEPROM array techniques for higher density |
US7808818B2 (en) * | 2006-01-12 | 2010-10-05 | Saifun Semiconductors Ltd. | Secondary injection for NROM |
US7365387B2 (en) * | 2006-02-23 | 2008-04-29 | Hewlett-Packard Development Company, L.P. | Gate-coupled EPROM cell for printhead |
EP1840901B1 (en) * | 2006-03-31 | 2010-04-28 | STMicroelectronics Srl | Method for programming a memory device suitable to minimize floating gate couplings and memory device |
TWI325165B (en) * | 2006-04-20 | 2010-05-21 | Ememory Technology Inc | Method for operating a single-poly single-transistor non-volatile memory cell |
US7457163B2 (en) | 2006-06-01 | 2008-11-25 | Sandisk Corporation | System for verifying non-volatile storage using different voltages |
US20080035973A1 (en) * | 2006-08-10 | 2008-02-14 | Hsin Chang Lin | Low-noise single-gate non-volatile memory and operation method thereof |
JP2008103675A (en) * | 2006-09-22 | 2008-05-01 | Toshiba Corp | Semiconductor integrated circuit |
US7518923B2 (en) * | 2006-12-29 | 2009-04-14 | Sandisk Corporation | Margined neighbor reading for non-volatile memory read operations including coupling compensation |
US7939861B2 (en) * | 2007-02-02 | 2011-05-10 | Synopsys, Inc. | Non-volatile memory devices having floating-gates FETs with different source-gate and drain-gate border lengths |
US8067795B2 (en) * | 2007-03-12 | 2011-11-29 | Texas Instruments Incorporated | Single poly EEPROM without separate control gate nor erase regions |
RU2422922C1 (en) | 2007-06-08 | 2011-06-27 | Долби Лэборетериз Лайсенсинг Корпорейшн | Hybrid derivation of surround sound audio channels by controllably combining ambience and matrix-decoded signal components |
US20090016118A1 (en) * | 2007-07-12 | 2009-01-15 | Silicon Storage Technology, Inc. | Non-volatile dram with floating gate and method of operation |
US7782668B2 (en) | 2007-11-01 | 2010-08-24 | Jonker Llc | Integrated circuit embedded with non-volatile one-time-programmable and multiple-time programmable memory |
US7787295B2 (en) | 2007-11-14 | 2010-08-31 | Jonker Llc | Integrated circuit embedded with non-volatile multiple-time programmable memory having variable coupling |
US7876615B2 (en) * | 2007-11-14 | 2011-01-25 | Jonker Llc | Method of operating integrated circuit embedded with non-volatile programmable memory having variable coupling related application data |
US7852672B2 (en) * | 2007-11-14 | 2010-12-14 | Jonker Llc | Integrated circuit embedded with non-volatile programmable memory having variable coupling |
US8305805B2 (en) | 2008-11-03 | 2012-11-06 | Invensas Corporation | Common drain non-volatile multiple-time programmable memory |
US8203861B2 (en) | 2008-12-30 | 2012-06-19 | Invensas Corporation | Non-volatile one-time—programmable and multiple-time programmable memory configuration circuit |
-
2009
- 2009-12-30 US US12/650,238 patent/US8203861B2/en not_active Expired - Fee Related
-
2012
- 2012-01-31 US US13/362,687 patent/US8582342B2/en active Active
-
2013
- 2013-01-04 US US13/734,500 patent/US8705263B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7729864B2 (en) * | 2003-05-30 | 2010-06-01 | Merck Sharp & Dohme Corp. | Computer systems and methods for identifying surrogate markers |
US7852656B2 (en) * | 2007-02-16 | 2010-12-14 | Magnachip Semiconductor Ltd. | One-time programmable cell and memory device having the same |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090124054A1 (en) * | 2007-11-14 | 2009-05-14 | Liu David K Y | Method of making integrated circuit embedded with non-volatile programmable memory having variable coupling |
US8580622B2 (en) | 2007-11-14 | 2013-11-12 | Invensas Corporation | Method of making integrated circuit embedded with non-volatile programmable memory having variable coupling |
US9224739B2 (en) | 2007-11-14 | 2015-12-29 | Invensas Corporation | Method of making integrated circuit embedded with non-volatile programmable memory having variable coupling |
US20130120023A1 (en) * | 2008-12-30 | 2013-05-16 | Invensas Corporation | Non-volatile one-time-programmable and multiple-time programmable memory configuration circuit |
US8582342B2 (en) | 2008-12-30 | 2013-11-12 | Invensas Corporation | Non-volatile one-time-programmable and multiple-time programmable memory configuration circuit |
US8705263B2 (en) * | 2008-12-30 | 2014-04-22 | Invensas Corporation | Non-volatile one-time-programmable and multiple-time programmable memory configuration circuit |
US9449709B1 (en) * | 2015-09-23 | 2016-09-20 | Qualcomm Incorporated | Volatile memory and one-time program (OTP) compatible memory cell and programming method |
Also Published As
Publication number | Publication date |
---|---|
US8203861B2 (en) | 2012-06-19 |
US8582342B2 (en) | 2013-11-12 |
US20130120023A1 (en) | 2013-05-16 |
US20100165698A1 (en) | 2010-07-01 |
US8705263B2 (en) | 2014-04-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8582342B2 (en) | Non-volatile one-time-programmable and multiple-time programmable memory configuration circuit | |
US7920426B2 (en) | Non-volatile memory programmable through areal capacitive coupling | |
US8325519B2 (en) | Method of operating integrated circuit embedded with non-volatile programmable memory having variable coupling related application data | |
US8208299B2 (en) | Integrated circuit embedded with non-volatile programmable memory having variable coupling and separate read/write paths | |
US7852672B2 (en) | Integrated circuit embedded with non-volatile programmable memory having variable coupling | |
US7746696B1 (en) | CMOS twin cell non-volatile random access memory | |
US7430137B2 (en) | Non-volatile memory cells in a field programmable gate array | |
US8305805B2 (en) | Common drain non-volatile multiple-time programmable memory | |
US8598642B2 (en) | Very dense NVM bitcell | |
US6525962B1 (en) | High current and/or high speed electrically erasable memory cell for programmable logic devices | |
US9224739B2 (en) | Method of making integrated circuit embedded with non-volatile programmable memory having variable coupling | |
KR100667898B1 (en) | Nonvolatile semiconductor memory device | |
JP2004253686A (en) | Electrically erasable programmable logic device | |
JP5554714B2 (en) | Integrated circuit incorporated in non-volatile programmable memory with variable coupling | |
KR100745030B1 (en) | Flash memory device, method for manufacturing the same and driving method for the same | |
US8445972B2 (en) | Semiconductor device with reconfigurable logic |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: JONKER LLC, NEVADA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LIU, DAVID K. Y.;GROSS, JOHN NICHOLAS;REEL/FRAME:029601/0346 Effective date: 20091103 |
|
AS | Assignment |
Owner name: TESSERA INTELLECTUAL PROPERTIES, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:JONKER LLC;REEL/FRAME:029603/0775 Effective date: 20110406 |
|
AS | Assignment |
Owner name: INVENSAS CORPORATION, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TESSERA INTELLECTUAL PROPERTIES, INC.;REEL/FRAME:029613/0296 Effective date: 20110425 |
|
AS | Assignment |
Owner name: JONKER LLC, NEVADA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LIU, DAVID K.Y.;GROSS, JOHN NICHOLAS;REEL/FRAME:030129/0521 Effective date: 20091103 Owner name: INVENSAS CORPORATION, CALIFORNIA Free format text: CHANGE OF NAME;ASSIGNOR:TESSERA INTELLECTUAL PROPERTIES, INC.;REEL/FRAME:030129/0381 Effective date: 20110425 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: ROYAL BANK OF CANADA, AS COLLATERAL AGENT, CANADA Free format text: SECURITY INTEREST;ASSIGNORS:INVENSAS CORPORATION;TESSERA, INC.;TESSERA ADVANCED TECHNOLOGIES, INC.;AND OTHERS;REEL/FRAME:040797/0001 Effective date: 20161201 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: BANK OF AMERICA, N.A., NORTH CAROLINA Free format text: SECURITY INTEREST;ASSIGNORS:ROVI SOLUTIONS CORPORATION;ROVI TECHNOLOGIES CORPORATION;ROVI GUIDES, INC.;AND OTHERS;REEL/FRAME:053468/0001 Effective date: 20200601 |
|
AS | Assignment |
Owner name: INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.), CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:052920/0001 Effective date: 20200601 Owner name: TESSERA, INC., CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:052920/0001 Effective date: 20200601 Owner name: INVENSAS CORPORATION, CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:052920/0001 Effective date: 20200601 Owner name: PHORUS, INC., CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:052920/0001 Effective date: 20200601 Owner name: DTS, INC., CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:052920/0001 Effective date: 20200601 Owner name: DTS LLC, CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:052920/0001 Effective date: 20200601 Owner name: FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS), CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:052920/0001 Effective date: 20200601 Owner name: IBIQUITY DIGITAL CORPORATION, MARYLAND Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:052920/0001 Effective date: 20200601 Owner name: TESSERA ADVANCED TECHNOLOGIES, INC, CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:052920/0001 Effective date: 20200601 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |