US20120199990A1 - Semiconductor Module Having Deflecting Conductive Layer Over a Spacer Structure - Google Patents
Semiconductor Module Having Deflecting Conductive Layer Over a Spacer Structure Download PDFInfo
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- US20120199990A1 US20120199990A1 US13/448,583 US201213448583A US2012199990A1 US 20120199990 A1 US20120199990 A1 US 20120199990A1 US 201213448583 A US201213448583 A US 201213448583A US 2012199990 A1 US2012199990 A1 US 2012199990A1
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- spacer structure
- semiconductor chip
- conductive layer
- conductive
- forming
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Abstract
A module includes a semiconductor chip and a conductive layer arranged over the semiconductor chip. The module also includes a spacer structure arranged to deflect the conductive layer away from the semiconductor chip.
Description
- This is a divisional application of U.S. application Ser. No. 11/686,222, entitled “Semiconductor Module Having Deflecting Conductive Layer Over a Spacer Structure,” which was filed on Mar. 14, 2007, and is hereby incorporated herein by reference.
- This invention relates to a semiconductor module.
- Semiconductor modules include one or more semiconductor chips having internal structures that contain active and possibly passive components. Such semiconductor modules may further include components external to the semiconductor chip(s). During operation of the semiconductor module there may occur electromagnetic interactions between the internal components of the semiconductor chip(s) and the external components. Such interactions may result in a decrease of the performance of the semiconductor module.
- Aspects of the invention are made more evident by way of example in the following detailed description of embodiments when read in conjunction with the attached figures, wherein:
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FIG. 1 shows a sectional side view of a first module; -
FIG. 2 shows a sectional side view of a second module; -
FIG. 3 shows a top plan view of a part of the second module; -
FIG. 4 shows a sectional side view of a third module; -
FIG. 5 shows a sectional side view of a fourth module; -
FIG. 6 shows a sectional side view of a fifth module; -
FIG. 7 shows a top plan view of the fifth module; and -
FIG. 8 shows an alternative embodiment of a sectional side view of a first module. - The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
- Modules described in the following comprise one or more semiconductor chips. The semiconductor chip may include an integrated circuit that comprises active semiconductor devices and may additionally comprise passive components. For instance, the integrated circuit may be an analog, digital or mixed signal circuit and may implement various functions, among them digital signal processing, signal amplification, active filtering, demodulation, mixing, analog-to-digital conversion, digital-to-analog conversion, etc. The integrated circuit may implement sensor or actuator structures, e.g., in form of a MEMS (Micro-Electrical Mechanical Systems) device. Specifically, the semiconductor chip may comprise functional areas operating at radio frequency.
- Modules described herein further comprise a conductive layer arranged over the semiconductor chip. The conductive layer may be used for an electrical connection between the semiconductor chip and possible external applications. Possible conductive layers may, for example, comprise one-dimensional conductive lines. Applicable materials for the fabrication of the conductive layer are, e.g., metals, metal alloys or organic conductors.
- Modules described herein further comprise a spacer structure arranged to deflect the conductive layer away from the semiconductor chip. The spacer structure may be made of arbitrary non-conducting materials, for example, an inorganic or organic dielectric material, such as polyimide, or a dielectric material with a preferably low value of its dielectric constant (low-k material). Other possibilities are printing ink or photoresist materials. Moreover, the spacer structure may be of optional shape or geometric form, thereby covering any desired region of the semiconductor chip. The spacer structure may or may not contact the semiconductor chip or the conductive layer directly.
- Modules described herein may further comprise one or more dielectric layers, which may be made of many organic or inorganic dielectric materials. The dielectric materials may have a low value of their dielectric constant. The dielectric layers may be composite structures manufactured out of multiple materials.
- Modules described herein may further comprise a mold compound or package that laterally adjoins the semiconductor chip or in which the semiconductor chip is embedded. The mold compound may, for example, be made of a thermoplastic resin or a thermosetting plastic, for example, epoxy resin.
- In the following, identical or corresponding parts of the drawings are denoted by the same reference signs.
FIG. 1 shows a sectional side view of amodule 100 representing a first embodiment. Themodule 100 comprises asemiconductor chip 1, aspacer structure 2 arranged on thesemiconductor chip 1 and aconductive layer 3 arranged on both thesemiconductor chip 1 and thespacer structure 2. Due to thespacer structure 2 arranged between thesemiconductor chip 1 and theconductive layer 3, theconductive layer 3 is deflected away from thesemiconductor chip 1. - In
FIG. 1 , internal structures of thesemiconductor chip 1 are not shown. However, it is known to a person skilled in the art that semiconductor chips may comprise passive components (such as, for example, inductors, resistors or capacitors) and active components (such as, for example, transistors or operational amplifiers). These components are comprised in a region of thesemiconductor chip 1, which is usually referred to as an active region. - The
conductive layer 3 may, for example, have the function of a redistribution layer, i.e., a layer providing an electrical connection between thesemiconductor chip 1 and possible external applications, which are likewise not explicitly shown inFIG. 1 . The conductive layer may contain passive components (such as inductors, resistors or capacitors). These passive components may be embedded in theconductive layer 3, for example, an inductor may be realized by a coil-shaped conductive line. Such “embedded passives” may, for example, be fabricated by thin-film technology (e.g., using sputtering and/or plating). - During the operation of the
module 100, electromagnetic coupling between the active and/or passive components of the active region of thesemiconductor chip 1 and the passive components of theconductive layer 3 may occur. In case of thesemiconductor chip 1 comprising functional areas working at radio-frequency, there may also occur coupling between active and/or passive elements and radio-frequency sensitive conduction lines in theconductive layer 3. Coupling may cause cross-talk of electric signals between different components. - Such coupling may decrease the performance of the involved components, which in turn may result in a decrease of the overall performance of the
module 100. In general, coupling may alter the characteristic operational parameters of themodule 100 in a way that is not desired by the designer. If aconductive layer 3 is routed at a distance of about 8 μm over an embedded inductor contained in thesemiconductor chip 1, the inductance of an inductor of thesemiconductor chip 1 is decreased from about 10 nH to about 6.5 nH. Moreover, the resonance frequency is shifted and the quality factor is reduced from about 15 to about 7. Note that such effects may occur for components in thesemiconductor chip 1 as well as for components in theconductive layer 3. The coupling may occur between active and passive components, but also between components of the same type, i.e., the combinations passive-passive or active-active. - One possibility to circumvent such coupling effects is to avoid critical areas in the
semiconductor chip 1 and theconductive layer 3 to meet each other, i.e., to avoid the overlap of involved components. As critical areas of thesemiconductor chip 1 and theconductive layer 3 are typically not engaging the whole semiconductor chip area, it may be possible to avoid or reduce coupling effects by choosing an appropriate geometric design of theconductive layer 3 that guarantees the same not to run over critical areas of thesemiconductor chip 1 or by changing the design of thesemiconductor chip 1. However, these approaches are expensive because they increase the required die area and may further be limited by design constraints. - According to
FIG. 1 , due to thespacer structure 2 arranged between thesemiconductor chip 1 and theconductive layer 3, the distance between thesemiconductor chip 1 and theconductive layer 3 is increased at relevant locations. Thereby the coupling between internal semiconductor chip components and components external to the semiconductor chip and its undesired effects on the performance of themodule 100 are decreased. This allows to route theconductive layer 3 directly over critical areas in thesemiconductor chip 1, i.e., allows to use this otherwise “forbidden” chip area for signal routing purposes by means of theconductive layer 3 or for the purpose to implement one or more passive components in the elevated zone of theconductive layer 3. - The sectional side view of the
module 100 inFIG. 1 only shows asingle spacer structure 2. It is, however, understood that further spacer structures designed in accordance withspacer structure 2 are provided. The number of spacer structures, their form and their dimensions in each spatial direction may depend on the layout of the active region of thesemiconductor chip 1 and/or the layout of theconductive layer 3, i.e., the locations of their respective critical regions. It is also understood that themodule 100 may comprise a plurality of conductive layers arranged beneath or over each other. Each of these conductive layers may comprise passive components. The spacer structure may be arranged between two different conductive layers, whereby couplings between the elevated conductive layer and the semiconductor chip as well as between the elevated conductive layer and the underlying conductive layer are decreased. - The height of the
spacer structure 2 may be at least 5 μm, particularly at least 8 μm, and more particularly at least 12 μm. With regard to the coupling strength, this height adds to the usual (i.e., without spacer structure 2) distance between theconductive layer 3 and internal passive or active components of thesemiconductor chip 1, which is typically about 8 μm. The lateral dimensions of thespacer structure 2 may be chosen such that thespacer structure 2 completely covers a critical region of thesemiconductor chip 1, e.g., a functional area operating at radio-frequency. Thus, the lateral dimensions of thespacer structure 2 may be equal to or smaller than 700 μm, more particularly equal to or smaller than 500 μm and still more particularly equal to or smaller than 300 μm. For the case of thesemiconductor chip 1 having a longer critical region, one of the corresponding lateral dimensions of thespacer structure 2 may exceed the above-mentioned values. Coupling can further be reduced with thespacer structure 2 being made of a dielectric material having a low dielectric constant. Values of the dielectric constant may be less than about 4.0 and more particularly less than about 2.5. - The
conductive layer 3 may comprise one or more conductive lines that are routed above thespacer structure 2. Due to thespacer structure 2, the conductive lines are deflected away from thesemiconductor chip 1, such that the distance between thesemiconductor chip 1 and the lines is locally increased. Thespacer structure 2 may show rounded edges. Thus, the curvature of the conductive lines (or generally the conductive layer 3) at the transitions between thesemiconductor chip 1 and thespacer structure 2 is smooth and the risk of damaging the conductive lines routed over the transitions is decreased. It may further be advantageous, if the conductive lines (or generally the conductive layer 3) are deflected away from thesemiconductor chip 1 at an inclination angle less than about 90 degrees, preferably at an inclination angle less than about 70 degrees. In this case, thespacer structure 2 may have a sectional shape of a trapezoid. - During the fabrication or the operation of the
module 100, the same may expand or contract (for example, due to temperature changes). This may result in lateral forces acting on conductive lines or on theconductive layer 3 routed over thesemiconductor chip 1 and thespacer structure 2. This leads to a risk of the conductive lines to be torn apart, which can be avoided (or minimized) by arranging the conductive lines in such a way that they linearly extend over thespacer structure 2 in a direction towards the center of thesemiconductor chip 1. In this case, only longitudinal forces are acting on the conductive lines, while the lateral forces are kept small. - The
spacer structure 2 may be manufactured using different techniques. A first method is stencil print processes or screen print processes. In these processes a structured stencil or screen, on which the desired position and shape of thespacer structure 2 are mapped to form openings, is arranged over thesemiconductor chip 1. In a next step, the material from which thespacer structure 2 is to be formed is pressed through the openings of the stencil (screen) and deposited over thesemiconductor chip 1. Then, the stencil (screen) is removed with the desiredspacer structure 2 remaining over thesemiconductor chip 1. Thespacer structure 2 can then be hardened in a curing process. Using this process, thespacer structure 2 may be made of a printable material, in particular epoxy resin or silicone. - A second method for manufacturing the
spacer structure 2 is thin-film technology processes, which are common and well-known to a person skilled in the art. In thin-film technology processes, thespacer structure 2 may be made of a photoresist material that is structured by photolithographic processes. - A third method for manufacturing the
spacer structure 2 uses common ink-jet or dispense processes. This process may automatically generate the above-mentioned rounded edges of thespacer structure 2 and may also use the printable materials as mentioned above. -
FIG. 2 shows a sectional side view of asecond module 200 representing a second embodiment. Themodule 200 comprises asemiconductor chip 1 and (in contrast to themodule 100 shown inFIG. 1 ) explicitly illustrates an internalactive structure 4 of thesemiconductor chip 1. Theactive structure 4 comprises alayer 4 a containing passive and/or active components and a semiconductor chip internalconductive layer 4 b. The shadedarea 4 c of thelayer 4 a indicates a critical area as described above (for example, a functional area of thesemiconductor chip 1 operating at radio-frequency). Thesemiconductor chip 1 may comprise an integrated circuit formed of the components comprised in thelayer 4 a. Examples for these components are inductors, resistors, capacitors or MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). - To generate the
active structure 4, the electronic properties of thesemiconductor chip 1 may be altered by doping it with impurity atoms. The impurity atoms are incorporated into thesemiconductor chip 1 at various depths and various concentrations. According to the desired functionality of the semiconductor chip 1 (respectively its integrated circuit), the components contained in thelayer 4 a are then electrically connected (for example, using conductive lines). The resultingconductive layer 4 b bringing the electrical connection about is known as “interconnect layer” in the art. Note that thisinterconnect layer 4 b is chip internal and has to be distinguished from theconductive layer 3 shown inFIG. 1 andFIG. 2 . Typically, a plurality of such interconnect layers are provided within thesemiconductor chip 1. - The
module 200 further comprises apassivation layer 5, which may, for example, be made of an inorganic material, e.g., silicon nitride or silicon oxide. Thepassivation layer 5 is still part of thesemiconductor chip 1. Embeddedcontact pads 6 are provided within thispassivation layer 5 and are electrically connected to theactive structure 4. Thecontact pads 6 may, for instance, be made of small aluminum or copper plates. - The
module 200 further comprises a first chipexternal dielectric layer 7, which is deposited over thesemiconductor chip 1, i.e., over thepassivation layer 5. Thedielectric layer 7 may be made of a dielectric material (preferably having a small dielectric constant) and may, for example, be fabricated and structured via deposition from the gas phase, lamination or thin-film technology. Thedielectric layer 7 is opened at the positions of thecontact pads 6. The corresponding opening procedure may, for example, be performed by a photolithographic process or an etching process. - In general the locations and the spatial dimensions of the
contact pads 6 do not necessarily match the electrical contacts of external applications (e.g., a circuit board not shown inFIG. 2 ) to which themodule 200 is to be connected. To provide this interconnection, aconductive layer 3 is arranged over thedielectric layer 7. Theconductive layer 3 is usually referred to as “redistribution layer.” The electrical connection to an external application may then be realized by acontact element 8. Thecontact element 8 may, for example, be made of a solder material in form of a ball. - The
module 200 further comprises aspacer structure 2 arranged over the firstdielectric layer 7. Note that thespacer structure 2 is arranged between the firstdielectric layer 7 and theconductive layer 3 resulting in a deflection of theconductive layer 3 away from thesemiconductor chip 1 and its active structure. The distance between the shadedcritical area 4 c in thelayer 4 a and theconductive layer 3 is thereby locally increased. Theconductive layer 3 over the spacer structure 2 (i.e., arranged within the outline of the spacer structure 2) may comprise embedded passive components like inductors, resistors or capacitors. - As illustrated in the cross sectional view of
FIG. 8 , the order of the firstdielectric layer 7 and thespacer structure 2 may be exchanged. More specifically, thespacer structure 2 may be directly deposited on thesemiconductor chip 1 and may thus be arranged in between thesemiconductor chip 1 and the thin-film layers conductive layer 3 is deflected away from thesemiconductor chip 1 and coupling effects are reduced. Accordingly, the chronology of the two steps of forming thespacer structure 2 and depositing the firstdielectric layer 7 may be arbitrary in general. - In some cases, however, the step of depositing the first
dielectric layer 7 and the step of forming thespacer structure 2 should be carried out in a specific order. If, for example, the firstdielectric layer 7 is deposited in a spinning process, the employed dielectric material is radially distributed over thesemiconductor chip 1 in a centrifugal process. If thespacer structure 2 would have been formed before this centrifugal process, this would result in “blind areas” located behind thespacer structure 2, i.e., areas over which the firstdielectric layer 7 cannot be distributed. Thus, if a spinning process is used to deposit the firstdielectric layer 7, thespacer structure 2 should be formed afterwards. Note that there are multiple processes for the deposition of thedielectric layer 7, the forming of thespacer structure 2 and combinations thereof. - A
second dielectric layer 9 is arranged over theconductive layer 3 and/or thespacer structure 2 and/or the firstdielectric layer 7. Thesecond dielectric layer 9 may, for example, be a solder stop layer used to prevent the (not yet hardened)contact element 8 to flow over other elements of themodule 200. Thesecond dielectric layer 9 may have the same properties as the above-described firstdielectric layer 7. -
FIG. 3 shows a top plan view of asector 300 of themodule 200 shown inFIG. 2 . Thesector 300 comprises the firstdielectric layer 7 arranged over the semiconductor chip 1 (not shown due to the chosen perspective), theconductive layer 3 and thespacer structure 2. Theconductive layer 3 is arranged over the firstdielectric layer 7 and thespacer structure 2. InFIG. 3 theconductive layer 3 is embodied as a conductive line routed over the firstdielectric layer 7 and climbing thespacer structure 2. On top of thespacer structure 2, the conductive line establishes a passive component. Here, the conductive line is circled in multiple windings resulting in an inductor of a spiral shape. -
FIG. 4 shows a sectional side view of athird module 400 as a third embodiment, wherein themodule 400 is mostly similar to themodule 200 shown inFIG. 2 . In contrast tomodule 200, theconductive layer 3 on the right hand side ofmodule 400 is opened to provide the possibility of an electrical connection between theconductive layer 3 and afurther contact element 10. Theconductive layer 3 may comprise an embedded passive component and accordingly thecontact element 10 may directly contact theconductive layer 3 and/or the passive component comprised therein. Thecontact element 10 may then also be connected to a possible external application. The mentioned passive component comprised in theconductive layer 3 may, for example, be an inductor of the type shown inFIG. 3 or any other passive element. -
FIG. 5 shows a sectional side view of afifth module 500 as a fourth embodiment. Themodule 500 comprises asemiconductor chip 1 and a firstdielectric layer 7 arranged over the same. Over the first dielectric layer 7 afirst spacer structure 2 a is arranged, which on its left and right side is covered by a first and a secondconductive layer conductive layers dielectric layer 7 and may further be connected to contact pads (not explicitly shown inFIG. 5 ). Asecond spacer structure 2 b is formed over thefirst spacer structure 2 a and partly covers the firstconductive layer 3 a. Thesecond spacer structure 2 b itself is covered by the secondconductive layer 3 b. Athird spacer structure 2 c is arranged over the firstconductive layer 3 a. Thethird spacer structure 2 c is covered by a third conductive layer 3 c. On top of thespacer structures conductive layers 3 b and 3 c may comprise or generate passive components. One specific example is an inductor implemented by one or more windings of a coil. InFIG. 5 , the upper portion ofconductive layer 3 b and conductive layer 3 c represent windings of a coil andconductive layer 3 a and the lower portion ofconductive layer 3 b represent terminals of the coil. These passive components may be contacted by external contact elements, for example, thecontact element 10 shown inFIG. 4 , thereby providing an electrical connection between the passive component and a possible external application. - Due to the formation of more than one spacer structure, the resulting overall spacer structure (i.e., the sum of the three
spacer structures FIG. 5 may also be realized by a vertical splitting of or trench generation in a single spacer structure. Due to the usage of multiple spacer structures and multiple conductive layers, themodule 500 provides a local screening and the possibility of multilayer redistribution. -
FIG. 6 shows a sectional side view of asixth module 600 representing a fifth embodiment, in which the internal structure of thesemiconductor chip 1 is not explicitly shown. In contrast to themodules semiconductor chip 1 comprised inmodule 600 is embedded in amold compound 11. The embedding was performed in such a way that the surface of thesemiconductor chip 1 over which the firstdielectric layer 7 and theconductive layer 3 are arranged, is not covered by themold compound 11. The common overall surface of thesemiconductor chip 1 and themold compound 11 forms a common plane, on which thedielectric layer 7 is deposited. Themold compound 11 may be made of various materials like plastic materials and may have arbitrary geometric forms, particularly the form of a disc. - Due to the application of the
mold compound 11, the first and seconddielectric layers conductive layer 3 can be extended beyond the surface of thesemiconductor chip 1. Therefore, thecontact elements 8 need not to be arranged directly over thesemiconductor chip 1, but may extend over a larger area. Due to themold compound 11 enlarging the surface area, thecontact elements 8 may be arranged at a greater distance between each other in comparison to thecontact elements 8 comprised in themodules FIG. 2 andFIG. 4 . Further, a larger amount ofcontact elements 8 may be provided on the common overall surface of thesemiconductor chip 1 and themold compound 11. Thespacer structure 2 again deflects theconductive layer 3 away from thesemiconductor chip 1. Note that thespacer structure 2 needs not necessarily be arranged directly over thesemiconductor chip 1. It may also be arranged partly or completely over themold compound 11, i.e., beyond the outline of thesemiconductor chip 1. - The embedding of the
semiconductor chip 1 in themold compound 11 may be realized by a form pressing process. During this process at least twosemiconductor chips 1 are placed on an adhesive layer with their active surface (i.e., the surface comprising the contact pads 6) face-down. In a next step, the adhesive layer together with the at least twosemiconductor chips 1 is placed on the flat bottom of a mold element. The mold element is open on its top side and bounded by a round boundary, which may be of wafer size. Afterwards, theviscous mold compound 11 is poured over the adhesive layer and the at least twosemiconductor chips 1. A die element (preferably of the same size as the mold element) is then pressed onto the stillviscous mold compound 11, such that the same is laterally distributed over the at least twosemiconductor chips 1 and the adhesive layer. This step is continued until both of them are covered and the whole mold element is filled with themold compound 11. After a hardening of themold compound 11, the generated molded part (“big module”) comprising the at least twosemiconductor chips 1 is taken out of the mold element and the adhesive layer is removed. Note that the thickness of themodule 600 can be controlled by simply choosing the amount of mold compound poured into the mold element. Typical values for the thickness of a module shown inFIG. 6 lie in the range of about 400 μm to about 1000 μm. - Next steps in the production of the
module 600 are (amongst possible other steps): depositing the firstdielectric layer 7, depositing theconductive layer 3, forming thespacer structure 2 and depositing thesecond dielectric layer 9. The chronology and properties of these further steps have been described above. In a last step, the big module comprising the at least twosemiconductor chips 1 can be diced into multiple modules containing one ormore semiconductor chips 1. -
FIG. 7 is a top plan view of themodule 600. Accordingly, the foregoingFIG. 6 represents a sectional side view ofFIG. 7 along the line A-A′. Themodule 600 illustrates only one critical region covered by onespacer structure 2. Note, however, that multiple critical regions and multiple spacer structures are possible.FIG. 7 further shows someadditional contact elements 8, which are not visible inFIG. 6 . - While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is, therefore, intended that the appended claims encompass any such modifications or embodiments.
Claims (40)
1. A module comprising:
a semiconductor chip;
a conductive layer arranged over the semiconductor chip; and
a spacer structure arranged to deflect the conductive layer away from the semiconductor chip, wherein the conductive layer comprises one or more conductive lines routed above the spacer structure, wherein the one or more conductive lines are deflected away from the semiconductor chip and deflected back to the semiconductor chip by the spacer structure.
2. The module according to claim 1 , wherein the semiconductor chip comprises an integrated circuit, wherein the conductive layer is electrically coupled to the integrated circuit.
3. The module according to claim 1 , wherein the module comprises a first dielectric layer between the semiconductor chip and the conductive layer.
4. The module according to claim 3 , wherein the spacer structure is arranged between the semiconductor chip and the first dielectric layer.
5. The module according to claim 3 , wherein the spacer structure is arranged between the first dielectric layer and the conductive layer.
6. The module according to claim 1 , wherein the spacer structure comprises a dielectric material having a dielectric constant of less than about 2.5.
7. The module according to claim 1 , wherein a height of the spacer structure is at least 12 μm, wherein a maximum lateral dimension of the spacer structure is equal to or smaller than about 300 μm, wherein the conductive layer is deflected away from the semiconductor chip at an angle less than about 70 degrees.
8. The module according to claim 1 , wherein the conductive layer comprises one or more conductive lines routed above the spacer structure.
9. The module according to claim 1 , wherein the conductive layer comprises a passive component arranged above the spacer structure.
10. The module according to claim 1 , wherein the semiconductor chip comprises a functional area operating at radio frequency, wherein the spacer structure is arranged above the functional area.
11. The module according to claim 1 , wherein the spacer structure is made of a printable material, in particular epoxy resin or silicone.
12. The module according to claim 1 , wherein the spacer structure is made of a photoresist material.
13. The module according to claim 1 , wherein the conductive layer comprises conductive lines linearly extending over the spacer structure in a direction towards the center of the semiconductor chip.
14. The module according to claim 1 , further comprising a mold compound laterally adjoining to the semiconductor chip.
15. The module according to claim 14 , wherein the conductive layer extends above the semiconductor chip and above the mold compound.
16. A module comprising:
a semiconductor chip;
a conductive layer arranged over the semiconductor chip; and
a spacer structure arranged to deflect the conductive layer away from the semiconductor chip, wherein the spacer structure is configured to have a top surface defined by areas of at least two different heights.
17. A method comprising:
forming a spacer structure arranged to deflect a conductive layer away from a semiconductor chip;
forming the conductive layer over the semiconductor chip, the conductive layer comprising a first and a second conductive line, wherein at least a portion of the first conductive line is formed over the spacer structure, and wherein all portions of the second conductive line are formed below a top surface of the spacer structure, wherein the spacer structure is formed over a functional area of the semiconductor chip operating at radio frequency, wherein the conductive layer comprises a capacitor formed above the spacer structure;
forming an external contact on the second conductive line; and
forming a first dielectric layer on the conductive layer, the first dielectric layer insulating the first conductive line so as to prevent any coupling of the first conductive line with a contact element over the spacer structure.
18. The method according to claim 17 , wherein a height of the spacer structure is at least 12 μm.
19. The method according to claim 17 , wherein the spacer structure comprises a dielectric material having a dielectric constant of less than about 2.5.
20. The method according to claim 17 , wherein a maximum lateral dimension of the spacer structure is equal to or smaller than about 300 μm.
21. The method according to claim 17 , wherein the conductive layer is deflected away from the semiconductor chip at an angle less than about 70 degrees.
22. The method according to claim 17 , further comprising depositing a second dielectric layer over the semiconductor chip before forming the conductive layer.
23. The method according to claim 22 , wherein the steps of forming the spacer structure, and forming the second dielectric layer are performed on a wafer, the method further comprising:
separating the wafer into chips;
arranging the chips on a carrier in a spaced-apart relationship;
covering the chips with a mold compound;
separating the mold compound with embedded chips on the carrier; and
thereafter, forming the conductive layer.
24. The method according to claim 23 , wherein forming the conductive layer comprises:
depositing a metal layer; and
structuring the metal layer by a photolithographic process.
25. The method according to claim 22 , wherein the forming of the spacer structure is performed before the deposition of the second dielectric layer.
26. The method according to claim 22 , wherein the forming of the spacer structure is performed after the deposition of the second dielectric layer and before the formation of the conductive layer.
27. The method according to claim 17 , wherein forming the spacer structure comprises:
depositing a spacer dielectric layer; and
structuring the spacer dielectric layer to generate the spacer structure.
28. The method according to claim 27 , wherein structuring is accomplished by a photolithographic structuring process.
29. The method according to claim 17 , wherein forming the spacer structure comprises depositing the spacer structure by a printing process.
30. The method according to claim 29 , wherein the printing process comprises a stencil print process or a screen print process.
31. The method according to claim 29 , wherein the printing process comprises an ink jet print process.
32. The method according to claim 17 , further comprising structuring the conductive layer to form one or more conductive lines or a resistor or a capacitor or an inductor above the spacer structure.
33. The method according to claim 17 , wherein all steps are performed on wafer level.
34. A method comprising:
providing a semiconductor chip;
covering the semiconductor chip with a mold compound;
forming a spacer structure above the semiconductor chip, wherein the spacer structure is formed over a functional area of the semiconductor chip operating at radio frequency; and
forming a conductive layer that extends over an area above the spacer structure and above surroundings of the spacer structure.
35. The method according to claim 34 , wherein the conductive layer comprises a first and a second conductive line, wherein at least a portion of the first conductive line is formed over the spacer structure, and wherein all portions of the second conductive line are formed below a top surface of the spacer structure, the method further comprising
forming a first dielectric layer on the conductive layer, the first dielectric layer insulating the first conductive line so as to prevent any coupling of the first conductive line with a contact element over the spacer structure.
36. The method according to claim 35 , further comprising forming an external contact on the second conductive line.
37. The method according to claim 34 , wherein the conductive layer comprises a capacitor formed above the spacer structure.
38. A method comprising:
forming a first dielectric layer over a semiconductor chip;
forming a spacer structure over a portion of the semiconductor chip, the portion of the semiconductor chip comprising functional areas working at radio frequencies;
forming a conductive layer over the semiconductor chip, the conductive layer comprising a first and a second conductive line, wherein at least a portion of the first conductive line is formed over the spacer structure and the second conductive line is formed adjacent the spacer structure, and wherein all portions of the second conductive line are below a top surface of the spacer structure;
forming a second dielectric layer on the conductive layer, the second dielectric layer completely covering an entire top surface of the first conductive line so as to prevent any coupling of the first conductive line with a contact element over the spacer structure; and
forming an external contact contacting the second conductive line through an opening in the second dielectric layer.
39. The method according to claim 38 , wherein the first conductive line comprises at least a portion of a capacitor.
40. The method according to claim 38 , wherein the first conductive line comprises at least a portion of an inductor.
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DE102007014363A1 (en) | 2008-10-02 |
US20080224302A1 (en) | 2008-09-18 |
DE102007014363B4 (en) | 2012-03-15 |
US9219034B2 (en) | 2015-12-22 |
US8178965B2 (en) | 2012-05-15 |
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