US20120226835A1 - PCI Express to PCI Express based low latency interconnect scheme for clustering systems - Google Patents
PCI Express to PCI Express based low latency interconnect scheme for clustering systems Download PDFInfo
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- US20120226835A1 US20120226835A1 US13/441,883 US201213441883A US2012226835A1 US 20120226835 A1 US20120226835 A1 US 20120226835A1 US 201213441883 A US201213441883 A US 201213441883A US 2012226835 A1 US2012226835 A1 US 2012226835A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/40—Constructional details, e.g. power supply, mechanical construction or backplane
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
Definitions
- This invention relates to cluster interconnect architecture for high-speed and low latency information and data transfer between the systems in the configuration
- Ethernet connection allowing transport speeds from 10 MB to as high as 10 GB/sec.
- TCP/IP protocols used with Ethernet have high over head with inherent latency that make it unsuitable for some distributed applications. Effort is under way in different areas of data transport to reduce the latency of the interconnect as this is a limitation on growth of the distributed computing power.
- PCIE PCI Express
- PCIE PCI Express
- PCIE PCI Express
- the typical PCIE provides 2.5 GB transfer rate per link (this may change as the standard and data rates change). Since the PCIE standard is starting become firm and used within the systems, what is disclosed is the use of PCIE standard based peripheral as an interconnect between individual stand-alone systems, typically through an interconnect module to PCIE based peripheral connected directly using data links, as an interconnect between stand-alone systems, typically through an interconnect module or a network switch (switch).
- This interconnect scheme by using only PCIE based protocols for data transfer over direct physical connection links between the PCIE based Peripheral devices (see FIG.
- the PCIE standard based peripheral at a peripheral endpoint of the system by directly connecting using PCIE protocol based data links to the PCIE standard based peripheral at the switch, provides for increase in the number of links per connection as band width needs increase and thereby allow scaling of the band width available within any single interconnect or the system of interconnects.
- FIG. 1 Typical Interconnected (multi-system) cluster (shown with eight systems connected in a star architecture using direct connected data links between PCIE standard based peripheral to PCIE standard based peripheral)
- FIG. 2 A cluster using multiple interconnect modules or switches to interconnect smaller clusters.
- PCI Express is a Bus or I/O interconnect standard for use inside the computer or embedded system enabling faster data transfers to and from peripheral devices.
- the standard is still evolving but has achieved a degree of stability such that other applications can be implemented using PCIE as basis.
- a PCIE based interconnect scheme to enable switching and inter-connection between external systems, such that the scalability can be applied to enable data transport between connected systems to form a cluster of systems is proposed. These connected systems can be any computing or embedded system.
- the scalability of the interconnect will allow the cluster to grow the bandwidth between the systems as they become necessary without changing to a different connection architecture.
- FIG. 1 is a typical cluster interconnect.
- the Multi-system cluster shown consist of eight units or systems ⁇ ( 1 ) to ( 8 ) ⁇ that are to be interconnected.
- Each system has a PCI express (PCIE) based peripheral module ⁇ ( 1 a ) to ( 8 a ) ⁇ as an IO module, at the interconnect port, with n-links built into or attached to the system.
- PCIE PCI express
- ( 9 ) is an interconnect module or a switch sub-system, which has number of PCIE based interconnect modules equal to or more than the number of systems to be interconnected, in this case of FIG. 1 this number being eight ⁇ ( 1 b ) to ( 8 b ) ⁇ , that can be interconnected for data transfer through the switch.
- a software based control input is provided to configure and/or control the operation of the switch.
- Link connections ⁇ ( 1 L) to ( 8 L) ⁇ attach the PCIE based peripheral modules on the respective systems to those on the switch with n links.
- the value of n can vary depending on the connect band width required by the system.
- the control is used to establish an internal link between PCIE based peripheral modules 1 b and 5 b inside the switch.
- the hand shake is established between outbound based PCIE based peripheral module (PCIE module) 1 a and inbound PCIE module 1 b and outbound PCIE module 5 a and inbound PCIE module 5 b .
- PCIE module PCIE based peripheral module
- This provides a through connection between the PCI modules 1 a to 5 b through the switch allowing data transfer.
- Data can then be transferred at speed between the modules and hence between systems.
- data can also be transferred and queued in storage implemented in the switch and then when links are free transferred out to the right systems at speed.
- Multiple systems can be interconnected at one time to form a multi-system that allow data and information transfer and sharing through the switch. It is also possible to connect smaller clusters together to take advantage of the growth in system volume by using an available connection scheme that interconnects the switches that form a node of the cluster.
- connections can grow by increasing the number of links connecting the PCIE modules between the systems in the cluster and the switch without completely changing the architecture of the interconnect. This scalability is of great importance in retaining flexibility for growth and scaling of the cluster.
- the system may consist of peripheral devices, storage devices and processors and any other communication devices.
- the interconnect is agnostic to the type of device as long as they have a PCIE module at the port to enable the connection to the switch. This feature will reduce the cost of expanding the system by changing the switch interconnect density alone for growth of the multi-system.
- PCIE is currently being standardized and that will enable the use of the existing PCIE modules to be used from different vendors to reduce the over all cost of the system.
- a standardized module in the system as well as the switch will allow the cost of software development to be reduced and in the long run use available software to configure and run the systems.
- System ( 1 ) has a PCIE module ( 1 a ) at the interconnect port and that is connected by the connection link or data-link or link ( 1 L) to a PCIE module ( 1 b ) at the IO port of the switch ( 9 ).
- System ( 5 ) is similarly connected to the switch trough the PCIE module ( 5 a ) at its interconnect port to the PCIE module ( 5 b ) at the switch ( 9 ) IO port by link ( 5 L).
- Each PCIE module operates for transfer of data to and from it by standard PCI Express protocols, provided by the configuration software loaded into the PCIE modules and switch.
- the switch operates by the software control and configuration loaded in through the software configuration input.
- FIG. 2 is that of a multi-switch cluster. As the need to interconnect larger number of systems increase, it will be optimum to interconnect multiple switches of the clusters to form a new larger cluster. Such a connection is shown in FIG. 2 .
- the shown connection is for two smaller clusters ( 12 - 1 and 12 - 2 ) interconnected using PCIE modules that can be connected together using any low latency switch to switch connection ( 11 - 10 and 11 - 2 ), connected using interconnect links ( 11 L) to provide sufficient band width for the connection.
- the switch to switch connection transmits and receives data and information using any suitable protocol and the switches provide the interconnection internally through the software configuration loaded into them.
- the disclosed interconnect scheme provides advantages for low latency multi-system cluster growth that are not available from any other source.
Abstract
PCI Express is a Bus or I/O interconnect standard for use inside the computer or embedded system enabling faster data transfers to and from peripheral devices. The standard is still evolving but has achieved a degree of stability such that other applications can be implemented using PCIE as basis. A PCIE based interconnect scheme to enable switching and inter-connection between external systems, such that the scalability can be applied to enable data transport between connected systems to form a cluster of systems is proposed. These connected systems can be any computing or embedded system. The scalability of the interconnect will allow the cluster to grow the bandwidth between the systems as they become necessary without changing to a different connection architecture.
Description
- This application is a continuation of Ser. No. 11/242,463 filed on Oct. 4, 2005 by the same inventor.
- This invention relates to cluster interconnect architecture for high-speed and low latency information and data transfer between the systems in the configuration
- The need for high speed and low latency cluster interconnect scheme for data and information transport between systems have been recognized as one needing attention in recent times. The growth of interconnected and distributed processing schemes have made it essential that high speed interconnect schemes be defined and established to provide the speed up the processing and data sharing between these systems.
- There are interconnect schemes that allow data transfer at high speeds, the most common and fast one existing today is the Ethernet connection allowing transport speeds from 10 MB to as high as 10 GB/sec. TCP/IP protocols used with Ethernet have high over head with inherent latency that make it unsuitable for some distributed applications. Effort is under way in different areas of data transport to reduce the latency of the interconnect as this is a limitation on growth of the distributed computing power.
- PCI Express (PCIE) is an emerging I/O interconnect standard for use inside computers, or embedded systems that allow serial high speed data transfer to and from peripheral devices. The typical PCIE provides 2.5 GB transfer rate per link (this may change as the standard and data rates change). Since the PCIE standard is starting become firm and used within the systems, what is disclosed is the use of PCIE standard based peripheral as an interconnect between individual stand-alone systems, typically through an interconnect module to PCIE based peripheral connected directly using data links, as an interconnect between stand-alone systems, typically through an interconnect module or a network switch (switch). This interconnect scheme by using only PCIE based protocols for data transfer over direct physical connection links between the PCIE based Peripheral devices (see
FIG. 1 ), without any intermediate conversion of transmitted data stream to other data transmission protocols or encapsulation of the transmitted data stream within other data transmission protocols, reduces the latencies of communication in a cluster. The PCIE standard based peripheral at a peripheral endpoint of the system, by directly connecting using PCIE protocol based data links to the PCIE standard based peripheral at the switch, provides for increase in the number of links per connection as band width needs increase and thereby allow scaling of the band width available within any single interconnect or the system of interconnects. This will allow the interconnect architecture to remain constant as the interconnect band width need goes from 2.5 GB with a X1 link (single data link) to much higher values of 10 GB with a X4 link (4 data links), 40 GB with a X16 link (16 data links) or a 80 GB with a X32 link (32 data links) and so on providing for easy scaling of the multi-system cluster. -
-
- 1. Reduced Latency of Data transfer as conversion from PCIE to other protocols like ethernet is avoided during transfer.
- 2. The number of links per connection can scale from X1 to larger numbers X32 or even X64 possible based on the bandwidth needed.
- 3. Minimum change in interconnect architecture is needed with increased bandwidth, enabling easy scaling with need.
- 4. Standardization of the PCIE based peripheral will make components easily available from multiple vendors, making the implementation of interconnect scheme easier and cheaper.
- 5. The PCIE based peripheral to PCIE based peripheral links in connections allow ease of software control and provide reliable bandwidth.
- FIG. 1—Typical Interconnected (multi-system) cluster (shown with eight systems connected in a star architecture using direct connected data links between PCIE standard based peripheral to PCIE standard based peripheral)
- FIG. 2—A cluster using multiple interconnect modules or switches to interconnect smaller clusters.
-
- (1) to (8): Number of Systems interconnected in
FIG. 1 - (9): Network Switch (switch) sub-system.
- (10): Software configuration and control input for the switch.
- (1 a) to (8 a): PCI Express based peripheral module (PCIE Modules) attached to systems.
- (1 b) to (8 b): PCI Express based peripheral modules (PCIE Modules) at switch.
- (1L) to (8L): PCIE based peripheral module to PCIE based peripheral module connections having n-links (n-data links).
-
- (12-1) and (12-2): clusters
- (9-1) and (9-2): interconnect modules or switch sub-systems.
- (10-1) and (10-2): Software configuration inputs
- (11-1) and (11-2): Switch to switch interconnect module in the cluster
- (11L): Switch to switch interconnection
- PCI Express is a Bus or I/O interconnect standard for use inside the computer or embedded system enabling faster data transfers to and from peripheral devices. The standard is still evolving but has achieved a degree of stability such that other applications can be implemented using PCIE as basis. A PCIE based interconnect scheme to enable switching and inter-connection between external systems, such that the scalability can be applied to enable data transport between connected systems to form a cluster of systems is proposed. These connected systems can be any computing or embedded system. The scalability of the interconnect will allow the cluster to grow the bandwidth between the systems as they become necessary without changing to a different connection architecture.
FIG. 1 is a typical cluster interconnect. The Multi-system cluster shown consist of eight units or systems {(1) to (8)} that are to be interconnected. Each system has a PCI express (PCIE) based peripheral module {(1 a) to (8 a)} as an IO module, at the interconnect port, with n-links built into or attached to the system. (9) is an interconnect module or a switch sub-system, which has number of PCIE based interconnect modules equal to or more than the number of systems to be interconnected, in this case ofFIG. 1 this number being eight {(1 b) to (8 b)}, that can be interconnected for data transfer through the switch. A software based control input is provided to configure and/or control the operation of the switch. Link connections {(1L) to (8L)} attach the PCIE based peripheral modules on the respective systems to those on the switch with n links. The value of n can vary depending on the connect band width required by the system. - When data has to be transferred between
say system 1 andsystem 5, in the simple case, the control is used to establish an internal link between PCIE basedperipheral modules 1 b and 5 b inside the switch. The hand shake is established between outbound based PCIE based peripheral module (PCIE module) 1 a andinbound PCIE module 1 b and outbound PCIE module 5 a and inbound PCIE module 5 b. This provides a through connection between the PCI modules 1 a to 5 b through the switch allowing data transfer. Data can then be transferred at speed between the modules and hence between systems. In more complex cases data can also be transferred and queued in storage implemented in the switch and then when links are free transferred out to the right systems at speed. - Multiple systems can be interconnected at one time to form a multi-system that allow data and information transfer and sharing through the switch. It is also possible to connect smaller clusters together to take advantage of the growth in system volume by using an available connection scheme that interconnects the switches that form a node of the cluster.
- If need for higher bandwidth and low latency data transfers between systems increase, the connections can grow by increasing the number of links connecting the PCIE modules between the systems in the cluster and the switch without completely changing the architecture of the interconnect. This scalability is of great importance in retaining flexibility for growth and scaling of the cluster.
- It should be understood that the system may consist of peripheral devices, storage devices and processors and any other communication devices. The interconnect is agnostic to the type of device as long as they have a PCIE module at the port to enable the connection to the switch. This feature will reduce the cost of expanding the system by changing the switch interconnect density alone for growth of the multi-system.
- PCIE is currently being standardized and that will enable the use of the existing PCIE modules to be used from different vendors to reduce the over all cost of the system. In addition using a standardized module in the system as well as the switch will allow the cost of software development to be reduced and in the long run use available software to configure and run the systems.
- As the expansion of the cluster in terms of number of systems, connected, bandwidth usage and control will all be cost effective, it is expected the over all system cost can be reduced and over all performance improved by standardized PCIE module use with standardized software control.
- Typical connect operation may be explained with reference to two of the systems, example system (1) and system (5). System (1) has a PCIE module (1 a) at the interconnect port and that is connected by the connection link or data-link or link (1L) to a PCIE module (1 b) at the IO port of the switch (9). System (5) is similarly connected to the switch trough the PCIE module (5 a) at its interconnect port to the PCIE module (5 b) at the switch (9) IO port by link (5L). Each PCIE module operates for transfer of data to and from it by standard PCI Express protocols, provided by the configuration software loaded into the PCIE modules and switch. The switch operates by the software control and configuration loaded in through the software configuration input.
-
FIG. 2 is that of a multi-switch cluster. As the need to interconnect larger number of systems increase, it will be optimum to interconnect multiple switches of the clusters to form a new larger cluster. Such a connection is shown inFIG. 2 . The shown connection is for two smaller clusters (12-1 and 12-2) interconnected using PCIE modules that can be connected together using any low latency switch to switch connection (11-10 and 11-2), connected using interconnect links (11L) to provide sufficient band width for the connection. The switch to switch connection transmits and receives data and information using any suitable protocol and the switches provide the interconnection internally through the software configuration loaded into them. -
-
- 1. Provide a low latency interconnect for the cluster.
- 2. Use of PCIExpress based protocols for data and information transfer within the cluster.
- 3. Ease of growth in bandwidth as the system requirements increase by increasing the number of links within the cluster.
- 4. Standardized PCIE component use in the cluster reduce initial cost.
- 5. Lower cost of growth due to standardization of hardware and software.
- 6. Path of expansion from a small cluster to larger clusters as need grows.
- 7. Future proofed system architecture.
- In fact the disclosed interconnect scheme provides advantages for low latency multi-system cluster growth that are not available from any other source.
Claims (8)
1. An interconnected cluster, the cluster comprising;
a PCIE Express enabled interconnect module comprise a plurality of ports, each said port having a PCI Express based peripheral module enabled for interconnection;
a switching mechanism in said interconnect module enabled to transfer data between a first of said plurality of ports on said interconnect module and any of a rest of said plurality of ports on said interconnect module;
a plurality of devices and systems that are PCI Express enabled; each said plurality of devices and systems comprise at least a system interconnect port comprise a PCIE express peripheral module enabled for interconnection;
said at least a system interconnect port of each said plurality of devices and systems connect to one of said plurality of ports of said interconnect module using at least a PCI Express link;
a data transfer mechanism to transfer data to and from each of said plurality of devices and systems to the one of said plurality of ports of said interconnect module connected to it, wherein said data transfer is done using a PCI-Express protocol;
wherein said data transfer mechanisms and said switching mechanisms together allow data received from a first of said plurality of devices and systems to be sent to any of a rest of said plurality of said plurality of devices and systems; and
wherein said data transfer mechanism and said switching mechanism together further allows data received from any of said rest of said plurality of devices and systems to be sent to said first of said plurality of devices and systems;
there by enabling the cluster with interconnection and communication capability between interconnected devices and systems using only PCI Express protocol over PCI Express links.
2. The interconnected cluster in claim 1 , where in, each said plurality of devices and systems is connected to said interconnect module by one or more PCI Express data links connected between said PCI Express peripheral module at said system interconnect port and said PCI Express peripheral module at said port of said interconnect module.
3. The interconnected cluster in claim 1 , where in, the connection between the PCI Express peripheral module at the interconnect port of each of the devices and systems and the connected PCI Express peripheral module at the port of the interconnect module can be by using multiple data links as the bandwidth requirements of the interconnect demand.
4. The interconnected cluster in claim 1 , where in, the interconnect module is a network switch.
5. The interconnected cluster in claim 1 , where in, the switching between the ports inside the interconnect module is controlled by the configuration software loaded into the interconnect module.
6. An interconnected cluster system comprising of two or more smaller clusters to form a larger cluster, each of said smaller clusters having multiple devices and systems and an interconnect module; said interconnected cluster system having suitable low latency interconnection between said interconnect modules of the small clusters to allow the overall system growth to the interconnected cluster system.
7. The interconnected cluster system of claim 6 , comprising of two or more smaller clusters having multiple devices and systems and the interconnect module each where in, the interconnection between interconnect modules is scalable.
8. The interconnected cluster system of claim 6 , comprising of two or more clusters each having multiple devices and systems and an interconnect module each where in, the cluster growth can take place without changing the architecture of the individual small clusters.
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US13/441,883 US20120226835A1 (en) | 2005-10-04 | 2012-04-08 | PCI Express to PCI Express based low latency interconnect scheme for clustering systems |
US14/588,937 US9519608B2 (en) | 2005-10-04 | 2015-01-03 | PCI express to PCI express based low latency interconnect scheme for clustering systems |
US15/175,800 US11194754B2 (en) | 2005-10-04 | 2016-06-07 | PCI express to PCI express based low latency interconnect scheme for clustering systems |
US17/523,878 US20220066976A1 (en) | 2005-10-04 | 2021-11-10 | PCI Express to PCI Express based low latency interconnect scheme for clustering systems |
US17/525,837 US20220100694A1 (en) | 2005-10-04 | 2021-11-12 | PCI Express to PCI Express based low latency interconnect scheme for clustering systems |
US17/858,083 US20220374388A1 (en) | 2005-10-04 | 2022-07-06 | PCI Express to PCI Express based low latency interconnect scheme for clustering systems |
US18/205,515 US20230315674A1 (en) | 2005-10-04 | 2023-06-03 | PCI Express to PCI Express based Low Latency Interconnect Scheme for Clustering Systems |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2014133527A1 (en) * | 2013-02-28 | 2014-09-04 | Intel Corporation | Leveraging an enumeration and/or configuration mechanism of one interconnect protocol for a different interconnect protocol |
US9235346B2 (en) | 2012-05-04 | 2016-01-12 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Dynamic map pre-fetching for improved sequential reads of a solid-state media |
US9337865B2 (en) | 2012-05-04 | 2016-05-10 | Seagate Technology Llc | Log-likelihood ratio (LLR) dampening in low-density parity-check (LDPC) decoders |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7073158B2 (en) * | 2002-05-17 | 2006-07-04 | Pixel Velocity, Inc. | Automated system for designing and developing field programmable gate arrays |
US8189603B2 (en) * | 2005-10-04 | 2012-05-29 | Mammen Thomas | PCI express to PCI express based low latency interconnect scheme for clustering systems |
CN100581172C (en) * | 2006-04-19 | 2010-01-13 | 杭州华三通信技术有限公司 | Method for accessing object magnetic dish and system for extensing disk content |
US20080151049A1 (en) * | 2006-12-14 | 2008-06-26 | Mccubbrey David L | Gaming surveillance system and method of extracting metadata from multiple synchronized cameras |
GB2459602B (en) * | 2007-02-21 | 2011-09-21 | Pixel Velocity Inc | Scalable system for wide area surveillance |
US7562176B2 (en) * | 2007-02-28 | 2009-07-14 | Lsi Corporation | Apparatus and methods for clustering multiple independent PCI express hierarchies |
CN101763221B (en) | 2008-12-24 | 2013-01-30 | 成都市华为赛门铁克科技有限公司 | Storing method, storing system and controller |
US20110115909A1 (en) * | 2009-11-13 | 2011-05-19 | Sternberg Stanley R | Method for tracking an object through an environment across multiple cameras |
US9432298B1 (en) | 2011-12-09 | 2016-08-30 | P4tents1, LLC | System, method, and computer program product for improving memory systems |
CN103222286B (en) | 2011-11-18 | 2014-07-09 | 华为技术有限公司 | Route switching device, network switching system and route switching method |
CN102870381B (en) * | 2012-06-29 | 2015-09-09 | 华为技术有限公司 | A kind of PCIE switching system, device and switching method |
US10380041B2 (en) | 2012-08-23 | 2019-08-13 | Dell Products, Lp | Fabric independent PCIe cluster manager |
US9086919B2 (en) | 2012-08-23 | 2015-07-21 | Dell Products, Lp | Fabric independent PCIe cluster manager |
US9794195B1 (en) * | 2015-06-26 | 2017-10-17 | Amazon Technologies, Inc. | Communication device with receded ports |
US10592291B2 (en) | 2016-08-12 | 2020-03-17 | Liqid Inc. | Disaggregated fabric-switched computing platform |
US11294839B2 (en) | 2016-08-12 | 2022-04-05 | Liqid Inc. | Emulated telemetry interfaces for fabric-coupled computing units |
US11880326B2 (en) | 2016-08-12 | 2024-01-23 | Liqid Inc. | Emulated telemetry interfaces for computing units |
US10747701B2 (en) | 2017-03-07 | 2020-08-18 | Liqid Inc. | Rackmount switch devices for peripheral component interconnect express (PCIe) systems |
CN108959131B (en) * | 2018-06-25 | 2022-05-31 | 联想(北京)有限公司 | Method for connecting electronic equipment and external equipment and electronic equipment |
US11102149B2 (en) * | 2019-12-20 | 2021-08-24 | Hewlett Packard Enterprise Development Lp | Modular, flexibly connected switch-port input-output cards |
Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020111753A1 (en) * | 2000-12-11 | 2002-08-15 | Andrew Moch | Measurement system having an improved scan list configuration |
US20040039986A1 (en) * | 2002-08-23 | 2004-02-26 | Solomon Gary A. | Store and forward switch device, system and method |
US20050160212A1 (en) * | 2004-01-15 | 2005-07-21 | Ati Technologies, Inc. | Method and device for transmitting data |
US20050270988A1 (en) * | 2004-06-04 | 2005-12-08 | Dehaemer Eric | Mechanism of dynamic upstream port selection in a PCI express switch |
US20060004837A1 (en) * | 2004-06-30 | 2006-01-05 | Genovker Victoria V | Advanced switching peer-to-peer protocol |
US20060050722A1 (en) * | 2004-09-03 | 2006-03-09 | James Bury | Interface circuitry for a receive ring buffer of an as fabric end node device |
US20060083257A1 (en) * | 2004-10-20 | 2006-04-20 | L-3 Communications Security & Detection Systems | Inspection system with data acquisition system interconnect protocol |
US7062581B2 (en) * | 2001-10-17 | 2006-06-13 | Stargen Technologies, Inc. | Interconnection fabric enumeration |
US20060126612A1 (en) * | 2004-11-23 | 2006-06-15 | Sandy Douglas L | Method of transporting a PCI express packet over an IP packet network |
US20060209863A1 (en) * | 2005-02-25 | 2006-09-21 | International Business Machines Corporation | Virtualized fibre channel adapter for a multi-processor data processing system |
US20060259656A1 (en) * | 2005-05-10 | 2006-11-16 | Sullivan Mark J | Simulating multiple virtual channels in switched fabric networks |
US20070019637A1 (en) * | 2005-07-07 | 2007-01-25 | Boyd William T | Mechanism to virtualize all address spaces in shared I/O fabrics |
US8189603B2 (en) * | 2005-10-04 | 2012-05-29 | Mammen Thomas | PCI express to PCI express based low latency interconnect scheme for clustering systems |
US8291145B2 (en) * | 2004-08-10 | 2012-10-16 | Hewlett-Packard Development Company, L.P. | Method and apparatus for setting a primary port on a PCI bridge |
Family Cites Families (61)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FI97927C (en) * | 1995-05-09 | 1997-03-10 | Nokia Telecommunications Oy | Non-transparent data transmission in a digital communication system |
JP3614236B2 (en) * | 1996-03-22 | 2005-01-26 | 富士通株式会社 | Non-instantaneous expansion system for cross-connect equipment |
US5805597A (en) * | 1996-06-04 | 1998-09-08 | National Semiconductor Corporation | Method and apparatus for providing low power basic telephony type service over a twisted pair ethernet physical layer |
US5961623A (en) * | 1996-08-29 | 1999-10-05 | Apple Computer, Inc. | Method and system for avoiding starvation and deadlocks in a split-response interconnect of a computer system |
US5991305A (en) * | 1997-02-14 | 1999-11-23 | Advanced Micro Devices, Inc. | Integrated multiport switch having independently resettable management information base (MIB) |
US6260092B1 (en) * | 1998-09-24 | 2001-07-10 | Philips Semiconductors, Inc. | Point to point or ring connectable bus bridge and an interface with method for enhancing link performance in a point to point connectable bus bridge system using the fiber channel |
US6362908B1 (en) * | 1998-12-02 | 2002-03-26 | Marconi Communications, Inc. | Multi-service adaptable optical network unit |
US7457897B1 (en) | 2004-03-17 | 2008-11-25 | Suoer Talent Electronics, Inc. | PCI express-compatible controller and interface for flash memory |
US6615306B1 (en) * | 1999-11-03 | 2003-09-02 | Intel Corporation | Method and apparatus for reducing flow control and minimizing interface acquisition latency in a hub interface |
US6725388B1 (en) * | 2000-06-13 | 2004-04-20 | Intel Corporation | Method and system for performing link synchronization between two clock domains by inserting command signals into a data stream transmitted between the two clock domains |
WO2002065709A1 (en) * | 2001-02-14 | 2002-08-22 | Kawasaki Microelectronics, Inc. | Network switching device |
US7145866B1 (en) * | 2001-03-01 | 2006-12-05 | Emc Corporation | Virtual network devices |
US6914914B1 (en) * | 2001-05-22 | 2005-07-05 | Rockwell Automation Technologies, Inc. | System and method for multi-chassis configurable time synchronization |
US7151774B1 (en) * | 2001-06-13 | 2006-12-19 | Advanced Micro Devices, Inc. | Method and apparatus for trunking links having different transmission rates |
US7543100B2 (en) * | 2001-06-18 | 2009-06-02 | 3Par, Inc. | Node controller for a data storage system |
US7274702B2 (en) * | 2001-11-27 | 2007-09-25 | 4198638 Canada Inc. | Programmable interconnect system for scalable router |
US7110413B2 (en) * | 2001-12-31 | 2006-09-19 | Hewlett-Packard Development Company | Downstream broadcast PCI switch |
US7284067B2 (en) * | 2002-02-20 | 2007-10-16 | Hewlett-Packard Development Company, L.P. | Method for integrated load balancing among peer servers |
US6625169B1 (en) * | 2002-06-14 | 2003-09-23 | Telesys Technologies, Inc. | Integrated communication systems for exchanging data and information between networks |
US20040083323A1 (en) * | 2002-10-24 | 2004-04-29 | Josef Rabinovitz | Large array of SATA data device assembly for use in a peripheral storage system |
US7000037B2 (en) * | 2002-10-24 | 2006-02-14 | Josef Rabinovitz | Large array of mass data storage devices connected to a computer by a serial link |
US8346884B2 (en) | 2003-01-21 | 2013-01-01 | Nextio Inc. | Method and apparatus for a shared I/O network interface controller |
US7103064B2 (en) * | 2003-01-21 | 2006-09-05 | Nextio Inc. | Method and apparatus for shared I/O in a load/store fabric |
US8102843B2 (en) | 2003-01-21 | 2012-01-24 | Emulex Design And Manufacturing Corporation | Switching apparatus and method for providing shared I/O within a load-store fabric |
US7953074B2 (en) * | 2003-01-21 | 2011-05-31 | Emulex Design And Manufacturing Corporation | Apparatus and method for port polarity initialization in a shared I/O device |
US7099969B2 (en) | 2003-11-06 | 2006-08-29 | Dell Products L.P. | Dynamic reconfiguration of PCI Express links |
US20050125590A1 (en) | 2003-12-09 | 2005-06-09 | Li Stephen H. | PCI express switch |
US7424564B2 (en) | 2004-03-23 | 2008-09-09 | Qlogic, Corporation | PCI—express slot for coupling plural devices to a host system |
US20050240713A1 (en) | 2004-04-22 | 2005-10-27 | V-Da Technology | Flash memory device with ATA/ATAPI/SCSI or proprietary programming interface on PCI express |
US8374175B2 (en) * | 2004-04-27 | 2013-02-12 | Hewlett-Packard Development Company, L.P. | System and method for remote direct memory access over a network switch fabric |
US7058738B2 (en) * | 2004-04-28 | 2006-06-06 | Microsoft Corporation | Configurable PCI express switch which allows multiple CPUs to be connected to multiple I/O devices |
US7434107B2 (en) * | 2004-07-19 | 2008-10-07 | Dell Products L.P. | Cluster network having multiple server nodes |
US20060050693A1 (en) * | 2004-09-03 | 2006-03-09 | James Bury | Building data packets for an advanced switching fabric |
US7395363B2 (en) | 2004-09-09 | 2008-07-01 | Intel Corporation | Methods and apparatus for multiple bit rate serial communication |
US20060088046A1 (en) * | 2004-10-26 | 2006-04-27 | Wong Kar L | Queue resource sharing for an input/output controller |
US7525986B2 (en) | 2004-10-28 | 2009-04-28 | Intel Corporation | Starvation prevention scheme for a fixed priority PCI-Express arbiter with grant counters using arbitration pools |
US7350014B2 (en) * | 2004-11-05 | 2008-03-25 | Intel Corporation | Connecting peer endpoints |
US20060098659A1 (en) * | 2004-11-05 | 2006-05-11 | Silicon Graphics Inc. | Method of data packet transmission in an IP link striping protocol |
US20060114918A1 (en) * | 2004-11-09 | 2006-06-01 | Junichi Ikeda | Data transfer system, data transfer method, and image apparatus system |
TWI286693B (en) | 2004-11-12 | 2007-09-11 | Via Tech Inc | Method for dynamically adjusting the data transfer order of PCI Express root ports |
US8285907B2 (en) * | 2004-12-10 | 2012-10-09 | Intel Corporation | Packet processing in switched fabric networks |
US8706942B2 (en) * | 2004-12-29 | 2014-04-22 | Intel Corporation | Direct memory access (DMA) address translation between peer-to-peer input/output (I/O) devices |
TWI268424B (en) | 2005-03-15 | 2006-12-11 | Uli Electronics Inc | Signal transmission method between computer system and peripherals adopting PCI express bus characterizing in saving power of transmitting signals |
US20060227768A1 (en) | 2005-04-07 | 2006-10-12 | Dell Products L.P. | System and method for communicating between a computer cluster and a remote user interface |
US7643495B2 (en) * | 2005-04-18 | 2010-01-05 | Cisco Technology, Inc. | PCI express switch with encryption and queues for performance enhancement |
US7565463B2 (en) | 2005-04-22 | 2009-07-21 | Sun Microsystems, Inc. | Scalable routing and addressing |
US7480303B1 (en) * | 2005-05-16 | 2009-01-20 | Pericom Semiconductor Corp. | Pseudo-ethernet switch without ethernet media-access-controllers (MAC's) that copies ethernet context registers between PCI-express ports |
TWI273420B (en) | 2005-07-21 | 2007-02-11 | Via Tech Inc | Data processing method and system based on a serial transmission interface |
US7525957B2 (en) | 2005-09-01 | 2009-04-28 | Emulex Design & Manufacturing Corporation | Input/output router for storage networks |
JP4670676B2 (en) | 2006-02-17 | 2011-04-13 | 日本電気株式会社 | Switch and network bridge device |
US7516263B2 (en) | 2006-02-27 | 2009-04-07 | Emerson Network Power - Embedded Computing, Inc. | Re-configurable PCI-Express switching device |
US20080034147A1 (en) | 2006-08-01 | 2008-02-07 | Robert Stubbs | Method and system for transferring packets between devices connected to a PCI-Express bus |
US20080052431A1 (en) | 2006-08-22 | 2008-02-28 | Freking Ronald E | Method and Apparatus for Enabling Virtual Channels Within A Peripheral Component Interconnect (PCI) Express Bus |
US8271604B2 (en) | 2006-12-19 | 2012-09-18 | International Business Machines Corporation | Initializing shared memories for sharing endpoints across a plurality of root complexes |
US7562176B2 (en) | 2007-02-28 | 2009-07-14 | Lsi Corporation | Apparatus and methods for clustering multiple independent PCI express hierarchies |
US8595343B2 (en) | 2008-11-14 | 2013-11-26 | Dell Products, Lp | System and method for sharing storage resources |
US8335884B2 (en) | 2009-07-10 | 2012-12-18 | Brocade Communications Systems, Inc. | Multi-processor architecture implementing a serial switch and method of operating same |
US8463934B2 (en) | 2009-11-05 | 2013-06-11 | Rj Intellectual Properties, Llc | Unified system area network and switch |
US20110246686A1 (en) | 2010-04-01 | 2011-10-06 | Cavanagh Jr Edward T | Apparatus and system having pci root port and direct memory access device functionality |
US8700856B2 (en) | 2012-03-23 | 2014-04-15 | Hitachi, Ltd. | Method for accessing mirrored shared memories and storage subsystem using method for accessing mirrored shared memories |
KR102007368B1 (en) | 2012-12-17 | 2019-08-05 | 한국전자통신연구원 | PCI express switch and computer system using the same |
-
2005
- 2005-10-04 US US11/242,463 patent/US8189603B2/en active Active
-
2012
- 2012-04-08 US US13/441,883 patent/US20120226835A1/en not_active Abandoned
-
2015
- 2015-01-03 US US14/588,937 patent/US9519608B2/en active Active
-
2016
- 2016-06-07 US US15/175,800 patent/US11194754B2/en active Active
-
2021
- 2021-11-10 US US17/523,878 patent/US20220066976A1/en not_active Abandoned
- 2021-11-12 US US17/525,837 patent/US20220100694A1/en active Pending
-
2022
- 2022-07-06 US US17/858,083 patent/US20220374388A1/en not_active Abandoned
-
2023
- 2023-06-03 US US18/205,515 patent/US20230315674A1/en active Pending
Patent Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020111753A1 (en) * | 2000-12-11 | 2002-08-15 | Andrew Moch | Measurement system having an improved scan list configuration |
US7062581B2 (en) * | 2001-10-17 | 2006-06-13 | Stargen Technologies, Inc. | Interconnection fabric enumeration |
US20040039986A1 (en) * | 2002-08-23 | 2004-02-26 | Solomon Gary A. | Store and forward switch device, system and method |
US20050160212A1 (en) * | 2004-01-15 | 2005-07-21 | Ati Technologies, Inc. | Method and device for transmitting data |
US20050270988A1 (en) * | 2004-06-04 | 2005-12-08 | Dehaemer Eric | Mechanism of dynamic upstream port selection in a PCI express switch |
US20060004837A1 (en) * | 2004-06-30 | 2006-01-05 | Genovker Victoria V | Advanced switching peer-to-peer protocol |
US8291145B2 (en) * | 2004-08-10 | 2012-10-16 | Hewlett-Packard Development Company, L.P. | Method and apparatus for setting a primary port on a PCI bridge |
US20060050722A1 (en) * | 2004-09-03 | 2006-03-09 | James Bury | Interface circuitry for a receive ring buffer of an as fabric end node device |
US20060083257A1 (en) * | 2004-10-20 | 2006-04-20 | L-3 Communications Security & Detection Systems | Inspection system with data acquisition system interconnect protocol |
US20060126612A1 (en) * | 2004-11-23 | 2006-06-15 | Sandy Douglas L | Method of transporting a PCI express packet over an IP packet network |
US20060209863A1 (en) * | 2005-02-25 | 2006-09-21 | International Business Machines Corporation | Virtualized fibre channel adapter for a multi-processor data processing system |
US20060259656A1 (en) * | 2005-05-10 | 2006-11-16 | Sullivan Mark J | Simulating multiple virtual channels in switched fabric networks |
US20070019637A1 (en) * | 2005-07-07 | 2007-01-25 | Boyd William T | Mechanism to virtualize all address spaces in shared I/O fabrics |
US8189603B2 (en) * | 2005-10-04 | 2012-05-29 | Mammen Thomas | PCI express to PCI express based low latency interconnect scheme for clustering systems |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9235346B2 (en) | 2012-05-04 | 2016-01-12 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Dynamic map pre-fetching for improved sequential reads of a solid-state media |
US9337865B2 (en) | 2012-05-04 | 2016-05-10 | Seagate Technology Llc | Log-likelihood ratio (LLR) dampening in low-density parity-check (LDPC) decoders |
WO2014133527A1 (en) * | 2013-02-28 | 2014-09-04 | Intel Corporation | Leveraging an enumeration and/or configuration mechanism of one interconnect protocol for a different interconnect protocol |
KR20150103136A (en) * | 2013-02-28 | 2015-09-09 | 인텔 코포레이션 | Leveraging an enumeration and/or configuration mechanism of one interconnect protocol for a different interconnect protocol |
CN104956347A (en) * | 2013-02-28 | 2015-09-30 | 英特尔公司 | Leveraging an enumeration and/or configuration mechanism of one interconnect protocol for a different interconnect protocol |
US9405718B2 (en) | 2013-02-28 | 2016-08-02 | Intel Corporation | Leveraging an enumeration and/or configuration mechanism of one interconnect protocol for a different interconnect protocol |
KR101695712B1 (en) | 2013-02-28 | 2017-01-12 | 인텔 코포레이션 | Leveraging an enumeration and/or configuration mechanism of one interconnect protocol for a different interconnect protocol |
RU2633126C2 (en) * | 2013-02-28 | 2017-10-11 | Интел Корпорейшн | Strengthening mechanism of transfer and/or configuration of one protocol of inter-connections for another protocol of inter-connections |
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US20220066976A1 (en) | 2022-03-03 |
US8189603B2 (en) | 2012-05-29 |
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US20230315674A1 (en) | 2023-10-05 |
US20220374388A1 (en) | 2022-11-24 |
US20160378708A1 (en) | 2016-12-29 |
US20220100694A1 (en) | 2022-03-31 |
US9519608B2 (en) | 2016-12-13 |
US11194754B2 (en) | 2021-12-07 |
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