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Numéro de publicationUS20120267779 A1
Type de publicationDemande
Numéro de demandeUS 13/430,439
Date de publication25 oct. 2012
Date de dépôt26 mars 2012
Date de priorité25 avr. 2011
Autre référence de publicationCN102760712A, US20160307863
Numéro de publication13430439, 430439, US 2012/0267779 A1, US 2012/267779 A1, US 20120267779 A1, US 20120267779A1, US 2012267779 A1, US 2012267779A1, US-A1-20120267779, US-A1-2012267779, US2012/0267779A1, US2012/267779A1, US20120267779 A1, US20120267779A1, US2012267779 A1, US2012267779A1
InventeursTzu-Hung Lin, Wen-Sung Hsu, Tai-Yu Chen
Cessionnaire d'origineMediatek Inc.
Exporter la citationBiBTeX, EndNote, RefMan
Liens externes: USPTO, Cession USPTO, Espacenet
Semiconductor package
US 20120267779 A1
Résumé
The invention provides a semiconductor package. The semiconductor package includes a semiconductor die having a central area and a peripheral area surrounding the central area. A first conductive bump is disposed on the semiconductor die in the central area. A second conductive bump is disposed on the semiconductor die in the peripheral area. An area ratio of the first conductive bump to the second conductive bump from a top view is larger than 1, and less than or equal to 3.
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Revendications(18)
1. A semiconductor package, comprising:
a semiconductor die; and
a first conductive bump and a second conductive bump respectively disposed on the semiconductor die, wherein an area ratio of the first conductive bump to the second conductive bump from a top view is larger than 1, and less than or equal to 3.
2. The semiconductor package as claimed in claim 1, wherein the semiconductor die has a central area and a peripheral area surrounding the central area, and wherein the first conductive bump is disposed on the semiconductor die in the central area, and the second conductive bump is disposed on the semiconductor die in the peripheral area.
3. The semiconductor package as claimed in claim 1, wherein the semiconductor die has a central area and a peripheral area surrounding the central area, and wherein the first conductive bump is disposed on the semiconductor die in the peripheral area, and the second conductive bump is disposed on the semiconductor die in the central area.
4. The semiconductor package as claimed in claim 1, wherein the first conductive bump and the second conductive bump are alternatively disposed on the semiconductor die.
5. The semiconductor package as claimed in claim 1, wherein the first conductive bump and the second conductive bump are randomly disposed on the semiconductor die.
6. The semiconductor package as claimed in claim 1, wherein the first conductive bump is a circular shape from the top view.
7. The semiconductor package as claimed in claim 1, wherein the second conductive bump is an oblong shape from the top view.
8. The semiconductor package as claimed in claim 1, wherein the first conductive bump connects to a power pad or ground pad of the semiconductor die.
9. The semiconductor package as claimed in claim 1, wherein the second conductive bump connects to a signal pad of the semiconductor die.
10. The semiconductor package as claimed in claim 1, further comprising:
a first under bump metallurgy layer pattern disposed between the semiconductor die and the first conductive bump; and
a second under bump metallurgy layer pattern disposed between the semiconductor die and the second conductive bump.
11. The semiconductor package as claimed in claim 10, wherein the first under bump metallurgy layer pattern is a circular shape from the top view.
12. The semiconductor package as claimed in claim 10, wherein the second under bump metallurgy layer pattern is a rectangular shape from the top view.
13. The semiconductor package as claimed in claim 10, further comprising:
a first conductive pillar connecting to and between the first under bump metallurgy layer pattern and the first conductive bump; and
a second conductive pillar connecting to and between the second under bump metallurgy layer pattern and the second conductive bump.
14. The semiconductor package as claimed in claim 13, wherein the first conductive pillar is a circular shape.
15. The semiconductor package as claimed in claim 13, wherein the second conductive pillar is an oblong shape from the top view.
16. The semiconductor package as claimed in claim 13, wherein an area ratio the first conductive pillar to the second conductive pillar from a top view is larger than 1, and less than or equal to 3.
17. The semiconductor package as claimed in claim 1, further comprising a substrate having a plurality of conductive traces thereon, wherein the first conductive bump and the second conductive bump are bonded onto the conductive traces, respectively.
18. The semiconductor package as claimed in claim 1, further comprising:
a solder resistance layer disposed on the substrate, away from an overlap region between the substrate and the semiconductor die; and
an underfill material filling a gap between the substrate and the semiconductor
Description
    CROSS REFERENCE TO RELATED APPLICATIONS
  • [0001]
    This application claims the benefit of U.S. Provisional Application No. 61/498,791 filed Apr. 25, 2011, the entirety of which is incorporated by reference herein.
  • BACKGROUND OF THE INVENTION
  • [0002]
    1. Field of the Invention
  • [0003]
    The present invention relates to a semiconductor package, and in particular, to a conductive bump design for a semiconductor package.
  • [0004]
    2. Description of the Related Art
  • [0005]
    For a semiconductor chip package design, an increased amount of input/output (I/O) connections for multi-functional chips is required. The impact of this will be pressure on printed circuit board (PCB) fabricators to minimize linewidth and space or to develop direct chip attach (DCA) semiconductors. However, the increased amount of input/output connections of a multi-functional chip package may induce thermal electrical problems, for example, problems with heat dissipation, cross talk, signal propagation delay, electromagnetic interference for RF circuits, etc. The thermal electrical problems may affect the reliability and quality of products.
  • [0006]
    Thus, a novel semiconductor package with better thermal and electrical properties is desirable.
  • BRIEF SUMMARY OF INVENTION
  • [0007]
    A semiconductor package is provided. An exemplary embodiment of a semiconductor package comprises a semiconductor die having a central area and a peripheral area surrounding the central area. A first conductive bump is disposed on the semiconductor die in the central area. A second conductive bump is disposed on the semiconductor die in the peripheral area, wherein an area ratio of the first conductive bump to the second conductive bump from a top view is larger than 1, and less than or equal to 3.
  • [0008]
    A detailed description is given in the following embodiments with reference to the accompanying drawings.
  • BRIEF DESCRIPTION OF DRAWINGS
  • [0009]
    The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
  • [0010]
    FIG. 1 a shows a cross section view of one exemplary embodiment of a semiconductor package of the invention.
  • [0011]
    FIG. 1 b shows a schematic view of a layout of conductive bumps of one exemplary embodiment of a semiconductor package of the invention.
  • [0012]
    FIG. 2 a shows a cross section view of another exemplary embodiment of a semiconductor package of the invention.
  • [0013]
    FIG. 2 b shows a schematic view of a layout of conductive bumps of another exemplary embodiment of a semiconductor package of the invention.
  • [0014]
    FIG. 3 a shows a cross section view of yet another exemplary embodiment of a semiconductor package of the invention.
  • [0015]
    FIG. 3 b shows a schematic view of a layout of conductive bumps of yet another exemplary embodiment of a semiconductor package of the invention.
  • [0016]
    FIG. 4 a shows a cross section view of still yet another exemplary embodiment of a semiconductor package of the invention.
  • [0017]
    FIG. 4 b shows a schematic view of a layout of conductive bumps of still yet another exemplary embodiment of a semiconductor package of the invention.
  • DETAILED DESCRIPTION OF INVENTION
  • [0018]
    The following description is a mode for carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. Wherever possible, the same reference numbers are used in the drawings and the descriptions to refer the same or like parts.
  • [0019]
    The present invention will be described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto and is only limited by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn to scale for illustrative purposes. The dimensions and the relative dimensions do not correspond to actual dimensions to practice the invention.
  • [0020]
    FIG. 1 a shows a cross section view of one exemplary embodiment of a semiconductor package 500 a of the invention. One exemplary embodiment of a semiconductor package 500 a is a flip chip package using copper pillars connecting to a semiconductor die and a substrate. As shown in FIG. 1 a, one exemplary embodiment of a semiconductor package 500 a comprises a semiconductor die 310 having a central area 302 and a peripheral area 304 surrounding the central area 310. The metal pads 202 and 204 belong to the uppermost metal layer of the interconnection structure (not shown) of the semiconductor die 310. In this embodiment, the metal pads 204 arranged in the central area 302 are used to transmit ground or power signals of the semiconductor die 310, and the metal pads 202 arranged in the peripheral area 304 are used to transmit signals of the semiconductor die 310. Therefore, the metal pads 204 may serve as ground or power pads, and the metal pads 202 may serve as signal pads. In one embodiment, a minimum pitch of the metal pads 204 in the central area 302 may be designed larger than a minimum pitch designed for the metal pads 202 in the peripheral area 304, which also serves as the minimum pitch for the metal pads of the design rule of the semiconductor package 500 a.
  • [0021]
    As shown in FIG. 1 a, a first passivation layer 206 is conformably formed covering the metal pads 202 and 204 by a deposition and patterning processes. In one embodiment, the first passivation layer 206 may comprise oxide, nitride, or oxynitride. The first passivation layer 206 has openings on the metal pads 202 and 204, so that a portion of the metal pads 202 and 204 are respectively exposed from the openings. Also, a second passivation layer 208 is formed by a coating patterning and curing process. In one embodiment, the second passivation layer 208 with openings therethrough may comprise polyimide for providing reliable insulation when the semiconductor die 310 is subjected to various types of environmental stresses. A portion of the metal pads 202 and 204 are respectively exposed from the openings of the second passivation layer 208. In this embodiment, the metal pads 204 are arranged in the central area 302, and the metal pads 202 are arranged in the peripheral area 304.
  • [0022]
    As shown in FIG. 1 a, under bump metallurgy (UBM) layer patterns 210 a and 210 b are formed on the passivation layer 208 by a deposition method such as a sputtering or plating method and a subsequent anisotropic etching process. The anisotropic etching process is performed after forming conductive pillars. Meanwhile, the UBM layer patterns 210 a and 210 b line sidewalls and bottom surfaces of the openings of the passivation layer 208. In this embodiment, the UBM layer patterns 210 a are arranged in the central area 302, and the UBM layer patterns 210 b are arranged in the peripheral area 304. Also, the UBM layer patterns 210 a and 210 b extend over a top surface of the passivation layer 208. In one embodiment, the UBM layer patterns 210 a and 210 b are composed of a Ti layer and a Cu layer on the Ti layer. In one embodiment, the UBM layer patterns 210 a arranged in the central area 302 are designed in a shape different from that of the UBM layer patterns 210 b arranged in the peripheral area 304 from the top view. For example, the UBM layer patterns 210 a arranged in the central area 302 are designed in a circular shape and the UBM layer patterns 210 b arranged in the peripheral area 304 are designed in a rectangular shape from the top view.
  • [0023]
    As shown in FIG. 1 a, the conductive pillars 212 a and 212 b are respectively formed on the UBM layer patterns 210 a and 210 b, filling the openings of the passivation layer 208. In this embodiment, the conductive pillars 212 a are arranged in the central area 302, and the conductive pillars 212 b are arranged in the peripheral area 304. Formation positions of the conductive pillars 212 a and 212 b are defined by a dry film photoresist or liquid photoresist patterns (not shown). In one embodiment, the conductive pillars 212 a and 212 b are used as a solder joint for subsequent conductive bumps, which are used to transmit input/output (I/O), ground or power signals of the semiconductor die 310, disposed thereon. Therefore, the conductive pillars 212 a and 212 b may help to increase the mechanical strength of the bump structure. In one embodiment, the conductive pillars 212 a and 212 b may be formed of copper, so that deformation may be prevented during a subsequent solder re-flow process.
  • [0024]
    As shown in FIG. 1 a, conductive buffer layers 214 a and 214 b are formed on the conductive pillars 212 a and 212 b by an electroplating method. In this embodiment, the conductive buffer layers 214 a are arranged in the central area 302, and the conductive buffer layers 214 b are arranged in the peripheral area 304. In one embodiment, the conductive buffer layer 240 is an optional element serving as a seed layer, an adhesion layer and a barrier layer for a subsequent conductive bump formed thereon. In one embodiment, the conductive buffer layers 214 a and 214 b may comprise Ni.
  • [0025]
    As shown in FIG. 1 a, conductive bumps 216 a and 216 b are respectively formed on the conductive buffer layers 214 a and 214 b by electroplating a solder with a patterned photoresist layer or by a screen printing process and a subsequent solder re-flow process. In this embodiment, the conductive bumps 216 a are arranged in the central area 302, and the conductive bumps 216 b are arranged in the peripheral area 304. In one embodiment, the conductive bumps 216 a electrically connect to the metal pads 204, which are used to transmit ground or power signals of the semiconductor die 310, and the conductive bumps 216 b electrically connect to the metal pads 202, which are used to transmit signals of the semiconductor die 310. In one embodiment of the invention, the conductive pillars 212 a/212 b, the overlying conductive bumps 216 a/216 b and the conductive buffer layers 214 a/214 b (optional) therebetween, collectively form bump structures. Additionally, the semiconductor die 310 and the bump structures collectively form a semiconductor package 500 a.
  • [0026]
    FIG. 1 b shows a schematic view of a layout 600 a of conductive bumps 216 a and 216 b of one exemplary embodiment of the semiconductor package 500 a of the invention. As shown in FIGS. 1 a and 1 b, it is noted that an area A1 of each of the conductive bumps 216 a arranged in the central area 302 is designed to be larger than an area A2 of the conductive bumps 216 b arranged in the peripheral area 304 to increase thermal conductivity and reduce electrical resistively, thereby improving thermal and electrical properties of the semiconductor package 500. In one embodiment as shown in FIGS. 1 and 2, an area ratio A1/A2 of each of the conductive bumps 216 a to each of the conductive bumps 216 b from a top view is larger than 1, and less than or equal to 3. In this embodiment, the area ratio A1/A2 of each of the conductive bumps 216 a to each of the conductive bumps 216 b from a top view is substantially equal to 1.5. In one embodiment, the conductive bumps 216 a arranged in the central area 302 are designed in a shape different from that of the conductive bumps 216 b arranged in the peripheral area 304 from the top view. For example, the conductive bumps 216 a are designed in a circular shape and the conductive bumps 216 b are designed in an oblong shape from the top view. Further, the conductive pillars 212 a arranged in the central area 302 are designed in a shape substantially the same at that of the conductive bumps 216 a. The conductive pillars 212 b arranged in the peripheral area 304 are designed in a shape substantially the same at that of the conductive bumps 216 b from the top view. Accordingly, the conductive pillars 212 a are designed in a circular shape and the conductive pillars 212 b are designed in an oblong shape from the top view. Moreover, an area of each of the conductive pillars 212 a arranged in the central area 302 is designed substantially the same at that of the area A1 of each the conductive bumps 216 a. An area of each of the conductive pillars 212 b arranged in the peripheral area 304 is designed substantially the same at that of the area A2 of each of the conductive bumps 216 b from the top view. Therefore, in one embodiment as shown in FIGS. 1 and 2, an area ratio A1/A2 of each of the conductive pillars 212 a to each of the conductive pillars 212 b from a top view is larger than 1, and less than or equal to 3. In this embodiment, the area ratio A1/A2 of each of the conductive pillars 212 a to each of the conductive pillars 212 b from a top view is substantially equal to 1.5.
  • [0027]
    Additionally, the semiconductor package 500 a can be bonded to a substrate 300, for example, a print circuit board (PCB), as shown in FIG. 1 a. In one embodiment, an underfill material 224 may optionally fill a space between the semiconductor package 500 a and the substrate 300. In one embodiment, the substrate 300 has conductive traces 230 a and 230 b disposed thereon. In this embodiment, the conductive traces 230 a are arranged in the central area 302, and the conductive traces 230 b are arranged in the peripheral area 304. In one embodiment, the substrate 200 may be formed of by semiconductor materials such as silicon, or organic materials such as bismaleimide triacine, (BT), polyimide or ajinomoto build-up film (ABF). In one embodiment, the conductive traces 230 a arranged in the central area 302 may be designed as ground/power trace segments, and the second conductive traces 230 b arranged in the peripheral area 304 may be designed as signal trace segments for routing. Also, the conductive traces 230 a and 230 b are used for input/output (I/O) connections of a semiconductor die 310 mounted directly onto the substrate 200. Therefore, each of the conductive traces 230 a and 230 b has a portion serving as a pad region of the substrate 200. FIG. 1 b also shows a relationship between the conductive traces 230 a/230 b and the conductive bumps 216 a/216 b of one exemplary embodiment of the semiconductor package 500 of the invention. Terminal portions of the conductive traces 230 a overlap with the conductive bumps 216 a in the central area 302, and terminal portions of the conductive traces 230 b overlap with the conductive bumps 216 b in the peripheral area 304.
  • [0028]
    In another embodiment, positions of the metal pads 202 and 204 can be exchanged. FIG. 2 a shows a cross section view of another exemplary embodiment of a semiconductor package 500 b of the invention. FIG. 2 b shows a schematic view of a layout 600 b of conductive bumps of another exemplary embodiment of a semiconductor package 500 b of the invention. Elements of this embodiment which are the same as those previously described in FIGS. 1 a and 1 b, are not repeated for brevity. Differences between the semiconductor packages 500 a and 500 b (the layouts 600 a and 600 b) are that the metal pads 204 of the semiconductor package 500 b for power/ground connections are arranged in the peripheral area 304. Also, the metal pads 202 of the semiconductor package 500 b for power/ground connections are arranged in the central area 302.
  • [0029]
    In yet another embodiment, the metal pads 202 and 204 can be arranged both in the the central area 302 and the peripheral area 304. Also, the metal pads 202 and 204 can be alternatively arranged in the central area 302 or the peripheral area 304. FIG. 3 a shows a cross section view of yet another exemplary embodiment of a semiconductor package 500 c of the invention. FIG. 3 b shows a schematic view of a layout 600 c of conductive bumps of yet another exemplary embodiment of a semiconductor package 500 c of the invention. Elements of this embodiment which are the same as those previously described in FIGS. 1 a and 1 b, are not repeated for brevity. As shown in FIGS. 3 a and 3 b, the metal pads adjacent to any one of the metal pads 202 are the metal pads 204. Also, the metal pads adjacent to any one of the metal pads 204 are the metal pads 202.
  • [0030]
    In still yet another embodiment, the metal pads 202 and 204 can be arranged both in the central area 302 and the peripheral area 304. Also, the metal pads 202 and 204 can be randomly arranged in the central area 302 or the peripheral area 304. FIG. 4 a shows a cross section view of still yet another exemplary embodiment of a semiconductor package 500 d of the invention. FIG. 4 b shows a schematic view of a layout 600 d of conductive bumps of still yet another exemplary embodiment of a semiconductor package 500 d of the invention. Elements of this embodiment which are the same as those previously described in FIGS. 1 a and 1 b, are not repeated for brevity. As shown in FIGS. 4 a and 4 b, any one of the metal pads 202 can be adjacent to the metal pads 202 or 204. Also, any one of the metal pads 204 can be adjacent to the metal pads 202 or 204.
  • [0031]
    Exemplary embodiments provide a semiconductor package. The semiconductor package is designed to arrange conductive bumps with two different areas (sizes) in one semiconductor package. Because the power/ground connections of the semiconductor chip 301 has a number much less than the signal connections, a minimum pitch of the metal pads 204 for power/ground connections may be designed larger than a minimum pitch designed for the metal pads 202 for signal connections. An area A1 of each of the conductive bumps 216 a connecting the metal pads 204 is designed to be larger than an area A2 of the conductive bumps 216 b connecting the metal pads 202 to increase thermal conductivity and reduce electrical resistively, thereby improving thermal and electrical properties of the semiconductor package 500. In one embodiment as shown in FIGS. 1 a and 1 b, an area ratio A1/A2 of each of the conductive bumps 216 a to each of the conductive bumps 216 b from a top view is larger than 1, and less than or equal to 3. In this embodiment, the area ratio A1/A2 of each of the conductive bumps 216 a to each of the conductive bumps 216 b from a top view is substantially equal to 1.5. In one embodiment, the conductive bumps 216 a arranged in the central area 302 are designed in a shape different from that of the conductive bumps 216 b arranged in the peripheral area 304 from the top view.
  • [0032]
    While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Citations de brevets
Brevet cité Date de dépôt Date de publication Déposant Titre
US3871015 *14 août 196911 mars 1975IbmFlip chip module with non-uniform connector joints
US4545610 *25 nov. 19838 oct. 1985International Business Machines CorporationMethod for forming elongated solder connections between a semiconductor device and a supporting substrate
US5569960 *10 mai 199529 oct. 1996Hitachi, Ltd.Electronic component, electronic component assembly and electronic component unit
US5989937 *26 août 199723 nov. 1999Lsi Logic CorporationMethod for compensating for bottom warpage of a BGA integrated circuit
US6053394 *13 janv. 199825 avr. 2000International Business Machines CorporationColumn grid array substrate attachment with heat sink stress relief
US6107685 *17 sept. 199922 août 2000Sony CorporationSemiconductor part and fabrication method thereof, and structure and method for mounting semiconductor part
US6534875 *17 sept. 199918 mars 2003Sony CorporationSemiconductor part for component mounting, mounting structure and mounting method
US6541857 *4 janv. 20011 avr. 2003International Business Machines CorporationMethod of forming BGA interconnections having mixed solder profiles
US6624004 *20 juin 200223 sept. 2003Advanced Semiconductor Engineering, Inc.Flip chip interconnected structure and a fabrication method thereof
US6674162 *13 mars 20016 janv. 2004Sanyo Electric Co., Ltd.Semiconductor device and manufacturing method thereof
US6734566 *21 févr. 200111 mai 2004Nec Electronics CorporationRecyclable flip-chip semiconductor device
US6750549 *31 déc. 200215 juin 2004Intel CorporationVariable pad diameter on the land side for improving the co-planarity of ball grid array packages
US6940176 *21 mai 20026 sept. 2005United Microelectronics Corp.Solder pads for improving reliability of a package
US7541217 *25 août 20082 juin 2009Industrial Technology Research InstituteStacked chip structure and fabrication method thereof
US7902679 *31 oct. 20078 mars 2011Megica CorporationStructure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump
US7906835 *13 août 200715 mars 2011Broadcom CorporationOblong peripheral solder ball pads on a printed circuit board for mounting a ball grid array package
US8337735 *3 févr. 201225 déc. 2012Ultratech, Inc.Solder mold plates used in packaging process and method of manufacturing solder mold plates
US8344505 *29 août 20071 janv. 2013Ati Technologies UlcWafer level packaging of semiconductor chips
US20030114024 *28 août 200219 juin 2003Kabushiki Kaisha ToshibaPrinted wiring board having plurality of conductive patterns passing through adjacent pads, circuit component mounted on printed wiring board and circuit module containing wiring board with circuit component mounted thereon
US20090057887 *29 août 20075 mars 2009Ati Technologies UlcWafer level packaging of semiconductor chips
Référencé par
Brevet citant Date de dépôt Date de publication Déposant Titre
US917789920 déc. 20123 nov. 2015Mediatek Inc.Semiconductor package and method for fabricating base for semiconductor package
US9324557 *23 avr. 201426 avr. 2016Avago Technologies General Ip (Singapore) Pte. Ltd.Method for fabricating equal height metal pillars of different diameters
US9460646 *17 juin 20134 oct. 2016Samsung Display Co., Ltd.Display device and bonding test system
US9679830 *19 août 201513 juin 2017Mediatek Inc.Semiconductor package
US20140117998 *17 juin 20131 mai 2014Samsung Display Co., Ltd.Display device and bonding test system
US20140374900 *1 avr. 201425 déc. 2014Heungkyu KwonSemiconductor package and method of fabricating the same
US20150262950 *23 avr. 201417 sept. 2015Lsi CorporationMethod for Fabricating Equal Height Metal Pillars of Different Diameters
US20160126161 *19 août 20155 mai 2016Mediatek Inc.Semiconductor package
US20170162545 *26 oct. 20168 juin 2017Samsung Electronics Co., Ltd.Stacked semiconductor device and a method of manufacturing the same
Événements juridiques
DateCodeÉvénementDescription
26 mars 2012ASAssignment
Owner name: MEDIATEK INC., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LIN, TZU-HUNG;HSU, WEN-SUNG;CHEN, TAI-YU;REEL/FRAME:027929/0783
Effective date: 20120314