US20130009276A1 - Methods of filling isolation trenches for semiconductor devices and resulting structures - Google Patents
Methods of filling isolation trenches for semiconductor devices and resulting structures Download PDFInfo
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- US20130009276A1 US20130009276A1 US13/616,199 US201213616199A US2013009276A1 US 20130009276 A1 US20130009276 A1 US 20130009276A1 US 201213616199 A US201213616199 A US 201213616199A US 2013009276 A1 US2013009276 A1 US 2013009276A1
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- trench
- oxide layer
- layer
- silicon oxide
- polysilicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
Abstract
The invention relates to a method and resulting structure that can substantially minimize and/or eliminate void formation during an isolation trench isolation fill process for typical trench shaped and goal-post shaped isolation regions. First, a thin thermal oxidation layer is grown on the sidewall of each trench and then a layer of polysilicon is deposited above the oxidation layer and oxidized. In one embodiment, a repeating series of polysilicon deposition and polysilicon oxidation steps are performed until each trench has been completely filled. In another embodiment, within a goal-post shaped trench having a wider upper portion and a narrower lower portion, the remainder of the upper wider trench portion is filled using a conventional high density plasma technique.
Description
- The present invention relates to the field of semiconductor devices and, in particular, to methods for filling high aspect ratio trench isolation regions in semiconductor devices and the resulting structures.
- Typically in semiconductor device applications, numerous devices are packed into a small area of a semiconductor substrate to create an integrated circuit. Generally, these devices need to be electrically isolated from one another to avoid problems among the devices. Accordingly, electrical isolation is an important part of semiconductor device design to prevent unwanted electrical coupling between adjacent components and devices. This is particularly true for high density memory, including but not limited to, flash memory.
- Shallow trench isolation (STI) is one known conventional isolation method and provides very good device-to-device isolation. An STI process generally includes the following steps. First, a trench is formed in a semiconductor substrate using wet or dry etching with a mask. Then, an insulating layer is deposited on the entire surface of the semiconductor substrate to fill the trench. Finally, chemical mechanical polishing (CMP) is used to planarize the insulating layer. The insulating layer remaining in the trench acts as an STI region for providing isolation among devices in the substrate. Additionally, a nitride or oxidation layer may be formed on the sidewalls and bottom of the trench before depositing the insulating layer.
- As semiconductor devices get smaller and more complex, and as packing density increases, the width of the STI regions also decreases. In addition, for certain types of electronic devices, a deeper isolation trench is desired. When filling an isolation trench with a high-density plasma oxide having good filling capability, voids or seams may exist in the isolation regions. This void formation problem occurs in the formation of traditional isolation trenches as well as the so called goal-post type shaped trenches. These void defects cause electrical isolation between the devices to be reduced. Poor isolation can lead to such problems as short circuits and can further reduce the lifetime of one or more circuits formed on a substrate.
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FIGS. 1A and 1B illustrate isolation trenches 11 formed in asemiconductor substrate 10 in accordance with the prior art. Before forming theisolation trenches 11, other layers may be blanket deposited over thesemiconductor substrate 10; for example,FIGS. 1A & 1B illustrate layers later used to form gate structures, including anoxide layer 12, apolysilicon layer 14, and anitride layer 16. After thetrenches 11 are formed throughlayers substrate 10, aninsulating layer 20 is deposited over thelayers semiconductor substrate 10 to fill thetrenches 11. Theinsulating layer 20 can be deposited using high density plasma (HDP) or high-density plasma chemical vapor deposition (HPDCVD) techniques. Due to the shape of thetrenches 11, the HDP or HPDCVD process tends to leavevoid regions 22 orseams 24 in theinsulating layer 20, as shown inFIGS. 1A and 1B , respectively. -
Voids 22 occur because theinsulating layer 20 deposited on the sidewalls at the top of atrench 11 grows thicker than the portion closer to the bottom of thetrench 11. Therefore, the opening at the top of thetrench 11 becomes closed-off before the entire volume of thetrench 11 can be filled causing the formation of thevoid region 22. Thevoid region 22 diminishes the isolation properties of the filledtrench 11. Moreover, the filling material, typically an oxide, tends to be non-conformal and thus, fails to conform to the profile of the surface ideally. -
Seams 24 occur where the opposing faces of the inward growing insulatinglayer 20 within atrench 11 are joined together. Whileseam 24, in and of itself, does no harm in the structure, if the structure ofFIG. 1B is exposed to etching steps during subsequent processing, the portion ofinsulating layer 20adjacent seam 24 may be more sensitive to etching than the rest ofmaterial 20, which will reduce the isolation properties of the filledtrench 11 in a similar manner to that ofvoid 22. - Another problem with
voids 22 andseams 24 are that they can be exposed during subsequent process steps and either trap contamination, and/or cause surface roughness. Consequently, films deposited after the roughness (voids 22 and seams 24) has been exposed will not form a consistent, flat layer, but will instead follow the contours of the void or seam below. The inconsistent, resulting film can lead to subsequent breaks in the film. These breaks, if patterned and etched later, will make it increasingly hard to remove the resulting film layer from the void, and thus can electrically short together two areas that are intended to be isolated. - Accordingly, there is a need and desire for a method of filling trench isolation regions that achieves high quality isolation, but also reduces the formation of voids and seams in the insulating material. An improved trench isolation region is also desired.
- The invention relates to a method and resulting structure that can substantially minimize and/or eliminate void formation during the shallow trench isolation fill process for typical trench shaped and goal-post shaped isolation regions. First, a thin thermal oxidation layer is grown on the sidewall of each trench and then a layer of polysilicon is deposited above the oxidation layer. In one embodiment, a repeating series of polysilicon deposition and polysilicon oxidation steps are performed until each trench has been completely filled. In another embodiment, within a goal-post shaped trench, the remainder of the wide trench is filled using a conventional high density plasma technique.
- The above described features of the invention will be more clearly understood from the following detailed description, which is provided with reference to the accompanying drawings in which:
-
FIG. 1A depicts a prior art semiconductor substrate including isolation trenches including voids; -
FIG. 1B depicts a prior art semiconductor substrate including isolation trenches including seams; -
FIG. 2 is a cross-sectional view of a semiconductor device with isolation trenches formed in a semiconductor substrate during an early fabrication stage in accordance with an exemplary embodiment of the invention; -
FIG. 3 shows a cross-sectional view of the semiconductor device at a fabrication stage subsequent toFIG. 2 ; -
FIG. 4 shows a cross-sectional view of the semiconductor device at a fabrication stage subsequent toFIG. 3 ; -
FIG. 5 shows a cross-sectional view of the semiconductor device at a fabrication stage subsequent toFIG. 4 ; -
FIG. 6 shows a cross-sectional view of the semiconductor device at a fabrication stage subsequent toFIG. 5 ; -
FIG. 7 shows a cross-sectional view of the semiconductor device at a fabrication stage subsequent toFIG. 6 ; -
FIG. 8 shows a cross-sectional view of the semiconductor device at a fabrication stage subsequent toFIG. 7 ; -
FIG. 9 shows a cross-sectional view of the semiconductor device at a fabrication stage subsequent toFIG. 8 ; -
FIG. 10 shows a cross-sectional view of the semiconductor device at a fabrication stage subsequent toFIG. 9 ; -
FIG. 11 shows a cross-sectional view of the semiconductor device at a fabrication stage subsequent toFIG. 10 ; -
FIG. 12 shows a cross-sectional view of the semiconductor device at an early fabrication stage in accordance with a second exemplary embodiment of the invention; -
FIG. 13 shows a cross-sectional view of a semiconductor device at a fabrication stage subsequent toFIG. 12 ; -
FIG. 14 shows a cross-sectional view of a semiconductor device at a fabrication stage subsequent toFIG. 13 ; -
FIG. 15 shows a cross-sectional view of a semiconductor device at a fabrication stage subsequent toFIG. 14 ; -
FIG. 16 shows a cross-sectional view of a semiconductor device at a fabrication stage subsequent toFIG. 15 ; -
FIG. 17 shows a cross-sectional view of a semiconductor device at a fabrication stage subsequent toFIG. 16 ; -
FIG. 18 shows a cross-sectional view of a portion of a memory cell according to another exemplary embodiment of the invention; -
FIG. 19 is a view of the structure of a memory array in a conventional NAND type flash memory; and -
FIG. 20 shows a processor system incorporating a memory cell device with shallow trench isolation regions constructed in accordance with the exemplary embodiment of the invention. - In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and show by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized, and that changes may be made without departing from the spirit and scope of the present invention. The progression of processing steps described is exemplary of embodiments of the invention; however, the sequence of steps is not limited to that set forth herein and may be changed as is known in the art, with the exception of steps necessarily occurring in a certain order
- The term “substrate” is to be understood as including all forms of semiconductor wafers and substrates including silicon, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor structures. Furthermore, when reference is made to a “substrate” in the following description, previous process steps may have been utilized to form regions or junctions in or above the base semiconductor structure or foundation. In addition, the semiconductor need not be silicon-based, but could be based on other semiconductors, for example, silicon-germanium, germanium or gallium arsenide.
- The present invention relates to methods for filling trench isolation regions that allow for better gap-fill characteristics while substantially mitigating the presence of voids and seams. The invention may be used in any integrated circuit high packing density environment, including but not limited to memory array, flash memory array being just one example.
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FIG. 2 depictsunfilled isolation trenches 200 to be used as isolation regions in asemiconductor substrate 100. Before forming thetrenches 200, anitride layer 210 may be blanket deposited over thesemiconductor substrate 100 as a part of the later fabrication of devices in and oversubstrate 100. In some instances, it may be desired to deposit an oxide layer and a polysilicon layer over the semiconductor substrate. For purposes of description of the embodiments of this invention, the embodiments are described as having anitride layer 210 deposited over thesemiconductor substrate 100. Theisolation trenches 200 are formed by any method known in the art that is suitable for forming anisolation trench 200. Thetrenches 200 comprisesidewalls 220 that terminate at a bottom 230. - Referring to
FIG. 3 , athermal oxide layer 310 is formed/grown on thesidewalls 220 andbottom 230 of theisolation trenches 200. It should be appreciated that the growth ofoxide layer 310 stops below thenitride layer 210. It should also be appreciated that when the oxide layer 260 and the polysilicon layer 250 are deposited over thesemiconductor substrate 100, theoxide layer 310 is formed/grown on the sidewalls of these layers as well. Althoughoxide layer 310 has been described as formed using a thermal oxidation process, it should be appreciated that the oxide layer could be formed by deposition, if desired. - Next, referring to
FIG. 4 , a layer ofpolysilicon 440 is deposited on thethermal oxide layer 310. Thepolysilicon layer 440 extends above thesubstrate 100 and additionally covers thenitride layer 210. Referring toFIG. 5 , thepolysilicon layer 440 is oxidized, thus converting thepolysilicon layer 440 into a puresilicon dioxide layer 450. - Referring to
FIG. 6 , another layer ofpolysilicon 550 is deposited above thesilicon dioxide layer 450. The layer ofpolysilicon 550 is oxidized to convert the polysilicon into a pure silicon dioxide layer 560 (i.e., a dielectric), as shown inFIG. 7 . The steps ofFIGS. 6 and 7 are repeated until eachtrench 200 is completely filled. Accordingly, referring toFIGS. 8 and 9 , a third layer ofpolysilicon 570 can be deposited and oxidized into a layer ofsilicon dioxide 580. The illustrated embodiment uses three layers of polysilicon to fill thetrenches 200. It should be appreciated, however, that the invention is not limited to using three layers. The described method can be used with any number of deposited layers to form void free trench isolation regions. - Referring to
FIG. 10 , once thetrenches 200 are filled, thetrenches 200 are subsequently planarized. This can be done by chemical mechanical polishing or by any other method known in the art. The final step, shown inFIG. 11 , is removing thenitride layer 210 from thesubstrate 100 surface by etching. It should be appreciated that any etching method known in the art can be used. - The invention solves the void formation problems associated with the prior art oxide deposition methods. The invention has the ability to use two beneficial materials to fill the trench structures. Polysilicon is very conformal and does not form voids when deposited. Silicon dioxide is known to be a good material for electrical isolation. The present invention combines the best properties from both materials and, as described above, first deposits polysilicon for its conformal properties and then oxidizes it into silicon dioxide to enhance or form good dielectric properties.
- In another exemplary embodiment, the process can be modified and applied to goal-post shaped trenches as explained below.
-
FIG. 12 depicts unfilled goal-post shapedisolation trenches 1200 to be used as isolation regions in asemiconductor substrate 100. Before forming thetrenches 1200, anitride layer 1210 may be blanket deposited over thesemiconductor substrate 100 as a part of the subsequent fabrication of devices in and oversubstrate 100. The illustrated embodiment is described as having anitride layer 1210 deposited over thesemiconductor substrate 100. However, it should be appreciated that any or all of the layers described can be blanket deposited over thesubstrate 100. Theisolation trenches 1200 are formed by any etching method known in the art that is suitable for forming anisolation trench 1200. The goal-post shapedisolation trenches 1200 in essence comprise tworespective trench portions trench portion 1201 being narrower and formed at abottom 1230 oftrench portion 1202, which is a much wider. Additionally,trench portions trench bottom 1230. - Referring to
FIG. 12 , athermal oxide layer 1240 is formed/grown on thesidewalls 1220 and bottom 1230 of theisolation trench portions oxide layer 1240 stops below thenitride layer 1210. Althoughoxide layer 1240 has been described as being formed using a thermal oxidation process, it should be appreciated that theoxide layer 1240 could be formed by deposition, if desired. - Next, referring to
FIG. 13 , a layer ofpolysilicon 1450 is deposited above thethermal oxide layer 1240 along the sidewalls oftrench portion 1202 and along the sidewalls oftrench portion 1201. Thepolysilicon layer 1450 extends above thesubstrate 100 and additionally covers thenitride layer 1210. Referring toFIG. 14 , the polysilicon layer 1450 (FIG. 13 ) is oxidized and converted into a puresilicon dioxide layer 1460. It should be appreciated that the thickness of the polysilicon layer 1450 (FIG. 13 ) should be based on the width of thenarrow trench portion 1201. The thickness of the polysilicon layer 1450 (FIG. 13 ) should be sufficient so that thenarrow trench portion 1201 is completely filled after the oxidation of the polysilicon. - Referring to
FIG. 15 , the remainder oftrench portion 1202 is filled using the standard high density plasma technique. Referring toFIG. 16 , thetrenches 1200 are planarized to the surface of thenitride layer 1210. This can be done by chemical mechanical polishing or by any other method known in the art. Thenitride layer 1210 is then removed by an etching process, as shown inFIG. 17 . It should be appreciated that any etching method known in the art can be used. - The illustrated second embodiment of the invention solves the prior art void and seam formation problems associated with filling goal-post shaped trenches with a high quality dielectric material. As discussed above, polysilicon is very conformal and does not form voids when deposited and silicon dioxide is known to be a good material for electrical isolation. The illustrated embodiments provide void free isolation regions.
- The second embodiment has been described with reference to using one layer of deposited
polysilicon 1450 which is oxidized to formoxide layer 1460. If desired, additional layers of polysilicon can be deposited overoxide layer 1460 and oxidized before the trench is filled using high density plasma to deposit an oxide. Additionally, layers of polysilicon can be deposited and oxidized until the trench is completely filled. - The trench isolation regions formed by the embodiments of the present invention may be used to separate active regions of an integrated circuit, for example, adjacent
memory cell regions flash memory array 800, which is partially shown inFIG. 18 . Thetrench isolation region 830, comprised of silicon dioxide 840 (formed as described above), is between a firstactive region 810 and a secondactive region 820 respectively associated with memory cells of theflash memory array 800. For example,FIG. 19 , depicts a NAND type flash memory comprising four memory cells MT1, MT2, MT3, and MT4 connected to one NAND string connected to one bit line BL. Thetrench isolation region 830 ofFIG. 18 , may be formed amongst any of the memory cells MT1, MT2, MT3, and MT4 to electrically isolate the memory cells from each other. The flash memory cells formed inregions -
FIG. 20 is a block diagram of aprocessor system 2000 utilizing amemory device 2010, e.g., a flash memory device, constructed in accordance with the present invention. That is, thememory device 2010 has cells separated by trench isolation regions constructed in accordance with the invention. Theprocessor system 2000 may be a computer system, a process control system or any other system employing a processor and associated memory. Thesystem 2000 includes a central processing unit (CPU) 2020, e.g., a microprocessor, that communicates with theflash memory 2010 and an I/O device 2030 over abus 2040. It must be noted that thebus 2040 may be a series of buses and bridges commonly used in a processor system, but for convenience purposes only, thebus 2040 has been illustrated as a single bus. A second I/O device 2050 is illustrated, but is not necessary to practice the invention. Theprocessor system 2000 also includes random access memory (RAM)device 2060 and may include a read-only memory (ROM) device (not shown), and peripheral devices such as afloppy disk drive 2070 and a compact disk (CD)ROM drive 2080 that also communicate with theCPU 2020 over thebus 2040 as is well known in the art. - The processes and devices described above illustrate preferred methods and typical devices of many that could be used and produced. The above description and drawings illustrate embodiments, which achieve the objects, features and advantages of the present invention. However, it is intended that the present invention be strictly limited to the above-described and illustrated embodiments. Any modification, though presently unforeseeable, of the present invention that comes within the spirit and scope of the following claims should be considered part of the present invention.
Claims (21)
1-13. (canceled)
14. A trench isolation region comprising:
a trench;
an oxide layer on the sidewalls and bottom of the trench;
a first silicon oxide layer deposited above said oxide layer, said first silicon oxide layer being formed by oxidizing a polysilicon layer; and
an insulator layer formed above said first silicon oxide layer to fill the remainder of the trench.
15. The trench isolation region of claim 14 , wherein said insulator layer is a second silicon oxide layer formed by oxidizing another polysilicon layer.
16. The trench isolation region of claim 14 , wherein said insulator is formed by high density plasma deposition.
17. The trench isolation region of claim 15 , further comprising a third silicon oxide layer deposited above said second silicon oxide layer formed by oxidizing another polysilicon layer.
18. The trench isolation region of claim 16 , wherein before said insulator layer is formed, a second silicon oxide layer is deposited above said first silicon oxide layer, said second silicon oxide layer being formed by oxidizing a second polysilicon layer and then said insulator is formed by high density plasma deposition.
19. The trench isolation region of claim 14 , wherein said trench comprises a first upper trench portion and a second lower trench portion being below the upper trench portion, wherein the lower trench portion has a width less than the width of the upper trench portion.
20. A memory device comprising:
an active area; and
a trench isolation region adjacent said active area, said region comprising:
a trench;
an oxide layer on the sidewalls and bottom of the trench;
a first silicon oxide layer deposited above said oxide layer, said first silicon oxide layer being formed by oxidizing a polysilicon layer; and
an insulator layer formed above said first silicon oxide layer to fill the remainder of the trench.
21. The memory device of claim 20 , wherein said insulator layer is a second silicon oxide layer formed by oxidizing another polysilicon layer.
22. The memory device of claim 20 , wherein said insulator is formed by high density plasma deposition.
23. The memory device of claim 21 , further comprising a third silicon oxide layer deposited above said second silicon oxide layer formed by oxidizing another polysilicon layer.
24. The memory device of claim 20 , wherein said trench comprises a first upper trench portion and a second lower trench portion being below the upper trench portion, wherein the lower trench portion has a width less than the width of the upper trench portion.
25. The memory device of claim 20 , wherein the memory device is flash memory.
26. The memory device of claim 22 , wherein before said insulator layer is formed, a second silicon oxide layer is deposited above said first silicon oxide layer, said second silicon oxide layer being formed by oxidizing a second polysilicon layer and then said insulator is formed by high density plasma deposition.
27. A system comprising:
a processor; and
a memory device coupled to said processor, said memory device comprising:
an active area; and
a trench isolation region adjacent said active area, said region comprising:
a trench;
an oxide layer on the sidewalls and bottom of the trench;
a first silicon oxide layer deposited above said oxide layer, said first silicon oxide layer being formed by oxidizing a polysilicon layer; and
an insulator layer formed above said first silicon oxide layer to fill the remainder of the trench.
28. The system of claim 27 , wherein said insulator layer is a second silicon oxide layer formed by oxidizing another polysilicon layer.
29. The system of claim 27 , wherein said insulator is formed by high density plasma deposition.
30. The system of claim 28 , further comprising a third silicon oxide layer deposited above said second silicon oxide layer formed by oxidizing another polysilicon layer.
31. The system of claim 27 , wherein said trench comprises a first upper trench portion and a second lower trench portion being below the upper trench portion, wherein the lower trench portion has a width less than the width of the upper trench portion.
32. The system of claim 27 , wherein the memory device is flash memory.
33. The system of claim 29 , wherein before said insulator layer is formed, a second silicon oxide layer is deposited above said first silicon oxide layer, said second silicon oxide layer being formed by oxidizing a second polysilicon layer and then said insulator is formed by high density plasma deposition.
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US13/616,199 US20130009276A1 (en) | 2006-04-18 | 2012-09-14 | Methods of filling isolation trenches for semiconductor devices and resulting structures |
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US11/405,629 US8304322B2 (en) | 2006-04-18 | 2006-04-18 | Methods of filling isolation trenches for semiconductor devices and resulting structures |
US13/616,199 US20130009276A1 (en) | 2006-04-18 | 2012-09-14 | Methods of filling isolation trenches for semiconductor devices and resulting structures |
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US13/616,199 Abandoned US20130009276A1 (en) | 2006-04-18 | 2012-09-14 | Methods of filling isolation trenches for semiconductor devices and resulting structures |
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DE102006037510B3 (en) * | 2006-08-10 | 2008-04-10 | Infineon Technologies Austria Ag | A method for producing a trench structure, the use of this method for producing a semiconductor device and semiconductor device having a trench structure |
US7803680B2 (en) * | 2007-01-12 | 2010-09-28 | Spansion Llc | Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications |
US8921183B2 (en) * | 2010-12-08 | 2014-12-30 | Nanya Technology Corporation | Method for fabricating trench isolation structure |
CN103050389A (en) * | 2012-12-14 | 2013-04-17 | 上海华虹Nec电子有限公司 | Growing method of low-stress IGBT (Insulated Gate Bipolar Transistor) groove type grid electrode |
CN103066008A (en) * | 2012-12-26 | 2013-04-24 | 上海宏力半导体制造有限公司 | Method for improving groove dielectric medium pore-filling capacity in flash memory shallow groove isolation technology |
JP2015179729A (en) * | 2014-03-19 | 2015-10-08 | 東京エレクトロン株式会社 | Method for forming silicon oxide film, and device for forming silicon oxide film |
KR102442309B1 (en) | 2015-07-09 | 2022-09-13 | 삼성전자주식회사 | Methods of forming an isolation structure in a semiconductor device |
JP7203515B2 (en) * | 2017-06-06 | 2023-01-13 | アプライド マテリアルズ インコーポレイテッド | Bottom-up growth of silicon oxide and silicon nitride using a sequential deposition-etch-processing method |
GB2574003B (en) * | 2018-05-21 | 2020-05-27 | X Fab Sarawak Sdn Bhd | Improvements relating to semiconductor devices |
GB2574002B (en) | 2018-05-21 | 2020-12-09 | X Fab Sarawak Sdn Bhd | Improved semiconductor device and method of fabrication |
CN111785629A (en) * | 2020-06-28 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of trench gate IGBT device |
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US6391784B1 (en) * | 1999-07-21 | 2002-05-21 | Advanced Micro Devices, Inc. | Spacer-assisted ultranarrow shallow trench isolation formation |
US20050247994A1 (en) * | 2002-07-16 | 2005-11-10 | Freidoon Mehrad | Shallow trench isolation structure and method |
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TW469579B (en) * | 1998-09-19 | 2001-12-21 | Winbond Electronics Corp | Method for producing shallow trench isolation (STI) |
US6316331B1 (en) * | 2000-10-13 | 2001-11-13 | Vanguard International Semiconductor Corp. | Method of making dishing-free insulator in trench isolation |
KR20020071063A (en) * | 2001-03-02 | 2002-09-12 | 삼성전자 주식회사 | Dent free trench isolation structure and method for fabricating the same |
DE10246949B4 (en) * | 2002-10-08 | 2012-06-28 | X-Fab Semiconductor Foundries Ag | Improved trench isolation and manufacturing process |
JP4515951B2 (en) * | 2005-03-31 | 2010-08-04 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof |
US20070224772A1 (en) * | 2006-03-21 | 2007-09-27 | Freescale Semiconductor, Inc. | Method for forming a stressor structure |
-
2006
- 2006-04-18 US US11/405,629 patent/US8304322B2/en active Active
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Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US6391784B1 (en) * | 1999-07-21 | 2002-05-21 | Advanced Micro Devices, Inc. | Spacer-assisted ultranarrow shallow trench isolation formation |
US20050247994A1 (en) * | 2002-07-16 | 2005-11-10 | Freidoon Mehrad | Shallow trench isolation structure and method |
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US20070243692A1 (en) | 2007-10-18 |
US8304322B2 (en) | 2012-11-06 |
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