US20130069701A1 - Phase interpolation circuit - Google Patents
Phase interpolation circuit Download PDFInfo
- Publication number
- US20130069701A1 US20130069701A1 US13/330,615 US201113330615A US2013069701A1 US 20130069701 A1 US20130069701 A1 US 20130069701A1 US 201113330615 A US201113330615 A US 201113330615A US 2013069701 A1 US2013069701 A1 US 2013069701A1
- Authority
- US
- United States
- Prior art keywords
- electrically connected
- type transistor
- drain
- input signal
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/131—Digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
- H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
- H03K2005/00026—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
- H03K2005/00052—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter by mixing the outputs of fixed delayed signals with each other or with the input signal
Definitions
- the invention relates to a phase interpolation circuit.
- the invention relates to a phase interpolation circuit capable of generating a differential output signal with 50% of duty cycle.
- a clock and data recovery circuit is generally configured to recover signals containing noise components, where a phase interpolation circuit is a core circuit composing the clock and data recovery circuit. Therefore, it is an important issue to ameliorate the phase interpolation circuit to improve whole performance of the clock and data recovery circuit.
- the phase interpolation circuit can be implemented through current mode logic to cope with the requirement of a high-speed transmission.
- the phase interpolation circuit of the current mode logic has following disadvantages: (1) a linearity thereof is liable to be influenced by a parasitic capacitance and a front-end circuit load, so that a duty cycle of an output signal has a great variation, especially under an influence of process variation; (2) it is of no avail for low-voltage operations, which leads to a limited operating range.
- the invention is directed to a phase interpolation circuit, in which a duty-cycle repeater is used to adjust a duty cycle of a differential output signal. In this way, a problem of dramatic variation of the duty cycle of the differential output signal due to an influence of process variation is resolved.
- the invention provides a phase interpolation circuit including a first multiplexer, a second multiplexer, an interpolator and a duty-cycle repeater.
- the first multiplexer receives a plurality of even order signals.
- the second multiplexer receives a plurality of odd order signals.
- the interpolator receives a first reference signal composed of one of the even order signals through the first multiplexer, and receives a second reference signal composed of one of the odd order signals through the second multiplexer.
- the interpolator divides a phase difference between the first reference signal and the second reference signal into a plurality of sub-phases according to a digital control signal, and selects one of the sub-phases to generate a differential input signal.
- the duty-cycle repeater adjusts a duty cycle of the differential input signal to generate a differential output signal with 50% of the duty cycle.
- the first multiplexer selects two even order signals complementing each other from the even order signals, and the interpolator selects one of the two selected even order signals as the first reference signal.
- the second multiplexer selects two odd order signals complementing each other from the odd order signals, and the interpolator selects one of the two selected odd order signals as the second reference signal.
- the interpolator includes a bias generating unit, a current source, a load unit and an input unit.
- the bias generating unit generates a plurality of first biases according to the digital control signal, and generates a plurality of second biases according to a complement of the digital control signal.
- the current source receives the first biases and the second biases to generate a first current and a second current.
- the input unit is electrically connected between the load unit and the current source, and switches paths that the first current and the second current are conducted to the load unit according to the first reference signal and the second reference signal, so as to generate the differential input signal.
- the duty-cycle repeater is used to adjust the duty cycle of the differential output signal to avoid dramatic variation of the duty cycle of the differential output signal due to influence of a process variation.
- the bias generating unit in the interpolator is independently configured outside a cascade structure formed by the load unit, the input unit and the current source. In this way, the interpolator avails implementing a low-voltage operation, and an operation range of the phase interpolation circuit is expanded.
- FIG. 1 is a block schematic diagram of a phase interpolation circuit according to an embodiment of the invention.
- FIG. 2 is a circuit diagram of an interpolator according to an embodiment of the invention.
- FIG. 3 is a circuit diagram of a duty-cycle repeater according to an embodiment of the invention.
- FIG. 4 is a circuit diagram of a phase blender according to an embodiment of the invention.
- FIG. 1 is a block schematic diagram of a phase interpolation circuit according to an embodiment of the invention.
- the phase interpolation circuit 100 includes a multiplexer 110 , a multiplexer 120 , an interpolator 130 and a duty-cycle repeater 140 .
- the phase interpolation circuit 100 can be used in a clock and data recovery circuit, especially in a clock and data recovery circuit of a high-speed transmission interface module (for example, a universal serial bus (USB) 3.0 interface module).
- a high-speed transmission interface module for example, a universal serial bus (USB) 3.0 interface module.
- the multiplexer 110 and the multiplexer 120 respectively receive a plurality of phase signals.
- 8 phase signals P 0 -P 7 i.e. 0°, 45°, 90°, 135°, . . . , 315° are obtained.
- the 8 phase signals P 0 -P 7 respectively have a phase difference of 45°.
- the phase signals P 0 , P 2 , P 4 and P 6 are respectively an even multiple of the basic phase of 45°, so that the phase signals P 0 , P 2 , P 4 and P 6 can be regarded as even order signals.
- the phase signals P 1 , P 3 , P 5 and P 7 are respectively an odd multiple of the basic phase of 45°, so that the phase signals P 1 , P 3 , P 5 and P 7 can be regarded as odd order signals.
- the multiplexer 110 receives four phase signals P 0 , P 2 , P 4 and P 6 , i.e. four even order signals P 0 , P 2 , P 4 and P 6 .
- the multiplexer 120 receives four phase signals P 1 , P 3 , P 5 and P 7 , i.e. four odd order signals P 1 , P 3 , P 5 and P 7 .
- a method of parity separation is used to distribute the phase signals to the two multiplexers, for example, the multiplexer 110 receives the phase signals of the even orders (P 0 , P 2 , P 4 and P 6 ) (i.e. the even order signals), and the second multiplexer 120 receives the phase signals of the odd orders (P 1 , P 3 , P 5 and P 7 ) (i.e. the odd order signals).
- the multiplexer 110 and the multiplexer 120 respectively select two phase signals for outputting.
- the multiplexer 110 selects the phase signal P 0 and the phase signal P 2 complementing to each other from the phase signals P 0 , P 2 , P 4 and P 6
- the multiplexer 120 selects the phase signal P 1 and the phase signal P 3 complementing to each other from the phase signals P 1 , P 3 , P 5 and P 7 .
- the interpolator 130 selects one of the two phase signals P 0 and P 2 (for example, the phase signal P 0 ) come from the multiplexer 110 as a reference signal, and selects one of the two phase signals P 1 and P 3 (for example, the phase signal P 1 ) come from the multiplexer 120 as another reference signal.
- the interpolator 130 receives a reference signal (for example, the phase signal P 0 ) composed of one of the phase signals P 0 , P 2 , P 4 and P 6 (i.e. the even order signals) through the multiplexer 110 , and receives a reference signal (for example, the phase signal P 1 ) composed of one of the phase signals P 1 , P 3 , P 5 and P 7 (i.e. the odd order signals) through the multiplexer 120 .
- the phase interpolation circuit 100 transmits the selected reference signals to the phase interpolator 130 for phase division.
- the interpolator 130 divides a phase difference between the two reference signals into a plurality of sub-phases according to a digital control signal, and selects one of the sub-phases to generate a differential input signal.
- the interpolator 130 can divide a plurality of the sub-phases between the two reference signals. Moreover, by switching the multiplexers 110 and 120 , the interpolator 130 can receive two reference signals composed of different phase signals, so as to generate more different sub-phases. In addition, in the present embodiment, the interpolator 130 receives the two reference signals in a differential input mode, and generates a differential input signal in a differential output mode. Therefore, the differential input signal of the present embodiment is composed of an input signal CKI and an input signal CKIB.
- the duty-cycle repeater 140 adjusts a duty cycle of the differential input signal to generate a differential output signal with 50% of the duty cycle, where the differential output signal is composed of an output signal CKO and an output signal CKOB.
- the phase interpolation circuit 100 can adjust the duty cycle of the differential output signal through the duty-cycle repeater 140 , so as to resolve a problem of dramatic variation of the duty cycle of the differential output signal due to an influence of a process variation.
- FIG. 2 is a circuit diagram of an interpolator according to an embodiment of the invention.
- the interpolator 130 includes a bias generating unit 210 , a current source 220 , a load unit 240 and an input unit 230 .
- the two reference signals received by the interpolator 130 are respectively the phase signal P 0 and the phase signal P 1 , and for simplicity's sake, the two reference signals are indicated by P 0 and P 1 .
- the digital control signal received by the interpolator 130 is represented as ⁇ bn, . . . , b 1 , b 0 ⁇
- a complement of the digital control signal is represented as ⁇ /bn, . . . , /b 1 , /b 0 ⁇ .
- the bias generating unit 210 generates a plurality of biases VA 0 -VAn according to the digital control signal ⁇ bn, . . . , b 1 , b 0 ⁇ , and generates a plurality of biases VB 0 -VBn according to the complement of the digital control signal ⁇ /bn, . . . , /b 1 , /b 0 ⁇ .
- the current source 220 receives the biases VA 0 -VAn and VB 0 -VBn to generate a current I 1 and a current I 2 .
- the input unit 230 is electrically connected between the load unit 240 and the current source 220 , and switches paths that the currents I 1 and I 2 are conducted to the load unit 240 according to the reference signals P 0 and P 1 . In this way, the input unit 230 generates the differential input signal composed of the input signals CKI and CKIB.
- the interpolator 130 not only avails implementing a low-voltage operation, but also avails reducing a parasitic capacitance effect, so as to achieve a better performance under a high-speed operation environment.
- the current source 220 includes N-type transistors MN 11 -MN 1 n and N-type transistors MN 21 -MN 2 n. Drains of the N-type transistors MN 11 -Mn 1 n and MN 21 -MN 1 are electrically connected to the input unit 230 , and sources of the N-type transistors MN 11 -Mn 1 n and MN 21 -MN 1 are electrically connected to ground.
- the N-type transistors MN 11 -Mn 1 n and the N-type transistors MN 21 -MN 1 are controlled by the biases VA 0 -VAn and VB 0 -VBn generated by the bias generating unit 210 for adjusting magnitudes of the currents I 1 and I 2 .
- the input unit 230 includes N-type transistors MN 3 -MN 6 . Drains of the N-type transistors MN 3 -MN 6 are electrically connected to the load unit 240 . Moreover, sources of the N-type transistors MN 3 and MN 4 are electrically connected to the drains of the N-type transistors MN 11 -MN 1 n, and sources of the N-type transistors MN 5 and MN 6 are electrically connected to the drains of the N-type transistors MN 21 -MN 2 n.
- the N-type transistors MN 3 and MN 4 form a differential input pair, and gates thereof respectively receive the reference signal P 0 and an inverted signal /P 0 of the reference signal P 0 .
- the N-type transistors MN 5 and MN 6 form another differential input pair, and gates thereof respectively receive the reference signal P 1 and an inverted signal /P 1 of the reference signal P 1 .
- the load unit 240 includes P-type transistors MP 5 -MP 8 .
- Sources of the P-type transistors MP 5 -MP 8 receive a power voltage VD.
- a gate of the P-type transistor MP 6 is electrically connected to a drain thereof, and a gate of the P-type transistor MP 8 is electrically connected to a drain thereof, so as to respectively form the diode structure.
- the P-type transistor MP 5 and the P-type transistor MP 6 are electrically connected in parallel, and a gate of the P-type transistor MP 5 receives a fixed voltage VT 2 .
- the P-type transistor MP 7 and the P-type transistor MP 8 are electrically connected in parallel, and a gate of the P-type transistor MP 7 receives the fixed voltage VT 2 .
- the two P-type transistors connected in parallel can provide better linearity and anti-noise capability.
- the bias generating unit 210 includes P-type transistors MP 11 -MP 1 n, P-type transistors MP 21 -MP 2 n, P-type transistors MP 31 -MP 3 n, and P-type transistors MP 41 -MP 4 n.
- a source of the P-type transistor MP 11 receives the power voltage VD
- a gate of the P-type transistor MP 11 receives a bit b 0 of the digital control signal
- a drain of the P-type transistor MP 11 is electrically connected to a gate of the N-type transistor MN 1 in the current source 220 .
- a source of the P-type transistor MP 21 is electrically connected to the drain of the P-type transistor MP 11 , a gate of the P-type transistor MP 21 receives a fixed voltage VT 1 , and a drain of the P-type transistor MP 21 is electrically connected to the ground. Deduced by analogy for connections of the P-type transistors MP 12 -MP 1 n and the P-type transistors MP 22 -MP 2 n.
- connections between the P-type transistors MP 31 -MP 3 n and the P-type transistors MP 41 -MP 4 n are similar to that between the P-type transistors MP 11 -MP 1 n and the P-type transistors MP 21 -MP 2 n, though a main difference there between is that the gates of the P-type transistors MP 11 -MP 1 n receive the digital control signal ⁇ bn, . . . , b 1 , b 0 ⁇ , and the gates of the P-type transistors MP 31 -MP 3 n receive the complement of the digital control signal ⁇ /bn, . . . , /b 1 , /b 0 ⁇ . Therefore, in an actual operation, conducting states of the P-type transistors MP 11 -MP 1 n are just opposite to conducting states of the P-type transistors MP 31 -MP 3 n.
- the interpolator 130 applies a differential input and differential output structure, so that each of the units has a similar structure to receive or generate an inverted signal.
- the phase interpolation performed by the interpolator 130 can be represented by a following equation (1):
- ⁇ AB w W ⁇ ⁇ A + W - w W ⁇ ⁇ B ( 1 )
- ⁇ A and ⁇ B are respectively phases of the reference signals P 0 and P 1 , W is a total interpolation amount, w is an interpolation amount, ⁇ AB is an interpolated phase of the differential input signal.
- the fixed voltage VT 1 in the bias generating unit 210 is use to bias the P-type transistors MP 21 -MP 2 n and the P-type transistors MP 41 -MP 4 n to a linear region. Therefore, regarding the P-type transistors MP 11 and MP 21 connected in series, when the P-type transistor MP 11 is turned on, the bias VA 0 is pulled up to the power voltage VD. Now, the N-type transistor MN 11 in the current source 220 is turned on to increase a current amount of the current I 1 . Comparatively, when the P-type transistor MP 11 is turned off, the bias VA 0 is pulled down to the ground level.
- the N-type transistor MN 11 in the current source 220 is turned off, and the current amount of the current I 1 is decreased.
- a conducted number of the N-type transistors MN 11 -MN 1 n and MN 21 -MN 2 n in the current source 220 is different.
- the currents I 1 and I 2 provided by the current source 220 are also varied, so as to adjust the interpolation amount w during the phase interpolation.
- the current source 220 includes six N-type transistors MN 11 -MN 13 and MN 21 -MN 23 , and the phases of the reference signals P 0 and P 1 are respectively 0° and 45°, in control of the interpolation phase, a resolution of the digital control signal is three bits.
- the digital control signal is ⁇ 011 ⁇
- only the P-type transistor MP 11 of the three P-type transistors MP 11 -MP 13 is turned on.
- FIG. 3 is a circuit diagram of a duty-cycle repeater according to an embodiment of the invention.
- the duty-cycle repeater 140 includes phase blenders 311 - 314 and inverters 321 - 324 .
- An input terminal of the inverter 322 is electrically connected to output terminals of the phase blender 311 and the phase blender 312 , simultaneously, and an input terminal of the phase blender 312 is electrically connected to an output terminal of the inverter 321 .
- the phase bender 311 inverts the input signal CKI and adjusts a duty cycle of the inverted input signal CKI.
- the inverter 321 inverts the input signal CKIB to generate an inverting input signal /CKIB.
- the phase blender 312 inverts the inverting input signal /CKIB, and adjusts a duty cycle of the inverted inverting input signal /CKIB.
- an input terminal of the inverter 324 is electrically connected to output terminals of the phase blender 313 and the phase blender 314 , simultaneously, and an input terminal of the phase blender 314 is electrically connected to an output terminal of the inverter 323 .
- the phase bender 313 inverts the input signal CKIB and adjusts a duty cycle of the inverted input signal CKIB.
- the inverter 323 inverts the input signal CKI to generate an inverting input signal /CKI.
- the phase blender 314 inverts the inverting input signal /CKI, and adjusts a duty cycle of the inverted inverting input signal /CKI.
- FIG. 4 is a circuit diagram of a phase blender according to an embodiment of the invention.
- the circuit of the present embodiment is used replace a conventional phase blender, therefore, when the circuit of the present embodiment is applied to the embodiment of FIG. 3 , sizes of the phase blenders 311 , 312 , 313 and 314 are equivalent, which is different to the conventional inverter-based phase blenders that have a shortage that the sizes of the four phase blenders are not equivalent if the output phase is accurately adjusted to 50%.
- B. W. Garlepp et al. “A Portable Digital DLL for High-Speed CMOS Interface Circuits”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, No. 5, pp. 632-644, May 1999.
- the phase blender 311 includes P-type transistors MP 9 -MP 11 , N-type transistors MN 7 -MN 9 , a delay device 410 and an inverter 420 .
- Sources of the P-type transistor MP 9 and the P-type transistor MP 10 receive the power voltage VD.
- a gate of the P-type transistor MP 9 is electrically connected to the ground, and a drain of the P-type transistor MP 9 is electrically connected to a drain of the P-type transistor MP 10 .
- a source of the P-type transistor MP 11 is electrically connected to the drain of the P-type transistor MP 10 , a gate of the P-type transistor MP 11 receives the input signal CKI, and a drain of the P-type transistor MP 11 is electrically connected to the inverter 322 .
- a drain of the N-type transistor MN 7 is electrically connected to the drain of the P-type transistor MP 11 , a gate of the N-type transistor MN 7 receives the input signal CKI.
- Drains of the N-type transistor MN 8 and the N-type transistor MN 9 are electrically connected to a source of the N-type transistor MN 7 .
- a gate of the N-type transistor MN 8 receives the power voltage VD, and a drain of the N-type transistor MN 8 is electrically connected to the ground.
- a gate of the N-type transistor MN 9 is electrically connected to the gate of the P-type transistor MP 10 , and a drain of the N-type transistor MN 9 is electrically connected to the ground.
- the delay device 410 delays the input signal CKI.
- the inverter 420 inverts the delayed input signal CKI, and outputs a signal to the gate of the N-type transistor MN 9 and the gate of the P-type transistor MP 10 .
- the P-type transistor MP 11 and the N-type transistor MN 7 form an inverter to invert the input signal CKI.
- the input signal CKI is delayed by the delay device 410 and is inverted by the inverter 420 .
- the output signal of the inverter 420 is used to control the P-type transistor MP 10 and the N-type transistor MN 9 , so as to adjust a charging current supplied to the P-type transistor MP 11 and a discharging current flowing through the N-type transistor MN 7 .
- the charging current supplied to the P-type transistor MP 11 is increased, and the discharging current flowing through the N-type transistor MN 7 is decreased, so that the duty cycle of the inverted input signal CKI is increased.
- the level of the output signal generated by the inverter 420 is increased, the duty cycle of the inverted input signal CKI is decreased. In this way, during a process of inverting the input signal CKI, the duty cycle of the inverted input signal CKI can be adjusted.
- the duty-cycle repeater is used to adjust the duty cycle of the signal output by the phase interpolator, so as to resolve the problem of dramatic variation of the duty cycle thereof due to influence of a process variation.
- the bias generating unit in the interpolator is independently configured outside the cascade structure. In this way, the interpolator avails implementing a low-voltage operation, and an operation range of the phase interpolation circuit is expanded.
Abstract
Description
- This application claims the priority benefit of Taiwan application serial no. 100133747, filed on Sep. 20, 2011. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
- 1. Field of the Invention
- The invention relates to a phase interpolation circuit. Particularly, the invention relates to a phase interpolation circuit capable of generating a differential output signal with 50% of duty cycle.
- 2. Description of Related Art
- In a high-speed transmission interface module (for example, a universal serial bus (USB) 3.0 interface module), a clock and data recovery circuit is generally configured to recover signals containing noise components, where a phase interpolation circuit is a core circuit composing the clock and data recovery circuit. Therefore, it is an important issue to ameliorate the phase interpolation circuit to improve whole performance of the clock and data recovery circuit.
- Generally, the phase interpolation circuit can be implemented through current mode logic to cope with the requirement of a high-speed transmission. However, the phase interpolation circuit of the current mode logic has following disadvantages: (1) a linearity thereof is liable to be influenced by a parasitic capacitance and a front-end circuit load, so that a duty cycle of an output signal has a great variation, especially under an influence of process variation; (2) it is of no avail for low-voltage operations, which leads to a limited operating range.
- Therefore, how to adjust the duty cycle of the output signal or implement the low-voltage operations is an important issue to be developed in design of the phase interpolation circuit.
- The invention is directed to a phase interpolation circuit, in which a duty-cycle repeater is used to adjust a duty cycle of a differential output signal. In this way, a problem of dramatic variation of the duty cycle of the differential output signal due to an influence of process variation is resolved.
- The invention provides a phase interpolation circuit including a first multiplexer, a second multiplexer, an interpolator and a duty-cycle repeater. The first multiplexer receives a plurality of even order signals. The second multiplexer receives a plurality of odd order signals. The interpolator receives a first reference signal composed of one of the even order signals through the first multiplexer, and receives a second reference signal composed of one of the odd order signals through the second multiplexer. The interpolator divides a phase difference between the first reference signal and the second reference signal into a plurality of sub-phases according to a digital control signal, and selects one of the sub-phases to generate a differential input signal. The duty-cycle repeater adjusts a duty cycle of the differential input signal to generate a differential output signal with 50% of the duty cycle.
- In an embodiment of the invention, the first multiplexer selects two even order signals complementing each other from the even order signals, and the interpolator selects one of the two selected even order signals as the first reference signal. Moreover, the second multiplexer selects two odd order signals complementing each other from the odd order signals, and the interpolator selects one of the two selected odd order signals as the second reference signal.
- In an embodiment of the invention, the interpolator includes a bias generating unit, a current source, a load unit and an input unit. The bias generating unit generates a plurality of first biases according to the digital control signal, and generates a plurality of second biases according to a complement of the digital control signal. The current source receives the first biases and the second biases to generate a first current and a second current. The input unit is electrically connected between the load unit and the current source, and switches paths that the first current and the second current are conducted to the load unit according to the first reference signal and the second reference signal, so as to generate the differential input signal.
- According to the above descriptions, the duty-cycle repeater is used to adjust the duty cycle of the differential output signal to avoid dramatic variation of the duty cycle of the differential output signal due to influence of a process variation. Moreover, the bias generating unit in the interpolator is independently configured outside a cascade structure formed by the load unit, the input unit and the current source. In this way, the interpolator avails implementing a low-voltage operation, and an operation range of the phase interpolation circuit is expanded.
- In order to make the aforementioned and other features and advantages of the invention comprehensible, several exemplary embodiments accompanied with figures are described in detail below.
- The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
-
FIG. 1 is a block schematic diagram of a phase interpolation circuit according to an embodiment of the invention. -
FIG. 2 is a circuit diagram of an interpolator according to an embodiment of the invention. -
FIG. 3 is a circuit diagram of a duty-cycle repeater according to an embodiment of the invention. -
FIG. 4 is a circuit diagram of a phase blender according to an embodiment of the invention. -
FIG. 1 is a block schematic diagram of a phase interpolation circuit according to an embodiment of the invention. Referring toFIG. 1 , thephase interpolation circuit 100 includes amultiplexer 110, amultiplexer 120, aninterpolator 130 and a duty-cycle repeater 140. Thephase interpolation circuit 100 can be used in a clock and data recovery circuit, especially in a clock and data recovery circuit of a high-speed transmission interface module (for example, a universal serial bus (USB) 3.0 interface module). - Referring to
FIG. 1 , themultiplexer 110 and themultiplexer 120 respectively receive a plurality of phase signals. For example, in an exemplary embodiment, by equally dividing 360 degrees into 8 parts, 8 phase signals P0-P7, i.e. 0°, 45°, 90°, 135°, . . . , 315° are obtained. The 8 phase signals P0-P7 respectively have a phase difference of 45°. Moreover, the phase signals P0, P2, P4 and P6 are respectively an even multiple of the basic phase of 45°, so that the phase signals P0, P2, P4 and P6 can be regarded as even order signals. Moreover, the phase signals P1, P3, P5 and P7 are respectively an odd multiple of the basic phase of 45°, so that the phase signals P1, P3, P5 and P7 can be regarded as odd order signals. - In an exemplary embodiment, the
multiplexer 110 receives four phase signals P0, P2, P4 and P6, i.e. four even order signals P0, P2, P4 and P6. Moreover, themultiplexer 120 receives four phase signals P1, P3, P5 and P7, i.e. four odd order signals P1, P3, P5 and P7. In other words, to facilitate a phase control, a method of parity separation is used to distribute the phase signals to the two multiplexers, for example, themultiplexer 110 receives the phase signals of the even orders (P0, P2, P4 and P6) (i.e. the even order signals), and thesecond multiplexer 120 receives the phase signals of the odd orders (P1, P3, P5 and P7) (i.e. the odd order signals). - The
multiplexer 110 and themultiplexer 120 respectively select two phase signals for outputting. For example, in the present embodiment, themultiplexer 110 selects the phase signal P0 and the phase signal P2 complementing to each other from the phase signals P0, P2, P4 and P6, and themultiplexer 120 selects the phase signal P1 and the phase signal P3 complementing to each other from the phase signals P1, P3, P5 and P7. Moreover, theinterpolator 130 selects one of the two phase signals P0 and P2 (for example, the phase signal P0) come from themultiplexer 110 as a reference signal, and selects one of the two phase signals P1 and P3 (for example, the phase signal P1) come from themultiplexer 120 as another reference signal. - In other words, the
interpolator 130 receives a reference signal (for example, the phase signal P0) composed of one of the phase signals P0, P2, P4 and P6 (i.e. the even order signals) through themultiplexer 110, and receives a reference signal (for example, the phase signal P1) composed of one of the phase signals P1, P3, P5 and P7 (i.e. the odd order signals) through themultiplexer 120. After the operation of signal selection is completed, thephase interpolation circuit 100 transmits the selected reference signals to thephase interpolator 130 for phase division. Here, theinterpolator 130 divides a phase difference between the two reference signals into a plurality of sub-phases according to a digital control signal, and selects one of the sub-phases to generate a differential input signal. - In this way, the
interpolator 130 can divide a plurality of the sub-phases between the two reference signals. Moreover, by switching themultiplexers interpolator 130 can receive two reference signals composed of different phase signals, so as to generate more different sub-phases. In addition, in the present embodiment, theinterpolator 130 receives the two reference signals in a differential input mode, and generates a differential input signal in a differential output mode. Therefore, the differential input signal of the present embodiment is composed of an input signal CKI and an input signal CKIB. - On the other hand, the duty-
cycle repeater 140 adjusts a duty cycle of the differential input signal to generate a differential output signal with 50% of the duty cycle, where the differential output signal is composed of an output signal CKO and an output signal CKOB. In other words, thephase interpolation circuit 100 can adjust the duty cycle of the differential output signal through the duty-cycle repeater 140, so as to resolve a problem of dramatic variation of the duty cycle of the differential output signal due to an influence of a process variation. - In order to fully convey the spirit of the invention to those skilled in the art, detailed structures of the
interpolator 130 and the duty-cycle repeater 140 are described below. -
FIG. 2 is a circuit diagram of an interpolator according to an embodiment of the invention. Referring toFIG. 2 , theinterpolator 130 includes abias generating unit 210, acurrent source 220, aload unit 240 and aninput unit 230. Here, it is assumed that the two reference signals received by theinterpolator 130 are respectively the phase signal P0 and the phase signal P1, and for simplicity's sake, the two reference signals are indicated by P0 and P1. Moreover, the digital control signal received by theinterpolator 130 is represented as {bn, . . . , b1, b0}, and a complement of the digital control signal is represented as {/bn, . . . , /b1, /b0}. - As shown in
FIG. 2 , thebias generating unit 210 generates a plurality of biases VA0-VAn according to the digital control signal {bn, . . . , b1, b0}, and generates a plurality of biases VB0-VBn according to the complement of the digital control signal {/bn, . . . , /b1, /b0}. Thecurrent source 220 receives the biases VA0-VAn and VB0-VBn to generate a current I1 and a current I2. Theinput unit 230 is electrically connected between theload unit 240 and thecurrent source 220, and switches paths that the currents I1 and I2 are conducted to theload unit 240 according to the reference signals P0 and P1. In this way, theinput unit 230 generates the differential input signal composed of the input signals CKI and CKIB. - It should be noticed that regarding a circuit structure of the
interpolator 130, theload unit 240, theinput unit 230 and thecurrent source 220 are connected in cascade to form a cascade structure of three stacked layers, and thebias generating unit 210 is independently configured outside the cascade structure. Moreover, the more the number of the stacked layer is, the greater a power voltage required by the circuit is. Therefore, compared to the conventional interpolator, since the conventional interpolator has a cascade structure of more than four stacked layers, theinterpolator 130 of the present embodiment not only avails implementing a low-voltage operation, but also avails reducing a parasitic capacitance effect, so as to achieve a better performance under a high-speed operation environment. - Further, the
current source 220 includes N-type transistors MN11-MN1 n and N-type transistors MN21-MN2 n. Drains of the N-type transistors MN11-Mn1 n and MN21-MN1 are electrically connected to theinput unit 230, and sources of the N-type transistors MN11-Mn1 n and MN21-MN1 are electrically connected to ground. Moreover, the N-type transistors MN11-Mn1 n and the N-type transistors MN21-MN1 are controlled by the biases VA0-VAn and VB0-VBn generated by thebias generating unit 210 for adjusting magnitudes of the currents I1 and I2. - The
input unit 230 includes N-type transistors MN3-MN6. Drains of the N-type transistors MN3-MN6 are electrically connected to theload unit 240. Moreover, sources of the N-type transistors MN3 and MN4 are electrically connected to the drains of the N-type transistors MN11-MN1 n, and sources of the N-type transistors MN5 and MN6 are electrically connected to the drains of the N-type transistors MN21-MN2 n. Here, the N-type transistors MN3 and MN4 form a differential input pair, and gates thereof respectively receive the reference signal P0 and an inverted signal /P0 of the reference signal P0. Similarly, the N-type transistors MN5 and MN6 form another differential input pair, and gates thereof respectively receive the reference signal P1 and an inverted signal /P1 of the reference signal P1. - The
load unit 240 includes P-type transistors MP5-MP8. Sources of the P-type transistors MP5-MP8 receive a power voltage VD. Moreover, a gate of the P-type transistor MP6 is electrically connected to a drain thereof, and a gate of the P-type transistor MP8 is electrically connected to a drain thereof, so as to respectively form the diode structure. Moreover, the P-type transistor MP5 and the P-type transistor MP6 are electrically connected in parallel, and a gate of the P-type transistor MP5 receives a fixed voltage VT2. Similarly, the P-type transistor MP7 and the P-type transistor MP8 are electrically connected in parallel, and a gate of the P-type transistor MP7 receives the fixed voltage VT2. In this way, the two P-type transistors connected in parallel can provide better linearity and anti-noise capability. - The
bias generating unit 210 includes P-type transistors MP11-MP1 n, P-type transistors MP21-MP2 n, P-type transistors MP31-MP3 n, and P-type transistors MP41-MP4 n. A source of the P-type transistor MP11 receives the power voltage VD, A gate of the P-type transistor MP11 receives a bit b0 of the digital control signal, and a drain of the P-type transistor MP11 is electrically connected to a gate of the N-type transistor MN1 in thecurrent source 220. Moreover, a source of the P-type transistor MP21 is electrically connected to the drain of the P-type transistor MP11, a gate of the P-type transistor MP21 receives a fixed voltage VT1, and a drain of the P-type transistor MP21 is electrically connected to the ground. Deduced by analogy for connections of the P-type transistors MP12-MP1 n and the P-type transistors MP22-MP2 n. - Moreover, connections between the P-type transistors MP31-MP3 n and the P-type transistors MP41-MP4 n are similar to that between the P-type transistors MP11-MP1 n and the P-type transistors MP21-MP2 n, though a main difference there between is that the gates of the P-type transistors MP11-MP1 n receive the digital control signal {bn, . . . , b1, b0}, and the gates of the P-type transistors MP31-MP3 n receive the complement of the digital control signal {/bn, . . . , /b1, /b0}. Therefore, in an actual operation, conducting states of the P-type transistors MP11-MP1 n are just opposite to conducting states of the P-type transistors MP31-MP3 n.
- According to the above descriptions, the
interpolator 130 applies a differential input and differential output structure, so that each of the units has a similar structure to receive or generate an inverted signal. Moreover, the phase interpolation performed by theinterpolator 130 can be represented by a following equation (1): -
- Where, ΦA and ΦB are respectively phases of the reference signals P0 and P1, W is a total interpolation amount, w is an interpolation amount, ΦAB is an interpolated phase of the differential input signal.
- In operation, the fixed voltage VT1 in the
bias generating unit 210 is use to bias the P-type transistors MP21-MP2 n and the P-type transistors MP41-MP4 n to a linear region. Therefore, regarding the P-type transistors MP11 and MP21 connected in series, when the P-type transistor MP11 is turned on, the bias VA0 is pulled up to the power voltage VD. Now, the N-type transistor MN11 in thecurrent source 220 is turned on to increase a current amount of the current I1. Comparatively, when the P-type transistor MP11 is turned off, the bias VA0 is pulled down to the ground level. Now, the N-type transistor MN11 in thecurrent source 220 is turned off, and the current amount of the current I1 is decreased. In other words, along with variations of the biases VA0-VAn and VB0-VBn, a conducted number of the N-type transistors MN11-MN1 n and MN21-MN2 n in thecurrent source 220 is different. In this way, the currents I1 and I2 provided by thecurrent source 220 are also varied, so as to adjust the interpolation amount w during the phase interpolation. - For example, if the
current source 220 includes six N-type transistors MN11-MN13 and MN21-MN23, and the phases of the reference signals P0 and P1 are respectively 0° and 45°, in control of the interpolation phase, a resolution of the digital control signal is three bits. Moreover, when the digital control signal is {011}, only the P-type transistor MP11 of the three P-type transistors MP11-MP13 is turned on. Namely, in the three N-type transistors MN11-MN13 used for controlling the current I1, only the N-type transistor MN11 is turned on. Therefore, according to the equation (1), ΦA=0, ΦB=45, W=3 and w=1, so that a phase of the input signal CKI generated by the differential input pair MN3 and MN4 is 30°. -
FIG. 3 is a circuit diagram of a duty-cycle repeater according to an embodiment of the invention. Referring toFIG. 3 , the duty-cycle repeater 140 includes phase blenders 311-314 and inverters 321-324. An input terminal of theinverter 322 is electrically connected to output terminals of thephase blender 311 and thephase blender 312, simultaneously, and an input terminal of thephase blender 312 is electrically connected to an output terminal of theinverter 321. Here, thephase bender 311 inverts the input signal CKI and adjusts a duty cycle of the inverted input signal CKI. - On the other hand, the
inverter 321 inverts the input signal CKIB to generate an inverting input signal /CKIB. Thephase blender 312 inverts the inverting input signal /CKIB, and adjusts a duty cycle of the inverted inverting input signal /CKIB. Moreover, as levels of the input signal CKI and the inverting input signal /CKIB are varied, the twophase blenders inverter 322 in different manners. Therefore, the output signal CKO generated by theinverter 322 can be represented as: CKO=(CKI+/CKIB)/2. Therefore, a duty cycle of the output signal CKO generated by theinverter 322 is adjusted to 50%, and skew of the output signal CKO is eliminated. - Similarly, an input terminal of the
inverter 324 is electrically connected to output terminals of thephase blender 313 and the phase blender 314, simultaneously, and an input terminal of the phase blender 314 is electrically connected to an output terminal of theinverter 323. Here, thephase bender 313 inverts the input signal CKIB and adjusts a duty cycle of the inverted input signal CKIB. Moreover, theinverter 323 inverts the input signal CKI to generate an inverting input signal /CKI. The phase blender 314 inverts the inverting input signal /CKI, and adjusts a duty cycle of the inverted inverting input signal /CKI. Moreover, the output signal CKOB generated by theinverter 324 can be represented as: CKOB=(CKIB+/CKI)/2. Therefore, a duty cycle of the output signal CKOB generated by theinverter 324 is adjusted to 50%, and skew of the output signal CKOB is eliminated. -
FIG. 4 is a circuit diagram of a phase blender according to an embodiment of the invention. The circuit of the present embodiment is used replace a conventional phase blender, therefore, when the circuit of the present embodiment is applied to the embodiment ofFIG. 3 , sizes of thephase blenders FIG. 4 , thephase blender 311 includes P-type transistors MP9-MP11, N-type transistors MN7-MN9, adelay device 410 and aninverter 420. Sources of the P-type transistor MP9 and the P-type transistor MP10 receive the power voltage VD. A gate of the P-type transistor MP9 is electrically connected to the ground, and a drain of the P-type transistor MP9 is electrically connected to a drain of the P-type transistor MP10. A source of the P-type transistor MP11 is electrically connected to the drain of the P-type transistor MP10, a gate of the P-type transistor MP11 receives the input signal CKI, and a drain of the P-type transistor MP11 is electrically connected to theinverter 322. - Moreover, a drain of the N-type transistor MN7 is electrically connected to the drain of the P-type transistor MP11, a gate of the N-type transistor MN7 receives the input signal CKI. Drains of the N-type transistor MN8 and the N-type transistor MN9 are electrically connected to a source of the N-type transistor MN7. Moreover, a gate of the N-type transistor MN8 receives the power voltage VD, and a drain of the N-type transistor MN8 is electrically connected to the ground. A gate of the N-type transistor MN9 is electrically connected to the gate of the P-type transistor MP10, and a drain of the N-type transistor MN9 is electrically connected to the ground. The
delay device 410 delays the input signal CKI. Theinverter 420 inverts the delayed input signal CKI, and outputs a signal to the gate of the N-type transistor MN9 and the gate of the P-type transistor MP10. - In operation, the P-type transistor MP11 and the N-type transistor MN7 form an inverter to invert the input signal CKI. Moreover, the input signal CKI is delayed by the
delay device 410 and is inverted by theinverter 420. Then, the output signal of theinverter 420 is used to control the P-type transistor MP10 and the N-type transistor MN9, so as to adjust a charging current supplied to the P-type transistor MP11 and a discharging current flowing through the N-type transistor MN7. For example, when a level of the output signal generated by theinverter 420 is decreased, the charging current supplied to the P-type transistor MP11 is increased, and the discharging current flowing through the N-type transistor MN7 is decreased, so that the duty cycle of the inverted input signal CKI is increased. Comparatively, when the level of the output signal generated by theinverter 420 is increased, the duty cycle of the inverted input signal CKI is decreased. In this way, during a process of inverting the input signal CKI, the duty cycle of the inverted input signal CKI can be adjusted. - In summary, since a duty cycle of a signal output by the phase interpolator is easy to be varied, in the invention, the duty-cycle repeater is used to adjust the duty cycle of the signal output by the phase interpolator, so as to resolve the problem of dramatic variation of the duty cycle thereof due to influence of a process variation. Moreover, by changing an internal bias, the bias generating unit in the interpolator is independently configured outside the cascade structure. In this way, the interpolator avails implementing a low-voltage operation, and an operation range of the phase interpolation circuit is expanded.
- It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Claims (9)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW100133747A | 2011-09-20 | ||
TW100133747A TW201315155A (en) | 2011-09-20 | 2011-09-20 | Phase interpolation circuit |
TW100133747 | 2011-09-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
US8384458B1 US8384458B1 (en) | 2013-02-26 |
US20130069701A1 true US20130069701A1 (en) | 2013-03-21 |
Family
ID=47721216
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/330,615 Expired - Fee Related US8384458B1 (en) | 2011-09-20 | 2011-12-19 | Phase interpolation circuit |
Country Status (2)
Country | Link |
---|---|
US (1) | US8384458B1 (en) |
TW (1) | TW201315155A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI813197B (en) * | 2022-03-09 | 2023-08-21 | 瑞昱半導體股份有限公司 | Signal conversion circuit and bias voltage generating circuit thereof |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101995389B1 (en) * | 2013-08-20 | 2019-07-02 | 에스케이하이닉스 주식회사 | Phase mixing circuit, semiconductor apparatus and semiconductor system including the same |
US9485084B2 (en) | 2014-06-09 | 2016-11-01 | Qualcomm Incorporated | Linearity of phase interpolators by combining current coding and size coding |
TWI556582B (en) | 2014-06-12 | 2016-11-01 | 財團法人工業技術研究院 | Capacitance phase interpolation circuit and method thereof, and multi-phase generator applying the same |
US9484901B1 (en) * | 2014-10-27 | 2016-11-01 | Altera Corporation | Interpolation circuitry and methods |
US9584304B2 (en) | 2015-03-30 | 2017-02-28 | Global Unichip Corporation | Phase interpolator and clock and data recovery circuit |
CN107147375A (en) * | 2016-03-01 | 2017-09-08 | 成都锐成芯微科技股份有限公司 | Dutycycle circuit for rectifying |
KR102548858B1 (en) | 2017-11-27 | 2023-06-28 | 삼성전자주식회사 | Duty cycle corrector and method of operating the same |
CN110233611B (en) * | 2019-06-18 | 2023-02-28 | 苏州兆凯电子有限公司 | Cascade phase interpolation method and circuit and clock data recovery circuit |
CN114629496A (en) * | 2020-12-11 | 2022-06-14 | 扬智科技股份有限公司 | Phase interpolation device and clock signal selector thereof |
KR20220163795A (en) | 2021-06-03 | 2022-12-12 | 삼성전자주식회사 | Digital phase interpolator, clock signal generator, and volitile memory device including the same |
KR20230169726A (en) * | 2022-06-09 | 2023-12-18 | 에스케이하이닉스 주식회사 | Phase blender circuit and multi-phase clock signal correction circuit including the same |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6121808A (en) * | 1998-05-18 | 2000-09-19 | National Semiconductor Corporation | DLL calibrated phase multiplexer and interpolator |
US6329859B1 (en) * | 2000-03-23 | 2001-12-11 | Bitblitz Communications, Inc. | N-way circular phase interpolator for generating a signal having arbitrary phase |
US6380783B1 (en) * | 2000-10-13 | 2002-04-30 | Silicon Communications Lab, Inc. | Cyclic phase signal generation from a single clock source using current phase interpolation |
US20060039487A1 (en) * | 2004-08-18 | 2006-02-23 | Best Scott C | Clocking architectures in high-speed signaling systems |
US7196564B2 (en) * | 2005-07-22 | 2007-03-27 | Texas Instruments Incorporated | High frequency balanced phase interpolator |
US7256627B1 (en) * | 2005-01-13 | 2007-08-14 | Advanced Micro Devices, Inc. | Alignment of local transmit clock to synchronous data transfer clock having programmable transfer rate |
US20090289676A1 (en) * | 2008-05-22 | 2009-11-26 | Elpida Memory, Inc. | DLL circuit |
US20100079180A1 (en) * | 2008-10-01 | 2010-04-01 | Jin-Gook Kim | Ac-coupling phase interpolator and delay-locked loop using the same |
US20110128061A1 (en) * | 2009-12-02 | 2011-06-02 | Mstar Semiconductor, Inc. | Phase Generating Apparatus and Method Thereof |
US8242821B2 (en) * | 2009-06-17 | 2012-08-14 | Samsung Electronics Co., Ltd. | Delay-locked loop for correcting duty ratio of input clock signal and output clock signal and electronic device including the same |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6111445A (en) | 1998-01-30 | 2000-08-29 | Rambus Inc. | Phase interpolator with noise immunity |
EP1277304B1 (en) | 2000-04-28 | 2009-07-01 | Broadcom Corporation | High-speed serial data transceiver systems and related methods |
US6384653B1 (en) | 2000-08-22 | 2002-05-07 | Cadence Design Systems | Linearly controlled CMOS phase interpolator |
US7180352B2 (en) | 2001-06-28 | 2007-02-20 | Intel Corporation | Clock recovery using clock phase interpolator |
US7197101B2 (en) | 2002-01-02 | 2007-03-27 | Intel Corporation | Phase interpolator based clock recovering |
JP2005050123A (en) | 2003-07-28 | 2005-02-24 | Nec Micro Systems Ltd | Skew correction circuit |
GB0413071D0 (en) | 2004-06-12 | 2004-07-14 | Texas Instruments Ltd | Triangulating phase interpolator |
US7298195B2 (en) | 2005-03-31 | 2007-11-20 | Agere Systems Inc. | Methods and apparatus for improved phase switching and linearity in an analog phase interpolator |
-
2011
- 2011-09-20 TW TW100133747A patent/TW201315155A/en unknown
- 2011-12-19 US US13/330,615 patent/US8384458B1/en not_active Expired - Fee Related
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6121808A (en) * | 1998-05-18 | 2000-09-19 | National Semiconductor Corporation | DLL calibrated phase multiplexer and interpolator |
US6329859B1 (en) * | 2000-03-23 | 2001-12-11 | Bitblitz Communications, Inc. | N-way circular phase interpolator for generating a signal having arbitrary phase |
US6380783B1 (en) * | 2000-10-13 | 2002-04-30 | Silicon Communications Lab, Inc. | Cyclic phase signal generation from a single clock source using current phase interpolation |
US20060039487A1 (en) * | 2004-08-18 | 2006-02-23 | Best Scott C | Clocking architectures in high-speed signaling systems |
US7256627B1 (en) * | 2005-01-13 | 2007-08-14 | Advanced Micro Devices, Inc. | Alignment of local transmit clock to synchronous data transfer clock having programmable transfer rate |
US7196564B2 (en) * | 2005-07-22 | 2007-03-27 | Texas Instruments Incorporated | High frequency balanced phase interpolator |
US20090289676A1 (en) * | 2008-05-22 | 2009-11-26 | Elpida Memory, Inc. | DLL circuit |
US20100079180A1 (en) * | 2008-10-01 | 2010-04-01 | Jin-Gook Kim | Ac-coupling phase interpolator and delay-locked loop using the same |
US8242821B2 (en) * | 2009-06-17 | 2012-08-14 | Samsung Electronics Co., Ltd. | Delay-locked loop for correcting duty ratio of input clock signal and output clock signal and electronic device including the same |
US20110128061A1 (en) * | 2009-12-02 | 2011-06-02 | Mstar Semiconductor, Inc. | Phase Generating Apparatus and Method Thereof |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI813197B (en) * | 2022-03-09 | 2023-08-21 | 瑞昱半導體股份有限公司 | Signal conversion circuit and bias voltage generating circuit thereof |
Also Published As
Publication number | Publication date |
---|---|
US8384458B1 (en) | 2013-02-26 |
TW201315155A (en) | 2013-04-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8384458B1 (en) | Phase interpolation circuit | |
JP4049511B2 (en) | Phase synthesis circuit and timing signal generation circuit | |
US8659341B2 (en) | System and method for level-shifting voltage signals using a dynamic level-shifting architecture | |
US8441279B2 (en) | Scan flip-flop circuits and scan test circuits including the same | |
KR20100104124A (en) | Logic circuit capable of level shifting | |
US9018990B2 (en) | Duty cycle tuning circuit and method thereof | |
US8384438B1 (en) | Single-to-differential conversion circuit and method | |
US20050280442A1 (en) | Semiconductor integrated circuit | |
EP3228009B1 (en) | Power efficient high speed latch circuits and systems | |
US7932766B2 (en) | Digitally controlled oscillator with the wide operation range | |
JP2002014743A (en) | Circuit and method for clock control | |
Singhvi et al. | A fine-grained, uniform, energy-efficient delay element for FD-SOI technologies | |
JP6134536B2 (en) | Output device | |
JP2007067819A (en) | Delay adjusting circuit and synchronous type semiconductor device equipped with the circuit | |
JP2011103607A (en) | Input circuit | |
JP2003234646A5 (en) | ||
US7157951B1 (en) | Digital clock manager capacitive trim unit | |
JP5618275B2 (en) | Multiplexer, demultiplexer, look-up table and integrated circuit using CMOS inverter | |
US20130135020A1 (en) | Multi-phase clock signal generation circuits | |
US20130038370A1 (en) | Multi-phase clock generator | |
US20120025888A1 (en) | Drive Strength Control of Phase Rotators | |
KR101342093B1 (en) | Delay line | |
US7667520B2 (en) | Level shift device having reduced error in the duty ratio of the output signal | |
JP5772188B2 (en) | Phase interpolation circuit and semiconductor device | |
CN107404316B (en) | Signal multiplexing device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SUNPLUS TECHNOLOGY CO., LTD., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HUANG, CHEN-WEI;REEL/FRAME:027413/0938 Effective date: 20111124 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FEPP | Fee payment procedure |
Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
LAPS | Lapse for failure to pay maintenance fees |
Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20210226 |