US20130093062A1 - Semiconductor structure and process thereof - Google Patents

Semiconductor structure and process thereof Download PDF

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Publication number
US20130093062A1
US20130093062A1 US13/276,306 US201113276306A US2013093062A1 US 20130093062 A1 US20130093062 A1 US 20130093062A1 US 201113276306 A US201113276306 A US 201113276306A US 2013093062 A1 US2013093062 A1 US 2013093062A1
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Prior art keywords
recess
predetermined depth
sidewall
semiconductor
semiconductor structure
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Abandoned
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US13/276,306
Inventor
Ying-Chih Lin
Hsuan-Hsu Chen
Jiunn-Hsiung Liao
Lung-En Kuo
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US13/276,306 priority Critical patent/US20130093062A1/en
Assigned to UNITED MICROELECTRONICS CORP. reassignment UNITED MICROELECTRONICS CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, HSUAN-HSU, KUO, LUNG-EN, LIAO, JIUNN-HSIUNG, LIN, YING-CHIH
Publication of US20130093062A1 publication Critical patent/US20130093062A1/en
Priority to US14/054,811 priority patent/US9013024B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate

Definitions

  • the present invention relates generally to a semiconductor structure and process thereof, and more specifically, to a semiconductor structure and process thereof, which laterally etches a part of a recess to make parts of the recess have different widths or different slopes of sidewalls.
  • Fin-shaped field effect transistor (FinFET) With increasing miniaturization of semiconductor devices, various Fin-shaped field effect transistor (FinFET) devices have been developed.
  • the Fin-shaped field effect transistor (FinFET) is advantageous for the following reasons.
  • manufacturing processes of Fin-shaped field effect transistor (FinFET) devices can be integrated into traditional logic device processes, and thus are more compatible.
  • the channel region is controlled more effectively. This therefore reduces drain-induced barrier lowering (DIBL) effect and short channel effect.
  • DIBL drain-induced barrier lowering
  • the channel region is longer for the same gate length. Therefore, the current between the source and the drain is increased.
  • the Fin-shaped field effect transistor includes a plurality of fin-shaped structures, and gate structures disposed across them. Therefore, the sidewall of the upper part of the recess between each fin-shaped structure is covered by gate structures and the inclined angle of the sidewall of the upper part of the recess would affect the shape of gate structures.
  • the sidewall of the upper part of the recess is preferred to be a vertical sidewall for approaching the demands of the gate structures disposed across the fin-shaped structures, thereby the electrical performance of the Fin-shaped field effect transistor (FinFET) can be achieved.
  • the sidewall of the recess etched by current processes has an inclined angle that can not approach the structural demand of a Fin-shaped field effect transistor (FinFET).
  • the present invention provides a semiconductor structure and process thereof, which laterally etches the sidewall of the upper part of a recess, to make the minimum width of the upper part of the recess larger than the maximum width of the lower part; or, to make the inclined angle of the sidewall of the upper part of the recess different from inclined angle of the sidewall of the lower part of the recess.
  • the present invention provides a semiconductor structure including a substrate, a recess and a material.
  • the recess is located in the substrate, wherein the recess has an upper part and a lower part.
  • the minimum width of the upper part is larger than the maximum width of the lower part.
  • the material is located in the recess.
  • the present invention provides a semiconductor process including the following steps.
  • a substrate is provided.
  • a recess is formed in the substrate and the recess has a first sidewall.
  • a material is filled in the recess and a part of the recess is exposed.
  • An etching process is performed to laterally etch the exposing part of the recess, therefore the recess includes an upper part and a lower part, wherein the upper part has a second sidewall and the lower part has the first sidewall.
  • the present invention provides a semiconductor structure and process thereof, which performs an etching process to laterally etch the recess, and the desired sidewall profile of the recess is therefore formed.
  • FIGS. 1-11 schematically depict a cross-sectional view of a semiconductor process according to one preferred embodiment of the present invention.
  • a Fin-shaped field effect transistor (FinFET) applying the present invention is used as an example illustrated in the following, but the present invention is not merely suited for forming a Fin-shaped field effect transistor (FinFET).
  • the present invention can also be applied to form other semiconductor components, which change recess profiles by performing etching processes.
  • the Fin-shaped field effect transistor (FinFET) applying the present invention has particular features, which are described as follows.
  • FIGS. 1-11 schematically depict a cross-sectional view of a semiconductor process according to one preferred embodiment of the present invention.
  • a substrate 110 is provided.
  • the substrate 110 may be a semiconductor substrate such as a silicon substrate, a silicon containing substrate, a III-V group-on-silicon (such as GaN-on-silicon) substrate, a graphene-on-silicon substrate or a silicon-on-insulator (SOI) substrate.
  • a pad oxide layer 122 and a pad nitride layer 124 are sequentially formed on the substrate 110 .
  • the pad oxide layer 122 includes an oxide layer, which may be formed by a thermal oxide process, a chemical oxide process, a chemical deposition process, etc.
  • the pad oxide layer 122 may be a silicon oxide layer formed by a thermal oxide layer.
  • the pad nitride layer 124 includes a nitride layer, which may be formed by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process or other suitable processes.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • the pad oxide layer 122 and the pad nitride layer 124 constitute a hard mask layer 120 , for etching the substrate 110 in the following processing steps.
  • a mask layer 130 is formed to pattern the hard mask layer 120 .
  • the mask layer 130 may be a single layer structure or a multi-layer structure.
  • the mask layer 130 is a multi-layer structure composed of an oxide layer 132 , an advance patterning film 134 , a dielectric anti-reflection coating (DARC) layer 136 , a bottom anti-reflective coating (BARC) layer 138 , a photoresist layer 139 , etc.
  • the oxide layer 132 , the advance patterning film 134 , the dielectric anti-reflection coating (DARC) layer 136 , the bottom anti-reflective coating (BARC) layer 138 and the photoresist layer 139 are sequentially formed on the hard mask layer 120 . Then, the mask layer 130 is patterned.
  • the photoresist layer 139 is patterned by exposing once or many times and then the pattern of the photoresist layer 139 is transferred once or many times to the bottom anti-reflective coating (BARC) layer 138 , the dielectric anti-reflection coating (DARC) layer 136 , the advance patterning film 134 and the oxide layer 132 .
  • BARC bottom anti-reflective coating
  • DARC dielectric anti-reflection coating
  • the hard mask layer 120 is patterned by using the mask layer 130 as a mask and then the mask layer 130 is removed.
  • the substrate 110 is etched by the hard mask layer 120 and at least a recess R is formed.
  • the size of each recess may be common or different. As the recesses have different sizes, the depths of the recesses are different.
  • the recess R has a first sidewall S 1 , and the recess R has a first predetermined depth d 1 .
  • the first sidewall S 1 is an upward-broadened oblique sidewall.
  • the first sidewall S 1 may have another shape.
  • the first predetermined depth d 1 is 2000 angstroms, according to the processing size commonly used in modern processes, but it is not limited thereto.
  • a material 140 is filled in the recess R and a part of the recess R is exposed, wherein the material of the material 140 may be oxide, and the part of the recess R has a second predetermined depth d 2 .
  • the material 140 entirely covers the recess R and the hard mask layer 120 .
  • the material 140 may fill up or partially fill the recess R, as long as the depth d 2 ′ of the top surface Q 1 of the material 140 is smaller than the second predetermined depth d 2 .
  • the material 140 is etched back until exposing the part of recess with the second predetermined depth d 2 .
  • the distance between the surface Q 2 of the material 140 and the top surface the substrate 110 is equal to the second predetermined depth d 2 .
  • the surface Q 2 of the material 140 is essentially parallel with a level and the surface Q 2 of the material 140 is a flat surface.
  • an etching process E is performed to laterally etch the exposing part of the recess R. Therefore, the recess R includes an upper part P 1 and a lower part P 2 .
  • the minimum width of the upper part P 1 is larger than the maximum width of the lower part P 2 .
  • the etching process E may include a dry etching process, such as a tetrafluoromethane, helium and oxygen containing dry etching process, but it is not limited thereto.
  • the sidewall profile of the exposing part of the recess R such as the inclined angle or the shape of the sidewall, can be controlled precisely by adjusting the processing parameters.
  • the connecting point of the upper part P 1 and the lower part P 2 has a turning point C.
  • the present invention is applied to form a Fin-shaped field effect transistor (FinFET) in this embodiment.
  • the upper part P 1 has a second sidewall S 2 and the lower part P 2 has the first sidewall S 1 .
  • the first sidewall S 1 and the second sidewall S 2 are upward-broadened oblique sidewalls.
  • the acute angle ⁇ 2 between the second sidewall S 2 and a level h is larger than the acute angle ⁇ 1 between the first sidewall S 1 and the level h.
  • the acute angle ⁇ 2 between the second sidewall S 2 and the level h is larger than 89°.
  • the second sidewall S 2 is essentially vertical to the level h.
  • a plurality of protruding parts 112 of the substrate 110 are suited for use as fin-shaped structures of a Fin-shaped field effect transistor (FinFET).
  • the numbers of the protruding parts 112 depend upon the needs.
  • the etching process E just laterally etches the exposing part of the recess R and the upper part P 1 is therefore formed. So, the length of the second sidewall S 2 of the upper part P 1 is equal to the second predetermined depth d 2 . If the first predetermined depth d 1 is 2000 angstroms, the second predetermined depth d 2 is preferred to be 400 angstroms (which is the thickness of the fin-shaped structures of the following formed Fin-shaped field effect transistor (FinFET)).
  • the material 140 is filled in the recess R and a part of the recess R with a third predetermined depth d 3 is exposed.
  • the processing steps include: as shown in FIG. 6 , the material 140 entirely covers the recess R and the hard mask layer 120 .
  • the material 140 is polished by methods such as a chemical mechanical polishing (CMP) process and the top surface of the material 140 therefore flushes with the top surface T of the hard mask layer 120 .
  • CMP chemical mechanical polishing
  • the material 140 is etched back until exposing the part of the recess R with the third predetermined depth d 3 .
  • the distance between the top surface Q 3 of the material 140 and the top surface of the substrate 110 is equal to the third predetermined depth d 3 .
  • the third predetermined depth d 3 is preferred to be 250 angstroms (which is the thickness that a gate structure of the following formed Fin-shaped field effect transistor (FinFET) can be disposed thereon).
  • the pad nitride layer 124 is removed. As shown in FIG. 10 , the pad oxide layer 122 is removed, meaning the semiconductor structure 100 is complete.
  • the semiconductor structure 100 shown in FIG. 10 is formed.
  • the semiconductor structure 100 includes the substrate 110 , the recess R and the material 140 .
  • the recess R having an upper part P 1 and a lower part P 2 is located in the substrate 110 .
  • the minimum width w 1 of the upper part P 1 is larger than the maximum w 2 of the lower part P 2 .
  • the material 140 is located in the recess R.
  • the connecting point of the upper part P 1 and the lower part P 2 has a turning point C.
  • the semiconductor structure 100 is used to form a Fin-shaped field effect transistor (FinFET) in this embodiment.
  • the upper part P 1 has the second sidewall S 2 and the lower part P 2 has the first sidewall S 1 .
  • the first sidewall 51 and the second sidewall S 2 are upward-broadened oblique sidewalls.
  • the acute angle ⁇ 2 between the second sidewall S 2 and the level h is larger than the acute angle ⁇ 1 between the first sidewall S 1 and the level h.
  • the acute angle ⁇ 2 between the second sidewall S 2 and the level h is larger than 89°.
  • the second sidewall S 2 is essentially vertical to the level h.
  • a plurality of protruding parts 112 of the substrate 110 can be fin-shaped structures of a Fin-shaped field effect transistor (FinFET), suited for having a gate structure formed thereon.
  • FinFET Fin-shaped field effect transistor
  • the first predetermined depth d 1 is 2000 angstroms
  • the second predetermined depth d 2 is preferred to be 400 angstroms
  • the third predetermined depth d 3 is preferred to be 250 angstroms.
  • a Fin field-effect transistor, a Tri-gate MOSFET or etc. may be sequentially formed.
  • a gate dielectric layer (not shown), a gate electrode layer (not shown) and a cap layer (not shown) cover the protruding parts 112 and the material 140 .
  • the cap layer (not shown), the gate electrode layer (not shown) and gate dielectric layer (not shown) are patterned to form a gate structure G, wherein the gate structure G includes a gate dielectric layer 152 , a gate electrode layer 154 and a cap layer 156 .
  • a spacer 160 is formed beside the gate structure G.
  • Each protruding parts 112 are used as a fin-shaped structure of a Fin field-effect transistor, a Tri-gate MOSFET or etc.
  • the material 140 located in the recess R is used to isolate transistors on each protruding parts 112
  • the present invention provides a semiconductor structure and process thereof, which performs an etching process to laterally etch the part of the recess for forming the desired sidewall profile of the recess.
  • the etching process E may include a dry etching process, such as a tetrafluoromethane, helium and oxygen containing dry etching process.
  • a dry etching process such as a tetrafluoromethane, helium and oxygen containing dry etching process.
  • the sidewall profile of the exposing part of the recess R can be controlled precisely by adjusting the processing parameters.
  • the present invention is applied to form the Fin-shaped field effect transistor (FinFET)
  • the upper part of the sidewall of the recess is laterally etched to make the upper part of the sidewall of the recess approximately vertical to the level.
  • the protruding parts of the substrate beside the recess is suited for a gate structure formed thereon, thereby the electrical performance of the Fin-shaped field effect transistor (FinFET) can improve.
  • the material in the semiconductor structure formed by the present invention will not have voids in it.

Abstract

A semiconductor structure includes a substrate, a recess and a material. The recess is located in the substrate, wherein the recess has an upper part and a lower part. The minimum width of the upper part is larger than the maximum width of the lower part. The material is located in the recess.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates generally to a semiconductor structure and process thereof, and more specifically, to a semiconductor structure and process thereof, which laterally etches a part of a recess to make parts of the recess have different widths or different slopes of sidewalls.
  • 2. Description of the Prior Art
  • With increasing miniaturization of semiconductor devices, various Fin-shaped field effect transistor (FinFET) devices have been developed. The Fin-shaped field effect transistor (FinFET) is advantageous for the following reasons. First, manufacturing processes of Fin-shaped field effect transistor (FinFET) devices can be integrated into traditional logic device processes, and thus are more compatible. In addition, since the three-dimensional structure of the FinFET increases the overlapping area between the gate and the substrate, the channel region is controlled more effectively. This therefore reduces drain-induced barrier lowering (DIBL) effect and short channel effect. Moreover, the channel region is longer for the same gate length. Therefore, the current between the source and the drain is increased.
  • The Fin-shaped field effect transistor (FinFET) includes a plurality of fin-shaped structures, and gate structures disposed across them. Therefore, the sidewall of the upper part of the recess between each fin-shaped structure is covered by gate structures and the inclined angle of the sidewall of the upper part of the recess would affect the shape of gate structures. In general, the sidewall of the upper part of the recess is preferred to be a vertical sidewall for approaching the demands of the gate structures disposed across the fin-shaped structures, thereby the electrical performance of the Fin-shaped field effect transistor (FinFET) can be achieved. However, the sidewall of the recess etched by current processes has an inclined angle that can not approach the structural demand of a Fin-shaped field effect transistor (FinFET).
    • SUMMARY OF THE INVENTION
  • The present invention provides a semiconductor structure and process thereof, which laterally etches the sidewall of the upper part of a recess, to make the minimum width of the upper part of the recess larger than the maximum width of the lower part; or, to make the inclined angle of the sidewall of the upper part of the recess different from inclined angle of the sidewall of the lower part of the recess.
  • The present invention provides a semiconductor structure including a substrate, a recess and a material. The recess is located in the substrate, wherein the recess has an upper part and a lower part. The minimum width of the upper part is larger than the maximum width of the lower part. The material is located in the recess.
  • The present invention provides a semiconductor process including the following steps. A substrate is provided. A recess is formed in the substrate and the recess has a first sidewall. A material is filled in the recess and a part of the recess is exposed. An etching process is performed to laterally etch the exposing part of the recess, therefore the recess includes an upper part and a lower part, wherein the upper part has a second sidewall and the lower part has the first sidewall.
  • The present invention provides a semiconductor structure and process thereof, which performs an etching process to laterally etch the recess, and the desired sidewall profile of the recess is therefore formed.
  • These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1-11 schematically depict a cross-sectional view of a semiconductor process according to one preferred embodiment of the present invention.
    •  DETAILED DESCRIPTION
  • A Fin-shaped field effect transistor (FinFET) applying the present invention is used as an example illustrated in the following, but the present invention is not merely suited for forming a Fin-shaped field effect transistor (FinFET). The present invention can also be applied to form other semiconductor components, which change recess profiles by performing etching processes. Besides, the Fin-shaped field effect transistor (FinFET) applying the present invention has particular features, which are described as follows.
  • FIGS. 1-11 schematically depict a cross-sectional view of a semiconductor process according to one preferred embodiment of the present invention. As shown in FIG. 1, a substrate 110 is provided. The substrate 110 may be a semiconductor substrate such as a silicon substrate, a silicon containing substrate, a III-V group-on-silicon (such as GaN-on-silicon) substrate, a graphene-on-silicon substrate or a silicon-on-insulator (SOI) substrate. A pad oxide layer 122 and a pad nitride layer 124 are sequentially formed on the substrate 110. The pad oxide layer 122 includes an oxide layer, which may be formed by a thermal oxide process, a chemical oxide process, a chemical deposition process, etc. If the substrate 110 is a silicon substrate, the pad oxide layer 122 may be a silicon oxide layer formed by a thermal oxide layer. The pad nitride layer 124 includes a nitride layer, which may be formed by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process or other suitable processes. The pad oxide layer 122 and the pad nitride layer 124 constitute a hard mask layer 120, for etching the substrate 110 in the following processing steps. A mask layer 130 is formed to pattern the hard mask layer 120. The mask layer 130 may be a single layer structure or a multi-layer structure. In this embodiment, the mask layer 130 is a multi-layer structure composed of an oxide layer 132, an advance patterning film 134, a dielectric anti-reflection coating (DARC) layer 136, a bottom anti-reflective coating (BARC) layer 138, a photoresist layer 139, etc. As shown in the figure, the oxide layer 132, the advance patterning film 134, the dielectric anti-reflection coating (DARC) layer 136, the bottom anti-reflective coating (BARC) layer 138 and the photoresist layer 139 are sequentially formed on the hard mask layer 120. Then, the mask layer 130 is patterned. For instance, the photoresist layer 139 is patterned by exposing once or many times and then the pattern of the photoresist layer 139 is transferred once or many times to the bottom anti-reflective coating (BARC) layer 138, the dielectric anti-reflection coating (DARC) layer 136, the advance patterning film 134 and the oxide layer 132.
  • As shown in FIG. 2, the hard mask layer 120 is patterned by using the mask layer 130 as a mask and then the mask layer 130 is removed. The substrate 110 is etched by the hard mask layer 120 and at least a recess R is formed. There are two common recesses depicted in the figure, but the numbers or sizes of the recesses applying the present invention are not limited. The size of each recess may be common or different. As the recesses have different sizes, the depths of the recesses are different. The recess R has a first sidewall S1, and the recess R has a first predetermined depth d1. In this embodiment, the first sidewall S1 is an upward-broadened oblique sidewall. In another embodiment, the first sidewall S1 may have another shape. In this embodiment, the first predetermined depth d1 is 2000 angstroms, according to the processing size commonly used in modern processes, but it is not limited thereto.
  • As shown in FIGS. 3-4, a material 140 is filled in the recess R and a part of the recess R is exposed, wherein the material of the material 140 may be oxide, and the part of the recess R has a second predetermined depth d2. In detail, as shown in FIG. 3, the material 140 entirely covers the recess R and the hard mask layer 120. The material 140 may fill up or partially fill the recess R, as long as the depth d2′ of the top surface Q1 of the material 140 is smaller than the second predetermined depth d2. As shown in FIG. 4, the material 140 is etched back until exposing the part of recess with the second predetermined depth d2. That is, the distance between the surface Q2 of the material 140 and the top surface the substrate 110 is equal to the second predetermined depth d2. Preferably, the surface Q2 of the material 140 is essentially parallel with a level and the surface Q2 of the material 140 is a flat surface.
  • As shown in FIG. 5, an etching process E is performed to laterally etch the exposing part of the recess R. Therefore, the recess R includes an upper part P1 and a lower part P2. The minimum width of the upper part P1 is larger than the maximum width of the lower part P2. The etching process E may include a dry etching process, such as a tetrafluoromethane, helium and oxygen containing dry etching process, but it is not limited thereto. As the etching process E is a dry etching process, the sidewall profile of the exposing part of the recess R, such as the inclined angle or the shape of the sidewall, can be controlled precisely by adjusting the processing parameters.
  • In this embodiment, the connecting point of the upper part P1 and the lower part P2 has a turning point C. The present invention is applied to form a Fin-shaped field effect transistor (FinFET) in this embodiment. The upper part P1 has a second sidewall S2 and the lower part P2 has the first sidewall S1. The first sidewall S1 and the second sidewall S2 are upward-broadened oblique sidewalls. The acute angle θ2 between the second sidewall S2 and a level h is larger than the acute angle θ1 between the first sidewall S1 and the level h. In a preferred embodiment, the acute angle θ2 between the second sidewall S2 and the level h is larger than 89°. In a still preferred embodiment, the second sidewall S2 is essentially vertical to the level h. In doing this, a plurality of protruding parts 112 of the substrate 110 are suited for use as fin-shaped structures of a Fin-shaped field effect transistor (FinFET). The numbers of the protruding parts 112 depend upon the needs. In this embodiment, the etching process E just laterally etches the exposing part of the recess R and the upper part P1 is therefore formed. So, the length of the second sidewall S2 of the upper part P1 is equal to the second predetermined depth d2. If the first predetermined depth d1 is 2000 angstroms, the second predetermined depth d2 is preferred to be 400 angstroms (which is the thickness of the fin-shaped structures of the following formed Fin-shaped field effect transistor (FinFET)).
  • As shown in FIGS. 6-8, the material 140 is filled in the recess R and a part of the recess R with a third predetermined depth d3 is exposed. The processing steps include: as shown in FIG. 6, the material 140 entirely covers the recess R and the hard mask layer 120. As shown in FIG. 7, the material 140 is polished by methods such as a chemical mechanical polishing (CMP) process and the top surface of the material 140 therefore flushes with the top surface T of the hard mask layer 120. As shown in FIG. 8, the material 140 is etched back until exposing the part of the recess R with the third predetermined depth d3. That is, the distance between the top surface Q3 of the material 140 and the top surface of the substrate 110 is equal to the third predetermined depth d3. In this embodiment, the third predetermined depth d3 is preferred to be 250 angstroms (which is the thickness that a gate structure of the following formed Fin-shaped field effect transistor (FinFET) can be disposed thereon).
  • As shown in FIG. 9, the pad nitride layer 124 is removed. As shown in FIG. 10, the pad oxide layer 122 is removed, meaning the semiconductor structure 100 is complete.
  • According to the above, the semiconductor structure 100 shown in FIG. 10 is formed. The semiconductor structure 100 includes the substrate 110, the recess R and the material 140. The recess R having an upper part P1 and a lower part P2 is located in the substrate 110. The minimum width w1 of the upper part P1 is larger than the maximum w2 of the lower part P2. The material 140 is located in the recess R.
  • The connecting point of the upper part P1 and the lower part P2 has a turning point C. The semiconductor structure 100 is used to form a Fin-shaped field effect transistor (FinFET) in this embodiment. The upper part P1 has the second sidewall S2 and the lower part P2 has the first sidewall S1. The first sidewall 51 and the second sidewall S2 are upward-broadened oblique sidewalls. The acute angle θ2 between the second sidewall S2 and the level h is larger than the acute angle θ1 between the first sidewall S1 and the level h. In a preferred embodiment, the acute angle θ2 between the second sidewall S2 and the level h is larger than 89°. In a still preferred embodiment, the second sidewall S2 is essentially vertical to the level h. In doing this, a plurality of protruding parts 112 of the substrate 110 can be fin-shaped structures of a Fin-shaped field effect transistor (FinFET), suited for having a gate structure formed thereon. If the first predetermined depth d1 is 2000 angstroms, the second predetermined depth d2 is preferred to be 400 angstroms and the third predetermined depth d3 is preferred to be 250 angstroms.
  • As shown in FIG. 11, after the semiconductor 100 is complete, a Fin field-effect transistor, a Tri-gate MOSFET or etc. may be sequentially formed. For example, a gate dielectric layer (not shown), a gate electrode layer (not shown) and a cap layer (not shown) cover the protruding parts 112 and the material 140. The cap layer (not shown), the gate electrode layer (not shown) and gate dielectric layer (not shown) are patterned to form a gate structure G, wherein the gate structure G includes a gate dielectric layer 152, a gate electrode layer 154 and a cap layer 156. A spacer 160 is formed beside the gate structure G. An ion implantation process is performed to form a source/drain region in each protruding parts 112 beside the spacer; and so on. The method of forming the gate structure is known in the art, and is not described herein. Each protruding parts 112 are used as a fin-shaped structure of a Fin field-effect transistor, a Tri-gate MOSFET or etc. The material 140 located in the recess R is used to isolate transistors on each protruding parts 112
  • To summarize, the present invention provides a semiconductor structure and process thereof, which performs an etching process to laterally etch the part of the recess for forming the desired sidewall profile of the recess. The etching process E may include a dry etching process, such as a tetrafluoromethane, helium and oxygen containing dry etching process. As the etching process E is a dry etching process, the sidewall profile of the exposing part of the recess R can be controlled precisely by adjusting the processing parameters.
  • For example, as the present invention is applied to form the Fin-shaped field effect transistor (FinFET), the upper part of the sidewall of the recess is laterally etched to make the upper part of the sidewall of the recess approximately vertical to the level. Thus, the protruding parts of the substrate beside the recess is suited for a gate structure formed thereon, thereby the electrical performance of the Fin-shaped field effect transistor (FinFET) can improve. Due to the material filling in the recess twice in the present invention (the material filling in the recess in the first time is shown in FIG. 3-4 and the material filling in the recess in the second time is shown in FIG. 6-8), the material in the semiconductor structure formed by the present invention will not have voids in it.
  • Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (26)

1. A semiconductor structure, comprising:
a substrate;
a recess located in the substrate, wherein the recess has an upper part and a lower part, and the minimum width of the upper part is larger than the maximum width of the lower part; and
a material located in the recess.
2. The semiconductor structure according to claim 1, wherein the connecting point of the upper part and the lower part has a turning point.
3. The semiconductor structure according to claim 1, wherein the sidewalls of the upper part and the lower part respectively comprise an upward-broadened oblique sidewall.
4. The semiconductor structure according to claim 3, wherein the acute angle between the oblique sidewall of the upper part and a level is larger than the acute angle between the oblique sidewall of the lower part and a level.
5. The semiconductor structure according to claim 4, wherein the acute angle between the oblique sidewall of the upper part and a level is larger than 89°.
6. The semiconductor structure according to claim 1, wherein the sidewall of the upper part is essentially vertical to a level.
7. The semiconductor structure according to claim 1, wherein the material comprises oxide.
8. The semiconductor structure according to claim 1, wherein the recess comprises a first predetermined depth and the upper part comprises a second predetermined depth.
9. The semiconductor structure according to claim 8, wherein the first predetermined depth is 2000 angstroms and the second predetermined depth is 400 angstroms.
10. The semiconductor structure according to claim 8, wherein the material fills a part of the recess below a third predetermined depth.
11. The semiconductor structure according to claim 10, wherein the second predetermined depth is larger than the third predetermined depth.
12. The semiconductor structure according to claim 11, wherein the first predetermined depth is 2000 angstroms, the second predetermined depth is 400 angstroms and the third predetermined depth is 250 angstroms.
13. A semiconductor process, comprising:
providing a substrate;
forming a recess in the substrate, wherein the recess has a first sidewall;
filling a material in the recess and exposing a part of the recess; and
performing an etching process to laterally etch the exposing part of the recess, therefore the recess comprises an upper part and a lower part, wherein the upper part has a second sidewall and the lower part has the first sidewall.
14. The semiconductor process according to claim 13, wherein the connecting point of the upper part and the lower part has a turning point.
15. The semiconductor process according to claim 13, wherein the first sidewall and the second sidewall are upward-broadened oblique sidewalls.
16. The semiconductor process according to claim 15, wherein the acute angle between the second sidewall and a level is larger than the acute angle between the first sidewall and a level.
17. The semiconductor process according to claim 16, wherein the acute angle between the second sidewall and a level is larger than 89°.
18. The semiconductor process according to claim 13, wherein the second sidewall is essentially vertical to a level.
19. The semiconductor process according to claim 13, wherein the recess has a first predetermined depth, and the part of the recess and the upper part have a second predetermined depth.
20. The semiconductor process according to claim 19, wherein the first predetermined depth is 2000 angstroms and the second predetermined depth is 400 angstroms.
21. The semiconductor process according to claim 19, wherein the steps of filling the material in the recess comprise:
filling the material until the material is higher than the second predetermined depth; and
etching back the material until exposing the part of the recess with the second predetermined depth.
22. The semiconductor process according to claim 19, after performing the etching process, further comprising:
filling the material in the recess until exposing a part of the recess with a third predetermined depth.
23. The semiconductor process according to claim 22, wherein the second predetermined depth is larger than the third predetermined depth.
24. The semiconductor process according to claim 23, wherein the first predetermined depth is 2000 angstroms, the second predetermined depth is 400 angstroms and the third predetermined depth is 250 angstroms.
25. The semiconductor process according to claim 13, wherein the etching process comprises a dry etching process.
26. The semiconductor process according to claim 25, wherein the dry etching process comprises a tetrafluoromethane, helium and oxygen containing dry etching process.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9159832B2 (en) * 2013-03-08 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor fin structures and methods for forming the same
US20170213892A1 (en) * 2013-06-28 2017-07-27 Intel Corporation NANOSTRUCTURES AND NANOFEATURES WITH Si (111) PLANES ON Si (100) WAFERS FOR III-N EPITAXY

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5013680A (en) * 1990-07-18 1991-05-07 Micron Technology, Inc. Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography
US6110797A (en) * 1999-12-06 2000-08-29 National Semiconductor Corporation Process for fabricating trench isolation structure for integrated circuits
US6150212A (en) * 1999-07-22 2000-11-21 International Business Machines Corporation Shallow trench isolation method utilizing combination of spacer and fill
US20020090795A1 (en) * 1999-05-20 2002-07-11 Ahn Dong-Ho Method of forming T-shaped isolation layer, method of forming elevated salicide source/drain region using the same, and semiconductor device having T-shaped isolation layer
US6734524B1 (en) * 2002-12-31 2004-05-11 Motorola, Inc. Electronic component and method of manufacturing same
US20050085042A1 (en) * 2003-06-23 2005-04-21 Jong-Sik Chun Dual gate oxide structure in semiconductor device and method thereof
US20050164468A1 (en) * 2003-06-26 2005-07-28 Steegen An L. Selective silicon-on-insulator isolation structure and method
US20080119020A1 (en) * 2006-11-17 2008-05-22 Micron Technology, Inc. Methods of forming a field effect transistors, pluralities of field effect transistors, and DRAM circuitry comprising a plurality of individual memory cells
US7416956B2 (en) * 2004-11-23 2008-08-26 Sandisk Corporation Self-aligned trench filling for narrow gap isolation regions
US7867845B2 (en) * 2005-09-01 2011-01-11 Micron Technology, Inc. Transistor gate forming methods and transistor structures

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10345346B4 (en) 2003-09-19 2010-09-16 Atmel Automotive Gmbh A method of manufacturing a semiconductor device having active regions separated by isolation structures
US7491618B2 (en) 2006-01-26 2009-02-17 International Business Machines Corporation Methods and semiconductor structures for latch-up suppression using a conductive region
US8232179B2 (en) * 2009-10-01 2012-07-31 International Business Machines Corporation Method to improve wet etch budget in FEOL integration

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5013680A (en) * 1990-07-18 1991-05-07 Micron Technology, Inc. Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography
US20020090795A1 (en) * 1999-05-20 2002-07-11 Ahn Dong-Ho Method of forming T-shaped isolation layer, method of forming elevated salicide source/drain region using the same, and semiconductor device having T-shaped isolation layer
US6150212A (en) * 1999-07-22 2000-11-21 International Business Machines Corporation Shallow trench isolation method utilizing combination of spacer and fill
US6110797A (en) * 1999-12-06 2000-08-29 National Semiconductor Corporation Process for fabricating trench isolation structure for integrated circuits
US6734524B1 (en) * 2002-12-31 2004-05-11 Motorola, Inc. Electronic component and method of manufacturing same
US20050085042A1 (en) * 2003-06-23 2005-04-21 Jong-Sik Chun Dual gate oxide structure in semiconductor device and method thereof
US20050164468A1 (en) * 2003-06-26 2005-07-28 Steegen An L. Selective silicon-on-insulator isolation structure and method
US7416956B2 (en) * 2004-11-23 2008-08-26 Sandisk Corporation Self-aligned trench filling for narrow gap isolation regions
US7867845B2 (en) * 2005-09-01 2011-01-11 Micron Technology, Inc. Transistor gate forming methods and transistor structures
US20080119020A1 (en) * 2006-11-17 2008-05-22 Micron Technology, Inc. Methods of forming a field effect transistors, pluralities of field effect transistors, and DRAM circuitry comprising a plurality of individual memory cells

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9159832B2 (en) * 2013-03-08 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor fin structures and methods for forming the same
US9698055B2 (en) 2013-03-08 2017-07-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor fin structures and methods for forming the same
US20170213892A1 (en) * 2013-06-28 2017-07-27 Intel Corporation NANOSTRUCTURES AND NANOFEATURES WITH Si (111) PLANES ON Si (100) WAFERS FOR III-N EPITAXY

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