US20130099379A1 - Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment - Google Patents
Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment Download PDFInfo
- Publication number
- US20130099379A1 US20130099379A1 US13/714,991 US201213714991A US2013099379A1 US 20130099379 A1 US20130099379 A1 US 20130099379A1 US 201213714991 A US201213714991 A US 201213714991A US 2013099379 A1 US2013099379 A1 US 2013099379A1
- Authority
- US
- United States
- Prior art keywords
- semiconductor device
- conductive layer
- electrode
- layer
- segment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13458—Terminal pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0236—Shape of the insulating layers therebetween
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02375—Top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02377—Fan-in arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/024—Material of the insulating layers therebetween
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
- H01L2224/1145—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/1146—Plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/116—Manufacturing methods by patterning a pre-deposited material
- H01L2224/1161—Physical or chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/116—Manufacturing methods by patterning a pre-deposited material
- H01L2224/1162—Manufacturing methods by patterning a pre-deposited material using masks
- H01L2224/11622—Photolithography
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
- H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H01L2224/13008—Bump connector integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13012—Shape in top view
- H01L2224/13013—Shape in top view being rectangular or square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
- H01L2224/13018—Shape in side view comprising protrusions or indentations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/1319—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/1354—Coating
- H01L2224/13575—Plural coating layers
- H01L2224/1358—Plural coating layers being stacked
- H01L2224/13582—Two-layer coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/1354—Coating
- H01L2224/13599—Material
- H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/1354—Coating
- H01L2224/13599—Material
- H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/13666—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0103—Zinc [Zn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/049—Nitrides composed of metals from groups of the periodic table
- H01L2924/0494—4th Group
- H01L2924/04941—TiN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Nonlinear Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Mathematical Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Optics & Photonics (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Liquid Crystal (AREA)
Abstract
A semiconductor device is provided with a plurality of protrusions which are made of a resin and which protrude higher than electrodes, and conductive layers which are electrically connected to the electrodes and which cover the top surfaces of the protrusions. A method for manufacturing the semiconductor device includes a step of applying a layer of the resin to the semiconductor device except for the electrodes, a step of patterning the conductive layers on the electrodes and the layer of the resin in accordance with the protrusions, and a step of removing the layer of the resin located between the conductive layers by the use of the patterned conductive layers as masks so as to form the protrusions.
Description
- This application is a continuation patent application of U.S. Ser. No. 12/852,826 filed Aug. 9, 2010, which is a continuation patent application of U.S. Ser. No. 11/456,354 filed Jul. 10, 2006 (now U.S. Pat. No. 7,795,129 issued Sep. 14, 2010), which is a continuation patent application of U.S. Ser. No. 11/099,255 filed Apr. 5, 2005 (now U.S. Pat. No. 7,132,749 issued Nov. 7, 2006), which is a divisional patent application of U.S. Ser. No. 10/726,275 filed Dec. 2, 2003 (now U.S. Pat. No. 7,098,127 issued Aug. 29, 2006), claiming priority to Japanese Patent Application No. 2002-350337 filed Dec. 2, 2002, all of which are hereby incorporated by reference.
- 1. Technical Field of the Invention
- The present invention relates to a semiconductor device, a method for manufacturing the same, a circuit substrate, an electro-optical apparatus, and electronic equipment.
- 2. Description of the Related Art
- Conventionally, so-called Au bumps are frequently used for mounting semiconductor devices, e.g., driver ICs. In the formation of the Au bump, a seed layer made of TiW/Au or the like is sputtered on a semiconductor element, a resist is patterned and, thereafter, Au electroplating is applied up to a height on the order of 20 μm. However, it is predicted that stable formation of bumps, such as formation of a resist having a high aspect ratio, etching of a seed layer, and the like, becomes difficult with a reduction in the pitch of the electrodes of the above-described driver IC.
- In recent years, an inexpensive electroless Ni bump was developed in response to the reduction in pitch. However, this bump is harder than the Au bump and, therefore, may be unsuitable, particularly for COG (Chip On Glass) techniques in which the driver IC is directly mounted on a display panel, from the viewpoint of the reliability of connection.
- Japanese Unexamined Patent Application Publication No. 2-272737 discloses a technology in which resin protrusions are disposed in the locations at a distance from electrodes, connection patterns for serving as conductive layers are disposed to cover and connect the surfaces of the protrusions and the electrodes and, thereby, protrusion electrodes are provided. According to this technology, protrusion electrodes having small diameters can easily be formed, and a reduction in semiconductor chip size is facilitated. In addition, the stress during mounting is absorbed because the resin protrusions have elasticity and, therefore, stabilization in mounting quality is facilitated.
- However, the above-described known technology has problems as described below.
- In the formation of the protrusion electrodes, it is necessary to perform patterning after a semiconductor element is coated with a resin, form a conductive layer by sputtering or the like and, furthermore, pattern the resulting conductive layer. In the known patterning, since a desired shape is given by, for example, photo-etching, a photomask or the like suitable for the desired shape must be prepared on an etching step basis and, therefore, the manufacturing cost is increased. There is a further problem in that fine patterning is required for both of the resin layer and the conductive layer, and the manufacturing process becomes complicated.
- When a plurality of protrusions are formed by photo-etching, the spacings between protrusions may be formed into tapered shapes. In this case, the spacings between base portions of the protrusions become small, and it may become difficult to respond to a reduction in the pitch of the protrusions.
- The present invention was made in consideration of the above-described points. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same capable of simplifying the manufacturing process and responding to a reduction in pitch, and to provide a circuit substrate, an electro-optical apparatus, and electronic equipment.
- In order to achieve above-described objects, the present invention adopts the following configuration.
- A method according to the present invention is for manufacturing a semiconductor device including electrodes, a plurality of protrusions which protrude higher than the electrodes and which are made of a resin in a predetermined pattern, and conductive layers which are electrically connected to the electrodes and which cover the top surfaces of the protrusions. The method includes the steps of applying a layer of the resin to the semiconductor device except for the electrodes; patterning the conductive layers on the electrodes and the layer of the resin in accordance with the predetermined pattern of the protrusions; and removing the of the resin located between the conductive layers by the use of the patterned conductive layers as masks, so as to form the protrusions.
- In the present invention, since the conductive layers are used as masks in patterning of the plurality of protrusions by removing the layer of the resin located between the conductive layers through the use of etching or the like, fine patterning of the layer of the resin is unnecessary and, therefore, the manufacturing process can be simplified. Preferably, this layer of the resin is removed by plasma processing. In this case, since the side surfaces of the protrusions which have a high probability of taking on tapered shapes are caused to become substantially perpendicular, spacings between the base portions of the protrusions adjacent to each other do not become small. Consequently, a reduction in pitch can be realized with respect to the disposition of the plurality of protrusions.
- The conductive layer may be formed by sputtering or plating in the configuration adopted. With respect to the formation by sputtering, since a resist remaining on the conductive layer can be simultaneously removed during the plasma processing performed after the conductive layer is patterned using the resist, no separate resin removal step is required. With respect to the formation by plating, since the conductive layer can have a large thickness, a break and the like can be prevented.
- The step of forming the conductive layers may includes a sub-step of forming first conductive layers covering the electrodes before the layer of the resin is formed and a sub-step of forming second conductive layers connecting the surface of the layer of the resin and the first conductive layers. In this case, since the electrodes can be covered (coated) with the first conductive layer, corrosion of the electrodes can be prevented, in contrast to the case where Al electrodes are used. Preferably, the first conductive layer is formed by electroless nickel plating. The first conductive layer and the second conductive layer may be formed by sputtering. In this case, since the first conductive layer can be extended to the active surface region of the semiconductor device, flexibility in formation of the protrusions can be further increased.
- A semiconductor device according to the present invention is manufactured by the above-described method for manufacturing a semiconductor device. A circuit substrate according to the present invention includes the above-described semiconductor device. In this manner, mounting can be performed with a reduced pitch in the present invention and, thereby, a high-performance semiconductor device and circuit substrate can be prepared.
- An electro-optical apparatus according to the present invention is provided with an electro-optical panel and the above-described semiconductor device electrically connected to the above-described electro-optical panel. Electronic equipment according to the present invention is provided with the above-described electro-optical apparatus.
- According to the present invention, mounting can be performed with a reduced pitch and, thereby, a high-performance electro-optical apparatus and electronic equipment including semiconductor devices mounted thereon with a reduced pitch and at a high density can be prepared.
-
FIG. 1 is a partial plan view of a semiconductor device according to the present invention. -
FIG. 2 is a sectional view of the section indicated by a line A-A shown in -
FIG. 1 . -
FIG. 3 is a sectional view of the section indicated by a line B-B shown in -
FIG. 1 . -
FIGS. 4( a) to 4(d) are diagrams showing the manufacturing process of protrusions. -
FIG. 5 is a partial plan view showing another form of the semiconductor device. -
FIG. 6 is a perspective view showing a schematic configuration of a liquid crystal display device according to the present invention. -
FIG. 7 is a perspective exploded view showing an example of a COG type liquid crystal display device. -
FIG. 8 is a sectional view of an organic EL panel according to the present invention. -
FIG. 9 is an external view of an electronic equipment of the present invention. -
FIG. 10 is a perspective view showing a cellular phone serving as another electronic equipment of the present invention. -
FIG. 11 is a sectional view of the section indicated by a line B-B shown inFIG. 1 showing a conductive layer comprising a first layer and a second layer. - The embodiments of the semiconductor device, the method for manufacturing the same, the circuit substrate, the electro-optical apparatus, and the electronic equipment according to the present invention will be described below with reference to
FIG. 1 toFIG. 10 . Here, the structure of the semiconductor device used in the manufacturing method of the present invention and an example of the manufacturing process thereof will be described in advance of descriptions of steps specific to the present invention. -
FIG. 1 is a partial plan view of a semiconductor element serving as a semiconductor device according to the present invention.FIG. 2 is a sectional view of the section indicated by a line A-A shown inFIG. 1 .FIG. 3 is a sectional view of the section indicated by a line B-B shown inFIG. 1 . The semiconductor element in the present embodiment may be a semiconductor substrate, e.g., a silicon wafer in a condition in which a plurality of semiconductor chips are provided, or may be an individual semiconductor chip. The semiconductor chip is usually a rectangular parallelepiped (including a cube). However, the shape is not so limited, and may be spherical. - In
FIG. 1 ,reference numeral 1 denotes a semiconductor element (semiconductor device),reference numeral 2 denotes an Al electrode provided on thesemiconductor element 1 in order to input and output electric signals,reference numeral 3 denotes a passivation film provided to protect an active surface of thesemiconductor element 1,reference numeral 4 denotes a protrusion made of a resin while the protrusions are disposed with the same pitch as that of theAl electrodes 2, andreference numeral 5 denotes a conductive layer (metal film) provided to cover theAl electrode 2 and the surface (top surface) of theprotrusion 4. - The
Al electrode 2 is formed by, for example, sputtering, and is patterned into a predetermined shape (e.g., the shape of a rectangle) by the use of a resin or the like. In the present embodiment, the case where electrodes are composed of Al electrodes is described as an example. However, the electrode may have a structure in which, for example, a Ti (titanium) layer, a TiN (titanium nitride) layer, an AlCu (aluminum/copper) layer, and a TiN layer (cap layer) are laminated in that order. The electrode is not limited to the above-described configuration, and the configuration may be appropriately changed in accordance with the required electrical characteristics, physical characteristics, and chemical characteristics. - A plurality of
Al electrodes 2 are provided in the vicinity of the edge of thesemiconductor element 1 with a predetermined pitch. Thepassivation film 3 is provided in order to cover the periphery of theAl electrodes 2. Thispassivation film 3 may be made of SiO2 (silicon oxide), SiN (silicon nitride), a polyimide resin, or the like. The thickness of thepassivation film 3 is, for example, in the order of 1 μm. - A plurality of
protrusions 4 are provided in the active surface side of theAl electrodes 2, and are aligned in the horizontal direction inFIG. 1 with the same pitch as that of theAl electrodes 2. Theprotrusions 4 protrude (for example, with a thickness of 1 to 30 μm) higher than theAl electrodes 2. Theprotrusion 4 may be made of a resin, e.g., a polyimide resin, a silicone-modified polyimide resin, an epoxy resin, a silicone-modified epoxy resin, benzocyclobutene (BCB), or polybenzoxazole (PBO). - The
conductive layer 5 may be formed from a metal, e.g., Au, TiW, Cu, Cr, Ni, Ti, W, NiV, or Al, or be formed by laminating some of these metals. Preferably, the conductive layer 5 (when having a laminated structure, at least one layer) is formed from a material, e.g., Cu, TiW, or Cr, having a corrosion resistance higher than that of theAl electrode 2. In this manner, corrosion of theAl electrode 2 can be prevented, and electrical failure can be prevented. - Steps of forming the
protrusions 4 on thesemiconductor element 1 having the above-described configuration will be sequentially described with reference toFIGS. 4( a) to (d).FIGS. 4( a) to (d) are sectional views of a cross section of the portion whereprotrusions FIG. 1) . In the drawing, alternate long and short dashed lines indicate each position where theprotrusions 4 are to be provided. - Although not shown in the drawing, a coating of a resist is applied all over the
passivation film 3 by a spin coating method, a dipping method, a splay coating method, or the like, the resist is patterned into a predetermined shape through an exposure treatment and a development treatment by the use of a mask formed into a predetermined pattern, the resist is patterned into a predetermined shape, and a part of thepassivation film 3 covering theAl electrode 2 is etched to form openings, so that thepassivation film 3 is patterned. Preferably, dry etching is used. - The dry etching may be reactive ion etching (RIE). Wet etching may also be used.
- As shown in
FIG. 4( a), the above-described resin (for example, polyimide) constituting theprotrusion 4 is applied to thepassivation film 3 provided on thesemiconductor element 1, so that theresin layer 4 a is formed. At this time, as shown inFIG. 1 andFIG. 3 , theresin layer 4 a is patterned all over the range L except for the regions immediately above the openings of the Al electrodes 2 (in the present embodiment, theAl electrodes 2 and theresin layer 4 are completely separated). - As shown in
FIG. 4( b), the conductive layer 5 (for example, TiW/Au) is formed all over the surface of thesemiconductor element 1 including theAl electrodes 2 and the surface (top surface) of theresin layer 4 a. A sputtering or plating treatment may be adopted as the method for manufacturing theconductive layer 5. When the plating treatment is performed, the layer formed in this step serves as a seed layer. - A resist coating is applied all over the
conductive layer 5 by a spin coating method, a dipping method, a spray coating method, or the like, and the resist is patterned into a predetermined shape through an exposure treatment and a development treatment by the use of a mask provided with openings corresponding to the two-dimensional shape (two-dimensional pattern) of theconductive layer 5. Subsequently, an etching treatment is performed, so that eachconductive layer 5 is provided by patterning in the location corresponding to that of a protrusion, as shown inFIG. 4( c). Thereafter, a step of peeling the remaining resist (on the conductive layer 5) resin is performed. However, this peeling step is unnecessary if theconductive layer 5 is a film simply formed by sputtering. A film may be formed by a plating treatment (for example, Au plating; a thickness of 0.5 to 10 μm). on the film formed by sputtering and, therefore, theconductive layer 5 may be composed of these laminated plural films. In this case, the steps of sputtering, resist application, plating, resist peeling, and etching are performed in sequence. - With respect to the
resin layer 4 a, resin layers exposed at the regions located between theconductive layers 5 are removed by etching. A plasma treatment (plasma processing) is preferable as the method for etching, and the exposedresin layer 4 a is removed by, for example, O2 plasma. At this time, since theconductive layers 5 serve as masks, the resins located between theconductive layers 5 can be removed without using a separately prepared element, such as a photomask. As shown inFIG. 4( d), unnecessary resins on thesemiconductor element 1 are removed by this plasma etching, and the protrusions 5 (protrusion electrodes) are formed while theconductive layers 5 connected to theAl electrodes 2 are provided on the surface (top surface) thereof. - When the
resin layer 4 a is removed by photo-etching, the spacings betweenprotrusions protrusions 4 become smaller than the distances between theconductive layers 5. Consequently, it is practically difficult to reduce the pitch of theprotrusions 4. However, when the plasma etching is performed,protrusions 4 having substantially perpendicular side surfaces can be formed and, thereby, it is possible to respond to a reduction in pitch of theprotrusions 4. Furthermore, when theconductive layer 5 is a film simply formed by sputtering, the resist remaining on theconductive layer 5 is removed by this plasma etching simultaneously with theresin layer 4 a. - As described above, in the semiconductor device and the method for manufacturing the same according to the present embodiment, the
protrusions 4 are formed by removing theresin layer 4 a through the use of the patternedconductive layers 5 as masks. Consequently, theprotrusions 4 can easily be formed and, in addition, preparation of any fine-pattern mask for patterning theprotrusions 4 is unnecessary, so that prevention of an increase in manufacturing cost can be facilitated. In the present embodiment, since the removal of the resin layer for forming the protrusions is performed by the plasma etching,protrusions 4 having substantially perpendicular side surfaces can be formed and, thereby, it is possible to respond to a further reduction in pitch of theprotrusions 4. In the present embodiment, when theconductive layer 5 is a film simply formed by sputtering, the remaining resist accompanying the formation of the conductive layer can be simultaneously peeled by the plasma treatment. Therefore, no separate peeling step is required, so that an improvement of the manufacturing efficiency can also be facilitated. - Another form of the method for manufacturing a semiconductor device according to the present invention will be described below.
- In the configuration of the above-described embodiment, the
conductive layer 5 directly connects theAl electrode 2 and the surface of theprotrusion 4 and includes a first conductive layer 5 a and a secondconductive layer 5 b. However, indirect connection may be adopted as shown inFIG. 11 . Specifically, the first conductive layer 5 a is formed in order to cover theAl electrode 2 before the formation of theresin layer 4 a by the above-described manufacturing method and, thereby, theresin layer 4 a is formed on regions except for the regions immediately above theAl electrodes 2. Once theresin layer 4 a is formed, the secondconductive layer 5 b is formed. Examples of methods for manufacturing the first conductive layer include an electroless nickel plating treatment, sputtering, and the like. - In the formation of the first conductive layer by the electroless nickel plating treatment, a zincate conversion treatment is performed on the
Al electrode 2 by the use of an alkaline zinc solution. That is, the surface of aluminum (Al electrode 2) is converted to zinc. In order to apply the alkaline zinc solution to theAl electrode 2, thesemiconductor element 1 may be immersed in the solution. In order to deposit zinc on the surface of theAl electrode 2, theAl electrode 2 may be immersed in the alkaline zinc solution, deposited zinc may be dissolved in nitric acid and, thereafter, theAl electrode 2 may be immersed in the alkaline zinc solution again. An electroless nickel plating solution is applied to theAl electrode 2 with the surface converted to zinc, so that a nickel layer is formed on theAl electrode 2 through the substitution reaction between zinc and nickel. This step is performed while thesemiconductor element 1 is immersed in the electroless nickel plating solution. Subsequently, the above-describedresin layer 4 a is formed, and the second conductive layer is formed. This second conductive layer is formed by patterning in order to connect the surface of the protrusion and the first conductive layer. The removal of theresin layer 4 a by a plasma treatment performed following this is similar to that in the above-described embodiment. - In the present embodiment, since the
Al electrode 2 is completely covered with the first conductive layer, corrosion of Al can be prevented. In addition, since the zincate conversion treatment is performed, the resist patterning for selectively applying Ni to the Al portion is unnecessary. - On the other hand, in the formation of the first conductive layer by the sputtering, the resist patterning is performed after the sputter film is formed, and the etching treatment and the resist peeling are performed, as in the above-described embodiment, so that the first conductive layer in a desired shape can be prepared (plating treatment may be performed). The steps following this are similar to those in the case where the electroless nickel plating treatment is performed.
- In the present embodiment, as in the electroless nickel plating treatment, corrosion of Al can be prevented and, in addition, since the first conductive layers can be extended to the active surface region of the
semiconductor element 1, flexibility in disposition of theprotrusions 4 can be further increased. - In the configuration of the above-described embodiment, the protrusions are extended to the active surface region of the
semiconductor element 1, although not limited to this. For example, as shown inFIG. 5 , theprotrusions 4 may be configured to simply extend to the vicinity of the outside edge of theactive surface region 1F of thesemiconductor element 1 in accordance with theAl electrodes 2 having small openings. -
FIG. 6 is a perspective view showing a schematic configuration of a liquid crystal display device for serving as the electro-optical apparatus according to an embodiment of the present invention. The liquid crystal display device shown inFIG. 6 is provided with a colorliquid crystal panel 51 for serving as the electro-optical panel and a COF (Chip On Film)type circuit substrate 100 which includes asemiconductor device 101 manufactured by the above-described method for manufacturing a semiconductor device and which is connected to theliquid crystal panel 51. If necessary, illumination devices, e.g., a backlight, and other accessory devices are attached to theliquid crystal panel 51. - In addition to the above-described COF, the present invention may be applied to a COG (Chip On Glass) type electro-optical apparatus in which a driver IC and the like are directly mounted on a display panel (liquid crystal panel).
FIG. 7 shows an example of the COG type liquid crystal display device. - In this drawing, a liquid
crystal display device 50 for serving as the electro-optical apparatus includes a frame-shapedshield case 68 made of a metal plate, aliquid crystal panel 52 for serving as the electro-optical panel, a liquidcrystal driving LSI 58, an ACF (Anisotropic Conductive Film) or a NCF (Non Conductive Film), although not shown in the drawing, for electrically connecting theliquid crystal panel 52 and bump provided on the active surface of the liquidcrystal driving LSI 58 to each other by a COG mounting system, and a holdingelement 172 for ensuring the strength of the whole assembly. - This
liquid crystal panel 52 has a configuration in which afirst substrate 53 is composed of 0.7 mm thick soda glass provided with a first transparent electrode layer on one surface, asecond substrate 54 is composed of 0.7 mm thick soda glass provided with a second transparent electrode layer on one surface, thefirst substrate 53 and thesecond substrate 54 are attached to each other in order that the first transparent electrode layer and the second transparent electrode layer face each other, and a liquid crystal composition is enclosed between these substrates. The liquidcrystal driving LSI 58 is directly, electrically connected to onesubstrate 54 by the use of the ACF or the NCF for COG. In this manner, the COG typeliquid crystal panel 52 is formed. The liquidcrystal driving LSI 58 is manufactured by the above-described method for manufacturing a semiconductor device. - In addition to the liquid crystal display device, an organic EL display device may also be used as the electro-optical apparatus.
FIG. 8 is a sectional view of an organic EL panel provided on the organic EL display device for serving as the electro-optical apparatus according to the present invention. In the rough configuration of the organic EL panel (electro-optical panel) 30, TFTs (Thin Film Transistors) 32 are provided in the matrix on asubstrate 31, and a plurality oflaminates 33 are further provided thereon. TheTFT 32 includes a source electrode, a gate electrode, and a drain electrode, and each of the gate electrode and the source electrode is electrically connected to, for example, one of theconductive layers 5 shown inFIG. 1 . The above-describedlaminate 33 is configured to include ananode layer 34, ahole injection layer 35, aluminescent layer 36, and acathode layer 37. The above-describedanode layer 34 is connected to the drain electrode of theTFT 32, and a current is supplied to theanode layer 34 via the source electrode and the drain electrode of theTFT 32 when theTFT 32 is in an on state. - In the
organic EL panel 30 having the above-described configuration, the light generated in theluminescent layer 36 by recombination of a hole injected from theanode layer 34 to theluminescent layer 36 via thehole injection layer 35 and an electron injected from thecathode layer 37 to theluminescent layer 36 is emitted from thesubstrate 31 side. - The method for manufacturing a semiconductor device, the circuit substrate, and the electro-optical apparatus according to the embodiments of the present invention are described above. Electronic equipment including the electro-optical apparatus of the present embodiment will be described. Electronic components, such as a liquid crystal display device for serving as the above-described electro-optical apparatus, a mother board provided with a CPU (central processing unit) and the like, a keyboard, and hard disk, are installed into a cabinet and, therefore, a notebook personal computer 60 (electronic equipment) shown in
FIG. 9 , for example, is prepared. -
FIG. 9 is an external view showing a notebook computer for serving as the electronic equipment according to an embodiment of the present invention. InFIG. 9 ,reference numeral 61 denotes a cabinet,reference numeral 62 denotes a liquid crystal display device (electro-optical apparatus), andreference numeral 63 denotes a keyboard. Although the notebook computer provided with the liquid crystal display device is shown inFIG. 9 , an organic EL display device may be included instead of the liquid crystal display device.FIG. 10 is a perspective view showing a liquid crystal display device (electro-optical apparatus) for serving as another electronic equipment. Acellular phone 70 shown inFIG. 10 is configured to include anantenna 71, anearpiece 72, amouthpiece 73, a liquidcrystal display device 74, anoperation button portion 75, and the like. The cellular phone shown inFIG. 10 may be configured to include an organic EL display device instead of the liquidcrystal display device 74 as well. - In the above-described embodiments, the notebook computer and the cellular phone are described as examples of the electronic equipment, although the present invention is not limited to these. The present invention may be applied to electronic equipment, e.g., liquid crystal projectors, multimedia-capable personal computers (PC) and engineering work stations (EWS), pagers, word processors, televisions, viewfinder type and monitor-direct-view type videotape recorders, electronic notepads, electronic desk-top calculators, car navigation devices, POS terminals, and devices provided with touch panels, among others.
- The semiconductor device, the method for manufacturing the same, the electro-optical apparatus, and the electronic equipment according to the embodiments of the present invention are described above. However, the present invention is not limited to the above-described embodiments, and many modifications within the scope of the present invention may be performed.
- For example, electronic components may be prepared by replacing the “semiconductor chip” and the “semiconductor element” in the above-described embodiments with the “electronic element”. Examples of electronic components prepared using such an electronic component include optical elements, resistors, capacitors, coils, oscillators, filters, temperature sensors, thermistors, varistors, volumes, and fuses.
- The entire disclosure of Japanese Patent Application No. 2002-350337 filed Dec. 2, 2002 is incorporated by reference.
Claims (15)
1. A semiconductor device comprising:
a circuit substrate having a first surface;
an electrode disposed on said first surface;
a protrusion formed from resin and including a top surface and side surfaces, said side surfaces formed perpendicular to said electrode and extending between said electrode and said top surface; and
a conductive layer electrically connected to said electrode and covering said top surface of said protrusion.
2. The semiconductor device of claim 1 , wherein said conductive layer completely covers said top surface.
3. The semiconductor device of claim 2 , wherein said conductive layer is flush with each of said side surfaces at an outer periphery of said conductive layer.
4. The semiconductor device of claim 1 , wherein said conductive layer is flush with at least one of said side surfaces at an outer periphery of said conductive layer.
5. The semiconductor device of claim 1 , wherein said conductive layer is flush with each of said side surfaces at an outer periphery of said conductive layer.
6. The semiconductor device of claim 1 , wherein said conductive layer extends over said top surface but is spaced apart from said side surfaces.
7. The semiconductor device of claim 1 , wherein said conductive layer includes a first segment and a second segment, said first segment being separate and distinct from said second segment.
8. The semiconductor device of claim 7 , wherein said first segment extends over said electrode and said second segment extends partially over said first segment and partially over said protrusion.
9. The semiconductor device of claim 8 , wherein said first segment is flush with an edge of said electrode.
10. A semiconductor device comprising:
a circuit substrate having a first surface;
an electrode disposed on said first surface;
a protrusion formed from resin and including a top surface and a side surface, the side surface being formed perpendicular to said electrode and extending between said electrode and said top surface; and
a conductive layer electrically connected to said electrode and completely covering said top surface of said protrusion.
11. The semiconductor device of claim 10 , wherein said conductive layer is flush with said side surface at an outer periphery of said conductive layer.
12. The semiconductor device of claim 10 , wherein said conductive layer extends over said top surface but is spaced apart from said side surface.
13. The semiconductor device of claim 10 , wherein said conductive layer includes a first segment and a second segment, said first segment being separate and distinct from said second segment.
14. The semiconductor device of claim 13 , wherein said first segment extends over said electrode and said second segment extends partially over said first segment and partially over said protrusion.
15. The semiconductor device of claim 14 , wherein said first segment is flush with an edge of said electrode.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/714,991 US20130099379A1 (en) | 2002-12-02 | 2012-12-14 | Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment |
US14/740,603 US9362246B2 (en) | 2002-12-02 | 2015-06-16 | Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment |
Applications Claiming Priority (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002350337A JP3969295B2 (en) | 2002-12-02 | 2002-12-02 | SEMICONDUCTOR DEVICE, ITS MANUFACTURING METHOD, CIRCUIT BOARD, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC DEVICE |
JP2002-350337 | 2002-12-02 | ||
US10/726,275 US7098127B2 (en) | 2002-12-02 | 2003-12-02 | Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment |
US11/099,255 US7132749B2 (en) | 2002-12-02 | 2005-04-05 | Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment |
US11/456,354 US7795129B2 (en) | 2002-12-02 | 2006-07-10 | Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment |
US12/852,826 US20100295176A1 (en) | 2002-12-02 | 2010-08-09 | Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment |
US13/714,991 US20130099379A1 (en) | 2002-12-02 | 2012-12-14 | Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/852,826 Continuation US20100295176A1 (en) | 2002-12-02 | 2010-08-09 | Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/740,603 Continuation US9362246B2 (en) | 2002-12-02 | 2015-06-16 | Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment |
Publications (1)
Publication Number | Publication Date |
---|---|
US20130099379A1 true US20130099379A1 (en) | 2013-04-25 |
Family
ID=32310687
Family Applications (6)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/726,275 Expired - Lifetime US7098127B2 (en) | 2002-12-02 | 2003-12-02 | Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment |
US11/099,255 Expired - Lifetime US7132749B2 (en) | 2002-12-02 | 2005-04-05 | Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment |
US11/456,354 Expired - Fee Related US7795129B2 (en) | 2002-12-02 | 2006-07-10 | Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment |
US12/852,826 Abandoned US20100295176A1 (en) | 2002-12-02 | 2010-08-09 | Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment |
US13/714,991 Abandoned US20130099379A1 (en) | 2002-12-02 | 2012-12-14 | Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment |
US14/740,603 Expired - Lifetime US9362246B2 (en) | 2002-12-02 | 2015-06-16 | Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment |
Family Applications Before (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/726,275 Expired - Lifetime US7098127B2 (en) | 2002-12-02 | 2003-12-02 | Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment |
US11/099,255 Expired - Lifetime US7132749B2 (en) | 2002-12-02 | 2005-04-05 | Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment |
US11/456,354 Expired - Fee Related US7795129B2 (en) | 2002-12-02 | 2006-07-10 | Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment |
US12/852,826 Abandoned US20100295176A1 (en) | 2002-12-02 | 2010-08-09 | Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/740,603 Expired - Lifetime US9362246B2 (en) | 2002-12-02 | 2015-06-16 | Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment |
Country Status (6)
Country | Link |
---|---|
US (6) | US7098127B2 (en) |
EP (1) | EP1427007B1 (en) |
JP (1) | JP3969295B2 (en) |
KR (1) | KR100643986B1 (en) |
CN (1) | CN1291456C (en) |
TW (1) | TWI239085B (en) |
Families Citing this family (50)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7663607B2 (en) | 2004-05-06 | 2010-02-16 | Apple Inc. | Multipoint touchscreen |
US6642136B1 (en) | 2001-09-17 | 2003-11-04 | Megic Corporation | Method of making a low fabrication cost, high performance, high reliability chip scale package |
US8021976B2 (en) | 2002-10-15 | 2011-09-20 | Megica Corporation | Method of wire bonding over active area of a semiconductor circuit |
US6936531B2 (en) * | 1998-12-21 | 2005-08-30 | Megic Corporation | Process of fabricating a chip structure |
US6815324B2 (en) * | 2001-02-15 | 2004-11-09 | Megic Corporation | Reliable metal bumps on top of I/O pads after removal of test probe marks |
US6818545B2 (en) * | 2001-03-05 | 2004-11-16 | Megic Corporation | Low fabrication cost, fine pitch and high reliability solder bump |
TWI313507B (en) | 2002-10-25 | 2009-08-11 | Megica Corporatio | Method for assembling chips |
US7902679B2 (en) * | 2001-03-05 | 2011-03-08 | Megica Corporation | Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump |
US7099293B2 (en) | 2002-05-01 | 2006-08-29 | Stmicroelectronics, Inc. | Buffer-less de-skewing for symbol combination in a CDMA demodulator |
US7932603B2 (en) * | 2001-12-13 | 2011-04-26 | Megica Corporation | Chip structure and process for forming the same |
TWI245402B (en) | 2002-01-07 | 2005-12-11 | Megic Corp | Rod soldering structure and manufacturing process thereof |
US7265045B2 (en) | 2002-10-24 | 2007-09-04 | Megica Corporation | Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging |
JP3969295B2 (en) * | 2002-12-02 | 2007-09-05 | セイコーエプソン株式会社 | SEMICONDUCTOR DEVICE, ITS MANUFACTURING METHOD, CIRCUIT BOARD, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC DEVICE |
US7394161B2 (en) * | 2003-12-08 | 2008-07-01 | Megica Corporation | Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto |
JP3873986B2 (en) | 2004-04-16 | 2007-01-31 | セイコーエプソン株式会社 | Electronic component, mounting structure, electro-optical device, and electronic apparatus |
JP2005340761A (en) * | 2004-04-27 | 2005-12-08 | Seiko Epson Corp | Packaging method of semiconductor device, circuit board, electro-optical device, and electronic apparatus |
JP2005347622A (en) * | 2004-06-04 | 2005-12-15 | Seiko Epson Corp | Semiconductor device, circuit board and electronic equipment |
JP3994989B2 (en) | 2004-06-14 | 2007-10-24 | セイコーエプソン株式会社 | Semiconductor device, circuit board, electro-optical device, and electronic apparatus |
US8067837B2 (en) | 2004-09-20 | 2011-11-29 | Megica Corporation | Metallization structure over passivation layer for IC chip |
JP4107275B2 (en) | 2004-09-09 | 2008-06-25 | セイコーエプソン株式会社 | Inspection probe and inspection apparatus, and inspection probe manufacturing method |
JP3998014B2 (en) | 2004-09-29 | 2007-10-24 | セイコーエプソン株式会社 | Semiconductor device, mounting structure, electro-optical device, method of manufacturing electro-optical device, and electronic apparatus |
JP4165495B2 (en) | 2004-10-28 | 2008-10-15 | セイコーエプソン株式会社 | Semiconductor device, semiconductor device manufacturing method, circuit board, electro-optical device, electronic device |
JP4207004B2 (en) * | 2005-01-12 | 2009-01-14 | セイコーエプソン株式会社 | Manufacturing method of semiconductor device |
JP2006196728A (en) | 2005-01-14 | 2006-07-27 | Seiko Epson Corp | Electronic component, electro-optical device and electronic apparatus |
US8294279B2 (en) | 2005-01-25 | 2012-10-23 | Megica Corporation | Chip package with dam bar restricting flow of underfill |
JP4142041B2 (en) | 2005-03-23 | 2008-08-27 | セイコーエプソン株式会社 | Manufacturing method of semiconductor device |
JP4635676B2 (en) * | 2005-03-25 | 2011-02-23 | セイコーエプソン株式会社 | Manufacturing method of semiconductor device |
JP4221606B2 (en) * | 2005-06-28 | 2009-02-12 | セイコーエプソン株式会社 | Manufacturing method of semiconductor device |
JP4232044B2 (en) * | 2005-07-05 | 2009-03-04 | セイコーエプソン株式会社 | Manufacturing method of semiconductor device |
JP4224717B2 (en) | 2005-07-11 | 2009-02-18 | セイコーエプソン株式会社 | Semiconductor device |
JP4145902B2 (en) * | 2005-07-19 | 2008-09-03 | セイコーエプソン株式会社 | Semiconductor device and manufacturing method thereof |
JP4273347B2 (en) * | 2005-08-03 | 2009-06-03 | セイコーエプソン株式会社 | Semiconductor device |
JP4235835B2 (en) | 2005-08-08 | 2009-03-11 | セイコーエプソン株式会社 | Semiconductor device |
JP4296434B2 (en) * | 2005-09-13 | 2009-07-15 | セイコーエプソン株式会社 | Semiconductor device |
US8243027B2 (en) | 2006-06-09 | 2012-08-14 | Apple Inc. | Touch screen liquid crystal display |
EP3805907A1 (en) | 2006-06-09 | 2021-04-14 | Apple Inc. | Touch screen liquid crystal display |
CN104965621B (en) | 2006-06-09 | 2018-06-12 | 苹果公司 | Touch screen LCD and its operating method |
US7582966B2 (en) | 2006-09-06 | 2009-09-01 | Megica Corporation | Semiconductor chip and method for fabricating the same |
US8440272B2 (en) * | 2006-12-04 | 2013-05-14 | Megica Corporation | Method for forming post passivation Au layer with clean surface |
US8493330B2 (en) | 2007-01-03 | 2013-07-23 | Apple Inc. | Individual channel phase delay scheme |
US9710095B2 (en) | 2007-01-05 | 2017-07-18 | Apple Inc. | Touch screen stack-ups |
TWI364146B (en) * | 2008-03-27 | 2012-05-11 | Taiwan Tft Lcd Ass | Contact structure and connecting structure |
JP4656191B2 (en) * | 2008-06-12 | 2011-03-23 | セイコーエプソン株式会社 | Manufacturing method of semiconductor device |
JP5331610B2 (en) * | 2008-12-03 | 2013-10-30 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit device |
US20100264522A1 (en) * | 2009-04-20 | 2010-10-21 | Chien-Pin Chen | Semiconductor device having at least one bump without overlapping specific pad or directly contacting specific pad |
KR101807849B1 (en) * | 2010-12-08 | 2017-12-12 | 삼성디스플레이 주식회사 | Organinc light emitting display device and manufacturing method for the same |
US8804056B2 (en) | 2010-12-22 | 2014-08-12 | Apple Inc. | Integrated touch screens |
US10301173B2 (en) * | 2013-08-28 | 2019-05-28 | Cavendish Kinetics, Inc. | RF MEMS electrodes with limited grain growth |
FR3055471B1 (en) | 2016-08-31 | 2018-09-14 | Stmicroelectronics (Crolles 2) Sas | CHIP PROTECTED AGAINST REAR-BACK ATTACKS |
FR3069703B1 (en) | 2017-07-27 | 2020-01-24 | Stmicroelectronics (Crolles 2) Sas | MICROCHIP |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56164556A (en) * | 1980-05-22 | 1981-12-17 | Toshiba Corp | Manufacture of semiconductor device |
JPH02272737A (en) | 1989-04-14 | 1990-11-07 | Citizen Watch Co Ltd | Projecting electrode structure of semiconductor and formation of projecting electrode |
JPH0430533A (en) * | 1990-05-28 | 1992-02-03 | Fujitsu Ltd | Manufacture of semiconductor device |
JP2833326B2 (en) * | 1992-03-03 | 1998-12-09 | 松下電器産業株式会社 | Electronic component mounted connector and method of manufacturing the same |
JP3261912B2 (en) | 1995-01-19 | 2002-03-04 | 富士電機株式会社 | Semiconductor device with bump and method of manufacturing the same |
US5707902A (en) * | 1995-02-13 | 1998-01-13 | Industrial Technology Research Institute | Composite bump structure and methods of fabrication |
US6284563B1 (en) * | 1995-10-31 | 2001-09-04 | Tessera, Inc. | Method of making compliant microelectronic assemblies |
US6211572B1 (en) * | 1995-10-31 | 2001-04-03 | Tessera, Inc. | Semiconductor chip package with fan-in leads |
TW324847B (en) | 1996-12-13 | 1998-01-11 | Ind Tech Res Inst | The structure of composite bump |
JPH10209210A (en) * | 1997-01-20 | 1998-08-07 | Sharp Corp | Semiconductor device, its manufacture, and its inspection method |
US6051489A (en) | 1997-05-13 | 2000-04-18 | Chipscale, Inc. | Electronic component package with posts on the active side of the substrate |
JPH10321631A (en) * | 1997-05-19 | 1998-12-04 | Oki Electric Ind Co Ltd | Semiconductor device and its manufacture |
JPH11233545A (en) * | 1997-11-10 | 1999-08-27 | Citizen Watch Co Ltd | Semiconductor device and its manufacture |
JP3430916B2 (en) | 1998-04-17 | 2003-07-28 | 松下電器産業株式会社 | Method for manufacturing semiconductor device |
JP2000299406A (en) * | 1999-04-15 | 2000-10-24 | Sanyo Electric Co Ltd | Semiconductor device |
US6387734B1 (en) * | 1999-06-11 | 2002-05-14 | Fujikura Ltd. | Semiconductor package, semiconductor device, electronic device and production method for semiconductor package |
JP2001110831A (en) * | 1999-10-07 | 2001-04-20 | Seiko Epson Corp | External connecting protrusion and its forming method, semiconductor chip, circuit board and electronic equipment |
JP3548061B2 (en) * | 1999-10-13 | 2004-07-28 | 三洋電機株式会社 | Method for manufacturing semiconductor device |
JP4127943B2 (en) * | 2000-01-06 | 2008-07-30 | 日本テキサス・インスツルメンツ株式会社 | Semiconductor device and manufacturing method thereof |
JP3481899B2 (en) * | 2000-03-08 | 2003-12-22 | 沖電気工業株式会社 | Method for manufacturing semiconductor device |
JP2002299341A (en) * | 2001-03-29 | 2002-10-11 | Seiko Epson Corp | Method of forming wiring pattern, semiconductor device, method of manufacturing the same, circuit substrate, and electronic apparatus |
JP3969295B2 (en) * | 2002-12-02 | 2007-09-05 | セイコーエプソン株式会社 | SEMICONDUCTOR DEVICE, ITS MANUFACTURING METHOD, CIRCUIT BOARD, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC DEVICE |
-
2002
- 2002-12-02 JP JP2002350337A patent/JP3969295B2/en not_active Expired - Lifetime
-
2003
- 2003-11-24 CN CNB2003101180535A patent/CN1291456C/en not_active Expired - Fee Related
- 2003-11-27 TW TW092133404A patent/TWI239085B/en not_active IP Right Cessation
- 2003-12-01 KR KR1020030086408A patent/KR100643986B1/en active IP Right Grant
- 2003-12-02 EP EP03027709.9A patent/EP1427007B1/en not_active Expired - Fee Related
- 2003-12-02 US US10/726,275 patent/US7098127B2/en not_active Expired - Lifetime
-
2005
- 2005-04-05 US US11/099,255 patent/US7132749B2/en not_active Expired - Lifetime
-
2006
- 2006-07-10 US US11/456,354 patent/US7795129B2/en not_active Expired - Fee Related
-
2010
- 2010-08-09 US US12/852,826 patent/US20100295176A1/en not_active Abandoned
-
2012
- 2012-12-14 US US13/714,991 patent/US20130099379A1/en not_active Abandoned
-
2015
- 2015-06-16 US US14/740,603 patent/US9362246B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP1427007A3 (en) | 2006-01-04 |
CN1291456C (en) | 2006-12-20 |
US20060246635A1 (en) | 2006-11-02 |
US7795129B2 (en) | 2010-09-14 |
TW200423358A (en) | 2004-11-01 |
US9362246B2 (en) | 2016-06-07 |
JP2004186333A (en) | 2004-07-02 |
TWI239085B (en) | 2005-09-01 |
KR20040048321A (en) | 2004-06-07 |
US7132749B2 (en) | 2006-11-07 |
KR100643986B1 (en) | 2006-11-10 |
US20040145031A1 (en) | 2004-07-29 |
EP1427007A2 (en) | 2004-06-09 |
US7098127B2 (en) | 2006-08-29 |
CN1505105A (en) | 2004-06-16 |
US20100295176A1 (en) | 2010-11-25 |
US20150279801A1 (en) | 2015-10-01 |
EP1427007B1 (en) | 2014-01-15 |
JP3969295B2 (en) | 2007-09-05 |
US20050170602A1 (en) | 2005-08-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9362246B2 (en) | Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment | |
US8142602B2 (en) | Method for mounting semiconductor device | |
US7078331B2 (en) | Method of forming redistribution bump and semiconductor chip and mount structure fabricated using the same | |
US7888799B2 (en) | Semiconductor device, circuit substrate, electro-optic device and electronic appliance | |
US7282801B2 (en) | Microelectronic device chip including hybrid Au bump, package of the same, LCD apparatus including microelectronic device chip and method of fabricating microelectronic device chip | |
JP4218622B2 (en) | Manufacturing method of semiconductor device | |
KR100764808B1 (en) | Electronic board, method of manufacturing the same, and electronic device | |
JP3938128B2 (en) | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD, CIRCUIT BOARD, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC DEVICE | |
US20040099959A1 (en) | Conductive bump structure | |
JP4151634B2 (en) | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD, CIRCUIT BOARD, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC DEVICE | |
JP2007042777A (en) | Semiconductor device and manufacturing method thereof, circuit board, electrooptical device, and electronic apparatus | |
CN100468668C (en) | Method for mounting semiconductor device, circuit board, electrooptic device, and electronic device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |