US20130117492A1

US20130117492A1 - Platform communication protocol

Info

Publication number: US20130117492A1
Application number: US13/729,783
Authority: US
Inventors: Seh W. Kwa; Neil Songer; Rob Gough; David J. Harriman
Original assignee: Individual
Current assignee: Individual
Priority date: 2008-09-30
Filing date: 2012-12-28
Publication date: 2013-05-09
Also published as: US9715269B2; US20180088652A1; US20150127874A1; US10146290B2; US8806258B2; US20100080272A1

Abstract

A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.

Description

BACKGROUND

This relates to communications between external devices and a platform.
Conventionally, external devices communicate with a platform (such as a computer or other processor-based device) by posing interrupts, events, and notifications to the platform. These interrupts can come at any time and have no regard for what activity is currently being undertaken on the platform.
Ideally, the platform may enter idle states to reduce power consumption. When the processor is in a reduced power consumption state and an interrupt comes in from an external device, the interrupt may cause the platform to power up to handle the interrupt. As a result, in many cases, it is difficult for the platform to minimize its power consumption because it has no effective control over the timing of the interrupts that arrive from external devices.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic depiction of one embodiment of the present invention;

FIG. 2 is an in-band message packet format for one embodiment;

FIG. 3 depicts a sequence for decoding in-band messages; and

FIG. 4 is a sequence that may be utilized by the embodiment shown in FIG. 1 to handle communications from external devices.

DETAILED DESCRIPTION

Platform power consumption may be reduced when activity within the system that includes both the platform and its external devices is aligned. As a result, the time that the system is idle may be increased which, in turn, allows better use of reduced power consumption states.
Generally, a system-wide clock is not visible to each source of activity. In other words, the system may include a number of external devices which are not synchronized with respect to communicating with the platform itself. In some embodiments, a synchronization mechanism that is system-wide may be provided by overlying existing sideband signaling or in-band messaging.
Without alignment, the external devices tend to assume bus mastering capabilities with an asynchronous interrupt generation or traffic cycle initiation. As a result, the platform would conventionally need to be designed to be ready for activities at any time, making platform power management less successful.
Generally, platform events follow an established timing, particularly when the platform is idle. An operating system timer tick is a form of scheduling reminder for the system microprocessor. Upon an interrupt that represents that scheduling reminder, the microprocessor conducts its workload in an active window and then enters a low power consumption state as it becomes idle. In one case, the interrupt may be IRQ0/8. The active window may be typically short, on the order of a few hundred microseconds, for a typical idle system. In contrast, the operating system timer tick may have a significantly longer periodicity. For example, Microsoft Windows® operating system has a current periodicity of 15.6 milliseconds. While that periodicity represents a significant idle period, there are also small time windows where some basic functions depend on system resource availability to make progress. An example is the support of display refresh in an idle system using a partial frame buffer.
These small time windows of system resource (such as system memory) availability, marked by synchronization signals, are known as heartbeats. Heartbeats are not necessarily periodic or static. The interval between heartbeats depends on the functionality, as well as the internal buffering resource on the platform. Since system resources, as well as the platforms themselves, are active during the heartbeats, interrupts and traffic cycles from external devices may be aligned in these heartbeat time windows. This may result in increasing the deterministic idle times on the platform and increasing power management opportunities.
In one embodiment, by extending an existing sideband signal used for devices to wake a sleeping system, external devices may be notified when opportunities exist to align their interrupts and traffic cycles to a time period when system resources are available. In addition to sideband signals, other signaling mechanisms may be used as well, including, for example, system management bus or simple serial transport (SST) approaches.
In other embodiments, in-band messaging may be used alone or in concert with out-of-band signaling to synchronize tasks, raised by external devices, with the host heartbeat. The in-band messaging may be particularly useful for devices that are not accessible via out-of-band signaling. These devices may include devices which have no out-of-band signaling infrastructure, as well as devices which are otherwise inaccessible by out-of-band signaling mechanisms.
To implement synchronization using out-of-band signaling, a broadcast mechanism may be used that may include global sideband signaling or messages through a system management bus. Use of sideband signaling is desirable, in some embodiments, because, otherwise, conventional signaling would defeat the intent if the primary interconnect or bus between the chipset and the device were prohibited to enter low power modes. In the following discussion, an example of shared sideband signal, available through PCI Express, to support the synchronization communication is provided, but the present invention is in no way limited to this specific example. See the PCI Express Base 2.0 Specification, Jan. 15, 2007, available from PCI-SIG, 3855 SW. 153^rdDrive, Beaverton, Oreg. 97006.
The use of a sideband WAKE# signal is further enhanced to provide the host chipset the ability to communicate the opportunity to synchronize traffic activities. The goal of this synchronization is to reduce platform power consumption by encouraging all system resources to perform direct memory access and microprocessor interaction activities in a common time window, such that the idle time between such activities is gathered together, allowing the use of lower power consumption states during this lengthened and more deterministic idle period.
In accordance with the PCI Express specification, an external device asserts WAKE# with the bus in the L2 state. As a result of the contact from the external device, the bus transitions to the L0 state after a period of time. In response, the chipset asserts a WAKE# signal and enters the L0 state from either the L0 or L1 state. The time for assertion of the WAKE# signal may be 10 nanoseconds to 50 microseconds, in some embodiments. The period of assertion of the WAKE# signal for the external device may be on the order of a microsecond in order to increase the time window for traffic alignment.
Referring to FIG. 1, a host chipset 12 in a platform or system 10 may be coupled to external devices. The external devices may include endpoints 34, 36, 38, and 40. They may also include other interfaces or components, such as the switch 44, as an example. The external devices may be any of the external devices conventionally found in computer systems, including a storage device, a display, an input/output (I/O) device, and a network card, to mention a few examples. The host chipset 12 may include a root complex 13 that may include one or more processors, system memory, a basic input/output system memory, and buses, among other components.
The host chipset 12 may include one or more internal switches 42. As used herein, a switch is simply a device that may or may not make downstream components directly inaccessible from the root complex. In one embodiment, the switch 42 may be configured so as to make the switch 44 inaccessible via out-of-band signaling. In such case, an in-band message 43, precipitated by the root complex and issued by the switch 42, may be used to communicate the availability of root complex resources to switch 44 and its downstream components, such as endpoints 38 and 40.
The host chipset 12 may assert the sideband WAKE# signal when the link is in the L0s or L1 state. Since the sideband WAKE# signal is a shared signal, it is possible for its assertion to occur when some links are in the L0s or L1 state, while others are in the L2 state.
When an external device asserts the sideband WAKE# signal, the host chipset 12 follows a standard wakeup sequence from the L2 state without change from the conventional PCI Express behavior. When the host chipset only asserts the sideband WAKE# signal, the host chipset 12 waits for the external device 14 to initiate a link training signaling exit from L0s or L1 and then initiates traffic. The external device initiates link training if traffic is desirable and, otherwise, remains in the L0s, L1, or L2 state.
If the host chipset 12 asserts the WAKE# signaling, followed by external device assertion, the host chipset and the external device use standard wakeup sequencing from the L2 state without change from conventional behavior. Other external devices with link states in the L0s or L1 states may observe those sideband WAKE# assertion as a hint to align their traffic when another device is waking up the system resource.
If the external device asserts the WAKE# signal, followed by the host chipset assertion, the host chipset avoids the sideband WAKE# assertion if it detected the assertion of a sideband WAKE# signal. The external device asserting the WAKE# signal continues the exit from the L2 state. Other external devices in L0s and L1 states may choose opportunistically to align their low power link state exit to initiate traffic.
In some embodiments, a notification is provided to external devices about the availability of system resources, as well as an internal resource. This affords external devices an opportunity to align their interrupts or traffic cycles when the resources become available, reducing the need to disturb the system resources and increasing power conservation.
In some embodiments, synchronization hints may be provided to external devices such that they can become well behaved in aligning their interrupt communication and traffic cycles with host chipset resource availability. Doing so affords greater power management opportunities.
Historically, the WAKE# signaling on a PCI Express link is a mechanism to support device signaling when desired to exit from deep system or device low power states. Through the use of the same mechanism to alert the device to the opportunity to align interrupt traffic cycles, a non-deep system or device low power system power conservation advantages may be achieved without significant additional overhead.
In cases where in-band messaging is more desirable or in cases (as described above) where an out-of-band signaling is not feasible, in-band messages may be utilized. In some cases, the root complex 13 may know the system 10 configuration or hierarchy. It may learn the system configuration, for example, as a result of an enumeration and configuration protocol used during the boot-up sequence. The basic input/output system may include code that causes devices within the system to be enumerated and enables the system to know the architecture or hierarchy of the system.
Then, the root complex 13 may determine how best to notify various external devices of the availability of root complex resources. In some cases, based on the hierarchy or configuration of the system, in-band messaging may be the best or only alternative and, in other cases, where suitable out-of-band signaling infrastructure is available, out-of-band signals may be utilized. It is also possible that, in some cases, entirely in-band messaging may be utilized and, in other cases, entirely out-of-band signaling may be utilized.
One message format for an in-band message 43, shown in FIG. 2, may include a conventional bus protocol message packet. In the example shown in FIG. 2, a PCI Express specification compliant message packet format is utilized. Bytes 0-3 provide conventional information about the nature of the message, including its length and type. Bytes 4-7 provide the requestor ID, a tag, and a message code which, in one embodiment, uniquely identifies the packet as one relating to in-band messaging. Bytes 8-12 may be reserved and may include a particular in-band message code 45.
The in-band message code 45, better shown in FIG. 3, may include a first code which is all zeros, indicated in diamond 52. When this first code is received, the endpoint knows that the root complex is fully active, as indicated in block 54. If that code is not the one that is received, then the sequence checks for a code, which includes a zero followed by all ones, indicating that a bus master mode is activated. In the bus master mode, the system memory path is available for device memory read/write bus master activities. If that code is not implicated, then, as determined in diamond 60, a code, which is zeros followed by ones, indicates that the root complex is inactive, as indicated in block 62.
In one embodiment, the in-band message may be a point-to-point message that propagates from an upstream component, such as root complex 13, to all downstream components. In the PCI Express protocol, it can be implemented as a 100b message, for example.
Thus, as one example, an endpoint may initially receive a code indicating that the root complex is inactive, may later receive a code indicating that the root complex is active, and then may receive a code indicating that the root complex is in bus master mode, and, finally, may receive a code indicating that the root complex is again inactive. In some embodiments, the endpoint may take advantage of the signaling that the root complex is active to implement bus mastering and initiation of interrupts. In this way, the system power consumption may be reduced and response time may actually be increased in some embodiments.
Referring to FIG. 4, sequence 18 may be implemented by hardware, firmware, or software stored on the host chipset 12 or in connection with other components. In the case of a software implementation, a computer readable medium, such as a semiconductor memory, may be used to store the software. The software may be stored in the root complex 13, as indicated in FIG. 1, or elsewhere within the system. The computer readable medium may store instructions that, when executed, perform the sequence illustrated in FIG. 4.
Initially, the host software 18 checks for host assertion of in-band messaging or out-of-band signaling at diamond 20. If there is such an assertion, a check at diamond 22 determines whether an external device initiates messaging or signaling. If so, the host asserts the signaling or messaging (block 29) and the sequence proceeds as described above.
In block 24, the enumeration file, for example developed by the basic input/output system is acquired. The root complex identifies nodes for in-band messaging and side-band signaling, as indicated in block 26. Then, in block 28, the signals and commands for in-band messaging or side band signaling are sent as appropriate.
Namely, in the case of use of out-of-band signaling, if the external device is the only one that asserts the WAKE# signaling, both the external device and the host chipset sequence from the L2 state without change from conventional operation. When the host chipset alone asserts the WAKE# signaling, the host chipset waits for the external device to initiate link training, signaling the exit from L0s or L1 and then initiates traffic. The external device initiates link training if traffic is desirable and, otherwise, remains in the L0s, L1, or L2 states. In the case where a host chipset assertion is followed by external device assertion, the standard wakeup sequence may be utilized. Similarly, with external device assertion, followed by host chipset assertion, the host chipset avoids sideband WAKE# signal assertion if it detected the assertion of the sideband WAKE# signal. The external device asserts the sideband WAKE# signal and continues its exit from the L2 state.
References throughout this specification to “one embodiment” or “an embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present invention. Thus, appearances of the phrase “one embodiment” or “in an embodiment” are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be instituted in other suitable forms other than the particular embodiment illustrated and all such forms may be encompassed within the claims of the present application.
While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.

Claims

1. An apparatus comprising:

logic to:

identify a time window corresponding to an opportunity for devices to interact with a system component;

send a signal to a device over an interconnect comprising one or more serial point-to-point differential links, wherein the signal is to indicate the time window to the device.

2. The apparatus of claim 1, wherein the time window corresponds to an active state of the system component.

3. The apparatus of claim 1, wherein timing window corresponds to power management state transitions affecting the system component.

4. The apparatus of claim 1, wherein the signal comprises an in band signal.

5. The apparatus of claim 4, wherein the signal comprises a message signal that is to indicate a present power state of the system component.

6. The apparatus of claim 5, wherein the message comprises a packet including an indicator that the packet communicates time window information.

7. The apparatus of claim 1, wherein the signal comprises a sideband signal.

8. The apparatus of claim 7, wherein the signal comprises a Peripheral Component Interconnect Express (PCIe)-compliant WAKE# signal.

9. The apparatus of claim 7, where in the logic is further to send an in-band signal to a second device, wherein the in-band signal is to indicate the time window.

10. The apparatus of claim 1, wherein the system component comprises a system microprocessor.

11. The apparatus of claim 1, wherein the system component is included in a root complex.

12. The apparatus of claim 1, wherein the interconnect comprises at least one of a physical layer to support a PCIe protocol layer, and a physical layer including one or more protocols.

13. The apparatus of claim 1, wherein the interconnect comprises a PCIe-compliant interconnect.

14. The apparatus of claim 1, wherein the time window corresponds to an interrupt affecting the system component.

15. The apparatus of claim 1, wherein the time window corresponds to a traffic cycle of the system component.

16. An apparatus comprising:

logic to:

receive a signal over an interconnect comprising one or more serial point-to-point differential links; and

interpret the signal to identify a time window representing an opportunity to time interactions with a system component.

17. The apparatus of claim 16, wherein the logic is further to send data over the interconnect to the system component based at least in part on the indicated time window.

18. The apparatus of claim 17, wherein the sending of data is to correspond to an active state of the system component.

19. The apparatus of claim 16, wherein the signal comprises a sideband signal.

20. The apparatus of claim 19, wherein the signal comprises a Peripheral Component Interconnect Express (PCIe)-compliant WAKE# signal.

21. The apparatus of claim 16, wherein the signal comprises an in-band message.

22. The apparatus of claim 16, wherein the interconnect comprises at least one of a physical layer to support a PCIe protocol layer, and a physical layer including one or more protocols.

23. The apparatus of claim 16, wherein the interconnect comprises a PCIe-compliant interconnect.

24. An apparatus comprising:

a root complex to:

determine availability of a wake signal for a particular one of a plurality of devices communicatively coupled to the root complex at least in part using a serial point-to-point differential link, wherein the wake signal is to communicate a hint to indicate an opportunity for the particular device to substantially align interactions of the particular device with a system component with a power management state transition of the system component, wherein determining that the wake signal is unavailable for the particular device is to cause the hint to be communicated to the particular device as a message, and determining the availability of the wake signal comprises includes determining whether the particular device is at least partially accessible via sideband signaling; and

send the hint to the particular device over the link when the link is in an operational power state.

25. The apparatus of claim 24, wherein the link comprises a PCIe-compliant link.

26. The apparatus of claim 24, wherein the wake signal comprises a sideband PCIe-compliant WAKE# signal and the message comprises an in-band message.

27. The apparatus of claim 24, wherein the operational power state comprises an L0 state.

28. A method comprising:

determining, for a device, a hint to indicate a time window representing an opportunity for the device to align interaction of the device with an active state of a system component;

sending the hint to the device over a serial point-to-point interconnect; and

receiving data from the device during the time window.

29. The method of claim 28, wherein the interconnect comprises a PCIe-compliant interconnect.

30. The method of claim 28, wherein the hint is one of a sideband signal and an in-band message.

31. The method of claim 30, wherein the in-band message is to be determined for the device when the sideband signal is unavailable for the interconnect.

32. The method of claim 30, wherein the signal comprises a PCIe-compliant WAKE# signal.

33. A system comprising:

a serial point-to-point interconnect;

a first device; and

a second device wherein the second device is communicatively coupled to the first device using the interconnect and the second device includes logic to:

send a signal to the first device over the interconnect, wherein the signal is to indicate a time window representing an opportunity for the first device to align interaction of the device with a microprocessor.

34. The system of claim 33, wherein the interconnect comprises a PCIe-compliant interconnect.

35. The system of claim 33, wherein the second device comprises a root complex.

36. The system of claim 33, wherein the second device comprises a switch.

37. The system of claim 33, wherein the first device is adapted to receive and interpret a version of the signal comprising a PCIe-compliant WAKE# signal.

38. The system of claim 33, wherein the first device is adapted to receive and interpret a version of the signal comprising an in-band message.

39. The system of claim 33, further comprising a third device, wherein the signal to the first device comprises a PCIe-compliant WAKE# signal and the logic is further to send an in-band message to the third device, wherein the in-band message is to indicate the time window.