US20130141992A1 - Volatile memory access via shared bitlines - Google Patents
Volatile memory access via shared bitlines Download PDFInfo
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- US20130141992A1 US20130141992A1 US13/312,867 US201113312867A US2013141992A1 US 20130141992 A1 US20130141992 A1 US 20130141992A1 US 201113312867 A US201113312867 A US 201113312867A US 2013141992 A1 US2013141992 A1 US 2013141992A1
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- memory
- memory cells
- bitline
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
Definitions
- the disclosures herein relate generally to volatile memory, and more specifically, to writing information to and reading information from static random access memory (SRAM). Writing to and reading information from SRAM expends valuable energy. Reduction of such energy expenditures by SRAM is desirable.
- SRAM static random access memory
- One use of SRAM is in an information handling system (IHS) to store information in an SRAM array.
- IHS information handling system
- a memory array in one embodiment, includes a plurality of memory cells configured in rows and columns.
- the memory array includes a first pair of memory cells situated in a first row of the memory array.
- the first pair of memory cells includes first and second memory cells that couple to a first intra-pair bitline between the first and second cells to share the first intra-pair bitline.
- the first and second memory cells also couple to first and second opposed inter-pair bitlines, respectively.
- the first and second memory cells are configured to couple via the first and second opposed inter-pair bitlines to second and third pairs of memory cells, respectively, in the first row of the memory array.
- an information handling system in another embodiment, is disclosed.
- the IHS includes a processor.
- the IHS also includes a memory that is coupled to the processor.
- the memory includes a plurality of memory cells configured in a memory array of rows and columns.
- the memory includes a first pair of memory cells situated in a first row of the memory array.
- the first pair of memory cells includes first and second memory cells that couple to a first intra-pair bitline between the first and second cells to share the first intra-pair bitline.
- the first and second memory cells also couple to first and second opposed inter-pair bitlines, respectively.
- the first and second memory cells are configured to couple via the first and second opposed inter-pair bitlines to second and third pairs of memory cells, respectively, in the first row of the memory array.
- a method in yet another embodiment, includes configuring a plurality of memory cells in rows and columns, wherein a first pair of memory cells is situated in a first row of the memory array.
- the first pair of memory cells includes first and second memory cells that couple to a first intra-pair bitline between the first and second cells to share the first intra-pair bitline.
- the first and second memory cells also couple to first and second opposed inter-pair bitlines, respectively.
- the method also includes sharing the first intra-pair bitline for writing and reading operations of the first pair of memory cells.
- the method further includes sharing the first opposed inter-pair bitline with a second pair of memory cells adjacent the first pair of memory cells in the first row for writing and reading operations of the first pair of memory cells and the second pair of memory cells.
- the method still further includes sharing the second opposed inter-pair bitline with a third pair of memory cells adjacent the first pair of memory cells in the first row for writing and reading operations of the first pair of memory cells and the third pair of memory cells.
- FIG. 1 is a schematic diagram of one embodiment of the disclosed memory circuit including a pair of SRAM memory cells.
- FIG. 2 is a block diagram of one embodiment of the disclosed array of memory cells.
- FIG. 3A is a flow chart that depicts one method for reading the contents of a memory cell.
- FIG. 3B is a flow chart that depicts one method for reading the contents of another memory cell.
- FIG. 4 is an information handling system (IHS) that includes the disclosed array of memory cells.
- IHS information handling system
- FIG. 5 is a schematic diagram of another embodiment of a the disclosed memory circuit including a pair of SRAM memory cells.
- FIG. 6 is a block diagram of another embodiment of the disclosed array of memory cells.
- FIG. 7 is a schematic diagram of a read/write head used included in the disclosed memory array.
- FIG. 8A is a is a flow chart that depicts a method for reading from the contents a memory cell.
- FIG. 8B is a is a flow chart that depicts a method for writing to a memory cell.
- FIG. 9 illustrates a representative portion of a memory cell layout pattern that practices the disclosed methodology.
- the disclosed memory circuit includes an array of memory cells wherein memory cells in adjacent columns share both complement (bl′) and true (bl) bitlines on boundaries between cells to provide energy saving during a read operation. More particularly, the two memory cells of a particular memory cell pair share an intra-cell bitline between the two cells of that pair. Moreover, adjacent pairs of memory cells may share an inter-cell bitline between the pairs of memory cells.
- a read/write head provides robust differential writing of data to the memory cells of the memory cell pairs, as well as energy efficient reading of memory cell data.
- Memory cells may be manufactured on integrated circuit wafers. Overlapping memory cells slightly may provide desirably efficient use of wafer area while leaving sufficient space for placing wordline pairs in each row of memory.
- FIG. 1 is a schematic diagram of one embodiment of the disclosed memory circuit 100 .
- memory circuit 100 includes at least static random access memory (SRAM) cells 101 and 102 arranged in at least two columns.
- SRAM static random access memory
- FIG. 1 shows only the memory cells 101 and 102 that may form the top-most cells of respective columns in a memory array. Other like memory cells may populate a memory array of columns and rows, such as the memory array that FIG. 2 shows.
- Memory cell 101 includes a cross-coupled inverter pair 105 , 110 for storing a data bit.
- memory cell 101 also includes pass-devices 115 and 120 that couple to inverters 105 and 110 to facilitate the reading and writing of information for that memory cell.
- Memory cell 102 includes a cross-coupled inverter pair 145 , 150 for storing another data bit.
- Memory cell 102 also includes pass-devices 155 and 160 that couple to inverters 145 and 150 to facilitate the reading and writing of information for that memory cell.
- Memory cells 101 and 102 may each store a logic value of the cross-coupled inverter pairs 145 , 150 and 155 , 160 respectively that may be accessed as either a true (T) data bit or a complement (C) bit.
- Bitlines bl 125 and blb 130 couple to memory cell 101 .
- the designations “bl” and “blb” indicate that these bitlines are differential bitlines that complement one another.
- bitline bl 125 is a true bitline and bitline blb 130 is a complement bitline. In other embodiments, the roles of bitlines 125 and 130 may reverse.
- Bitlines bl 165 and blb 170 and also wordlines wl_A 190 and wl_B 195 , couple to memory cell 102 .
- Bitlines blb 130 and blb 170 couple to the respective downstream output gates 103 and 103 ′.
- data output gates 103 and 103 ′ function as evaluation gates for data content of memory cells 101 and 102 .
- gate 103 and gate 103 ′ may be implemented as two inverters, wherein one inverter couples to bitline 130 and the other inverter couples to bitline 170 .
- Bitlines blb 130 and blb 170 are corresponding bitlines of SRAM memory cells 101 and 102 because they each exhibit the same logic convention in their respective SRAM cells.
- Data output gate 103 senses bitlines blb 130 and data output gate 103 ′ senses blb 170 in a single-ended read operation of the complement of the logic value that cell 101 or 102 stores depending on which wordline, wl_A 190 or wl_B 195 , activates during the read operation.
- Gate 103 or gate 103 ′ thus acts as an evaluation gate for the data contents of the selected memory cell and outputs the data content of the addressed memory cell on output data_out 104 or data_out 104 ′ respectively in one embodiment.
- the output data bit at data_out 104 corresponds to the stored bit in memory cell 101 when the wordline wl_A 190 activates for a single-ended read operation.
- the output data bit at data_out 104 ′ corresponds to the stored bit in memory cell 102 when wordline wl_B 195 activates for a single-ended read operation.
- Bitline drive circuit ( 230 in FIG. 2 ) couples to bitlines bl 125 and blb 130 , or to bl 165 and blb 170 to select a particular one of memory cells 101 and 102 , i.e. a particular column, for a write operation.
- Wordline drive circuit ( 240 in FIG. 2 ) couples to wordlines wl_A 190 and wl_B 195 to select a particular row of a memory array that multiple rows and columns of memory cells 101 and 102 may form.
- wordline drive circuit selects and activates both wordlines wl_A 190 and wl_B 195 .
- this action effectively connects pass-device 115 to bitline bl 125 and also connects pass device 120 to bitline blb 130 .
- Differentially activating bitlines bl 125 and blb 130 in this manner writes a data bit into memory cell 101 by forcing the inverter pair 105 , 110 to assume a state corresponding to the state of bitlines 125 and 130 .
- bitline drive circuit ( 230 in FIG.
- bitline drive circuit ( 230 in FIG. 2 ) forces the desired logic state onto bitline 125 while also forcing the complement of the desired logic value onto bitline 130 .
- the bitline drive circuit ( 230 in FIG. 2 ) need not drive bitlines bl 165 and blb 170 that associate with memory cell 102 .
- wordline drive circuit ( 240 in FIG. 2 ) activates both wordlines wl_A 190 and wl_B 195 to write information to memory cell 101 , this action also activates pass devices 155 and 160 of memory cell 102 . However, this action does not affect the contents of memory cell 102 because bitline drive circuitry (not shown) does not activate bitlines blb 165 and blb 170 when performing a write operation to memory cell 101 .
- Memory cell arrays may include a single row or multiple rows with multiple columns.
- the particular aspect ratio of the rows and columns may depend on the application for the memory cell array and other considerations such as the energy needed to pre-charge bitlines and timing considerations.
- At least two columns of memory cells form the exemplary embodiment of the disclosed memory circuit.
- FIG. 2 shows the disclosed memory array 200 of memory cells 101 , 102 arranged in columns and rows.
- the columns are arranged in pairs of cells according to the teachings of FIG. 1 with representative memory cell pairs 101 , 102 being identified in particular in row 1 .
- This particular embodiment includes four (4) rows of cells, namely rows 1 , 2 , 3 and 4 .
- Other embodiments may include a larger or smaller number of rows of cells depending on the particular application. For example, eight or sixteen columns may be included in the memory array to accommodate bytes of data. Similarly, nine or eighteen columns may be included in the memory array to accommodate bytes of data with a parity check bit. While memory array 200 may include fewer or more columns than the six (6) representative columns that FIG. 2 shows, for discussion purposes FIG.
- FIG. 2 identifies the two center columns of array 200 as column A (COL A) and column B (COL B).
- Memory array 200 may include more columns than the center columns identified as column A and column B.
- FIG. 2 uses prime designators to differentiate the memory cell pairs 101 , 102 in the different rows of memory array 200 .
- row 1 includes memory cells 101 , 102 in COL A and COL B, respectively.
- Row 2 includes memory cells 101 ′, 102 ′ in COL A and COL B, respectively.
- Row 3 includes memory cells 101 ′′, 102 ′′ in COL A and COL B, respectively.
- Row 4 includes memory cells 101 ′′′, 102 ′′′ in COL A and COL B, respectively.
- bitlines bl 125 and blb 130 of COL A extend vertically through each of memory cells 101 , 101 ′, 101 ′′ and 101 ′′′. Bitline blb 130 of COL A also couples to the input of gate 103 .
- bitlines bl 165 and blb 170 of COL B extend vertically through each of memory cells 102 , 102 ′, 102 ′′ and 102 ′′′. Bitline blb 170 of COL B also couples to the input of gate 103 ′.
- Bitlines bl 125 and 165 extend vertically through each of the memory cells in COL A and COL B, and terminate in ends 125 A and 165 A as also shown in FIG. 1 .
- the terminations at ends 125 A and 165 A may be open circuits.
- differential bitline drive circuit 230 selects the appropriate bitlines to designate a particular column for differential write operations to a memory cell in memory array 200 .
- Wordline drive circuit 240 further selects a particular row of memory array 200 by activating appropriate wordlines 220 corresponding to that row.
- the differential pair of bitlines 125 and 130 along with wordlines wl_A 190 and wl_B 195 in row 1 uniquely select memory cell 101 of COL A for data bit storage.
- the differential pair of bitlines 165 and 170 along with wordlines wl_A 190 and wl_B 195 of row 1 may uniquely select memory cell 102 of COL B for data bit storage.
- bitline drive circuit 230 precharges all of the bitlines 210 to the supply voltage (not specifically shown) when memory array 200 is in the quiescent or inactive state.
- the pre-charge voltage level corresponds to a logic 1.
- a memory that needlessly causes a memory cell bitline to discharge carries a penalty in wasted energy in the memory array.
- the disclosed memory array 200 may avoid wasting energy by arranging memory cells in pairs, as exemplified by memory cell pair 101 and 102 of FIGS. 1 and 2 .
- wordline drive circuit 240 activates only wordline wl_A 190 of row 1 to read the contents of memory cell 101 of COL A in row 1 .
- Bitline 130 then reflects the state of memory cell 101 .
- Bitline 125 associated with memory cell 101 of COLA, and bitlines 165 and 170 associated memory cell 102 of COL B may remain in the pre-charged state and hence do not waste energy. Leaving the bitlines in the pre-charged state may conserve energy.
- Gate 103 or gate 103 ′ senses the state of memory cell 101 or memory cell 102 respectively by passing the data bit from the selected memory cell to the data output line data_out 104 or 104 ′ via either bitline 130 or 170 .
- the output data reflects the state of the memory cell uniquely appearing on one bitlines 130 or 170 , and addressed on one corresponding wordlines wl_A 190 or wl_B 195 .
- the non-selected bitline remains at logic level 1. More specifically, gate 103 and 103 ′ couple to input bitlines 130 and 170 respectively.
- wordline wl_A 190 activates pass gate 120 of memory cell 101
- the complement of the logic state of memory cell 101 appears on bitline 130 , while bitline 170 remains in a pre-charged logical 1 state.
- wordline wl_B 195 activates pass gate 160
- the complement of the state of memory cell 102 appears on bitline 170 while bitline 130 remains in a pre-charged logical 1 state.
- TABLE 1 shows the logic states or “truth table” of gate 103 when gate 103 is an inverter.
- bitline 170 data output 104 0 1 1 1 1 1 0
- bitline 170 is in its pre-charged state (logical 1), which corresponds to the TABLE 1 entries having a logic 1 in the bitline 170 column.
- Wordline wl_A 190 activates pass device 120 which reflects the complement of the memory contents of memory cell 101 to bitline 130 . If the memory cell contains a logic 1, then the complement 0 appears on bitline 130 . From TABLE 1, a logic level 1 then appears at the data output data_out 104 . Similarly, if memory cell 101 contained a logic level 0, then the complement logic value 1 appears on bitline 130 , which results in a logic level 0 appearing at the data output data_out 104 .
- the data bit stored in memory cell 102 reflects in the data output data_out ‘ 104 when wordline wl_B 195 activates pass device 160 of memory cell 102 .
- bitline blb 130 stays at a logic 1 level.
- Memory cell 102 content of logic level 1 appears as the complement 0 on bitline blb 170 which appears as a logic level 1 at data output data_out’ 104 .
- memory cell 102 content of logic level 0 appears as the complement 1 on bitline blb 170 which appears as a logic level 0 at data output data_out 104 .
- gates 103 and 103 ′ act as evaluation gates that senses respective single-ended read bitlines of a pair of cells, and pass the data from the memory cell selected by the wordline.
- gate 103 is a inverter gate.
- Exemplary memory cells 101 and 102 each include a true memory bitline bl and a complement memory bitline blb.
- a memory read operation may be configured to sense the true bitlines with substantially equal results to the scenario wherein a memory read operation senses the complement bit lines blb. Sensing true bitlines produces the complement of the memory cell logic state at the data output.
- Table 2 below shows the state changes of the bitlines of SRAM cells 101 and 102 in row 1 of memory array 200 when wordline drive circuit 240 addresses one of cells 101 and 102 .
- Bitline state changes consume energy.
- the disclosed methodology may reduce bitline state changes.
- wordline circuit 240 addresses memory cell 101 to read the data contents of that SRAM cell.
- memory cell 101 is the addressed cell and SRAM cell 102 is the unaddressed cell of an memory cell pair.
- blb may change state according to the memory contents of the memory cell (may expend energy)
- Unaddressed memory cell bl may change state, state change does not propagate beyond this cell blb remains in precharge state (no state change)
- wordline circuit 240 addresses memory cell 101 for a read operation by activating the blb bitline 130 of memory cell 101
- the blb bitline 130 of addressed SRAM cell 101 may change state depending on the memory content of the memory cell and drives evaluation gate 103 . This state change on the blb bitline of addressed SRAM cell 101 and also the possible state change on the bl line of the unaddressed may consume energy.
- bitline 165 at 165 A for read operations when memory cell 101 is the addressed memory cell, a state change occurring on the bitline bl 165 of the unaddressed memory cell 102 does not propagate further downstream beyond termination 165 A to circuitry that might otherwise load down the bitline bl 165 and consume more energy.
- the memory circuit may conserve energy during a read operation by avoiding the need for bitline bl 165 to drive logic gates downstream of termination 165 A in the column (e.g. COL B) that includes the unaddressed memory cell 102 .
- bitline bl 165 of memory cell 102 includes an effective termination for read operations at 165 A
- bitline bl 125 of memory cell 101 includes an effective termination for read operations at 125 A.
- these terminations are effective terminations with respect to read operations and do not affect write operations.
- termination 125 A prevents the propagation of data signals further downstream beyond termination 125 A to circuitry that might otherwise load down bitline bl 125 and consume more energy.
- FIG. 3A is a flow chart describing one embodiment of the disclosed method of reading from a column A (COL A) of the SRAM memory cells 101 and 102 .
- Process flow commences at start block 305 .
- Wordline drive circuit 240 selects wordline wl_A, as per block 310 . More particularly, wordline drive circuit 240 transmits the wordline activate signal to the column A memory cell, as per block 315 .
- the wordline activate signal turns on pass devices ( 120 and 155 in FIG. 1 ), as per block 320 .
- the complement of the data bit stored in memory cell 101 appears on the complement bit line blb 130 .
- evaluation gates 103 such as inverters in one embodiment, evaluate the complement operation of bitline blb 130 of COLA, as per block 325 .
- Evaluation gate 103 outputs a bit corresponding to the data bit stored in column A memory cell 101 at data_out 104 , as per block 330 .
- Process flow ends at end block 335 or restarts at start block 305 to read another memory cell.
- FIG. 3B is a flow chart describing one embodiment of the disclosed method of reading from a column B (COL B) of the SRAM memory cells 101 and 102 .
- Process flow commences at start block 345 .
- Wordline drive circuit 240 selects wordline wl_B, as per block 350 . More particularly, wordline drive circuit 240 transmits the wordline activate signal to the column B memory cell, as per block 355 .
- the wordline activate signal turns on pass devices ( 115 and 160 in FIG. 1 ), as per block 360 .
- the complement of the data bit stored in memory cell 101 appears on the complement bit line blb 170 .
- the evaluation gate 103 ′ (inverter) evaluates the complement of bitline blb 130 of COL B, as per block 365 .
- Evaluation gate 103 ′ outputs a bit corresponding to the data bit stored in column B memory cell 102 at data_out 104 ′, as per block 370 .
- Process flow ends at end block 375 or restarts at start block 345 to read another memory cell.
- the choice of activating either wordline wl_A or wordline wl_B selects which one of memory cells of column A or column B respectively outputs data to its respective complement bitline blb.
- the evaluation gates processes complement the respective bitlines blb, evaluating and outputting the data from the selected memory cell to the respective data_out line.
- FIG. 4 shows an information handling system (IHS) 400 that is configured to employ the disclosed SRAM memory circuit technology and is described in more detail below.
- IHS information handling system
- FIG. 5 shows another embodiment of the disclosed memory circuit as memory circuit 500 .
- Memory circuitry 500 includes of a pair of SRAM memory cells 501 and 502 that operate in an energy efficient manner. SRAM memory cells 501 and 502 are arranged in at least two columns of which FIG. 5 depicts the two top-most cells.
- Memory cell 501 includes a cross-coupled inverter pair 505 and 510 , and pass devices 515 and 520 .
- Memory cell 501 couples to bitlines bl 525 and bl′ 530 , and to wordline wl_a 595 , via pass devices 515 and 520 as shown.
- Memory cell 502 includes cross-coupled inverter pair 545 and 550 , and pass devices 555 and 560 .
- Memory cell 502 couples to bitlines bl′ 530 and bl 565 , and to wordline wl_b 590 , via pass devices 555 and 560 as shown.
- SRAM memory cells 501 and 502 share bitline bl′ 530 as discussed in more detail below.
- Pass devices 515 and 520 couple to wordline wl_a 595 at nodes 910 and 915 , respectively.
- Pass devices 555 and 560 couple to wordline wl_b 590 at nodes 920 and 925 , respectively.
- FIG. 6 shows a memory array 600 including SRAM memory cells 501 and 502 embedded in the array.
- Memory array 600 arranges the SRAM memory cells in columns and rows as shown.
- bitlines are shown generally as bitlines 605
- wordlines are shown generally as wordlines 610 , although specific bitlines and specific wordlines will have other numbers.
- Memory array 600 further includes read/write heads 700 , 700 ′ and 700 ′′.
- Memory cells 501 and 502 share bitline bl′ 530 at node 517 .
- memory cell 501 shares bitline bl 525 with adjacent memory cell 502 ′ at node 507
- memory cell 502 shares bitline bl 565 with adjacent memory cell 501 ′′ at node 527 .
- columns of memory cells share a common bitline located between the cell columns.
- activating wordline wl_a 595 during a single-ended read operation causes the complement of the data contents of memory cell 501 to appear on bitline bl′ 530 .
- activating wordline wl_b 590 causes the complement of the data contents of memory cell 502 to appear on bitline bl′ 530 .
- Data contents of either memory cell 501 or 502 appear on the same bitline bl′ 530 , thus providing sharing of this bitline bl′ 530 .
- Activation of wordline wl_a 595 or wl_b 590 uniquely selects either SRAM memory cell 501 or 502 , respectively, to place its data on shared bitline bl′ 530 .
- bitlines bl 525 and bl 565 remain at the pre-charge logic level 1 during read operations even though pass devices 515 or 560 may be active. Thus, bitlines bl 525 and bl 565 do not needlessly discharge and waste energy during read operations of cells 501 and 502 .
- wordline wl_a 595 activates pass devices 515 and 520 via nodes 910 and 915 , respectively.
- a read/write head 700 acts as a driver that forces a desired data bit onto bitline bl 525 and simultaneously forces the complement of the data bit value onto bitline bl′ 530 to write the data bit value to memory cell 501 .
- bitlines bl 525 and 565 form an opposed pair of intra-cell bitlines in that they are on opposites sides of a cell pair. Intra-cell bitlines may be shared by adjacent columns within memory cell pairs.
- FIG. 7 shows a representative read/write head 700 configured to perform single-ended reading of, and robust differential writing to, a selected memory cell in memory array 600 .
- Read/write head 700 couples to bitlines bl 525 , bl′ 530 , and bl 565 to drive data onto, and to receive data from, those bitlines during write and read operations, respectively.
- bitline bl 525 As shown in FIG. 7 , read/write head 700 shares bitline bl 525 with the partially shown read/write head 700 ′ to its left (i.e. read/write head 700 ′ in FIG. 6 ).
- read/write head 700 ′ includes gate 730 ′ further including write enable and wl_b enable inputs, which may enable driver 735 to drive data 0 data to inter-pair bitline bl 525 during a write data operation to a column B col_B memory cell exemplified by memory cell 502 ′.
- Read/write head 700 also shares bitline bl 565 with the partially shown read/write head to its right (read/write head 701 ′′ in FIG. 6 ).
- Read/write head 700 ′′ includes gate 710 ′ further including write enable and wl_a enable inputs, which may enable driver 705 to drive data 2 data to inter-pair bitline bl 565 during a write data operation to a column A col_A memory cell exemplified by memory cell 501 ′′.
- addressing circuitry transmits an enable signal on write enable input 710 A of AND gate 710 to enable driver 705 , while input 702 enables driver 720 .
- the addressing circuitry also transmits an enable signal to the remaining input 710 B of gate 710 (and also to wordline wl_a 595 ), thus enabling gate 710 .
- Driver 705 sends a data bit on input 701 to bitline bl 525 .
- the inverter 725 complements (inverts) the data bit and drives the complement of the data bit through the write enabled driver 720 onto bitline bl′ 530 for a robust write operation to memory cell 501 through the enabled pass devices 515 and 520 .
- addressing circuitry (not shown) signals wordline wl_b 590 to enable memory cell 502 and also enable gate 730 on input 730 B of FIG. 7 .
- a driver 735 sends a data bit from input 701 to bitline bl 565 through driver 735 .
- the inverter 725 complements (inverts) the data bit and drives the complement of the data bit onto bitline bl′ 530 through driver 720 for a robust write operation to memory cell 502 through the enabled pass devices 555 and 560 .
- bitline 530 is a shared bitline because memory circuit 500 employs this bitline for both write operations to memory cell 501 and write operations to memory cell 502 via the common node 517 . Since shared bitline 530 is between memory cells 501 and 502 of a particular memory cell pair, bitline 530 is an “intra-pair” shared bitline for that memory cell pair.
- the wordline wl_a 595 or wl_b 590 activates pass device 520 or pass device 555 , respectively of FIG. 5 .
- Output data driver 715 of read/write head 700 of FIG. 7 is also enabled with read enable input 706 .
- the complement of the data contents of the selected memory cell reflects to the common shared bitline bl′ 530 and transmits through driver 715 to data output 704 .
- bitline bl′ 530 reflects the complement of the data stored in the enabled memory cell, so output data driver may be configured as an inverter, so that data output 704 reflects the contents of the memory cell rather than the complement of the content of the memory cell.
- the disclosed memory circuit topology includes two different types of bitline sharing, exemplified by intra-pair bitlines 530 ′, 530 , and 530 ′′ and by inter-pair bitlines 525 and 565 .
- FIG. 6 shows that within the memory cell pair 501 , 502 the two memory cells share a common “intra-pair” bitline bl′ 530 and share a common node 517 for differential memory write operations to either of cells 501 and 502 .
- intra-pair shared bitline 530 is a bl′ bitline that passes through and couples to all of the cell pairs in the cell pair column of which memory cell pair 501 , 502 are the uppermost cells.
- Intra-pair bitline bl′ 530 couples as well to read/write head 700 , as FIG. 7 depicts.
- Memory array 600 also uses intra-pair bitline bl′ 530 for single-ended read operations.
- the disclosed memory circuit topology also employs “inter-pair” bitline sharing that is a type of bitline sharing different from the “intra-pair” bitline sharing discussed above.
- “intra-pair” bitline sharing refers to sharing of a bitline by two cells within a cell pair in a particular row
- “inter-pair” bitline sharing refers to sharing of a bitline between two adjacent cell pairs in the same row of the memory array, such as memory array 600 .
- cell pair 501 , 502 and cell pair 501 ′, 502 ′ share inter-pair bitline bl 525 that runs between these two cell pairs, as illustrated in FIG. 6 .
- cell pair 501 , 502 and cell pair 501 ′′, 502 ′′ share inter-pair bitline bl 565 that runs between these two cell pairs.
- Memory array 600 replicates the topology of the three cell pairs of row 1 in the remaining square boxes of memory array 600 in rows 2 , 3 and 4 below row 1 .
- the read/write heads 700 ′, 700 and 700 ′′ cooperate with the intra-pair bitline sharing and inter-pair bitline sharing arrangement above to efficiently write data to, and read data from, the memory cells of memory array 600 . Since bitline bl 525 ′ and bitline bl 565 ′′ are situated on the peripheral edge or border of the memory array, the memory array does not implement inter-pair bitline sharing for these particular bitlines.
- Table 3 summarizes the different types of bitline sharing that memory array 600 employs to efficiently write data to, and read data from, the memory array. As seen in Table 3, write operations employ both the disclosed intra-pair bitline sharing and inter-pair bitline sharing, while read operations employ the disclosed single-ended intra-pair bitline sharing.
- FIG. 8A is a flow chart describing a representative read memory operation from a memory cell in the disclosed SRAM array 600 .
- the read memory operation to memory cell 501 or memory cell 502 starts at start block 805 .
- Read/write head 700 transmits a wordline select signal to select wordline wl_a 595 or wordline wl_b 590 of wordline drive circuit 620 , as per block 810 , corresponding to memory cell 501 or memory cell 502 respectively.
- the memory read circuit of read/write head 700 transmits a wordline enable signal to the wordline drive circuit 620 driving the selected wordline wl_a 595 or wordline wl_b 590 corresponding to memory cell 501 or 502 respectively, as per block 815 .
- the wordline drive circuit 620 transmits an on signal to pass device 520 in memory cell 501 on wordline wl_a 595 , or to pass device 555 on wordline wl_b 590 which turns on the memory cell pass device 520 of memory cell 501 or turns on the memory cell pass device 555 of memory cell 502 respectively, as per block 820 .
- the memory read circuit of read/write head 700 also transmits a read enable signal 706 to gate 715 coupling the shared complement bitline bl′ 530 in the read/write head to data out 1 704 , as per block 825 .
- Gate 715 evaluates the complement bitline bl′ 530 , as per block 830 .
- Gate 715 outputs the data corresponding to the contents of the selected memory cell 501 or memory cell 502 from complement bitline bl′ 530 on the data out 1 line at 704 , as per block 835 .
- the read memory operation terminates according to block 840 .
- the disclosed memory circuit may commence another memory read or write operation immediately after the read operation discussed above.
- FIG. 8B shows a flow chart describing a representative write operation to a memory cell of the disclosed SRAM array.
- the write memory operation begins at start block 850 .
- the write memory circuit of read/write head 700 selects either wordline wl_a 595 to write data to memory cell 501 , or wordline wl_b 590 to write data to memory cell 502 , according to block 855 .
- the write memory circuit transmits a wordline enable signal as per block 860 to the wordline drive circuit 620 (which enables both pass devices 515 and 520 or both pass devices 555 and 560 of memory cell 501 or 502 respectively), and to enable either gate 710 or gate 730 in the read/write head controlling driver of the bitline corresponding to a write operation to memory cell 501 or 502 respectively.
- the write memory circuit transmits a write enable signal 710 A or 730 A to gate 710 or 730 controlling the driver 705 or 735 of the selected bitline bl 525 or bitline bl 565 respectively, and to driver of the shared complement bitline 530 in the read/write head 700 as per block 865 .
- the read/write head 700 receives data from data input (write data 1 ) 701 , as per block 870 .
- the read/write head 700 writes data to the selected memory cell as per block 875 by driving the data through the bitline driver 705 or 735 to bitline 525 or 565 , and by driving the data complemented by inverter 725 through driver 720 to the shared complement bitline bl′ 530 for a differential write memory operation of the memory cell 501 or 502 respectively.
- the write memory operation terminates according to block 880 .
- the disclosed memory circuit may commence another memory read or write operation immediately after the write operation discussed above.
- FIG. 9 shows a representative portion of an integrated circuit layout pattern that practices the disclosed methodology.
- Memory array 900 includes memory cell pair 501 , 502 , and memory cell pair 901 , 902 .
- Memory cells 501 , 502 , 901 , 902 occupy areas bounded by borders 935 , 940 , 945 and 950 , respectively.
- Memory cells physically overlap slightly to conserve space in array 900 .
- cell area borders 935 and 945 overlap by a width 905 .
- the entire ROW 1 of memory cells slightly overlaps ROW 2 of memory cells by width 905 .
- columns of memory cells overlap slightly to conserve space.
- memory cell borders 935 and 945 of column A overlap memory cell borders 940 and 950 of column B (col_B) respectively overlap by a width 907 . More generally, adjacent rows of memory cells overlap by width 905 , and adjacent columns of cells overlap by width 907 .
- memory cells 501 and 502 exhibit a particular layout symmetry.
- the orientation of the circuitry of memory cell 502 is “upside down and reversed” with respect to the orientation of the circuitry of memory cell 501 , such that memory cells 501 and 502 exhibit quadrilateral symmetry.
- memory cell 501 couples to a bl bitline on its left edge, and bl′ bitline on its right edge, and a wordline along the lower edge.
- memory cell 502 couples to a bl bitline on its right edge, a bl′ bitline on its left edge and a wordline along the upper edge.
- columns in a column have the same symmetry, while memory cells in a particular row alternate in symmetry.
- Column B (col_B) memory cells exhibit “upside down and reversed” symmetry (quadrilateral symmetry) with respect to the column A (col_A) memory cells.
- This arrangement of symmetries facilitates sharing of bitlines between memory cells in adjacent columns. For example, the columns of memory cells adjacent to bitlines bl 525 and 565 as well as bitlines bl′ 530 and 530 ′′ (also depicted in FIG. 6 ) share those bitline, respectively.
- Memory cells 502 ′ and 501 share node 507 of bitline bl 525 .
- Memory cells 501 and 502 share node 517 of bitline bl′ 530 .
- Memory cells 502 and 501 ′′ share node 527 of bitline bl 565 .
- the “upside down and reversed” (quadrilateral) symmetry in alternating columns of memory cells facilitates pairing of cells, exemplified by memory cells 501 and 502 , into column A (col_A) and column B (col_B) memory cells.
- Wordlines 610 alternate between wordlines that service column A (col_A) exemplified by wordline wl_a 595 , and wordlines that service column B (col_B) exemplified by wordline wl_b 590 .
- wordline wl_a 595 connects to memory cell 501 at nodes 910 and 915
- wordline wl_b 590 connects to memory cell 502 via nodes 920 and 925
- Nodes 910 ′ and 915 ′, and nodes 920 ′ and 925 ′ connect wl_a and wl_b wordlines to memory cells 901 and 902 respectively.
- wordlines 610 serve alternate columns of memory cells, with wl_a wordlines coupled to col_A memory cells and wl_b wordlines coupled to col_B memory cells.
- pairs of memory cells exhibiting quadrilateral symmetry it is meant that the topology of the memory cell pairs is such that pairs of memory cells are reflected in both the horizontal and vertical axes, e.g. column B (col_B) memory cells are upside-down and reversed with column A (col_A) memory cells.
- the arrangement of symmetries in memory cells facilitates straight paths for wordlines 610 which in turn facilitates compact arrangement of memory cells along columns. Sharing bitlines facilitates compact arrangement of memory cells in the along rows.
- the symmetries and pairing of memory cells according to the embodiment facilitates a more compact memory array than in other arrangements, and sharing of bitlines results in energy efficiency of reading SRAM.
- Sharing of the bitlines as provided by the exemplary embodiments has the benefit that the memory read operation does not needlessly discharge bitlines associated with memory cells for which the data would be discarded. Practicing the disclosed technology may achieve significant energy savings.
- IHS 400 employs the disclosed SRAM memory array 200 and/or 600 as SRAM cache 450 and/or SRAM system memory 420 .
- IHS 400 includes a processor 410 that may include multiple cores and SRAM cache 450 .
- IHS 400 processes, transfers, communicates, modifies, stores or otherwise handles information in digital form, analog form or other form.
- IHS 400 includes a bus 415 that couples processor 410 to system memory 420 via a memory controller 425 and memory bus 430 .
- system memory 420 is external to processor 410 .
- System memory 420 may be a static random access memory (SRAM) array of FIG. 2 or FIG. 6 and/or a dynamic random access memory (DRAM) array.
- SRAM static random access memory
- DRAM dynamic random access memory
- a video graphics controller 435 couples display 440 to bus 415 .
- Nonvolatile storage 445 such as a hard disk drive, CD drive, DVD drive, or other nonvolatile storage couples to bus 415 to provide IHS 400 with permanent storage of information.
- I/O devices 490 such as a keyboard and a mouse pointing device, couple to bus 415 via I/O controller 455 and I/O bus 460 .
- One or more expansion busses 465 such as USB, IEEE 1394 bus, ATA, SATA, PCI, PCIE, DVI, HDMI and other busses, couple to bus 415 to facilitate the connection of peripherals and devices to IHS 400 .
- a network interface adapter 405 couples to bus 415 to enable IHS 400 to connect by wires or wirelessly to a network and other information handling systems.
- IHS 400 may take the form of a desktop, server, portable, laptop, notebook, or other form factor computer or data processing system.
- IHS 400 may take other form factors such as a gaming device, a personal digital assistant (PDA), a portable telephone device, a communication device or other devices that include a processor and memory.
- PDA personal digital assistant
- IHS 400 is especially sensitive to energy consumption in the form of a portable, laptop, notebook, gaming device, PDA or any battery-powered device.
- IHS 400 may include a computer program product on digital media 475 such as a CD, DVD or other media.
- digital media 475 includes an application 482 .
- a user may load application 482 on nonvolatile storage 445 as application 482 ′.
- Nonvolatile storage 445 may store an operating system 481 .
- IHS 400 initializes, the IHS loads operating system 481 and application 485 ′ into system memory 420 for execution as operating system 481 ′ and application 482 ′′.
- Operating system 481 ′ governs the operation of IHS 400 .
Abstract
A memory includes an array of memory cells that form rows and columns. The rows of the array include memory cell pairs. The memory cells may include two cross-coupled inverters and two pass-devices that couple to alternate sides of the cross-coupled inverters. The two memory cells of a memory cell pair share a common intra-pair bitline. Adjacent memory cell pairs share a common inter-pair bitline. To perform a data read operation on a particular memory cell in a memory cell pair in the rows and columns of the array, wordline drive circuitry transmits wordline activate signals to select both the row for the data read operation and a particular one of the pair of memory cells for the data read operation.
Description
- This patent application relates to the U.S. patent application entitled “Single-Ended Volatile Memory Access”, inventors Michael Lee and Bao Truong, Attorney Docket No. AUS920110481US1 (application Ser. No. to be assigned, filed on the same day as the subject patent application, and assigned to the same assignee), the disclosure of which is incorporated herein by reference in its entirety.
- The disclosures herein relate generally to volatile memory, and more specifically, to writing information to and reading information from static random access memory (SRAM). Writing to and reading information from SRAM expends valuable energy. Reduction of such energy expenditures by SRAM is desirable. One use of SRAM is in an information handling system (IHS) to store information in an SRAM array.
- In one embodiment, a memory array is disclosed that includes a plurality of memory cells configured in rows and columns. The memory array includes a first pair of memory cells situated in a first row of the memory array. The first pair of memory cells includes first and second memory cells that couple to a first intra-pair bitline between the first and second cells to share the first intra-pair bitline. The first and second memory cells also couple to first and second opposed inter-pair bitlines, respectively. The first and second memory cells are configured to couple via the first and second opposed inter-pair bitlines to second and third pairs of memory cells, respectively, in the first row of the memory array.
- In another embodiment, an information handling system (IHS) is disclosed. The IHS includes a processor. The IHS also includes a memory that is coupled to the processor. The memory includes a plurality of memory cells configured in a memory array of rows and columns. The memory includes a first pair of memory cells situated in a first row of the memory array. The first pair of memory cells includes first and second memory cells that couple to a first intra-pair bitline between the first and second cells to share the first intra-pair bitline. The first and second memory cells also couple to first and second opposed inter-pair bitlines, respectively. The first and second memory cells are configured to couple via the first and second opposed inter-pair bitlines to second and third pairs of memory cells, respectively, in the first row of the memory array.
- In yet another embodiment, a method is disclosed that includes configuring a plurality of memory cells in rows and columns, wherein a first pair of memory cells is situated in a first row of the memory array. The first pair of memory cells includes first and second memory cells that couple to a first intra-pair bitline between the first and second cells to share the first intra-pair bitline. The first and second memory cells also couple to first and second opposed inter-pair bitlines, respectively. The method also includes sharing the first intra-pair bitline for writing and reading operations of the first pair of memory cells. The method further includes sharing the first opposed inter-pair bitline with a second pair of memory cells adjacent the first pair of memory cells in the first row for writing and reading operations of the first pair of memory cells and the second pair of memory cells. The method still further includes sharing the second opposed inter-pair bitline with a third pair of memory cells adjacent the first pair of memory cells in the first row for writing and reading operations of the first pair of memory cells and the third pair of memory cells.
- The appended drawings illustrate only exemplary embodiments of the invention and therefore do not limit its scope because the inventive concepts lend themselves to other equally effective embodiments.
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FIG. 1 is a schematic diagram of one embodiment of the disclosed memory circuit including a pair of SRAM memory cells. -
FIG. 2 is a block diagram of one embodiment of the disclosed array of memory cells. -
FIG. 3A is a flow chart that depicts one method for reading the contents of a memory cell. -
FIG. 3B is a flow chart that depicts one method for reading the contents of another memory cell. -
FIG. 4 is an information handling system (IHS) that includes the disclosed array of memory cells. -
FIG. 5 is a schematic diagram of another embodiment of a the disclosed memory circuit including a pair of SRAM memory cells. -
FIG. 6 is a block diagram of another embodiment of the disclosed array of memory cells. -
FIG. 7 is a schematic diagram of a read/write head used included in the disclosed memory array. -
FIG. 8A is a is a flow chart that depicts a method for reading from the contents a memory cell. -
FIG. 8B is a is a flow chart that depicts a method for writing to a memory cell. -
FIG. 9 illustrates a representative portion of a memory cell layout pattern that practices the disclosed methodology. - In one embodiment, the disclosed memory circuit includes an array of memory cells wherein memory cells in adjacent columns share both complement (bl′) and true (bl) bitlines on boundaries between cells to provide energy saving during a read operation. More particularly, the two memory cells of a particular memory cell pair share an intra-cell bitline between the two cells of that pair. Moreover, adjacent pairs of memory cells may share an inter-cell bitline between the pairs of memory cells. A read/write head provides robust differential writing of data to the memory cells of the memory cell pairs, as well as energy efficient reading of memory cell data. Memory cells may be manufactured on integrated circuit wafers. Overlapping memory cells slightly may provide desirably efficient use of wafer area while leaving sufficient space for placing wordline pairs in each row of memory.
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FIG. 1 is a schematic diagram of one embodiment of the disclosedmemory circuit 100. In this particular embodiment,memory circuit 100 includes at least static random access memory (SRAM)cells FIG. 1 shows only thememory cells FIG. 2 shows.Memory cell 101 includes across-coupled inverter pair FIG. 1 ,memory cell 101 also includes pass-devices inverters Memory cell 102 includes across-coupled inverter pair Memory cell 102 also includes pass-devices inverters Memory cells cross-coupled inverter pairs -
Bitlines bl 125 andblb 130, and also wordlines wl_A 190 andwl_B 195, couple tomemory cell 101. The designations “bl” and “blb” indicate that these bitlines are differential bitlines that complement one another. In one embodiment,bitline bl 125 is a true bitline andbitline blb 130 is a complement bitline. In other embodiments, the roles ofbitlines Bitlines bl 165 andblb 170, and also wordlineswl_A 190 andwl_B 195, couple tomemory cell 102.Bitlines blb 130 andblb 170 couple to the respectivedownstream output gates data output gates memory cells gate 103 andgate 103′ may be implemented as two inverters, wherein one inverter couples to bitline 130 and the other inverter couples tobitline 170.Bitlines blb 130 andblb 170 are corresponding bitlines ofSRAM memory cells Data output gate 103 senses bitlines blb 130 anddata output gate 103′ senses blb 170 in a single-ended read operation of the complement of the logic value thatcell wl_A 190 orwl_B 195, activates during the read operation.Gate 103 orgate 103′ thus acts as an evaluation gate for the data contents of the selected memory cell and outputs the data content of the addressed memory cell onoutput data_out 104 or data_out 104′ respectively in one embodiment. - More particularly, the output data bit at
data_out 104 corresponds to the stored bit inmemory cell 101 when thewordline wl_A 190 activates for a single-ended read operation. Alternatively, the output data bit atdata_out 104′ corresponds to the stored bit inmemory cell 102 when wordlinewl_B 195 activates for a single-ended read operation. Bitline drive circuit (230 inFIG. 2 ) couples to bitlines bl 125 andblb 130, or to bl 165 andblb 170 to select a particular one ofmemory cells FIG. 2 ) couples to wordlineswl_A 190 andwl_B 195 to select a particular row of a memory array that multiple rows and columns ofmemory cells - To store a data bit in
memory cell 101 during a differential write operation, wordline drive circuit (240 inFIG. 2 ) selects and activates both wordlines wl_A 190 andwl_B 195. Returning toFIG. 1 , this action effectively connects pass-device 115 tobitline bl 125 and also connectspass device 120 tobitline blb 130. Differentially activating bitlines bl 125 andblb 130 in this manner writes a data bit intomemory cell 101 by forcing theinverter pair bitlines memory cell 101, bitline drive circuit (230 inFIG. 2 ) forces the desired logic state ontobitline 125 while also forcing the complement of the desired logic value ontobitline 130. For write operations tomemory cell 101, the bitline drive circuit (230 inFIG. 2 ) need not drive bitlines bl 165 andblb 170 that associate withmemory cell 102. - When wordline drive circuit (240 in
FIG. 2 ) activates both wordlines wl_A 190 andwl_B 195 to write information tomemory cell 101, this action also activates passdevices memory cell 102. However, this action does not affect the contents ofmemory cell 102 because bitline drive circuitry (not shown) does not activate bitlines blb 165 andblb 170 when performing a write operation tomemory cell 101. - Memory cell arrays may include a single row or multiple rows with multiple columns. The particular aspect ratio of the rows and columns may depend on the application for the memory cell array and other considerations such as the energy needed to pre-charge bitlines and timing considerations. At least two columns of memory cells form the exemplary embodiment of the disclosed memory circuit.
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FIG. 2 shows the disclosedmemory array 200 ofmemory cells FIG. 1 with representative memory cell pairs 101,102 being identified in particular inrow 1. This particular embodiment includes four (4) rows of cells, namelyrows memory array 200 may include fewer or more columns than the six (6) representative columns thatFIG. 2 shows, for discussion purposesFIG. 2 identifies the two center columns ofarray 200 as column A (COL A) and column B (COL B).Memory array 200 may include more columns than the center columns identified as column A and column B.FIG. 2 uses prime designators to differentiate the memory cell pairs 101, 102 in the different rows ofmemory array 200. For example,row 1 includesmemory cells Row 2 includesmemory cells 101′, 102′ in COL A and COL B, respectively.Row 3 includesmemory cells 101″, 102″ in COL A and COL B, respectively.Row 4 includesmemory cells 101′″, 102′″ in COL A and COL B, respectively. - In
memory array 200 ofFIG. 2 , bitlines bl 125 andblb 130 of COL A extend vertically through each ofmemory cells Bitline blb 130 of COL A also couples to the input ofgate 103. Inmemory array 200, bitlines bl 165 andblb 170 of COL B extend vertically through each ofmemory cells Bitline blb 170 of COL B also couples to the input ofgate 103′.Bitlines bl ends FIG. 1 . In one embodiment, the terminations at ends 125A and 165A may be open circuits. - Returning to
FIG. 2 , the following example describes a write operation to one ofmemory cells ROW 1 ofmemory array 200, namely theparticular memory cells bitline drive circuit 230 selects the appropriate bitlines to designate a particular column for differential write operations to a memory cell inmemory array 200.Wordline drive circuit 240 further selects a particular row ofmemory array 200 by activatingappropriate wordlines 220 corresponding to that row. In particular, the differential pair ofbitlines wordlines wl_A 190 andwl_B 195 inrow 1 uniquelyselect memory cell 101 of COL A for data bit storage. Alternatively, the differential pair ofbitlines wordlines wl_A 190 andwl_B 195 ofrow 1 may uniquelyselect memory cell 102 of COL B for data bit storage. - In one embodiment,
bitline drive circuit 230 precharges all of thebitlines 210 to the supply voltage (not specifically shown) whenmemory array 200 is in the quiescent or inactive state. The pre-charge voltage level corresponds to alogic 1. A memory that needlessly causes a memory cell bitline to discharge carries a penalty in wasted energy in the memory array. The disclosedmemory array 200 may avoid wasting energy by arranging memory cells in pairs, as exemplified bymemory cell pair FIGS. 1 and 2 . In one embodiment,wordline drive circuit 240 activates only wordlinewl_A 190 ofrow 1 to read the contents ofmemory cell 101 of COL A inrow 1.Bitline 130 then reflects the state ofmemory cell 101.Bitline 125 associated withmemory cell 101 of COLA, and bitlines 165 and 170 associatedmemory cell 102 of COL B, may remain in the pre-charged state and hence do not waste energy. Leaving the bitlines in the pre-charged state may conserve energy. -
Gate 103 orgate 103′ senses the state ofmemory cell 101 ormemory cell 102 respectively by passing the data bit from the selected memory cell to the dataoutput line data_out bitline bitlines wl_B 195. The non-selected bitline remains atlogic level 1. More specifically,gate wl_A 190 activatespass gate 120 ofmemory cell 101, the complement of the logic state ofmemory cell 101 appears onbitline 130, whilebitline 170 remains in a pre-charged logical 1 state. Alternatively, when wordline wl_B195 activatespass gate 160, the complement of the state ofmemory cell 102 appears onbitline 170 whilebitline 130 remains in a pre-charged logical 1 state. - TABLE 1 shows the logic states or “truth table” of
gate 103 whengate 103 is an inverter. -
TABLE 1 bitline 130bitline 170data output 1040 1 1 1 1 0
In reading the contents ofmemory cell 101 ofrow 1,bitline 170 is in its pre-charged state (logical 1), which corresponds to the TABLE 1 entries having alogic 1 in thebitline 170 column.Wordline wl_A 190 activatespass device 120 which reflects the complement of the memory contents ofmemory cell 101 tobitline 130. If the memory cell contains alogic 1, then thecomplement 0 appears onbitline 130. From TABLE 1, alogic level 1 then appears at thedata output data_out 104. Similarly, ifmemory cell 101 contained alogic level 0, then thecomplement logic value 1 appears onbitline 130, which results in alogic level 0 appearing at thedata output data_out 104. - In a similar manner, to read the contents of
memory cell 102, the data bit stored inmemory cell 102 reflects in the data output data_out ‘104 when wordlinewl_B 195 activatespass device 160 ofmemory cell 102. In this case,bitline blb 130 stays at alogic 1 level.Memory cell 102 content oflogic level 1 appears as thecomplement 0 onbitline blb 170 which appears as alogic level 1 at data output data_out’ 104. Similarly,memory cell 102 content oflogic level 0 appears as thecomplement 1 onbitline blb 170 which appears as alogic level 0 atdata output data_out 104. - In one embodiment, since one of the two wordlines wl_A 190 and
wl_B 195 uniquely activates only one of the single-ended bitlines blb 130 andblb 170 of the pair ofmemory cells memory cells memory array 200 may reduce the discharge of energy on unneeded bitlines. In this embodiment,gates gate 103 is a inverter gate. -
Exemplary memory cells - In summary, for one embodiment of the disclosed methodology, Table 2 below shows the state changes of the bitlines of
SRAM cells row 1 ofmemory array 200 whenwordline drive circuit 240 addresses one ofcells wordline circuit 240 addressesmemory cell 101 to read the data contents of that SRAM cell. In this scenario,memory cell 101 is the addressed cell andSRAM cell 102 is the unaddressed cell of an memory cell pair. -
TABLE 2 Addressed memory cell bl remains in precharge state (no state change) blb may change state according to the memory contents of the memory cell (may expend energy) Unaddressed memory cell bl may change state, state change does not propagate beyond this cell blb remains in precharge state (no state change)
When wordlinecircuit 240 addressesmemory cell 101 for a read operation by activating the blb bitline 130 ofmemory cell 101, theblb bitline 130 of addressedSRAM cell 101 may change state depending on the memory content of the memory cell and drivesevaluation gate 103. This state change on the blb bitline of addressedSRAM cell 101 and also the possible state change on the bl line of the unaddressed may consume energy. However, in one embodiment, by virtue of the effective termination ofbitline 165 at 165A for read operations (FIG. 1 andFIG. 2 ), whenmemory cell 101 is the addressed memory cell, a state change occurring on the bitline bl 165 of theunaddressed memory cell 102 does not propagate further downstream beyondtermination 165A to circuitry that might otherwise load down thebitline bl 165 and consume more energy. In this manner, the memory circuit may conserve energy during a read operation by avoiding the need forbitline bl 165 to drive logic gates downstream oftermination 165A in the column (e.g. COL B) that includes theunaddressed memory cell 102. The remaining bitline bl of addressedSRAM cell 101 and the bitline blb ofunaddressed memory cell 102 remain in the precharge state, thus conserving energy during a read operation. Whereas bitline bl 165 ofmemory cell 102 includes an effective termination for read operations at 165A, bitline bl 125 ofmemory cell 101 includes an effective termination for read operations at 125A. In one embodiment, these terminations are effective terminations with respect to read operations and do not affect write operations. The teachings above apply in a similar manner whenmemory cells memory cell 102 is the addressed memory cell andmemory cell 101 is the unaddressed memory cell. In that case, whenmemory cell 102 becomes the addressed memory cell andmemory cell 101 is the unaddressed memory cell, thentermination 125A prevents the propagation of data signals further downstream beyondtermination 125A to circuitry that might otherwise load downbitline bl 125 and consume more energy. -
FIG. 3A is a flow chart describing one embodiment of the disclosed method of reading from a column A (COL A) of theSRAM memory cells start block 305.Wordline drive circuit 240 selects wordline wl_A, as perblock 310. More particularly,wordline drive circuit 240 transmits the wordline activate signal to the column A memory cell, as perblock 315. The wordline activate signal turns on pass devices (120 and 155 inFIG. 1 ), as perblock 320. In response, the complement of the data bit stored inmemory cell 101 appears on the complementbit line blb 130. Theevaluation gates 103, such as inverters in one embodiment, evaluate the complement operation ofbitline blb 130 of COLA, as perblock 325.Evaluation gate 103 outputs a bit corresponding to the data bit stored in columnA memory cell 101 atdata_out 104, as perblock 330. Process flow ends atend block 335 or restarts at start block 305 to read another memory cell. -
FIG. 3B is a flow chart describing one embodiment of the disclosed method of reading from a column B (COL B) of theSRAM memory cells start block 345.Wordline drive circuit 240 selects wordline wl_B, as perblock 350. More particularly,wordline drive circuit 240 transmits the wordline activate signal to the column B memory cell, as perblock 355. The wordline activate signal turns on pass devices (115 and 160 inFIG. 1 ), as perblock 360. In response, the complement of the data bit stored inmemory cell 101 appears on the complementbit line blb 170. Theevaluation gate 103′ (inverter) evaluates the complement ofbitline blb 130 of COL B, as perblock 365.Evaluation gate 103′ outputs a bit corresponding to the data bit stored in columnB memory cell 102 at data_out 104′, as perblock 370. Process flow ends atend block 375 or restarts at start block 345 to read another memory cell. - In summary, the choice of activating either wordline wl_A or wordline wl_B selects which one of memory cells of column A or column B respectively outputs data to its respective complement bitline blb. The evaluation gates processes complement the respective bitlines blb, evaluating and outputting the data from the selected memory cell to the respective data_out line.
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FIG. 4 shows an information handling system (IHS) 400 that is configured to employ the disclosed SRAM memory circuit technology and is described in more detail below. -
FIG. 5 shows another embodiment of the disclosed memory circuit asmemory circuit 500.Memory circuitry 500 includes of a pair ofSRAM memory cells SRAM memory cells FIG. 5 depicts the two top-most cells.Memory cell 501 includes across-coupled inverter pair devices Memory cell 501 couples to bitlines bl 525 and bl′ 530, and to wordlinewl_a 595, viapass devices Memory cell 502 includescross-coupled inverter pair devices Memory cell 502 couples to bitlines bl′ 530 andbl 565, and to wordlinewl_b 590, viapass devices SRAM memory cells devices nodes devices nodes -
FIG. 6 shows amemory array 600 includingSRAM memory cells Memory array 600 arranges the SRAM memory cells in columns and rows as shown. InFIG. 6 , bitlines are shown generally asbitlines 605 and wordlines are shown generally aswordlines 610, although specific bitlines and specific wordlines will have other numbers.Memory array 600 further includes read/write heads 700, 700′ and 700″.Memory cells node 517. Moreover,memory cell 501 shares bitline bl 525 withadjacent memory cell 502′ atnode 507, whilememory cell 502 shares bitline bl 565 withadjacent memory cell 501″ atnode 527. In general, inmemory array 600, columns of memory cells share a common bitline located between the cell columns. - Returning now to
FIG. 5 , activating wordlinewl_a 595 during a single-ended read operation causes the complement of the data contents ofmemory cell 501 to appear on bitline bl′ 530. Similarly, activating wordlinewl_b 590 causes the complement of the data contents ofmemory cell 502 to appear on bitline bl′ 530. Data contents of eithermemory cell wl_b 590 uniquely selects eitherSRAM memory cell bl 565 remain at thepre-charge logic level 1 during read operations even thoughpass devices bl 565 do not needlessly discharge and waste energy during read operations ofcells - During a differential write operation to
memory cell 501 ofSRAM cell pair devices nodes FIG. 7 ) acts as a driver that forces a desired data bit ontobitline bl 525 and simultaneously forces the complement of the data bit value onto bitline bl′ 530 to write the data bit value tomemory cell 501. Similarly, when selecting wordlinewl_b 590 for a differential write operation tomemory cell 502 ofSRAM cell pair write head 700 forces a desired data bit value ontobitline bl 565 and forces the complement of that data bit value onto the shared bitline bl′ 530.Bitlines bl -
FIG. 7 shows a representative read/write head 700 configured to perform single-ended reading of, and robust differential writing to, a selected memory cell inmemory array 600. Read/write head 700 couples to bitlines bl 525, bl′ 530, and bl 565 to drive data onto, and to receive data from, those bitlines during write and read operations, respectively. As shown inFIG. 7 , read/write head 700 shares bitline bl 525 with the partially shown read/write head 700′ to its left (i.e. read/write head 700′ inFIG. 6 ). Returning toFIG. 7 , read/write head 700′ includesgate 730′ further including write enable and wl_b enable inputs, which may enabledriver 735 to drive data0 data to inter-pair bitline bl 525 during a write data operation to a column B col_B memory cell exemplified bymemory cell 502′. Read/write head 700 also shares bitline bl 565 with the partially shown read/write head to its right (read/write head 701″ inFIG. 6 ). Read/write head 700″ includesgate 710′ further including write enable and wl_a enable inputs, which may enabledriver 705 to drive data2 data to inter-pair bitline bl 565 during a write data operation to a column A col_A memory cell exemplified bymemory cell 501″. - During a differential write operation to
memory cell 501 of an SRAMmemory cell pair input 710A of ANDgate 710 to enabledriver 705, whileinput 702 enablesdriver 720. For this write operation tomemory cell 501 to proceed, the addressing circuitry (not shown) also transmits an enable signal to the remaininginput 710B of gate 710 (and also to wordline wl_a 595), thus enablinggate 710.Driver 705 sends a data bit oninput 701 tobitline bl 525. Simultaneously, theinverter 725 complements (inverts) the data bit and drives the complement of the data bit through the write enableddriver 720 onto bitline bl′ 530 for a robust write operation tomemory cell 501 through theenabled pass devices - For a differential write operation to
memory cell 502 ofFIG. 5 , addressing circuitry (not shown) signals wordline wl_b 590 to enablememory cell 502 and also enablegate 730 oninput 730B ofFIG. 7 . More specifically, adriver 735 sends a data bit frominput 701 tobitline bl 565 throughdriver 735. Simultaneously, theinverter 725 complements (inverts) the data bit and drives the complement of the data bit onto bitline bl′ 530 throughdriver 720 for a robust write operation tomemory cell 502 through theenabled pass devices write head 700 differentially writes toSRAM memory cell 501 viabitlines write head 700 differentially writes toSRAM memory cell 502 viabitlines Bitline 530 is a shared bitline becausememory circuit 500 employs this bitline for both write operations tomemory cell 501 and write operations tomemory cell 502 via thecommon node 517. Since sharedbitline 530 is betweenmemory cells bitline 530 is an “intra-pair” shared bitline for that memory cell pair. - During a singled-ended read operation, the wordline wl_a 595 or
wl_b 590 activatespass device 520 orpass device 555, respectively ofFIG. 5 . Output data driver 715 of read/write head 700 ofFIG. 7 is also enabled with read enableinput 706. The complement of the data contents of the selected memory cell reflects to the common shared bitline bl′ 530 and transmits through driver 715 todata output 704. In this embodiment bitline bl′ 530 reflects the complement of the data stored in the enabled memory cell, so output data driver may be configured as an inverter, so thatdata output 704 reflects the contents of the memory cell rather than the complement of the content of the memory cell. - Returning to
FIG. 6 , the disclosed memory circuit topology includes two different types of bitline sharing, exemplified byintra-pair bitlines 530′, 530, and 530″ and byinter-pair bitlines memory cell pair row 1 as a representative memory cell pair,FIG. 6 shows that within thememory cell pair common node 517 for differential memory write operations to either ofcells row 2 the memory cell pairs 901 and 902 belowmemory cell pair bitline 530 is a bl′ bitline that passes through and couples to all of the cell pairs in the cell pair column of whichmemory cell pair write head 700, asFIG. 7 depicts.Memory array 600 also uses intra-pair bitline bl′ 530 for single-ended read operations. - Returning again to
FIG. 6 , the disclosed memory circuit topology also employs “inter-pair” bitline sharing that is a type of bitline sharing different from the “intra-pair” bitline sharing discussed above. Whereas “intra-pair” bitline sharing refers to sharing of a bitline by two cells within a cell pair in a particular row, “inter-pair” bitline sharing refers to sharing of a bitline between two adjacent cell pairs in the same row of the memory array, such asmemory array 600. For example,cell pair cell pair 501′, 502′ share inter-pair bitline bl 525 that runs between these two cell pairs, as illustrated inFIG. 6 . Likewise,cell pair cell pair 501″, 502″ share inter-pair bitline bl 565 that runs between these two cell pairs.Memory array 600 replicates the topology of the three cell pairs ofrow 1 in the remaining square boxes ofmemory array 600 inrows row 1. The read/write heads 700′, 700 and 700″ cooperate with the intra-pair bitline sharing and inter-pair bitline sharing arrangement above to efficiently write data to, and read data from, the memory cells ofmemory array 600. Sincebitline bl 525′ andbitline bl 565″ are situated on the peripheral edge or border of the memory array, the memory array does not implement inter-pair bitline sharing for these particular bitlines. -
TABLE 3 Write Operations intra-pair bitline sharing inter-pair bitline sharing Read Operations intra-pair bitline sharing (singled-ended) - Table 3 summarizes the different types of bitline sharing that
memory array 600 employs to efficiently write data to, and read data from, the memory array. As seen in Table 3, write operations employ both the disclosed intra-pair bitline sharing and inter-pair bitline sharing, while read operations employ the disclosed single-ended intra-pair bitline sharing. -
FIG. 8A is a flow chart describing a representative read memory operation from a memory cell in the disclosedSRAM array 600. The read memory operation tomemory cell 501 ormemory cell 502 starts atstart block 805. Read/write head 700 transmits a wordline select signal to select wordline wl_a 595 or wordline wl_b 590 ofwordline drive circuit 620, as perblock 810, corresponding tomemory cell 501 ormemory cell 502 respectively. The memory read circuit of read/write head 700 transmits a wordline enable signal to thewordline drive circuit 620 driving the selected wordlinewl_a 595 or wordline wl_b 590 corresponding tomemory cell block 815. Thewordline drive circuit 620 transmits an on signal to passdevice 520 inmemory cell 501 onwordline wl_a 595, or to passdevice 555 on wordlinewl_b 590 which turns on the memorycell pass device 520 ofmemory cell 501 or turns on the memorycell pass device 555 ofmemory cell 502 respectively, as perblock 820. The memory read circuit of read/write head 700 also transmits a read enablesignal 706 to gate 715 coupling the shared complement bitline bl′ 530 in the read/write head to data out1 704, as perblock 825. Gate 715 evaluates the complement bitline bl′ 530, as perblock 830. Gate 715 outputs the data corresponding to the contents of the selectedmemory cell 501 ormemory cell 502 from complement bitline bl′ 530 on the data out1 line at 704, as perblock 835. The read memory operation terminates according to block 840. In actual practice, the disclosed memory circuit may commence another memory read or write operation immediately after the read operation discussed above. -
FIG. 8B shows a flow chart describing a representative write operation to a memory cell of the disclosed SRAM array. The write memory operation begins atstart block 850. The write memory circuit of read/write head 700 selects eitherwordline wl_a 595 to write data tomemory cell 501, or wordlinewl_b 590 to write data tomemory cell 502, according to block 855. The write memory circuit transmits a wordline enable signal as perblock 860 to the wordline drive circuit 620 (which enables bothpass devices devices memory cell gate 710 orgate 730 in the read/write head controlling driver of the bitline corresponding to a write operation tomemory cell signal gate driver bitline bl 525 orbitline bl 565 respectively, and to driver of the sharedcomplement bitline 530 in the read/write head 700 as per block 865. The read/write head 700 receives data from data input (write data1) 701, as perblock 870. The read/write head 700 writes data to the selected memory cell as perblock 875 by driving the data through thebitline driver inverter 725 throughdriver 720 to the shared complement bitline bl′ 530 for a differential write memory operation of thememory cell -
FIG. 9 shows a representative portion of an integrated circuit layout pattern that practices the disclosed methodology.Memory array 900 includesmemory cell pair memory cell pair Memory cells borders array 900. For example, cell area borders 935 and 945 overlap by awidth 905. Theentire ROW 1 of memory cells slightly overlapsROW 2 of memory cells bywidth 905. Similarly, columns of memory cells overlap slightly to conserve space. By example, memory cell borders 935 and 945 of column A (col_A) overlap memory cell borders 940 and 950 of column B (col_B) respectively overlap by awidth 907. More generally, adjacent rows of memory cells overlap bywidth 905, and adjacent columns of cells overlap bywidth 907. - Returning to
FIG. 5 ,memory cells memory cell 502 is “upside down and reversed” with respect to the orientation of the circuitry ofmemory cell 501, such thatmemory cells memory cell 501 couples to a bl bitline on its left edge, and bl′ bitline on its right edge, and a wordline along the lower edge. In contrast,memory cell 502 couples to a bl bitline on its right edge, a bl′ bitline on its left edge and a wordline along the upper edge. - Returning to
FIG. 9 , cells in a column have the same symmetry, while memory cells in a particular row alternate in symmetry. Column B (col_B) memory cells exhibit “upside down and reversed” symmetry (quadrilateral symmetry) with respect to the column A (col_A) memory cells. This arrangement of symmetries facilitates sharing of bitlines between memory cells in adjacent columns. For example, the columns of memory cells adjacent to bitlines bl 525 and 565 as well as bitlines bl′ 530 and 530″ (also depicted inFIG. 6 ) share those bitline, respectively.Memory cells 502′ and 501share node 507 ofbitline bl 525.Memory cells share node 517 of bitline bl′ 530.Memory cells share node 527 ofbitline bl 565. The “upside down and reversed” (quadrilateral) symmetry in alternating columns of memory cells facilitates pairing of cells, exemplified bymemory cells Wordlines 610 alternate between wordlines that service column A (col_A) exemplified by wordlinewl_a 595, and wordlines that service column B (col_B) exemplified by wordlinewl_b 590. Specifically, wordline wl_a 595 connects tomemory cell 501 atnodes wl_b 590 connects tomemory cell 502 vianodes Nodes 910′ and 915′, andnodes 920′ and 925′ connect wl_a and wl_b wordlines tomemory cells wordlines 610 serve alternate columns of memory cells, with wl_a wordlines coupled to col_A memory cells and wl_b wordlines coupled to col_B memory cells. By pairs of memory cells exhibiting quadrilateral symmetry, it is meant that the topology of the memory cell pairs is such that pairs of memory cells are reflected in both the horizontal and vertical axes, e.g. column B (col_B) memory cells are upside-down and reversed with column A (col_A) memory cells. In summary, the arrangement of symmetries in memory cells facilitates straight paths forwordlines 610 which in turn facilitates compact arrangement of memory cells along columns. Sharing bitlines facilitates compact arrangement of memory cells in the along rows. The symmetries and pairing of memory cells according to the embodiment facilitates a more compact memory array than in other arrangements, and sharing of bitlines results in energy efficiency of reading SRAM. - Sharing of the bitlines as provided by the exemplary embodiments has the benefit that the memory read operation does not needlessly discharge bitlines associated with memory cells for which the data would be discarded. Practicing the disclosed technology may achieve significant energy savings.
- Returning now to
FIG. 4 , information handling system (IHS) 400 employs the disclosedSRAM memory array 200 and/or 600 asSRAM cache 450 and/orSRAM system memory 420.IHS 400 includes aprocessor 410 that may include multiple cores andSRAM cache 450.IHS 400 processes, transfers, communicates, modifies, stores or otherwise handles information in digital form, analog form or other form.IHS 400 includes abus 415 that couplesprocessor 410 tosystem memory 420 via amemory controller 425 andmemory bus 430. In one embodiment,system memory 420 is external toprocessor 410.System memory 420 may be a static random access memory (SRAM) array ofFIG. 2 orFIG. 6 and/or a dynamic random access memory (DRAM) array. Avideo graphics controller 435 couples display 440 tobus 415.Nonvolatile storage 445, such as a hard disk drive, CD drive, DVD drive, or other nonvolatile storage couples tobus 415 to provideIHS 400 with permanent storage of information. I/O devices 490, such as a keyboard and a mouse pointing device, couple tobus 415 via I/O controller 455 and I/O bus 460. One ormore expansion busses 465, such as USB, IEEE 1394 bus, ATA, SATA, PCI, PCIE, DVI, HDMI and other busses, couple tobus 415 to facilitate the connection of peripherals and devices toIHS 400. Anetwork interface adapter 405 couples tobus 415 to enableIHS 400 to connect by wires or wirelessly to a network and other information handling systems.IHS 400 may take the form of a desktop, server, portable, laptop, notebook, or other form factor computer or data processing system.IHS 400 may take other form factors such as a gaming device, a personal digital assistant (PDA), a portable telephone device, a communication device or other devices that include a processor and memory.IHS 400 is especially sensitive to energy consumption in the form of a portable, laptop, notebook, gaming device, PDA or any battery-powered device. -
IHS 400 may include a computer program product ondigital media 475 such as a CD, DVD or other media. In one embodiment,digital media 475 includes anapplication 482. A user may loadapplication 482 onnonvolatile storage 445 asapplication 482′.Nonvolatile storage 445 may store anoperating system 481. WhenIHS 400 initializes, the IHS loadsoperating system 481 and application 485′ intosystem memory 420 for execution asoperating system 481′ andapplication 482″.Operating system 481′ governs the operation ofIHS 400. - The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, blocks, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, blocks, operations, elements, components, and/or groups thereof.
- The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. For example, those skilled in the art will appreciate that the logic sense (logic high (1), logic low (0)) of the apparatus and methods described herein may be reversed and still achieve equivalent results. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
Claims (20)
1. A memory array, comprising:
a plurality of memory cells configured in rows and columns;
a first pair of memory cells situated in a first row of the memory array, the first pair of memory cells including first and second memory cells that couple to a first intra-pair bitline between the first and second cells to share the first intra-pair bitline, the first and second memory cells also coupling to first and second opposed inter-pair bitlines, respectively;
wherein the first and second memory cells are configured to couple via the first and second opposed inter-pair bitlines to second and third pairs of memory cells, respectively, in the first row of the memory array.
2. The memory array of claim 1 , wherein the first and second memory cells share the first intra-cell bitline for both reading and writing operations.
3. The memory cell of claim 2 , wherein the first and second memory cells share the first intra-cell bitline for single-ended reading operations.
4. The memory cell of claim 1 , wherein the first pair of memory cells shares the first opposed inter-pair bitline with the second pair of memory cells.
5. The memory cell of claim 4 wherein the first pair of memory cells shares the second opposed inter-pair bitline with the third pair of memory cells.
6. The memory array of claim 1 , wherein each memory cell of the first, second and third memory cell pairs includes a cross-coupled inverter pair and two pass-devices that couple to alternate sides of the cross-coupled inverter pair.
7. The memory array of claim 1 , further comprising first, second and third read/write heads coupled to the first, second and third memory cell pairs, respectively.
8. The memory array of claim 1 , wherein the rows and columns of the memory cells overlap and cell pairs exhibit quadrilateral symmetry.
9. The memory array of claim 1 , wherein the memory cells comprise static random access memory (SRAM).
10. An information handling system (IHS), comprising:
a processor;
a memory, coupled to the processor, the memory including:
a plurality of memory cells configured in a memory array of rows and columns;
a first pair of memory cells situated in a first row of the memory array, the first pair of memory cells including first and second memory cells that couple to a first intra-pair bitline between the first and second cells to share the first intra-pair bitline, the first and second memory cells also coupling to first and second opposed inter-pair bitlines, respectively;
wherein the first and second memory cells are configured to couple via the first and second opposed inter-pair bitlines to second and third pairs of memory cells, respectively, in the first row of the memory array.
11. The IHS of claim 10 , wherein the first and second memory cells share the first intra-cell bitline for both reading and writing operations.
12. The IHS of claim 11 , wherein the first and second memory cells share the first intra-cell bitline for single-ended reading operations.
13. The IHS of claim 10 , wherein the first pair of memory cells shares the first opposed inter-pair bitline with the second pair of memory cells.
14. The IHS of claim 10 , wherein the first pair of memory cells shares the second opposed inter-pair bitline with the third pair of memory cells.
15. The IHS of claim 10 , wherein each memory cell of the first, second and third memory cell pairs includes a cross-coupled inverter pair and two pass-devices that couple to alternate sides of the cross-coupled inverter pair.
16. The IHS of claim 10 , further comprising first, second and third read/write heads coupled to the first, second and third memory cell pairs, respectively.
17. The IHS of claim 10 , wherein the rows and columns of the memory cells overlap and cell pairs exhibit quadrilateral symmetry.
18. The IHS of claim 10 , wherein the plurality of memory cells comprise static random access memory (SRAM).
19. A method, comprising:
configuring a plurality of static random access memory (memory) cells in rows and columns, wherein a first pair of memory cells is situated in a first row of the memory array, the first pair of memory cells including first and second memory cells that couple to a first intra-pair bitline between the first and second cells to share the first intra-pair bitline, the first and second memory cells also coupling to first and second opposed inter-pair bitlines, respectively;
sharing the first intra-pair bitline for writing and reading operations of the first pair of memory cells;
sharing the first opposed inter-pair bitline with a second pair of memory cells adjacent the first pair of memory cells in the first row for writing and reading operations of the first pair of memory cells and the second pair of memory cells; and
sharing the second opposed inter-pair bitline with a third pair of memory cells adjacent the first pair of memory cells in the first row for writing and reading operations of the first pair of memory cells and the third pair of memory cells.
20. The method of claim 19 , further comprising accessing, by respective first, second and third write heads, the first, second and third pairs of memory cells.
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US13/312,867 US20130141992A1 (en) | 2011-12-06 | 2011-12-06 | Volatile memory access via shared bitlines |
US14/102,476 US9042149B2 (en) | 2011-12-06 | 2013-12-10 | Volatile memory access via shared bitlines |
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US13/312,867 US20130141992A1 (en) | 2011-12-06 | 2011-12-06 | Volatile memory access via shared bitlines |
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US14/102,476 Continuation US9042149B2 (en) | 2011-12-06 | 2013-12-10 | Volatile memory access via shared bitlines |
Publications (1)
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US20130141992A1 true US20130141992A1 (en) | 2013-06-06 |
Family
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