US20130181266A1

US20130181266A1 - Semiconductor device and method of fabricating the same

Info

Publication number: US20130181266A1
Application number: US13/768,932
Authority: US
Inventors: Myung-Ok Kim
Original assignee: Hynix Semiconductor Inc
Current assignee: SK Hynix Inc
Priority date: 2008-04-04
Filing date: 2013-02-15
Publication date: 2013-07-18
Also published as: JP2009253300A; CN101552237A; US20090250732A1; CN101552237B; KR20090106015A; TWI474396B; TW200943414A; KR100958798B1; US8399324B2

Abstract

In a method of fabricating a semiconductor device on a substrate having thereon a conductive layer, the conductive layer is patterned to form a plurality of opened regions. A gate insulation layer is formed on a side wall of each of the opened regions. A pillar pattern is formed in each opened region. On each pillar pattern, a gate electrode, which encloses the pillar pattern, is formed by removing the conductive layer between the pillar patterns.

Description

CROSS-REFERENCE(S) TO RELATED APPLICATIONS

The present application claims priority of Korean Patent Application No. 10-2008-0031475, filed on Apr. 4, 2008, which is incorporated herein by reference in its entirety.

BACKGROUND

The disclosure relates to a method of fabricating a semiconductor device, and more particularly, to a semiconductor device in which channels are formed in a vertical direction and to a method of fabricating such device.
As semiconductor device integrity increases, a semiconductor device with channels formed in an up and down direction relative to the substrate of the device (referred to herein as vertical channels), and capable of implementing a configuration of 4F², has been known to the inventors as one method of improving cell efficiency.
FIG. 1 is a schematic cross-sectional view of a known conventional semiconductor device with vertical channels.
Referring to FIG. 1, the known semiconductor device includes a substrate 10, a pillar pattern having a pillar head 11 and a pillar neck 12, a gate hard mask layer 13 for protecting an upper portion of the pillar pattern, a side wall protection layer 14 for protecting a side wall of the pillar head 11, a gate insulation layer 15 surrounding the pillar neck 12 and a gate electrode 16. Furthermore, source and drain regions may be formed on the substrate 10 and the pillar head 11, and a vertical channel may be formed in the pillar neck 12 to selectively connect the regions.
However, since a diameter of the pillar neck 12 is smaller than a diameter of the pillar head 11 and a gate hard mask layer 13 is placed over the pillar head 11 in the above configuration of the pillar pattern, it is potential that a pillar pattern may leans over or adheres to another pillar pattern, as shown in FIG. 2.
Also, since the pillar head 11 and pillar neck 12 are formed by etching without an etch stop layer, it is potential that the heights of respective pillar patterns are not even such as H1<H2. This results in different channel lengths in different pillar patterns, as shown in FIG. 3.
In addition, when a conductive layer is filled in the space between adjacent pillar patterns in order to later form the gate electrode 16, voids 21 and seams are potentially formed inside the conductive layer due to a high aspect ratio between the pillar patterns, as shown in FIG. 4. When a process of patterning the conductive layer is performed later, the gate insulation layer 15 and the substrate 17 are potentially punched through (see 22 of FIG. 5) due to different etching speeds originating from the presence of the aforementioned voids 21 and seams. Furthermore, the side wall protection layer 14 is possibly lost excessively due to an inappropriate etching selection ratio during the conductive layer patterning process, which attacks the pillar head 11, as shown in FIG. 6 (see 23 of FIG. 6).

SUMMARY

In accordance with one or more embodiments, a method of fabricating a semiconductor device on a substrate having thereon a conductive layer comprises: patterning the conductive layer to form a plurality of opened regions; forming a gate insulation layer on a side wall of each of the opened regions; forming a pillar pattern in each opened region; and forming on each pillar pattern a gate electrode, which encloses said pillar pattern, by removing the conductive layer between the pillar patterns.
In accordance with one or more embodiments, a method of fabricating a semiconductor device comprises: sequentially forming a first etch stop layer, a conductive layer, a second etch stop layer, and a plurality of hard mask layer patterns on a substrate; forming a plurality of opened regions by etching the second etch stop layer, the conductive layer and the first etch stop layer using the hard mask layer patterns as an etching barrier; forming a gate insulation layer on a side wall of each of the opened regions; forming a pillar pattern inside each opened region; forming a gate hard mask layer pattern covering each pillar pattern and a portion of the conductive layer surrounding said pillar pattern; and forming on each pillar pattern a gate electrode from said portion of the conductive layer by etching portions of the conductive layer between the pillar patterns using the gate hard mask layer pattern as an etching barrier.
In accordance with one or more embodiments, a semiconductor device comprises: a substrate having at least one pillar pattern grown thereon, a gate insulation layer extending around and covering a side wall of the at least one pillar pattern, a gate electrode extending around and partially covering the gate insulation layer, and a side wall protection layer positioned above the gate electrode, extending around and partially covering the gate insulation layer.

BRIEF DESCRIPTION OF THE DRAWINGS

Various embodiments are illustrated by way of example, and not by limitation, in the figures of the accompanying drawings.

FIG. 1 is a schematic cross-sectional view of a known semiconductor device with vertical channels.

FIGS. 2-6 are electron microscopic pictures showing various defects that can occur in the known semiconductor device.

FIGS. 7A to 7J are schematic views that illustrate a method of fabricating a semiconductor device with vertical channels in accordance with various embodiments.

DESCRIPTION OF EMBODIMENTS

In the figures, the dimensions of layers and regions are exaggerated for clarity of illustration. Like reference numerals refer to like elements throughout the drawings. In addition, different English alphabetical characters following a reference numeral of a layer refer to different states of the layer after one or more processing steps, such as partial deformations of the layer by an etch process or a polishing process.
It will also be understood that when a layer is referred to as being “on/under” another layer or substrate, it can be directly on/under the other layer or substrate, or intervening layers may also be present. In addition, when a layer is referred to as being ‘between’ two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
FIGS. 7A to 7J describe a method of fabricating a semiconductor device with vertical channels in accordance with various embodiments.
As shown in FIGS. 7A and 7B, a first insulation layer 32, a conductive layer 33, a second insulation layer 34 and a hard mask layer 35 are formed sequentially on a substrate 31, such as
.
The conductive layer 33 is a thin layer which will serve as a gate electrode, and comprises at least one thin layer of a material selected from the group consisting of polysilicon, tungsten silicide (WSi₂), titanium silicide (TiSi₂), tungsten (W), titanium nitride (TiN), tantalum (Ta) and tantalum nitride (TaN). For example, the conductive layer 33 in some embodiments has a stacked configuration of a tungsten layer and a titanium nitride layer, or a tungsten layer, a titanium nitride layer and a polysilicon layer.
The first insulation layer 32 is a thin layer for insulating between the substrate 31 and the conductive layer 33 and defining an etch stop layer in a subsequent etching process. The second insulation layer 34 is a thin layer for insulating between the conductive layer 33 and the hard mask layer 35 and defining another etch stop layer in a subsequent etching process. The first insulation layer 32 and/or the second insulation layer 34 comprise(s) any one thin layer selected from the group consisting of a silicon oxide layer (SiO₂), a silicon oxynitride layer, an aluminum oxide layer (Al₂O₃), a tantalum oxide layer (Ta₂O₅), a zirconium oxide layer (ZrO₂), a hafnium oxide layer (HfO₂) and a radium oxide layer (La2O3). In some embodiments, the first insulation layer 32 and the second insulation layer 34 are formed of the same material.
The hard mask layer 35 serves as a thin layer for protecting an upper portion of a side wall of a pillar pattern to be formed later. For this purpose, the hard mask layer 35 comprises any one thin layer selected from the group consisting of a nitride layer, an oxide layer and a silicon oxynitride layer.
Subsequently, an amorphous carbon layer 36, a silicon oxynitride layer (SiON) 37, an antireflection layer 38 and a photoresist pattern 39 are formed on the hard mask layer 35 to obtain a multilayer structure that has a top plan view as shown in FIG. 7A. FIG. 7B is a cross-sectional view taken long line I-I′ of FIG. 7A.
The photoresist pattern 39 is formed with a plurality of holes corresponding to opened regions where pillar patterns are to be formed later. The holes are shown as circles in FIG. 7A in which the underlying layer 38 is shown as being exposed through the holes. Other, shapes for the holes are not excluded.
As shown in FIG. 7C, the antireflection layer 38, the silicon oxynitride layer 37 and the amorphous carbon layer 36 are etched, in, e.g., a first etching process, using the photoresist pattern 39 as an etching barrier or mask. As a result, an amorphous carbon layer pattern 36A is formed by etching the amorphous carbon layer 36.
Subsequently, the hard mask layer 35 is etched, in, e.g., a second etching process, to form a plurality of hard mask layer patterns 35A using the amorphous carbon layer pattern 36A as an etching barrier or mask. After that, the second insulation layer 34, the conductive layer 33 and the first insulation layer 32 are etched subsequently, in, e.g., third and fourth etching processes, using the hard mask layer pattern 35A as an etching barrier or mask to form a plurality of opened regions 40.
To be specific, the hard mask layer 35 is etched, in the second etching process and using the amorphous carbon layer pattern 36A as an etching barrier or mask, and, in some embodiments, the etching is stopped on a surface of the second insulation layer 34. Subsequently, the second insulation layer 34 and the conductive layer 33 are etched, in the third etching process and using the hard mask layer pattern 35A as an etching barrier or mask, and in some embodiments the etching is stopped on a surface of the first insulation layer 32. Finally, the first insulation layer 32 is etched in the fourth etching process. In some embodiments, the etching may be stopped on a surface of the substrate 31. As a result, the opened regions 40 having substantially the same height are obtained.
Hereinafter, the etched second insulation layer 34, the conductive layer 33 and the first insulation layer 32 are referred to as a second insulation layer pattern 34A, a conductive layer pattern 33A and a first insulation layer pattern 32A, respectively.
Each opened region 40 is generally at 90° with respect to the substrate 31, and may have a slope ranging from approximately 70° to approximately 110°.
Next, the photoresist pattern 39, the antireflection layer 38, the silicon oxynitride layer 37 and the amorphous carbon layer pattern 36A are removed by
.
As shown in FIG. 7D, a gate insulation layer 41 is formed on a side wall of each opened region 40, i.e., the side walls of the first insulation layer pattern 32A, the conductive layer pattern 33A, the second insulation layer pattern 34A and the hard mask layer pattern 35A.
The gate insulation layer 41 is formed by (i) depositing at least one thin film selected from the group consisting of a silicon oxide layer (SiO₂), a silicon oxynitride layer, an aluminum oxide layer (Al₂O₃), a tantalum oxide layer (Ta₂O₅), a zirconium oxide layer (ZrO₂), a hafnium oxide layer (HfO₂) and a radium oxide layer (La₂O₃) along the profile of the substrate 31 where the opened regions 40 are formed, and (ii) performing an overall etching process. Accordingly, the gate insulation layer 41 exists only on the side wall of each opened region 40 while the substrate 31 at the bottom of each opened region 40 remains exposed without being covered by the gate insulation layer 41.
Meanwhile, deposition thicknesses of the first insulation layer 32, the second insulation layer 34 and the gate insulation layer 41 are targeted in some embodiments to ensure the same level of final electrical thicknesses thereof.
Subsequently, the substrate 31 exposed at the bottom of each opened region 40 is doped with impurities to form an impurity region, and the impurity region is then divided by a division process to form a buried bit line. The buried bit line defines a data transfer line in the semiconductor device for inputting/outputting data to/from a capacitor (to be described hereinafter).
As shown in FIGS. 7E and 7F, a pillar pattern 42 is formed in each opened region 40 by performing an epitaxial growth process. FIG. 7E is a top plan view of the multilayer structure obtained after the epitaxial growth process. FIG. 7F is a cross-sectional view taken long line II-II′ of FIG. 7E.
In particular, a plurality of pillar patterns 42 are each (i) formed with silicon (Si) crystals grown from the substrate 31 exposed at the bottom of one opened region 40 in the epitaxial growth process until the respective opened region 40 is buried or filled completely, and then (ii) planarized by performing a planarization process such as an etch back process or a chemical mechanical polishing. In some embodiments, the polishing may be stopped, or over-polishing may be performed, on an upper surface of the hard mask layer pattern 35A to thereby remove a portion of the hard mask layer pattern 35A.
The pillar patterns 42 formed in the epitaxial growth process have substantially the same diameter throughout its axial dimension, and side walls of the pillar patterns 42 have substantially vertical profile.
Additionally, in some embodiments, before the epitaxial growth process, a light etch treatment (LET) process is performed to remove foreign materials or native oxide from the exposed surface of the substrate 31 at the bottom of each opened region 40. The LET process is performed using a mixture gas of, e.g., CF₄and O₂, in a downstream-type plasma etcher.
Next, a source region and a drain region are formed by doping impurities on the upper part of each pillar pattern 42. The source and drain regions define therebetween a vertical channel on each pillar pattern 42 corresponding to the respective buried bit line.
As shown in FIGS. 7G and 7H, a pad oxide layer 43 and a gate hard mask layer 44 are formed in sequence on the upper surfaces of the pillar patterns 42 and the hard mask layer pattern 35A.
The gate hard mask layer 44 is a thin film for protecting the pillar patterns 42 and for patterning the underlying layers, and it is formed of a nitride layer or an oxide layer, or a stacked structure thereof. The pad oxide layer 43 is formed to relieve thin film stresses of the gate hard mask layer 44 and the pillar patterns 42.
Subsequently, an amorphous carbon layer 45, a silicon oxynitride layer 46, an antireflection layer 47 and a photoresist pattern 48 are formed on the gate hard mask layer 44 in sequence. The resulting multilayer structure has a top plan view shown in FIG. 7G. FIG. 7H is a cross-sectional view taken long line III-III′ of FIG. 7G. In some embodiments, another hard mask layer (not shown) is further interposed between the gate hard mask layer 44 and the amorphous carbon layer 45 to help patterning the gate hard mask layer 44.
The photoresist pattern 48 has multiple photoresist projections denoted at 48 in FIG. 7G, an opened region where the underlying antireflection layer 47 is exposed. The conductive layer 33 under the opened region of the photoresist pattern 48 will be later removed. Each photoresist projection of the photoresist pattern 48 is located above and corresponding to one pillar pattern 42. In the plan view of FIG. 7G, the boundary of the pillar pattern 42 (dot-dot lines) is positioned completely within the boundary of the respective photoresist projection of the photoresist pattern 48. In some embodiments, each photoresist projection and the corresponding pillar pattern 42 have the same shape, e.g., circular shapes as shown in FIG. 7G. Other shapes, as discussed above, are not excluded. In some embodiments, each photoresist projection and the corresponding pillar pattern 42 are coaxially.
As shown in FIGS. 7I and 7J, the antireflection layer 47, the silicon oxynitride layer 46, and the amorphous carbon layer 45 are etched, in, e.g., a fifth etching process, using the photoresist pattern 48 as an etching barrier or mask.
After that, the gate hard mask layer 44 and the pad oxide layer 43 are etched, in, e.g., a sixth etching process, using an amorphous carbon layer pattern 45A formed by etching the amorphous carbon layer 45 as an etching barrier or mask, and then the hard mask layer pattern 35A, the second insulation layer pattern 34A, the conductive layer pattern 33A and the first insulation layer pattern 32A are etched, in, e.g., seventh and eights etching processes, using the gate hard mask layer pattern 44A as an etching barrier or mask. In some embodiments, the etching of the gate hard mask layer 44 and the underlying layers is performed in-situ or ex-situ. Reference numeral 43A represents a pad oxide layer pattern.
To be more specific, the hard mask layer pattern 35A is etched in the sixth etching process and using the gate hard mask layer pattern 44A as an etching barrier or mask and, in some embodiments, the etching stops on a surface of the second insulation layer pattern 34A. Subsequently, the second insulation pattern 34A and the conductive layer pattern 33A are etched in sequence, in the seventh etching process, using the same etching barrier, i.e., 44A. In some embodiments, the etching stops on a surface of the first insulation layer pattern 32A. Finally, the first insulation layer pattern 32A is etched in the eighth etching process, and, in some embodiments, the etching stops on a surface of the substrate 31. The fifth through eighth etching processes in some embodiments are similar to the first through fourth etching processes, respectively.
As a result of the etching processes discussed above, an etched first insulation layer pattern 32B, an etched second insulation pattern 34B, a gate electrode 33B and a side wall protection layer 35B for protecting the upper portion of each pillar pattern 42 are formed on the side wall of the pillar pattern 42. The gate insulation layer 41, the gate electrode 33B and the side wall protection layer 35B are shaped to surround the pillar pattern 42.
After that, the photoresist pattern 48, the antireflection layer 47, the silicon oxynitride layer 46 and the amorphous carbon layer pattern 45A are removed, e.g., by a process similar to the process for removing layers 39-36.
Next, a capacitor (not shown) is formed adjacent to the source and drain regions formed on each pillar pattern 42. As a result, a complete semiconductor device with vertical channels is fabricated.
Since the pillar patterns 42 are formed through the growth process rather than by etching the substrate 31, and since the growth process is performed to fill or bury the already formed opened regions 40, it is possible to prevent the pillar patterns 42, which now have sufficient mechanical strength, from leaning over.
Also, the heights of the opened regions 40 are made evenly, resulting in the heights of the pillar patterns 42 to be even as well. Accordingly, channels of the same length can be obtained.
In addition, since the gate electrode 33B is formed on a flat substrate 31 by depositing the conductive layer 33, forming the pillar pattern 42, and patterning the conductive layer 33 in sequence, formations of voids and seams, e.g., by the burial of a conductive layer as in the known device/method, can be avoided. Accordingly, attacks on the gate insulation layer and the substrate can be prevented.
Furthermore, since the side wall protection layer 35B is covered with the gate hard mask layer pattern 44A from above, loss of the side wall protection layer 35B can be avoided during the formation of the gate electrode 33B.
Accordingly, reliability and stability of semiconductor devices manufactured in accordance with various embodiments, particularly those of no more than 40 nm, can be enhanced and yield can be improved.
While specific embodiments have been described, it will be apparent to those skilled in the art that various changes and modifications may be made.

Claims

1-15. (canceled)

16. A semiconductor device, comprising:

a substrate having at least one pillar pattern grown thereon,

a gate insulation layer extending around and covering a side wall of the at least one pillar pattern,

a gate electrode extending around and partially covering the gate insulation layer, and

a side wall protection layer positioned above the gate electrode, extending around and partially covering the gate insulation layer.

17. The device of claim 16, wherein the side wall of the at least one pillar pattern is substantially normal to a plane of the substrate throughout an entire height of said at least one pillar pattern.

18. The device of claim 16, further comprising

at least one insulation layer extending around and partially covering the gate insulation layer,

wherein said gate electrode, said side wall protection layer and said at least one insulation layer completely cover said gate insulation layer over an entire height of the at least one pillar pattern.

19. The device of claim 18, wherein said at least one insulation layer comprises a first insulation layer between the gate electrode and the substrate, and a second insulation layer between the gate electrode and the side wall protection layer.

20. The device of claim 16, further comprising

a gate hard mask layer formed above and completely covering upper surfaces of the side wall protection layer, the gate insulation layer, and the at least one pillar pattern.