US20130187284A1 - Low Cost and High Performance Flip Chip Package - Google Patents
Low Cost and High Performance Flip Chip Package Download PDFInfo
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- US20130187284A1 US20130187284A1 US13/357,078 US201213357078A US2013187284A1 US 20130187284 A1 US20130187284 A1 US 20130187284A1 US 201213357078 A US201213357078 A US 201213357078A US 2013187284 A1 US2013187284 A1 US 2013187284A1
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Abstract
Description
- To interface bare semiconductor dies to a support surface such as a printed circuit board, there is a need for an appropriate package substrate to interface and route the semiconductor dies within a package, such as a ball grid array (BGA) package, chip scale package (CSP), or system-in-package (SiP), to the printed circuit board. A conventional interface substrate may start with a core material with laminate film layers built up on both sides of the core material. A flip-chip die may then be coupled to the interface substrate using solder bumps.
- Demand for higher performance, power efficiency, and reduced form factor have driven successive generations of die shrinks, resulting in flip-chip dies with very high density interconnect features. As the solder bump interconnects are also required to become increasingly dense, the manufacturability, cost, and reliability requirements for interface substrates have gradually become more difficult to meet. Moreover, with shrinking die sizes, effective thermal dissipation from the smaller available die surface area has also become a greater concern.
- The present disclosure is directed to low cost and high performance flip chip packages, substantially as shown in and/or described in connection with at least one of the figures, and as set forth more completely in the claims.
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FIG. 1 presents a cross-sectional view of an exemplary flip-chip package using a conventional interface substrate. -
FIGS. 2A , 2B, 2C, 2D, 2E, 2F and 2G present cross-sectional views of an exemplary flip chip package assembly. - The following description contains specific information pertaining to implementations in the present disclosure. One skilled in the art will recognize that the present disclosure may be implemented in a manner different from that specifically discussed herein. The drawings in the present application and their accompanying detailed description are directed to merely exemplary implementations. Unless noted otherwise, like or corresponding elements among the figures may be indicated by like or corresponding reference numerals. Moreover, the drawings and illustrations in the present application are generally not to scale, and are not intended to correspond to actual relative dimensions.
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FIG. 1 presents a cross-sectional view of an exemplary flip-chip package using a conventional interface substrate.FIG. 1 includes package 100 (or “semiconductor package” 100), which includesflip chip 110 mounted onsubstrate 120 through a plurality of solder bumps, with anexemplary solder bump 115 as shown.Underfill 116 is also placed belowflip chip 110 to support and insulate the plurality ofsolder humps 115.Substrate 120 includes acentral core 140 having a plurality of vias, with an exemplary via 145 as shown.Central core 140 may have a thickness of 800 microns or more. An upperthin film 130 and apassivation layer 138 are formed abovecentral core 140. Similarly, a lowerthin film 150 and apassivation layer 158 are formed belowcentral core 140. A plurality of conductive traces, with an exemplaryconductive trace 122 as shown, is also formed withinsubstrate 120 to route connections between the solder bumps offlip chip 110 and the solder balls ofpackage 100, with anexemplary solder ball 105 as shown.Lid 160 may be adhesively attached to a backside offlip chip 110 and the top ofsubstrate 120 to encapsulatepackage 100, as shown. Thus,package 100 is ready to be mounted to a support surface, such as a printed circuit board. - As discussed in the background, demand for higher performance, power efficiency, and reduced form factor have driven successive generations of die shrinks for
flip chip 110, requiring a correspondingly higher pitch betweensolder bumps 115. For example, for aflip chip 110 using a 40 nm process, in high volume manufacturing, a 150 micron pitch is standard betweensolder bumps 115. However, solder bumping is quickly reaching its technological limit as the minimum practical solder bump pitch is considered to be 130 to 150 microns. -
Flip chip 110 is manufactured using smaller feature sizes, such as 28 nm and below, solder bumping technology is unable to keep pace with the reduced bump pitch demanded offlip chip 110. Thus, a die size offlip chip 110 must increase, resulting in significant cost and form factor increases. Even if the die size offlip chip 110 is successfully reduced, effective thermal dissipation from the smaller die surface area also becomes a greater concern. Moreover, at fine solder bump pitch densities, reliability issues with the solder bump interconnects become increasingly pronounced, with solder joint cracking, electromigration performance degradation, and other issues resulting in lower yields and increased costs. -
FIGS. 2A-2G present cross-sectional views of an exemplary flip chip package assembly. Starting withFIG. 2A ,FIG. 2A includespanel substrate 270 withheat spreader 280 andbackside tape 284.Heat spreader 280 may include electrically conductive materials such as copper or other metals.Backside tape 284 may be applied toheat spreader 280 for mechanical protection and support during assembly, as known in the art. A plurality of recesses inheat spreader 280, withexemplary recess 282 as shown, are provided for receiving dies. While only three recesses are shown in the cross-sectional view ofFIG. 2A , it should be understood thatpanel substrate 270 may accommodate recess grids of any size. - Next, in
FIG. 2B , an adhesive thermal interface material (TIM) 286 is printed throughmask 285 and intorecesses 282 ofheat spreader 280. Although adhesive TIM 286 is utilized inFIG. 2B , any die attach material or method of attachment may also be utilized. - Continuing with
FIG. 2C , a semiconductor die may be placed in each ofrecesses 286 ofheat spreader 280, with exemplary semiconductor die 210 as shown. Each semiconductor die 210 includes a plurality of die contact pads, with exemplary diecontact pad 212 as shown. Diecontact pads 212 may be electrically conductive materials such as copper or other metals. Each semiconductor die 210 may be a flip-chip. After situating the semiconductor dies 210 inrespective recesses 286,adhesive TIM 286 may spread to attach each of the semiconductor dies 210 toheat spreader 280, as shown. - Moving to
FIG. 2D , laminatedielectric film 230 a may be formed over semiconductor dies 210 andheat spreader 280. Laminatedielectric film 230 a may utilize organic materials such as Bismaleimide-Triazine (BT), Ajinomoto Build-up Film (ABF), FR-4 laminates, E679-FBG, ECL4785GS, and E700. - Turning to
FIG. 2E , a first level interconnect is created. First, a plurality of vias, with an exemplary via 232 as shown, is formed through laminatedielectric film 230 a, for example by laser drilling. Next, the plurality ofvias 232 and the top of laminatedielectric film 230 a are plated to form a plurality of traces, with anexemplary trace 234 as shown. The plated plurality ofvias 232 and the plurality oftraces 234 may be electrically conductive materials such as copper or other metals, and may also be the same materials as the plurality ofdie contact pads 212. As a result, the plurality ofvias 232 may be directly connected to a respective plurality of diecontact pads 212. Thus, the plurality of semiconductor dies 210 may have no flip chip solder bumps for each respectivedie contact pad 212. The plurality ofvias 232 may eventually connect to a respective plurality of package contact pads, as discussed below. - In
FIG. 2F , an additional two levels of interconnects are created. However, any number of interconnect levels may be provided by repeating, for as many levels as necessary, the formation of laminate dielectric films, vias, and traces as demonstrated inFIGS. 2D and 2E . As shown inFIG. 2F ,laminate dielectric film 230 b and laminatedielectric film 230 c are formed to create a stack of laminatedielectric films 290. Laminatedielectric films package contact pads 202, with an exemplarypackage contact pad 202 as shown, is formed above the stack of laminatedielectric films 290. The plurality ofpackage contact pads 202 may be electrically conductive materials such as copper or other metals, and may be surrounded by a solder resist 204, as shown. The traces and vias within the stack of laminatedielectric films 290 combine to form a plurality ofelectrical connection routes 295, connecting the plurality ofdie contact pads 212 to a respective plurality ofpackage contact pads 202. As a result, the plurality ofvias 232 in the lowerlaminate dielectric film 230 a is also electrically connected to a respective plurality ofpackage contact pads 202. - Subsequently, in
FIG. 2G ,panel substrate 270 undergoes singulation to result inpackages backside tape 284 is also removed after singulating. Thus, a flip chip package is provided where thepackage substrate 206 tightly integrates the semiconductor die 210 without the use of solder bump interconnects. Solder balls may be coupled to packagecontact pads 202 to preparepackages Flip chip package 200 a inFIG. 2G provide several advantages compared to the conventionalflip chip package 100 inFIG. 1 . First, since the process of assemblingpackage 200 a does not utilize flip chip solder bumps, such as solder bumps 115, the associated processes of solder bumping, reflowing, defluxing, and addingunderfill 116 may be advantageously avoided. Since the pitch betweendie contact pads 212 is no longer limited by solder bump technology, very high density semiconductor dies 210 may be supported, as the new technological limitation is the alignment ofvias 232 to corresponding diecontact pads 212. With present laser via drilling processes, a minimum supported pitch betweendie contact pads 212 can be as low as 15 microns for high volume manufacturing and approximately 12.5 microns for low volume manufacturing, compared to the limit of 130 to 150 microns for solder bumping. - Since reflow processes can be avoided entirely and the formation of
vias 232 can be carried out at essentially room temperature, coefficient of thermal expansion (CTE) mismatches arising from such reflow processes are also advantageously avoided. Conductivity and electromigration performance is also improved aselectrical connection routes 295 may be composed wholly of highly conductive materials such as copper, in comparison to the required solder bumps 115 ofpackage 100. - Furthermore, the tight coupling of semiconductor die 210 to package
substrate 206 eliminates the need for a separate substrate fabrication process aspackage 200 a is assembled using a substrate panel level process. Thus,central core 140 ofsubstrate 120 may be completely omitted inpackage substrate 206, resulting in a coreless substrate. Thus, pre-soldering, core materials, and core via drilling and plating steps may be omitted, and layer counts may also be reduced as layers do not need to be built on both sides of a core. By reducing the number of required steps and materials, a very cost effective package assembly may be provided while providing a thinner form factor and higher electrical performance. Moreover, sinceheat spreader 280 is already an integral part ofpackage 200 a and is coupled to semiconductor die 210 via a surroundingadhesive TIM 286, improved thermal dissipation may be provided and package height may be even further reduced as a separate heat sink is not required. - With regards to electrical performance, according to electrical simulations, package 200 a may be expected to have an approximately 60% reduction in package resistance and an approximately 70% reduction in inductance when compared to
package 100, both considerable improvements. However, since capacitance is largely related to the build-up stack of laminatedielectric films 290, little variance in capacitance is expected betweenpackage 100 and package 200 a. The removal of the thickcentral core 140 with itslarge vias 145 is also expected to provide significant improvements in crosstalk, simultaneous switching output (SSO) noise, and signal path impedance mismatch, which in turn reduces serial interface differential return loss and parallel interface signal reflection. These signal improvements may be especially relevant for high speed, high density memory devices. - From the above description it is manifest that various techniques can be used for implementing the concepts described in the present application without departing from the scope of those concepts. Moreover, while the concepts have been described with specific reference to certain implementations, a person of ordinary skill in the art would recognize that changes can be made in form and detail without departing from the spirit and the scope of those concepts. As such, the described implementations are to be considered in all respects as illustrative and not restrictive. It should also be understood that the present application is not limited to the particular implementations described herein, but many rearrangements, modifications, and substitutions are possible without departing from the scope of the present disclosure.
Claims (12)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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US13/357,078 US20130187284A1 (en) | 2012-01-24 | 2012-01-24 | Low Cost and High Performance Flip Chip Package |
US14/247,222 US8957516B2 (en) | 2012-01-24 | 2014-04-07 | Low cost and high performance flip chip package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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US13/357,078 US20130187284A1 (en) | 2012-01-24 | 2012-01-24 | Low Cost and High Performance Flip Chip Package |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US14/247,222 Continuation US8957516B2 (en) | 2012-01-24 | 2014-04-07 | Low cost and high performance flip chip package |
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