US20130308695A1 - Method and System for Adaptive Tone Cancellation for Mitigating the Effects of Electromagnetic Interference - Google Patents
Method and System for Adaptive Tone Cancellation for Mitigating the Effects of Electromagnetic Interference Download PDFInfo
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- US20130308695A1 US20130308695A1 US13/953,005 US201313953005A US2013308695A1 US 20130308695 A1 US20130308695 A1 US 20130308695A1 US 201313953005 A US201313953005 A US 201313953005A US 2013308695 A1 US2013308695 A1 US 2013308695A1
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
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Abstract
Description
- This patent application is a continuation of U.S. patent application Ser. No. 12/835,419 filed on Jul. 13, 2010, which claims benefit of U.S. Provisional Patent Application Ser. No. 61/360,800 filed on Jul. 1, 2010.
- The above stated applications are hereby incorporated herein by reference in their entireties.
- Certain embodiments of the invention relate to signal processing. More specifically, certain embodiments of the invention relate to a method and system for adaptive tone cancellation for mitigating the effects of electromagnetic interference.
- In almost any communication system, interference, externally and/or internally generated, limits the performance of the communication system. Differential signaling is one technique that can be utilized for dealing with such interference. However, while differential signaling may reduce the effects of such interference, it does not eliminate them.
- Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.
- A system and/or method is provided for adaptive tone cancellation for mitigating the effects of electromagnetic interference, substantially as illustrated by and/or described in connection with at least one of the figures, as set forth more completely in the claims.
- These and other advantages, aspects and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings.
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FIG. 1 . is a diagram depicting two communication devices communicating over a plurality of physical channels, in accordance with an embodiment of the invention. -
FIG. 2A is a diagram depicting an exemplary portion of a communication device that may be operable to provide interference cancellation, in accordance with an embodiment of the invention. -
FIG. 2B is a diagram illustrating an exemplary tone generator operable to track an interference signal, in accordance with an embodiment of the invention. -
FIG. 2C is a diagram illustrating an exemplary data multiplexer in accordance with an embodiment of the invention. -
FIG. 2D is a diagram illustrating a plurality of error multiplexers in accordance with an embodiment of the invention. -
FIG. 3 is a diagram illustrating exemplary magnetics comprising a common mode sense circuit, in accordance with an embodiment of the invention. -
FIG. 4 is a flow chart illustrating exemplary steps for interference cancellation, in accordance with an embodiment of the invention. - Certain embodiments of the invention may be found in a method and system for adaptive tone cancellation for mitigating the effects of electromagnetic interference. In various embodiments of the invention, an Ethernet PHY may receive one or more signals via a corresponding one or more physical channels and generate one or more estimate signals, each of which approximates interference present in a corresponding one of the received signals. The Ethernet PHY may subtract each one of the estimate signals from a corresponding one of the received signals. The subtracting may occur at the input of one or more slicers in the Ethernet PHY. The received signals may be processed via one or more equalizers in the Ethernet PHY. One of the received signals at an output of one of the equalizers may be utilized to generate the one or more estimate signals. The Ethernet PHY may receive a common mode signal from a common mode sensor coupled to one of the physical channels. The common mode signal may be utilized to generate the one or more estimate signals. A decision output of a slicer in the Ethernet PHY may be subtracted from an output of an equalizer in the Ethernet PHY, and a signal resulting from the subtraction may be utilized to generate the one or more estimate signals.
- The one or more estimate signals may be generated utilizing a selected one of the following signals: a signal output by an equalizer in the Ethernet PHY, a signal resulting from a subtraction of a slicer decision output from the equalizer output, and a signal output by a common mode sensor coupled to one of the physical channels. The selection may be based on a strength of the interference. The Ethernet PHY may be operable to generate a pair of phase-quadrature signals having a frequency that tracks a frequency of the interference. An adaptive filter in the Ethernet PHY may utilize the phase-quadrature signals to generate the one or more estimate signals. The one or more estimate signals may be generated utilizing a selected one of a decision output of a slicer and an error output of the slicer. The selected one of the decision output and the error output may be utilized by the adaptive filter for generating the one or more estimate signals. The selection may be based on a strength of the interference.
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FIG. 1 is a diagram depicting two communication devices communicating over a plurality of physical channels, in accordance with an embodiment of the invention. Referring toFIG. 1 there is shown acommunication device 102 a and acommunication device 102 b which communicate over acable 108 that comprises physical channels 106 1-106 N, where N is an integer greater than or equal to 1. - Each of the
communication devices communication devices communication devices cable 108 in accordance with IEEE 802.3 (Ethernet) standards. For example, for 10/100/1G/10GGBASE-T thecable 108 may comprise twisted pairs 106 1-106 4, and thecommunication devices - In operation, signals 103 1-103 N may be present on the channels 106 1-106 N.
Electromagnetic interference signal 104 may be incident on thecable 108 and may appear on the channels 106 1-106 N asinterference components 104′1-104′N. Thus, the signals 103 1-103 N may comprise desired components 105 1-105 N, (not shown) respectively, andinterference components 104′1-104′N (not shown), respectively. Exemplary sources of theinterference 104 comprise broadcast radio and/or television signals, cellular signals, walkie-talkie signals, and interference radiated from other electronic devices or cables located near thecable 108. Degraded communications over thecable 108 resulting from theinterference 104 may manifest itself in the form of, for example, increased receive error rates in thecommunication devices interference component 104′n may be generated, and estimated interference signal may be subtracted from the signal 103 n received via the channel 106 n. - In an exemplary embodiment of the invention, the
interference components 104′1-104′N may be estimated by detecting the common mode signal on one of the channels 106 1-106 N utilizing a common mode sense circuit. In an exemplary embodiment of the invention, theinterference components 104′1-104′N may be estimated utilizing the output of one of a plurality of equalizers that process signals received via channels 106 1-106 N, thus eliminating the need for the common mode sense circuit. In an exemplary embodiment of the invention, either the equalizer output or the common mode sense circuit output may be selected based on the strength of one or more of theinterference components 104′1-104′N. The strength of the interference components may be determined by, for example, monitoring an error rate in the receiver. -
FIG. 2A is a diagram depicting an exemplary portion of a communication device that may be operable to provide interference cancellation, in accordance with an embodiment of the invention. Referring toFIG. 2A there is shown a portion of acommunication device 102 which may communicate over four physical channels, that is, N=4. The communication device comprisesmagnetics 202,memory 222,processor 224, and anEthernet PHY 200. Depicted portions of theEthernet PHY 200 comprise analog-to-digital converters (ADCs) 204 1-204 4, equalizers 206 1-206 4, combiners 208 1-208 4, slicers 210 1-210 4, low density parity check (LDPC)decoder 212, error multiplexer 214 1-214 4, adaptive filter 216 1-216 4,tone generator 218, andADC 220. In the exemplary embodiment of the invention depicted inFIGS. 2A-2D , N is equal to 4, but the invention is not so limited. - In various embodiments of the invention, the various components depicted in
FIG. 2A may be interconnected via differential traces on and/or in printed circuit boards (PCBs) and/or integrated circuits (ICs) on and/or in which the components are fabricated. Such differential signal routing may reduce noise coupled into the signals within and/or on the PCBs and/or ICs. - The
magnetics 202 may comprise suitable logic, circuitry, interfaces, and/or code that may be operable to couple the channels 106 1-106 4 to theEthernet PHY 200. In this regard, themagnetics 202 may provide noise and/or EMI suppression and/or may impedance match the channels 106 1-106 4 to theEthernet PHY 200. In this regard, themagnetics 202 may comprise one or more transformers and/or one or more inductive chokes. In some instances, themagnetics 202 may also comprise other components such as resistors, capacitors, and/or inductors for achieving impedance matching, isolation, and/or noise and/or EMI suppression. In some embodiments of the invention, the magnetics 302 may comprise a commonmode sense circuit 326 which may output acommon mode signal 203. Thecommon mode signal 203 may comprise theinterference component 104′n of the signal 103 n. Utilizing thecommon mode signal 203 may mean that thesignal 203 comprises (ideally) only the interference signal and thus it may be easier to lock onto the interference component. Utilizing thecommon mode signal 203 may require additional circuitry in the form of the common mode sense circuit and thecommon mode ADC 220. Additional details of themagnetics 202 are described below with respect toFIG. 3 . - The
processor 224 may comprise suitable logic, circuitry, interfaces, and/or code that may be operable to control operation of theEthernet PHY 200. In this regard, theprocessor 224 may be operable to configure one or more components of the Ethernet PHY 100. For example, theprocessor 224 may configure coefficients of the equalizers 206 1-206 4 and/or the adaptive filters 216 1-216 4, provide control signals to the multiplexers 214 1-214 4, and provide one or more control signals to thetone generator 218. - The
memory 222 may comprise any suitable memory such as RAM, ROM, flash, and/or magnetic storage. Theprocessor 224 may utilize thememory 222 to control operation of theEthernet PHY 200. - Each of the ADCs 204 1-204 4 and 220 may comprise suitable logic, circuitry, interfaces, and/or code that may be operable to convert an analog signal to a digital representation. In this regard, the analog signals 103 1-103 4 coupled into the
PHY 200 via themagnetics 202 may be converted to digital signals 205 1-205 4. Similarly, the analogcommon mode signal 203 output by themagnetics 202 may be converted to the digitalcommon mode signal 221. - Each of the equalizers 206 1-206 4 may comprise suitable logic, circuitry, interfaces, and/or code may be operable to filter and/or otherwise process the digitized received signals 205 1-205 4. The equalizers 206 1-206 4 may, for example, filter the received signals to compensate for nonlinear, e.g., frequency dependent, distortion introduced by the physical channels 106 1-106 4.
- Each of the combiners 208 1-208 4 may comprise suitable logic, circuitry, interfaces, and/or code that may be operable to add and/or subtract digital signals. A weighting may be applied to one or more of the signals prior to addition or subtraction of the signals.
- Each of the slicers 210 1-210 4 may comprise suitable logic, circuitry, interfaces, and/or code for implementing various aspects of the invention. Each of the slicers 210 1-210 4 may be operable to determine a symbol value corresponding to a voltage of the corresponding one of the signals 209 1-209 4. In an exemplary embodiment of the invention, each of the slicers 210 1-210 4 may determine which double square 128 (DSQ128) symbol value is represented by the voltage of the corresponding one of the signals 209 1-209 4. Also, each of the slicers 210 1-210 4 may be operable to generate an error signal corresponding to the difference between the voltage of the corresponding one of the signals 209 1-209 4 and the ideal voltage of the determined symbol.
- The
LDPC decoder 212 may comprise suitable logic, circuitry, interfaces, and/or code that may be operable to decode the received symbols output by the slicers 210 1-210 4 to recover data originally transmitted by the source device. The decoding may correct for errors introduced while the data was in transmit. - Each of the error multiplexers 214 1-214 4 may comprise suitable logic, circuitry, interfaces, and/or code that may be operable to select between a corresponding one of signals 209 1-209 4 and a corresponding one of signals 213 1-213 4.
- The adaptive filters 216 1-216 4 may comprise suitable logic, circuitry, interfaces, and/or code that may be operable to generate, respectively, signals 217 1-217 4. The signals 217 1-217 4 comprise estimations of the
interference components 104′1-104′4 present in the received signals 103 1-103 4, respectively. A pair of quadrature-phase signals generated by thetone generator 218, and an output from a corresponding one of the error multiplexers 214 1-214 4 may be input to each of the adaptive filters 216 1-216 4. - The
tone generator 218 may comprise suitable logic, circuitry, interfaces, and/or code that may be operable to lock to theinterference component 104′n of the signal 207 n and/or lock to thecommon mode signal 221 - In operation, signals 103 1-103 4 may be received via the channels 106 1-106 4 and may be coupled into the
Ethernet PHY 200 by themagnetics 202. The signals 103 1-103 4 may comprise desired components 105 1-105 4 andinterference components 104′1-104′4 resulting from the EMI 104 (FIG. 1 ). Additionally, in various embodiments of the invention, themagnetics 202 may output thecommon mode signal 203 which may correspond to theinterference component 104′n of the physical channel 106 n, where n may be any value between 1 and 4, inclusive. - The signals 103 1-103 4 may be digitized by the ADCs 204 1-204 4 and processed by the equalizers 206 1-206 4 to generate signals 207 1-207 4. The
signal 203 may be digitized by theADC 220 to generate thesignal 221. A data multiplexer of thetone generator 218 may select one of the input signals or a combination of input signals as described below inFIG. 2C . Thetone generator 218 may then process the selected signal to isolate and/or enhance theinterference 104′n and generate the quadrature-phase signals 219 1 and 219 2. - The adaptive filters 216 1-216 4 may, based on the output of a corresponding one of the error multiplexers 214 1-214 4, utilize the phase-quadrature signals 219 1 and 219 2 to generate the estimate signals 217 1-217 4. In this regard, an estimate signal 217 n may be generated for each physical channel 106 n to account for phase and/or amplitude variations among the
interference components 104′1-104′4. Such variations may result from, for example, variations in length and/or impedance among the channels 106 1-106 4. To match the phase of the signal 217 n to the phase of theinterference 104′n, the adaptive filter 216 n may scale one or both of the signals 219 1 and 219 2 and combine the scaled versions of the signals 219 1-219 2, thus utilizing trigonometric identities to achieve the desired phase. To match the amplitude of the signal 217 n to the amplitude of theinterference 104′n, the adaptive filter 217 n may scale one or both of the signals 219 1 and 219 2 and and/or may scale the signal resulting from the combination of the signals 219 1 and 219 2. Operation of the error multiplexers 214 1-214 4 is described below with respect toFIG. 2D . - The combiners 208 1-208 4 may subtract the estimate signals 217 1-217 4 from the signals 207 1-207 4, respectively, to generate the signals 209 1-209 4, which may comprise
interference components 104″1-104″4, respectively. Thus, in instances that the estimate signals 217 1-217 4 are zero, then theinterference components 104′1-104′4 are equal to theinterference components 104″1-104″4. Conversely, in instances that the estimate signals 217 1-217 4 exactly match theinterference components 104′1-104′4, then theinterference components 104″1-104″4 of the signals 209 1-209 4 are zero. - The slicers 210 1-210 4 may process the signals 209 1-209 4 and, for each sample value, determine the symbol represented by the voltage. In an exemplary embodiment of the invention, the
Ethernet PHY 200 may support 10GBASE-T and each slicer 210 n may determine which one of 16 possible symbols is represented by a voltage of the signal 209 n. The slicer may output the determined symbol as signal 211 n and may output the difference between the ideal voltage of the determined symbol and the voltage of the signal 209 n as signal 213 n. - The
LDPC 212 may process the four received symbols from the slicers 210 1-210 4 and determine the data originally transmitted by the source device. TheLDPC 212 may provide forward error correction. - For convenience and clarity of description, signals upstream from the combiners 208 1-208 N, including the signals 103 1-103 4, the signals 205 1-205 4, and the signals 207 1-207 4, may be referred to as “received signals.”
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FIG. 2B is a diagram illustrating an exemplary tone generator operable to track an interference signal, in accordance with an embodiment of the invention. Referring toFIG. 2B , thetone generator 218 may comprise adata multiplexer 230, afilter 232, automatic gain control (AGC) 234, phase locked loop (PLL) 236, andtone generation block 238. - The data multiplexer 230 may comprise suitable logic, circuitry, interfaces, and/or code which may be controlled to select one of a plurality of signals to be conveyed to the
filter 232. An exemplary data multiplexer is described below with respect toFIG. 2C . - The
filter 232 may comprise suitable logic, circuitry, interfaces, and/or code having a frequency response such that frequencies within a selected band are attenuated less than frequencies outside the selected band. In various embodiments of the invention, thefilter 232 may be configurable such that it has a bandpass frequency response in one or more configurations and a high-pass frequency response in one or more other configurations. The frequency response of thefilter 232, for example the center frequency for a bandpass response or the cut-off frequency for a high-pass response, may be controlled via thecontrol signal 239 which may be generated by theprocessor 224. In an exemplary embodiment of the invention, thefilter 232 may comprise a second order infinite impulse response (IIR) filter. - The
AGC 234 may comprise suitable logic, circuitry, interfaces, and/or code that may be operable to apply a gain to thesignal 233 to generate thesignal 235. The amount of gain applied may be based on feedback such that levels ofsignal 235 are kept within an optimum range for operation of thePLL 236. - The
PLL 236 may comprise suitable logic, circuitry, interfaces, and/or code that may be operable to generate asignal 237 having a frequency that tracks the frequency of theinterference 104′n. In an exemplary embodiment of the invention, thePLL 236 may comprise a phase detector, a loop filter and one or more numerical controlled oscillators (NGOs) in a feedback path from the loop filter to the phase detector. The output of the loop filter may be thesignal 237. - The
tone generation block 238 may comprise suitable logic, circuitry, interfaces, and/or code that may be operable to generate phase-quadrature tones 219 1 and 219 2 having a frequency that tracks the frequency of theinterference 104′n. - In operation, the
data multiplexer 230 may select signal 207 n, signal 221, or a signal corresponding to a difference between the signals 207 n and the signal 211 g. The data multiplexer 230 may be controlled by theprocessor 224. In this regard, theprocessor 224 may control the data multiplexer 230 based on the presence and/or strength of one or more of theinterference components 104″1-104″4, which may be determined by, for example, monitoring the error outputs 213 1-213 4 and/or an error rate out of theLDPC 212. - The signal selected by the data multiplexer 230 may be output as
signal 231 to thefilter 232. Thefilter 232 may process thesignal 231 to generate thesignal 233. Ideally, thesignal 233 comprises only theinterference 104′n, but in reality other signals and/or noise will also be present. - The frequency response of the
filter 232 may be set by theprocessor 224. Furthermore, theprocessor 224 may disable one or more portions of thetone generator 218. In this regard, thetone generator 218 being disabled may result in the estimate signals 217 1-217 4 (FIG. 2A ) being zero and thus the signals 209 1-209 4 (FIG. 2A ) being equal to the signals 207 1-207 4 (FIG. 2A ). Theprocessor 224 may enable and disable portions of thetone generator 218 based on the presence and/or strength of one or more of theinterference components 104″1-104″4, which may be determined by, for example, monitoring the error outputs 213 1-213 4 and/or an error rate out of theLDPC 212. - The
PLL 236 may lock to thesignal 235 and output thesignal 237. In this regard, because thefilter 232 cannot perfectly pass only theinterference 104′n, there may be other noise and/or components of thesignal 233 that do not result from theinterference 104. Accordingly, by locking to the frequency of theinterference 104′n and generating thesignal 237 from an oscillator that is more spectrally pure, thesignals 237 may represent a cleaner version of theinterference 104′n. That is, thesignal 237 may be free of some noise or other signal components that are present in thesignal 233. - The
tone generation block 238 may receive the output of thePLL 238 and generate phase quadrature signals 219 1 and 219 2 having a frequency that accurately tracks the frequency of theinterference 104′n. -
FIG. 2C is a diagram illustrating an exemplary data multiplexer in accordance with an embodiment of the invention. Referring toFIG. 2C , thedata multiplexer 230 may comprise combiners 244 1-244 4, 2-to-1 multiplexers 242 1-242 4, and a 5-to-1multiplexer 241. - Each of the combiners 244 1-244 4 may comprise suitable logic, circuitry, interfaces, and/or code that may be operable to add and/or subtract digital signals. A weighting may be applied to one or more of the signals prior to addition or subtraction of the signals. The combiners 244 1-244 4 may subtract the estimate signals 207 1-207 4 from the signals 211 1-211 4, respectively, to generate the signals 245 1-245 4.
- Each 2-to-1 multiplexer 242 n may comprise suitable logic, circuitry, interfaces, and/or code that may be operable to select between the signal 211 n and the signal 245 n and output the selected signal as signal 243 n.
- The 5-to-1
multiplexer 241 may comprise suitable logic, circuitry, interfaces, and/or code that may be operable to select one of thesignal 243 1, 243 2, 243 3, 243 4, and 221. - In operation, the processor 224 (
FIG. 2A ) may generate thesignal 241 to control the multiplexers 242 1-242 4 and 244. In an exemplary embodiment of the invention, thesignal 221 may be selected if it is available. If thesignal 221 is not available, one of the signals 207 1-207 4 may be selected when theinterference components 104″1-104″4 are strong and one of the signals 245 1-245 4 may be selected when theinterference components 104″1-104″4 are weak. In this regard, thedata multiplexer 218 may be controlled based on the presence and/or strength of theinterference 104, which may be determined by, for example, monitoring the error outputs 213 1-213 4 and/or the error rate out of theLDPC decoder 212. -
FIG. 2D is a diagram illustrating a plurality of error multiplexers in accordance with an embodiment of the invention. Referring toFIG. 2D , each error multiplexer 214 n may comprise suitable logic, circuitry, interfaces, and/or code that may be operable to select between the signal 209 n and the signal 213 n and output the selected signal as signal 215 n. - In operation, the processor 224 (
FIG. 2A ) may generate thesignal 251 to control the error multiplexers 214 1-214 4.Signal 251 may be generated based on the presence and/or strength of theinterference components 104″1-104″4, which may be determined by, for example, monitoring the error outputs 213 1-213 4 and/or the error rate out of theLDPC decoder 212. In an exemplary embodiment of the invention, the signals 209 1-209 4 may be selected when theinterference components 104″1-104″4 of the signals 209 1-209 4 are strong and the signals 213 1-213 4 may be selected when theinterference components 104″1-104″4 of the signals 209 1-209 4 are weak. In this regard, the error multiplexers 214 1-214 4 may initially be configured to select signals 209 1-209 4 until thetone generator 218 has a chance to converge and start generating estimate signals 217 1-217 4 that reduce theinterference components 104″1-104″4 of the signals 209 1-209 4. Once theinterference components 104″1-104″4 have been sufficiently reduced, the error multiplexers 214 1-214 4 may be reconfigured to select the signals 213 1-213 4. -
FIG. 3 is a diagram illustrating exemplary magnetics comprising a common mode sense circuit, in accordance with an embodiment of the invention. Referring toFIG. 3 , themagnetics 202 may couple the channels 106 1-106 N to the differential signal traces 306 1-306 N. Themagnetics 202 may comprise chokes 302 1-302 N, transformers 304 1-304 N+1, andresistors 306 a and 306 b. In this regard, thecommon mode sensor 326 may comprise theresistors 306 a and 306 b and the transformer 304 N+1. - The chokes 302 1-302 N may be operable to attenuate common mode signals while passing differential signals. In an exemplary embodiment of the invention, the chokes 302 1-302 N may comprise one or more inductors and/or ferrites.
- The transformers 304 1-304 N+1 may be operable to inductively couple the differential outputs of the chokes 302 1-302 N to the differential signal traces 306 1-306 N+1. Each of the transformers 304 1-304 N+1 may comprise a primary winding, a secondary winding, and a core.
- The
resistors 306 a and 306 b and the transformer 304 N+1 form an exemplary commonmode sense circuit 326. In another exemplary embodiment of the invention, thecommon mode sensor 326 may comprise a center tap of one of the transformers 304 1-304 N. In such an embodiment of the invention, theresistors 306 a and 306 b and the transformer 304 N+1 may be unnecessary. - In operation, common mode energy on the two conductors of channel 106 N may sum through the
resistors 306 a and 306 b and appear as a single-ended raw common mode signal at the primary winding 304 N+1. The transformer 304 N+1 may convert the single-ended raw common mode signal to a differential raw common mode signal on the differential trace 306 N+1. -
FIG. 4 is a flow chart illustrating exemplary steps for interference cancellation, in accordance with an embodiment of the invention. Referring toFIG. 4 , the exemplary steps may begin withstep 402 in which theprocessor 224 may detect the presence of interference and enable interference cancellation. For example, the presence of interference may be detected based on an error rate out of theLDPC decoder 212. The cancellation of interference may comprise, for example, enabling various portions of thetone generator 218. Instep 404, it may be determined whether thecommon mode signal 221 is available from theADC 220. That is, it may be determined whether a commonmode sense circuit 326 is present. In instances that there is no common mode sense circuit, the exemplary steps may advance to step 408. Instep 408, it may be determined whether one or more of theinterference components 104′1-104′N is above a threshold. In instances that the interference is above a threshold, the steps may advance to step 412. Instep 412, thedata multiplexer 230 may be configured to select the signal 207 n to be output assignal 231. Subsequent to step 412, the exemplary steps may advance to step 414. - Returning to step 408, in instances that the
interference components 104′1-104′N are above a threshold, the exemplary steps may advance to step 410. Instep 410, the data multiplexer may be configured to select the difference between an equalizer output 207 n and the corresponding slicer decision output 211 n. Subsequent to step 410, the exemplary steps may advance to step 414. - Returning to step 404, in instances that the
signal 221 is available, the exemplary steps may advance to step 406. Instep 406, thedata multiplexer 230 may be configured to select thesignal 221 to be output as thesignal 231. - In
step 414, it may be determined whether the interference present in one or more of the signals 209 1-209 N is above a threshold. Subsequent to step 406, the exemplary steps may advance to step 414. - In
step 414, it may be determined whether one or more of theinterference components 104″1-104″N are above a threshold. In instances that the interference is above a threshold, the exemplary steps may advance to step 416. Instep 416, the error multiplexers 214 1-214 N may be configured to select the signals 209 1-209 N, respectively. Subsequent to step 416 the exemplary steps may advance to step 420. - Returning to step 414, in instances that the
interference components 104″1-104″N are below a threshold, the exemplary steps may advance to step 418. Instep 418, the error multiplexers 214 1-214 N may be configured to select the signals 213 1-213 N, respectively. Subsequent to step 418 the exemplary steps may advance to step 420. - In
step 420, thetone generator 218 may lock to the interference and output phase-quadrature tones 219 1 and 219 2. Instep 422, the adaptive filters 216 1-216 N may utilize the signals 219 1 and 219 2 and the output of the error multiplexers 214 1-214 N to generate the estimate signals 217 1-217 N. Instep 424, the estimate signals 217 1-217 N may be subtracted from the signals 207 1-207 N, in order to reduce theinterference components 104″1-104″N. Subsequent to step 424, the exemplary steps may return to step 414. - Various embodiments of a method and system for adaptive tone cancellation for mitigating the effects of electromagnetic interference are provided. In an exemplary embodiment of the invention, an
Ethernet PHY 200 may receive one or more signals 103 1-103 N via a corresponding one or more physical channels 106 1-106 N. TheEthernet PHY 200 may generate one or more estimate signals 217 1-217 N, each of which approximatesinterference 104′1-104′N present in a corresponding one of the received signals 103 1-103 N. TheEthernet PHY 200 may be operable to subtract each one of the estimate signals 217 1-217 N from a corresponding one of received signals 207 1-207 N, where received signals 207 1-207 N may correspond to the received signals 103 1-103 4 at the output of equalizers 106 1-106 4. The subtracting may occur at the input of one or more slicers 210 in theEthernet PHY 200. A signal 207 n output by an equalizer 206 n may be utilized to generate the one or more estimate signals 217 1-217 N. TheEthernet PHY 200 may receive acommon mode signal 203 from acommon mode sensor 326 coupled to one of the physical channels 106 1-106 N. Thecommon mode signal 203 may be utilized to generate the one or more estimate signals 217 1 -217 N. A decision output 211 n of a slicer 210 n in theEthernet PHY 200 may be subtracted from an output 207 n of an equalizer 206 n in theEthernet PHY 200. A signal 245 n resulting from the subtraction may be utilized to generate the one or more estimate signals 217 1-217 N. - The one or more estimate signals 217 1-217 N may be generated utilizing a selected one of the following signals: (1) an equalizer output 207 n; (2) a signal 245 n resulting from a subtraction of a slicer decision output 211 n from the equalizer output 207 n; and (3) a
signal 221 output by a commonmode sense circuit 326 coupled to one of the physical channels 106 1-106 N. The selection may be based on a strength of theinterference 104′1-104′N that may be present in the signals 207 1-207 N. TheEthernet PHY 200 may be operable to generate a pair of phase-quadrature signals 219 1 and 219 2 having a frequency that tracks a frequency of theinterference 104′1-104′N. An adaptive filter 216 n in theEthernet PHY 200 may utilize the phase-quadrature signals 219 1 and 219 2 to generate the one or more estimate signals 217 1 and 217 2. The estimate signal 217 n may be generated utilizing a selected one of a decision output 211 n of a slicer 210 n and an error output 213 n of the slicer 210 n. The selected one of the decision output 211 n and the error output 213 n may be utilized by the adaptive filter 216 n to generate the estimate signal 217 n. The selection may be based on strength of theinterference 104″n present in the signal 209 n. - Other embodiments of the invention may provide a non-transitory computer readable medium and/or storage medium, and/or a non-transitory machine readable medium and/or storage medium, having stored thereon, a machine code and/or a computer program having at least one code section executable by a machine and/or a computer, thereby causing the machine and/or computer to perform the steps as described herein for adaptive tone cancellation for mitigating the effects of electromagnetic interference.
- Accordingly, the present invention may be realized in hardware, software, or a combination of hardware and software. The present invention may be realized in a centralized fashion in at least one computer system, or in a distributed fashion where different elements are spread across several interconnected computer systems. Any kind of computer system or other apparatus adapted for carrying out the methods described herein is suited. A typical combination of hardware and software may be a general-purpose computer system with a computer program that, when being loaded and executed, controls the computer system such that it carries out the methods described herein.
- The present invention may also be embedded in a computer program product, which comprises all the features enabling the implementation of the methods described herein, and which when loaded in a computer system is able to carry out these methods. Computer program in the present context means any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following: a) conversion to another language, code or notation; b) reproduction in a different material form.
- While the present invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present invention without departing from its scope. Therefore, it is intended that the present invention not be limited to the particular embodiment disclosed, but that the present invention will include all embodiments falling within the scope of the appended claims.
Claims (20)
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US13/953,005 US20130308695A1 (en) | 2010-07-01 | 2013-07-29 | Method and System for Adaptive Tone Cancellation for Mitigating the Effects of Electromagnetic Interference |
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US36080010P | 2010-07-01 | 2010-07-01 | |
US12/835,419 US8498217B2 (en) | 2010-07-01 | 2010-07-13 | Method and system for adaptive tone cancellation for mitigating the effects of electromagnetic interference |
US13/953,005 US20130308695A1 (en) | 2010-07-01 | 2013-07-29 | Method and System for Adaptive Tone Cancellation for Mitigating the Effects of Electromagnetic Interference |
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US12/835,419 Continuation US8498217B2 (en) | 2010-07-01 | 2010-07-13 | Method and system for adaptive tone cancellation for mitigating the effects of electromagnetic interference |
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US13/953,005 Abandoned US20130308695A1 (en) | 2010-07-01 | 2013-07-29 | Method and System for Adaptive Tone Cancellation for Mitigating the Effects of Electromagnetic Interference |
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US20120002711A1 (en) | 2012-01-05 |
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