US20140154997A1 - Rf testing system - Google Patents

Rf testing system Download PDF

Info

Publication number
US20140154997A1
US20140154997A1 US14/054,213 US201314054213A US2014154997A1 US 20140154997 A1 US20140154997 A1 US 20140154997A1 US 201314054213 A US201314054213 A US 201314054213A US 2014154997 A1 US2014154997 A1 US 2014154997A1
Authority
US
United States
Prior art keywords
signal
test
test equipment
evaluation
module circuitry
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US14/054,213
Inventor
Yen-Liang Chen
Chun-Hsien Peng
Ying-chou Shih
Yu-An Chen
Chun-Wei Yang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MediaTek Inc
Original Assignee
MediaTek Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MediaTek Inc filed Critical MediaTek Inc
Priority to US14/054,213 priority Critical patent/US20140154997A1/en
Priority to SG2013079553A priority patent/SG2013079553A/en
Priority to CN201310628205.XA priority patent/CN103852714B/en
Assigned to MEDIATEK INC. reassignment MEDIATEK INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, YU-AN, CHEN, YEN-LIANG, PENG, CHUN-HSIEN, YANG, CHUN-WEI, SHIH, YING-CHOU
Publication of US20140154997A1 publication Critical patent/US20140154997A1/en
Priority to US14/696,807 priority patent/US10110325B2/en
Priority to US14/953,673 priority patent/US9525500B2/en
Priority to US15/071,536 priority patent/US20160197684A1/en
Priority to US15/071,513 priority patent/US10069578B2/en
Priority to US15/074,978 priority patent/US10320494B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/0082—Monitoring; Testing using service channels; using auxiliary channels
    • H04B17/0085—Monitoring; Testing using service channels; using auxiliary channels using test signal generators
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/20—Monitoring; Testing of receivers
    • H04B17/29—Performance testing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/46—Monitoring; Testing

Definitions

  • the present invention relates to semiconductor devices, and in particular to radio frequency (RF) testing systems for semiconductor devices.
  • RF radio frequency
  • Semiconductor devices are manufactured in the form of wafers comprising many thousands of devices.
  • the wafers are diced into dies and packaged into integrated circuits (IC).
  • IC integrated circuits
  • Each IC has been implemented by integrating more and more digital and analog circuits into a single chip.
  • ATE automatic test equipment
  • DUT device under test
  • processing RF signals emanating from the DUT leading to increased cost and time to conduct the tests. Therefore, there is a need for an effective RF test technique for transceivers that can solve the above-mentioned problems.
  • an integrated circuit includes an RF transmitter configured to generate an RF signal in response to a command signal from test equipment; an RF receiver configured to generate an evaluation signal according to the RF signal, and report the evaluation signal to the test equipment, so that the test equipment performs a test analysis on the evaluation signal to determine a test result, wherein the test equipment is external to the IC.
  • an integrated circuit in another exemplary embodiment, includes: an RF transmitter configured to generate an RF signal in response to a command signal from test equipment, and transmits the RF signal to a module circuitry for performing signal conversion by the module circuitry to generate an evaluation signal, wherein the evaluation signal is reported to the test equipment, so that the test equipment performs a test analysis on the evaluation signal to determine a test result, wherein the test equipment and the module circuitry are both external to the IC.
  • an integrated circuit includes: an RF receiver configured to receives an RF signal from a module circuitry in response to a command signal from test equipment, to generate an evaluation signal according to the received RF signal, and report the evaluation signal to the test equipment, so that the test equipment performs a test analysis on the evaluation signal to determine a test result, wherein the module circuitry and the test equipment are both external to the IC.
  • test equipment communicating with an integrated circuit (IC)
  • the test equipment includes: a control port configured to send a command signal to the IC for initiating a RF test process; an input port configured to receive an evaluation signal indicative of an electrical characteristic of an RF signal of the IC, wherein the evaluation signal is a baseband signal; and a test analyzer configured to perform a test analysis on the evaluation signal to determine a test result.
  • a radio frequency (RF) testing system includes: test equipment; a module circuitry; and an integrated circuit (IC) configured to communicate with the module circuitry by an RF signal in response to a command signal from the test equipment, generate an evaluation signal by the RF signal, and report the evaluation signal to the test equipment, so that the test equipment performs a test analysis on the evaluation signal to determine the test result, wherein the module circuitry is external to the IC and the test equipment.
  • RF radio frequency
  • a radio frequency (RF) testing system includes: test equipment; a module circuitry; and an integrated circuit (IC) configured to communicate with the module circuitry by an RF signal in response to a command signal from the test equipment, wherein the module circuitry generates an evaluation signal according to the RF signal from the IC, and reports the evaluation signal to the test equipment, so that the test equipment performs a test analysis on the evaluation signal to determine the test result, wherein the module circuitry is external to the IC and the test equipment.
  • IC integrated circuit
  • FIG. 1 is a block diagram of a conventional radio frequency (RF) testing system 1 ;
  • FIG. 2 is a simplified schematic block diagram of an RF testing system 3002 according to an embodiment of the invention.
  • FIG. 3 is a detailed schematic block diagram of an RF testing system 3003 according to an embodiment of the invention.
  • FIG. 4 is a detailed schematic block diagram of the RF testing system 3004 according to another embodiment of the invention.
  • FIGS. 5A-5B are schematic block diagrams of the signal converter 330 according to different embodiments of the invention.
  • FIG. 6 is a detailed schematic block diagram of the RF testing system 3006 according to yet another embodiment of the invention.
  • FIG. 7 is a detailed schematic block diagram of the RF testing system 3007 according to still yet another embodiment of the invention.
  • FIG. 8A ⁇ 8C are block diagrams of the external source generator 310 according to different embodiments of the invention.
  • FIG. 9 is a schematic block diagram of an RF testing system 3009 according to an embodiment of the invention.
  • FIG. 10 is a schematic block diagram of an RF testing system 3010 according to another embodiment of the invention.
  • FIG. 11 is a schematic block diagram of an RF testing system 3011 according to yet another embodiment of the invention.
  • FIG. 12 is a schematic block diagram of an RF testing system 3012 according to still yet another embodiment of the invention.
  • FIG. 13 is a schematic block diagram of an RF testing system 3013 according to still another embodiment of the invention.
  • FIG. 14 is a schematic block diagram of an RF testing system 3014 according to still another embodiment of the invention.
  • FIG. 1 is a block diagram of a conventional radio frequency (RF) testing system 3001 .
  • the RF testing system 3001 comprises an integration circuit (IC) 10 and automatic test equipment (ATE) 12 .
  • the ATE 12 applies semiconductor testing for digital and analog elements in the IC 10 during the hardware manufacturing procedure.
  • the IC 10 is a device under test (DUT) that receives power and testing patterns from the ATE 12 and outputs testing responses to the ATE 12 .
  • the ATE 12 is an electronic apparatus that receives a test program and performs tests accordingly on the DUT by supplying stimulus signals.
  • the ATE 12 also receives outcome signals, takes signal measurements, evaluates test results based on the signal measurements, and determines whether the DUT is good or bad.
  • the ATE 12 comprises a signal generator 1200 , a digitizer 1202 , a test result analyzer 1204 and a test controller 1206 .
  • the test controller 1206 sends a test control signal S CTRL to control all the registers in the IC 10 by some digital or analog pins to operate under a test mode.
  • the signal generator 1200 may provide an analog signal or/and RF signal (test pattern S TEST — IN ) to be injected into the IC 10 for the test of RF circuits.
  • the digitizer 1202 digitizes an output response S TEST — OUT from the IC 10 and converts analog signal or/and RF signal to digital signal.
  • the test result analyzer 1204 analyzes the evaluated signal performance of the digitized signal to determine whether the DUT has any faulty components for the wafer-level test or final test.
  • the IC 10 in FIG. 1 includes an RF testing system 30 , which comprises a baseband circuit 1000 and an RF transceiver 1002 .
  • the ATE 12 performs an RF test to the IC 10 , particularly to all transceivers for various communication systems adopted by the IC 10 by feeding the analog or/and RF test pattern S TEST IN into the IC 10 .
  • the RF testing system 30 illustrates a transmitter path and receiver path, wherein the transmitter path comprising a digital-to-analog converter (DAC) 10020 , a filter 10022 , a modulator 10024 , and a power amplifier (PA) 10026 , and the receiver path comprising a low noise amplifier (LNA) 10027 , a demodulator 10025 , a filter 10023 , and an analog-to-digital converter (ADC) 10021 .
  • the signal generator 1200 in the ATE 12 generates and injects a test pattern S TEST — IN in high frequency to a testing interface (not shown) for testing the RF receiver in the RF testing system 30 .
  • the ATE 12 may further receive analog or/and RF signal S TEST — OUT from the output of the transmitter path to evaluate the quality of transmitter of the IC 10 .
  • the ATE 12 supplies the analog or/and RF test pattern S TEST — IN to the IC 10 and receives the analog or/and RF output response S TEST — OUT from the IC 10 , therefore there is high-speed communication between the ATE 12 and the IC 10 , requiring the ATE 12 to work at a high speed, resulting in an increased cost of the ATE 12 .
  • FIG. 2 is a simplified schematic block diagram of an RF testing system 3002 according to an embodiment of the invention.
  • the RF testing system 3002 may comprise an IC 100 , ATE 200 , and a testing module board (e.g. a module circuitry) 300 .
  • the ATE 200 initializes a test process by sending a command signal S CMD to the IC 100 .
  • the IC 100 is arranged to enter into a test mode, and, in contrast to the ATE 200 controlling the test process in the conventional approach, the IC 100 takes control of the test operations.
  • this is for illustrative purpose rather than a limitation of the present invention.
  • the test process control may take place in the testing module board 300 , where the ATE 200 send the command signal S CMD to the testing module board 300 , and the testing module board 300 then sends a control signal to the IC 100 accordingly.
  • the ATE 200 may be equipped with the test process controlling.
  • the test process aims to locate defective build elements in mixed-mode circuitry or analog circuitry in the IC 100 . Under the test mode, the IC 100 communicates with the testing module board 300 using RF signals or analog signals.
  • the IC 100 may transmit the RF signals S RF — OUT to the testing module board 300 for transmission-performance evaluation or receive RF signals S RF — IN from the testing module board 300 , which is generated by the testing module board 300 itself or the IC 100 itself and passing through the testing module board 300 using an external loopback path, to evaluate the reception performance of the IC 100 (details will be described later).
  • the output signals S ev1 may be an evaluation signal which is low-frequency (e.g., baseband, close to zero) produced and sent by the IC 100 to the ATE 200 for a test analysis.
  • the output signals S ev2 may be an evaluation signal which is low-frequency (e.g., baseband, close to zero) produced and sent by the testing module board 300 to the ATE 200 for a test analysis.
  • the testing module board 300 which is external to the IC 100 and ATE 200 , comprises discrete components to assist signal property analysis as well as RF testing signal generation and receive a control signal S CTRL from the ATE 200 in the test mode. In this way, the ATE 200 does not need to process high-frequency (e.g. radio frequency) signals, and therefore the cost can be reduced.
  • the DUT is not necessarily equipped with a digital signal processor, that is, the IC 100 can be a system-on-chip (SOC) circuit or a stand-alone RF IC.
  • SOC system-on-chip
  • FIG. 3 is a detailed schematic block diagram of the RF testing system 3003 according to an embodiment of the invention.
  • the RF testing system 3003 may comprise an IC 100 and ATE 200 .
  • the IC 100 may be a system-on-chip (SOC) or a stand-alone RF IC having digital-to-analog converters (DAC) and analog-to-digital converters (ADC).
  • the IC 100 comprises a signal generator 110 , an RF transmitter 120 , an attenuator 130 , an RF receiver 140 , and communication ports 170 , 180 .
  • the RF transmitter 120 and the RF receiver 140 may belong to the same or different transceiver systems.
  • the transmitter 120 and the receiver 140 may both belong to a WLAN system, or they may respectively belong to a WLAN system and a Bluetooth system.
  • the signal generator 110 comprises a memory circuit 111 that keeps various test patterns for the RF test process therein, and a baseband circuit 112 that performs digital power control (not shown) and/or digital compensations (not shown) such as in-phase/quadrature (IQ) mismatch and digital pre-distortion.
  • the RF transmitter 120 comprises a DAC 121 , a filter circuit 122 , a modulator 123 , and a power amplifier (PA) 124 .
  • PA power amplifier
  • the RF receiver 140 comprises a demodulator 142 , a filter 143 , and an ADC 144 .
  • the modulator 123 and demodulator 142 may further receive carrier signals from one or more local oscillators (not shown) to modulate and demodulate the outgoing and incoming RF signals, respectively.
  • the communication port 170 outputs an evaluation signal S ev1 generated by the RF receiver 140 to the ATE 200 .
  • the ATE 200 may comprise a test analyzer 210 , a test controller 220 , and communication ports 240 , 246 .
  • the test controller 220 of the ATE 200 directs the command signal S CMD through the communication ports 240 and 180 to components of the IC 100 , thereby controlling components of the IC 100 to perform the RF test process.
  • the IC 100 enters a test mode and generates a test pattern signal S t internally.
  • the test pattern S t is sent to the RF transmitter 120 to undergo various analog circuits passing in the transmitter path, rendering an outgoing RF signal S RF — OUT , which is further sent to the RF receiver 140 through the internal attenuator 130 .
  • the test analyzer 210 can be used to measure power at frequency associated with wanted tone, image tone or second-order or third-order harmonics to test transmitter/receiver gain, image rejection ratio (IRR), input second intercept point (IIP2), input third intercept point (IIP3), etc.
  • IRR image rejection ratio
  • IIP2 input second intercept point
  • IIP3 input third intercept point
  • the lock-time measure can also be implemented by software or hardware in the test analyzer 210 to test the lock time of a phase-locked loop (PLL), which comprises the instantaneous frequency estimation, lock-time calculation using the information of the frequency estimates, and pass/fail decision.
  • Some estimators of modulated tests such as error vector magnitude (EVM) and spectrum estimators can also be implemented in the test analyzer 210 to evaluate the quality of the RF transmitter 120 .
  • EVM error vector magnitude
  • spectrum estimators can also be implemented in the test analyzer 210 to evaluate the quality of the RF transmitter 120 .
  • the outgoing RF signal S RF — OUT is transferred to the demodulator 142 of the RF receiver 140 through the attenuator 130 to undergo RF impairments in a receiver path, outputting a first baseband evaluation signal S ev1 through the communication port 170 to the test analyzer 210 of the ATE 200 for test analysis.
  • FIG. 4 is a detailed schematic block diagram of the RF testing system 3004 according to another embodiment of the invention.
  • the circuit configuration is similar to that in FIG. 3 except that the testing module board 300 is connected to the IC 100 and a low noise amplifier (LNA) 141 and switches SW 1 , SW 2 are involved.
  • the input of the demodulator 142 can be from the internal attenuator 130 or from the LNA 141 when the internal loopback path or the external loopback path is selected, respectively (details will be described later). When the internal loop-back path is selected (corresponding to FIG.
  • the switch SW 1 is opened and the switch SW 2 is closed, so that the outgoing RF signal S RF — OUT is looped back through the internal attenuator 130 between the output of the RF transmitter 120 and the input of the RF receiver 140 , such that the signal performance of the RF transmitter 120 and RF receiver 140 can be evaluated without the use of the external testing module board 300 .
  • the external loopback configuration is selected.
  • the switch SW 1 is closed and the switch SW 2 is opened.
  • test controller 220 of the ATE 200 further directs the control signal S CTRL through the communication ports 242 , 372 to control the testing module board 300 , and the communication port 160 of the IC 100 acquires the incoming RF signal S RF — IN from the testing module board 300 .
  • the testing module board 300 which is external to the IC 100 and the ATE 200 , may comprise an input port 370 , a loopback port 374 , a control port 372 , an output port 376 , an adjustable attenuator 320 , a switch SW 3 , and a signal converter 330 .
  • a testing load board (not shown) is provided to hold the testing module board 300 and the IC 100 together.
  • the testing load board may comprise an IC socket (not shown) to accept the IC 100 and a module slot (not shown) to hold the testing module board 300 in place during the test.
  • the input port 370 accepts the response RF signal S RF — OUT from the IC 100 .
  • the control port 372 receives the control signal S CTRL from the test controller 220 of the ATE 200 to enable the testing module board 300 to work under the test mode.
  • the control signal S CTRL controls the attenuator 320 and switching of the switch SW 3 .
  • the attenuator 320 receives controls via the control signal S CTRL to adjust the attenuation level to the RF signal S RF — OUT .
  • the switch SW 3 is selected by the control signal S CTRL to switch between the signal converter configuration (i.e. through the signal converter 330 ) and the external loopback configuration (i.e. through the loopback port 374 ).
  • the switch SW 3 is switched to the loopback port 374 , the outgoing RF signal S RF — OUT from the RF transmitter 120 is attenuated by the attenuator 320 of the testing module board 300 , and then output to the LNA 141 of the RF receiver 140 through the loopback port 374 to undergo RF impairments in a receiver path.
  • the RF transmitter output signal S RF — OUT is looped back through the attenuator 320 as an input RF signal S RF — IN to the RF receiver 140 for a further test in the receiver path.
  • the input RF signal S RF — IN is down-converted into the baseband, which is digitized into digital words regarded as the evaluation signal S ev1 sent to the test analyzer 210 of the ATE 200 for test analysis.
  • FIGS. 5A-5B are schematic block diagrams of the signal converter 330 according to different embodiments of the invention.
  • the signal converter 330 may be implemented in different circuits, thereby converting RF signals into analog/digital signals.
  • the signal converter 330 may comprise a power detector 331 and an ADC 332 , as illustrated in FIG. 5A .
  • the signal converter 330 may have similar components, such as an LNA 333 , a demodulator 334 , a filter 335 , and an ADC 336 , as those in the RF receiver 140 , as illustrated in FIG. 5B .
  • the invention is not limited to the aforementioned implementations of the signal converter 330 .
  • a reference RF receiver can be implemented in various circuits, and the details will not be described here.
  • evaluation signals S ev1 and S ev2 may be in analog or digital form.
  • the RF transmitter 120 and the RF receiver 140 do not have DAC/ADC circuits, and the test analyzer 210 may further comprise a digitizer (not shown) to convert the incoming analog evaluation signals into digital signals, thereby performing digital signal analysis of the RF test process.
  • the present embodiment depicts an RF testing system where signal received/transmitted by the ATE 200 is only low-frequency signals. Only low-frequency command signal S CMD and evaluation signals S ev1 are exchanged between the IC 100 and the ATE 200 . In addition, only low-frequency control signal S CTRL and evaluation signals S ev2 are exchanged between the testing module board 300 and the ATE 200 . It should be noted that high-speed communication is only between the IC 100 and the testing module board 300 . This leads to a reduction in the circuit complexity of the ATE 200 , thereby decreasing design and manufacturing cost.
  • three configurations which are the internal loopback configuration, the external loopback configuration, and the signal converter configuration, are provided to test the transmission performance of the IC 100 .
  • a test analysis of the transmission performance of the IC 100 can be performed by the test analyzer 210 of the ATE 200 .
  • the transmitter path is usually tested at the system level test by the EVM and spectrum, nonlinearity tests such as IIP2 and IIP3, an image signal test, a carrier leakage test, and a transmission power test.
  • FIG. 7 is a detailed schematic block diagram of the RF testing system 3007 according to still yet another embodiment of the invention.
  • the circuit configuration and connection is similar to those in the RF testing system 3006 , except that in the RF testing system 3007 , an external source generator 310 and a switch SW 4 are placed at the testing module board 300 for further performing Rx test process.
  • the switch SW 4 is controlled by the control signal S CTRL to switch between the incoming RF signals from the RF transmitter 120 or from the external source generator 310 .
  • the external source generator 310 may start to generate the single-tone, two-tone, and modulation signals required in the RF Rx test process.
  • the switch SW 4 is switched to the external source generator 310 and the switch SW 3 is switched to the communication port 374 .
  • the generated signals from the external source generator 310 are fed into the attenuator 320 , and then the attenuated RF signals are transmitted to the LNA 141 of the RF receiver 140 via the communication port 374 , thereby evaluating the reception performance of the IC 100 in the receiver path at the test analyzer 210 .
  • the RF receiver 140 may output the first evaluation signal S ev1 through the communication port 170 to the test analyzer 210 of the ATE 200 for test analysis.
  • a test analysis of the reception performance of the IC 100 can be performed by the test analyzer 210 of the ATE 200 .
  • the evaluated characteristics for the receiver path comprise a receiver gain test, an image signal test, a DC offset test, an NF test, and nonlinearity tests such as IIP2 and IIP3.
  • FIG. 8A ⁇ 8C are block diagrams of the external source generator 310 according to different embodiments of the invention.
  • the external source generator 310 may be a single-tone generator, a dual-tone generator, and/or a reference RF transmitter, as illustrated in FIG. 8A , 8 B and 8 C, respectively.
  • the DAC in FIG. 8C may be coupled to a test pattern generator not shown, or receive test pattern from the TE 200 . Implementations of the signal-tone generator, dual-tone generator, and the reference RF transmitter are well-known to those skilled in the art, and the details will not be described here.
  • FIG. 9 is a schematic block diagram of an RF testing system 3009 according to an embodiment of the invention.
  • the IC 500 may be a stand-alone RF IC without a signal generator. Accordingly, the function of the signal generator is moved to the ATE 200 .
  • the test controller 220 may control the signal generator 230 internally, thereby transmitting predefined RF test patterns to the RF transmitter 120 .
  • the circuit configuration and connection of the remaining components in the RF testing system 3009 are similar to those in the RF testing system 3003 , and the details can be referred to in the aforementioned embodiments of FIG. 3 . Similar to the embodiment of FIG. 3 , the internal loopback configuration is also selected in the RF testing system 3009 .
  • the RF transmitter 120 receives the external RF test pattern signals from the signal generator 230 of the ATE 200 . Then, the outgoing RF signal generated by the RF transmitter 120 may be internally fed back to the RF receiver 140 through the internal attenuator 130 . In addition, the evaluation signal S ev1 output by the RF receiver 140 can be fed into the test analyzer 210 for test analysis.
  • FIG. 10 is a schematic block diagram of an RF testing system 3010 according to another embodiment of the invention.
  • the IC 500 may be a stand-alone RF IC without a signal generator. Accordingly, the function of the signal generator is moved to the ATE 200 .
  • the test controller 220 may control the signal generator 230 internally, thereby transmitting predefined RF test patterns to the RF transmitter 120 .
  • the circuit configuration and connection of the remaining components in the RF testing system 3010 are similar to those in the RF testing system 3004 , and the details can be referred to in the aforementioned embodiments of FIG. 4 . Similar to the embodiment of FIG. 4 , the external loopback configuration is also selected in the RF testing system 3010 .
  • the RF transmitter 120 receives the external RF test pattern signals from the signal generator 230 of the ATE 200 and generates the outgoing RF test signal S RF — OUT . Then, the outgoing RF test signal S RF — OUT from the RF transmitter 120 is transmitted to the testing module board 300 .
  • the RF test signal S RF — OUT is attenuated by the attenuator 320 in the testing module board 300 , and the attenuated RF test signal is further fed back into the RF receiver 140 through the communication port 160 . Subsequently, the evaluation signal S ev1 output by the RF receiver 140 can be fed into the test analyzer 210 for test analysis.
  • FIG. 11 is a schematic block diagram of an RF testing system 3011 according to yet another embodiment of the invention.
  • the IC 500 may be a stand-alone RF IC without a signal generator. Accordingly, the function of the signal generator is moved to the ATE 200 .
  • the test controller 220 may control the signal generator 230 internally, thereby transmitting predefined RF test patterns to the RF transmitter 120 .
  • the circuit configuration and connection of the remaining components in the RF testing system 3011 are similar to those in the RF testing system 3006 , and the details can be referred to in the aforementioned embodiments of FIG. 6 . Similar to the embodiment of FIG. 6 , the signal converter configuration is also selected in the RF testing system 3011 .
  • the RF transmitter 120 receives the external RF test pattern signals from the signal generator 230 of the ATE 200 . Then, the outgoing RF test signal S RF — OUT from the RF transmitter 120 is transmitted to the testing module board 300 .
  • the RF test signal S RF — OUT is attenuated by the attenuator 320 in the testing module board 300 , and the attenuated RF test signal is further fed into the signal converter 330 for signal conversion.
  • a second evaluation signal S ev2 is generated by the signal converter 330 , and is further transmitted to the test analyzer 210 of the ATE 200 through the communication port 376 .
  • FIG. 12 is a schematic block diagram of an RF testing system 3012 according to still yet another embodiment of the invention.
  • the IC 500 may be a stand-alone RF IC without a signal generator.
  • the circuit configuration and connection of the components in the RF testing system 3012 are similar to those in the RF testing system 3007 except that the signal generator 230 has been moved to the ATE 200 , and the details can be referred to in the aforementioned embodiments of FIG. 7 .
  • the testing module board 300 is controlled by the control signals S CTRL generated by the test controller 220 of the ATE 200 .
  • the external source generator 310 may start to generate the single-tone, two-tone, and modulation signals required in the RF Rx test process. Meanwhile, the switch SW 4 is switched to the external source generator 310 and the switch SW 3 is switched to the communication port 374 , so that the generated signals from the external source generator 310 may be fed into the attenuator 320 , and then the attenuated RF signals can be transmitted to the LNA 141 of the RF receiver 140 via the communication port 374 , thereby evaluating the reception performance of the IC 100 in the receiver path at the test analyzer 210 .
  • the RF receiver 140 may output the first evaluation signal S ev1 through the communication port 170 to the test analyzer 210 of the ATE 200 for test analysis.
  • a test analysis of the reception performance of the IC 100 can be performed by the test analyzer 210 of the ATE 200 .
  • evaluation signals S ev1 and S ev2 may be in analog or digital form.
  • the above-mentioned RF transmitter and RF receiver do not have DAC/ADC circuits, and the test analyzer 210 may further comprise a digitizer (not shown) to convert the incoming analog evaluation signals into digital signals, thereby performing digital signal analysis of the RF test process.
  • FIG. 13 is a schematic block diagram of an RF testing system 3013 according to still another embodiment of the invention.
  • the IC 500 may be a SOC or a stand-alone RF IC having a test controller, and the circuit configuration and connection of the components in the RF testing system 3013 are similar to those in the RF testing system 3007 except that the test controller 220 has been moved to the IC 500 .
  • the test analyzer 210 of the ATE 200 is capable of initiating an RF Tx or Rx test process by issuing a command signal (i.e.
  • test analyzer 210 of the ATE 200 is still responsible for receiving the evaluation signal (i.e. a low-speed analog/digital signal) from either the RF receiver 140 or the signal convertor 330 for digital signal analysis.
  • the evaluation signal i.e. a low-speed analog/digital signal
  • the digitizer 240 of the ATE 200 may convert the evaluation signal into digital signals before the test analysis is performed by the test analyzer 210 .
  • FIG. 14 is a schematic block diagram of an RF testing system 3014 according to still another embodiment of the invention.
  • the IC 500 may be a SOC or a stand-alone RF IC, and the circuit configuration and connection of the components in the RF testing system 3014 are similar to those in the RF testing system 3007 except that the test controller 220 has been moved to the testing module board 300 .
  • the ATE 200 is capable of initiating an RF Tx or Rx test process by issuing a command signal (i.e.
  • test analyzer 210 of the ATE 200 is still responsible for receiving the evaluation signal (i.e. a low-speed analog/digital signal) from either the RF receiver 140 or the signal convertor 330 for digital signal analysis.
  • the evaluation signal i.e. a low-speed analog/digital signal
  • the digitizer 240 of the ATE 200 may convert the evaluation signal into digital signals before the test analysis is performed by the test analyzer 210 .

Abstract

An integrated circuit (IC) is provided. The IC includes an RF transmitter configured to generate an RF signal in response to a command signal from test equipment; an RF receiver configured to generate an evaluation signal according to the RF signal, and report the evaluation signal to the test equipment, so that the test equipment performs a test analysis on the evaluation signal to determine a test result, wherein the test equipment is external to the IC.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application claims the benefit of U.S. Provisional Application No. 61/731,845, filed at Nov. 30, 2012, the entirety of which is incorporated by reference herein.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to semiconductor devices, and in particular to radio frequency (RF) testing systems for semiconductor devices.
  • 2. Description of the Related Art
  • Semiconductor devices are manufactured in the form of wafers comprising many thousands of devices. The wafers are diced into dies and packaged into integrated circuits (IC). Each IC has been implemented by integrating more and more digital and analog circuits into a single chip.
  • Due to the increasing complexity of the testing of integrated RF circuits, to identify the “good” and “bad” ICs during production is a challenging problem for those conducting the wafer-level test or final test. In the traditional testing of RF circuits, what is used is expensive automatic test equipment (ATE), such as UltraFlex or Flex with RF instruments, or equipment used in mixing signals is used for generating an RF test signal (or RF patterns) to a device under test (DUT) and processing RF signals emanating from the DUT, leading to increased cost and time to conduct the tests. Therefore, there is a need for an effective RF test technique for transceivers that can solve the above-mentioned problems.
    • BRIEF SUMMARY OF THE INVENTION
  • A detailed description is given in the following embodiments with reference to the accompanying drawings.
  • In an exemplary embodiment, an integrated circuit (IC) is provided. The IC includes an RF transmitter configured to generate an RF signal in response to a command signal from test equipment; an RF receiver configured to generate an evaluation signal according to the RF signal, and report the evaluation signal to the test equipment, so that the test equipment performs a test analysis on the evaluation signal to determine a test result, wherein the test equipment is external to the IC.
  • In another exemplary embodiment, an integrated circuit (IC) is provided. The IC includes: an RF transmitter configured to generate an RF signal in response to a command signal from test equipment, and transmits the RF signal to a module circuitry for performing signal conversion by the module circuitry to generate an evaluation signal, wherein the evaluation signal is reported to the test equipment, so that the test equipment performs a test analysis on the evaluation signal to determine a test result, wherein the test equipment and the module circuitry are both external to the IC.
  • In yet another exemplary embodiment, an integrated circuit (IC) is provided. The IC includes: an RF receiver configured to receives an RF signal from a module circuitry in response to a command signal from test equipment, to generate an evaluation signal according to the received RF signal, and report the evaluation signal to the test equipment, so that the test equipment performs a test analysis on the evaluation signal to determine a test result, wherein the module circuitry and the test equipment are both external to the IC.
  • In still another exemplary embodiment, test equipment communicating with an integrated circuit (IC) is provided. The test equipment includes: a control port configured to send a command signal to the IC for initiating a RF test process; an input port configured to receive an evaluation signal indicative of an electrical characteristic of an RF signal of the IC, wherein the evaluation signal is a baseband signal; and a test analyzer configured to perform a test analysis on the evaluation signal to determine a test result.
  • In yet another exemplary embodiment, a radio frequency (RF) testing system is provided. The RF testing system includes: test equipment; a module circuitry; and an integrated circuit (IC) configured to communicate with the module circuitry by an RF signal in response to a command signal from the test equipment, generate an evaluation signal by the RF signal, and report the evaluation signal to the test equipment, so that the test equipment performs a test analysis on the evaluation signal to determine the test result, wherein the module circuitry is external to the IC and the test equipment.
  • In yet another exemplary embodiment, a radio frequency (RF) testing system is provided. The RF testing system includes: test equipment; a module circuitry; and an integrated circuit (IC) configured to communicate with the module circuitry by an RF signal in response to a command signal from the test equipment, wherein the module circuitry generates an evaluation signal according to the RF signal from the IC, and reports the evaluation signal to the test equipment, so that the test equipment performs a test analysis on the evaluation signal to determine the test result, wherein the module circuitry is external to the IC and the test equipment.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
  • FIG. 1 is a block diagram of a conventional radio frequency (RF) testing system 1;
  • FIG. 2 is a simplified schematic block diagram of an RF testing system 3002 according to an embodiment of the invention;
  • FIG. 3 is a detailed schematic block diagram of an RF testing system 3003 according to an embodiment of the invention;
  • FIG. 4 is a detailed schematic block diagram of the RF testing system 3004 according to another embodiment of the invention;
  • FIGS. 5A-5B are schematic block diagrams of the signal converter 330 according to different embodiments of the invention;
  • FIG. 6 is a detailed schematic block diagram of the RF testing system 3006 according to yet another embodiment of the invention;
  • FIG. 7 is a detailed schematic block diagram of the RF testing system 3007 according to still yet another embodiment of the invention;
  • FIG. 8A˜8C are block diagrams of the external source generator 310 according to different embodiments of the invention;
  • FIG. 9 is a schematic block diagram of an RF testing system 3009 according to an embodiment of the invention;
  • FIG. 10 is a schematic block diagram of an RF testing system 3010 according to another embodiment of the invention;
  • FIG. 11 is a schematic block diagram of an RF testing system 3011 according to yet another embodiment of the invention;
  • FIG. 12 is a schematic block diagram of an RF testing system 3012 according to still yet another embodiment of the invention;
  • FIG. 13 is a schematic block diagram of an RF testing system 3013 according to still another embodiment of the invention; and
  • FIG. 14 is a schematic block diagram of an RF testing system 3014 according to still another embodiment of the invention.
    •  DETAILED DESCRIPTION OF THE INVENTION
  • The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
  • FIG. 1 is a block diagram of a conventional radio frequency (RF) testing system 3001. As illustrated in FIG. 1, the RF testing system 3001 comprises an integration circuit (IC) 10 and automatic test equipment (ATE) 12. The ATE 12 applies semiconductor testing for digital and analog elements in the IC 10 during the hardware manufacturing procedure. The IC 10 is a device under test (DUT) that receives power and testing patterns from the ATE 12 and outputs testing responses to the ATE 12. The ATE 12 is an electronic apparatus that receives a test program and performs tests accordingly on the DUT by supplying stimulus signals. The ATE 12 also receives outcome signals, takes signal measurements, evaluates test results based on the signal measurements, and determines whether the DUT is good or bad. The ATE 12 comprises a signal generator 1200, a digitizer 1202, a test result analyzer 1204 and a test controller 1206. The test controller 1206 sends a test control signal SCTRL to control all the registers in the IC 10 by some digital or analog pins to operate under a test mode. The signal generator 1200 may provide an analog signal or/and RF signal (test pattern STEST — IN) to be injected into the IC 10 for the test of RF circuits. The digitizer 1202 digitizes an output response STEST — OUT from the IC 10 and converts analog signal or/and RF signal to digital signal. The test result analyzer 1204 analyzes the evaluated signal performance of the digitized signal to determine whether the DUT has any faulty components for the wafer-level test or final test.
  • The IC 10 in FIG. 1 includes an RF testing system 30, which comprises a baseband circuit 1000 and an RF transceiver 1002. The ATE 12 performs an RF test to the IC 10, particularly to all transceivers for various communication systems adopted by the IC 10 by feeding the analog or/and RF test pattern STEST IN into the IC 10. The RF testing system 30 illustrates a transmitter path and receiver path, wherein the transmitter path comprising a digital-to-analog converter (DAC) 10020, a filter 10022, a modulator 10024, and a power amplifier (PA) 10026, and the receiver path comprising a low noise amplifier (LNA) 10027, a demodulator 10025, a filter 10023, and an analog-to-digital converter (ADC) 10021. For an RF test, the signal generator 1200 in the ATE 12 generates and injects a test pattern STEST — IN in high frequency to a testing interface (not shown) for testing the RF receiver in the RF testing system 30. The ATE 12 may further receive analog or/and RF signal STEST — OUT from the output of the transmitter path to evaluate the quality of transmitter of the IC 10.
  • In the conventional RF test, the ATE 12 supplies the analog or/and RF test pattern STEST — IN to the IC 10 and receives the analog or/and RF output response STEST — OUT from the IC 10, therefore there is high-speed communication between the ATE 12 and the IC 10, requiring the ATE 12 to work at a high speed, resulting in an increased cost of the ATE 12.
  • FIG. 2 is a simplified schematic block diagram of an RF testing system 3002 according to an embodiment of the invention. As illustrated in FIG. 2, the RF testing system 3002 may comprise an IC 100, ATE 200, and a testing module board (e.g. a module circuitry) 300. The ATE 200 initializes a test process by sending a command signal SCMD to the IC 100. In response, the IC 100 is arranged to enter into a test mode, and, in contrast to the ATE 200 controlling the test process in the conventional approach, the IC 100 takes control of the test operations. However, this is for illustrative purpose rather than a limitation of the present invention. In other embodiments (which will be illustrated later), the test process control may take place in the testing module board 300, where the ATE 200 send the command signal SCMD to the testing module board 300, and the testing module board 300 then sends a control signal to the IC 100 accordingly. Or, the ATE 200 may be equipped with the test process controlling. Moreover, the test process aims to locate defective build elements in mixed-mode circuitry or analog circuitry in the IC 100. Under the test mode, the IC 100 communicates with the testing module board 300 using RF signals or analog signals. For example, the IC 100 may transmit the RF signals SRF — OUT to the testing module board 300 for transmission-performance evaluation or receive RF signals SRF — IN from the testing module board 300, which is generated by the testing module board 300 itself or the IC 100 itself and passing through the testing module board 300 using an external loopback path, to evaluate the reception performance of the IC 100 (details will be described later). The output signals Sev1 may be an evaluation signal which is low-frequency (e.g., baseband, close to zero) produced and sent by the IC 100 to the ATE 200 for a test analysis. Similarly, the output signals Sev2 may be an evaluation signal which is low-frequency (e.g., baseband, close to zero) produced and sent by the testing module board 300 to the ATE 200 for a test analysis. The testing module board 300, which is external to the IC 100 and ATE 200, comprises discrete components to assist signal property analysis as well as RF testing signal generation and receive a control signal SCTRL from the ATE 200 in the test mode. In this way, the ATE 200 does not need to process high-frequency (e.g. radio frequency) signals, and therefore the cost can be reduced. As the test analysis is performed by the ATE 200, the DUT is not necessarily equipped with a digital signal processor, that is, the IC 100 can be a system-on-chip (SOC) circuit or a stand-alone RF IC. In the following sections, different test configurations will be described.
  • FIG. 3 is a detailed schematic block diagram of the RF testing system 3003 according to an embodiment of the invention. The RF testing system 3003 may comprise an IC 100 and ATE 200. For example, the IC 100 may be a system-on-chip (SOC) or a stand-alone RF IC having digital-to-analog converters (DAC) and analog-to-digital converters (ADC). As illustrated in FIG. 3, the IC 100 comprises a signal generator 110, an RF transmitter 120, an attenuator 130, an RF receiver 140, and communication ports 170, 180. The RF transmitter 120 and the RF receiver 140 may belong to the same or different transceiver systems. For examples, the transmitter 120 and the receiver 140 may both belong to a WLAN system, or they may respectively belong to a WLAN system and a Bluetooth system. In some implementations, the signal generator 110 comprises a memory circuit 111 that keeps various test patterns for the RF test process therein, and a baseband circuit 112 that performs digital power control (not shown) and/or digital compensations (not shown) such as in-phase/quadrature (IQ) mismatch and digital pre-distortion. The RF transmitter 120 comprises a DAC 121, a filter circuit 122, a modulator 123, and a power amplifier (PA) 124. Similarly, the RF receiver 140 comprises a demodulator 142, a filter 143, and an ADC 144. The modulator 123 and demodulator 142 may further receive carrier signals from one or more local oscillators (not shown) to modulate and demodulate the outgoing and incoming RF signals, respectively. In this internal loopback configuration, the communication port 170 outputs an evaluation signal Sev1 generated by the RF receiver 140 to the ATE 200.
  • As illustrated in FIG. 3, the ATE 200 may comprise a test analyzer 210, a test controller 220, and communication ports 240, 246. The test controller 220 of the ATE 200 directs the command signal SCMD through the communication ports 240 and 180 to components of the IC 100, thereby controlling components of the IC 100 to perform the RF test process. In response, the IC 100 enters a test mode and generates a test pattern signal St internally. The test pattern St is sent to the RF transmitter 120 to undergo various analog circuits passing in the transmitter path, rendering an outgoing RF signal SRF — OUT, which is further sent to the RF receiver 140 through the internal attenuator 130. The test analyzer 210 can be used to measure power at frequency associated with wanted tone, image tone or second-order or third-order harmonics to test transmitter/receiver gain, image rejection ratio (IRR), input second intercept point (IIP2), input third intercept point (IIP3), etc. In the test analyzer 210, we can implement a noise-power estimator to calculate noise power or signal-to-noise ratio (SNR) of the receiver for the NF test. The lock-time measure can also be implemented by software or hardware in the test analyzer 210 to test the lock time of a phase-locked loop (PLL), which comprises the instantaneous frequency estimation, lock-time calculation using the information of the frequency estimates, and pass/fail decision. Some estimators of modulated tests such as error vector magnitude (EVM) and spectrum estimators can also be implemented in the test analyzer 210 to evaluate the quality of the RF transmitter 120.
  • Specifically, in the internal loopback configuration, the outgoing RF signal SRF — OUT is transferred to the demodulator 142 of the RF receiver 140 through the attenuator 130 to undergo RF impairments in a receiver path, outputting a first baseband evaluation signal Sev1 through the communication port 170 to the test analyzer 210 of the ATE 200 for test analysis.
  • FIG. 4 is a detailed schematic block diagram of the RF testing system 3004 according to another embodiment of the invention. The circuit configuration is similar to that in FIG. 3 except that the testing module board 300 is connected to the IC 100 and a low noise amplifier (LNA) 141 and switches SW1, SW2 are involved. The input of the demodulator 142 can be from the internal attenuator 130 or from the LNA 141 when the internal loopback path or the external loopback path is selected, respectively (details will be described later). When the internal loop-back path is selected (corresponding to FIG. 3), the switch SW1 is opened and the switch SW2 is closed, so that the outgoing RF signal SRF — OUT is looped back through the internal attenuator 130 between the output of the RF transmitter 120 and the input of the RF receiver 140, such that the signal performance of the RF transmitter 120 and RF receiver 140 can be evaluated without the use of the external testing module board 300. In the embodiment of FIG. 4, the external loopback configuration is selected. In response, the switch SW1 is closed and the switch SW2 is opened. In addition, the test controller 220 of the ATE 200 further directs the control signal SCTRL through the communication ports 242, 372 to control the testing module board 300, and the communication port 160 of the IC 100 acquires the incoming RF signal SRF — IN from the testing module board 300.
  • As illustrated in FIG. 4, the testing module board 300, which is external to the IC 100 and the ATE 200, may comprise an input port 370, a loopback port 374, a control port 372, an output port 376, an adjustable attenuator 320, a switch SW3, and a signal converter 330. In some implementations, a testing load board (not shown) is provided to hold the testing module board 300 and the IC 100 together. The testing load board may comprise an IC socket (not shown) to accept the IC 100 and a module slot (not shown) to hold the testing module board 300 in place during the test. The input port 370 accepts the response RF signal SRF — OUT from the IC 100. The control port 372 receives the control signal SCTRL from the test controller 220 of the ATE 200 to enable the testing module board 300 to work under the test mode. The control signal SCTRL controls the attenuator 320 and switching of the switch SW3. Specifically, the attenuator 320 receives controls via the control signal SCTRL to adjust the attenuation level to the RF signal SRF — OUT. The switch SW3 is selected by the control signal SCTRL to switch between the signal converter configuration (i.e. through the signal converter 330) and the external loopback configuration (i.e. through the loopback port 374). In the external loopback configuration, the switch SW3 is switched to the loopback port 374, the outgoing RF signal SRF — OUT from the RF transmitter 120 is attenuated by the attenuator 320 of the testing module board 300, and then output to the LNA 141 of the RF receiver 140 through the loopback port 374 to undergo RF impairments in a receiver path. In other words, the RF transmitter output signal SRF — OUT is looped back through the attenuator 320 as an input RF signal SRF — IN to the RF receiver 140 for a further test in the receiver path. In the RF receiver 140, the input RF signal SRF — IN is down-converted into the baseband, which is digitized into digital words regarded as the evaluation signal Sev1 sent to the test analyzer 210 of the ATE 200 for test analysis.
  • In the signal converter configuration, as shown in FIG. 6, the switch SW3 is switched to the signal converter 330, the outgoing RF signal SRF — OUT from the RF transmitter 120 is attenuated by the attenuator 320 of the testing module board 300, and then converted by the signal converter 330. In other words, the RF transmitter output signal SRF — OUT is not looped back to the IC 100, but processed by the testing module board 300 to generate the evaluation signal Sev2 sent to the test analyzer 210 of the ATE 200 through ports 374 and 244 for test analysis. FIGS. 5A-5B are schematic block diagrams of the signal converter 330 according to different embodiments of the invention. The signal converter 330 may be implemented in different circuits, thereby converting RF signals into analog/digital signals. For example, the signal converter 330 may comprise a power detector 331 and an ADC 332, as illustrated in FIG. 5A. Alternatively, the signal converter 330 may have similar components, such as an LNA 333, a demodulator 334, a filter 335, and an ADC 336, as those in the RF receiver 140, as illustrated in FIG. 5B. It should be noted that the invention is not limited to the aforementioned implementations of the signal converter 330. For those skilled in the art, it is appreciated that a reference RF receiver can be implemented in various circuits, and the details will not be described here.
  • It should be noted that the evaluation signals Sev1 and Sev2 may be in analog or digital form. In some implementations, the RF transmitter 120 and the RF receiver 140 do not have DAC/ADC circuits, and the test analyzer 210 may further comprise a digitizer (not shown) to convert the incoming analog evaluation signals into digital signals, thereby performing digital signal analysis of the RF test process.
  • In comparison to conventional RF test mechanisms, the present embodiment depicts an RF testing system where signal received/transmitted by the ATE 200 is only low-frequency signals. Only low-frequency command signal SCMD and evaluation signals Sev1 are exchanged between the IC 100 and the ATE 200. In addition, only low-frequency control signal SCTRL and evaluation signals Sev2 are exchanged between the testing module board 300 and the ATE 200. It should be noted that high-speed communication is only between the IC 100 and the testing module board 300. This leads to a reduction in the circuit complexity of the ATE 200, thereby decreasing design and manufacturing cost.
  • In view of the above, three configurations, which are the internal loopback configuration, the external loopback configuration, and the signal converter configuration, are provided to test the transmission performance of the IC 100. Upon receiving the evaluation signal Sev1 or Sev2, a test analysis of the transmission performance of the IC 100 can be performed by the test analyzer 210 of the ATE 200. For example, the transmitter path is usually tested at the system level test by the EVM and spectrum, nonlinearity tests such as IIP2 and IIP3, an image signal test, a carrier leakage test, and a transmission power test.
  • FIG. 7 is a detailed schematic block diagram of the RF testing system 3007 according to still yet another embodiment of the invention. The circuit configuration and connection is similar to those in the RF testing system 3006, except that in the RF testing system 3007, an external source generator 310 and a switch SW4 are placed at the testing module board 300 for further performing Rx test process. The switch SW4 is controlled by the control signal SCTRL to switch between the incoming RF signals from the RF transmitter 120 or from the external source generator 310. Specifically, referring to FIG. 7, upon receiving the control signal SCTRL indicating initiation of an RF Rx test process, the external source generator 310 may start to generate the single-tone, two-tone, and modulation signals required in the RF Rx test process. Meanwhile, the switch SW4 is switched to the external source generator 310 and the switch SW3 is switched to the communication port 374. In response, the generated signals from the external source generator 310 are fed into the attenuator 320, and then the attenuated RF signals are transmitted to the LNA 141 of the RF receiver 140 via the communication port 374, thereby evaluating the reception performance of the IC 100 in the receiver path at the test analyzer 210. Similarly, the RF receiver 140 may output the first evaluation signal Sev1 through the communication port 170 to the test analyzer 210 of the ATE 200 for test analysis. Upon receiving the evaluation signal Sev1, a test analysis of the reception performance of the IC 100 can be performed by the test analyzer 210 of the ATE 200. For example, the evaluated characteristics for the receiver path comprise a receiver gain test, an image signal test, a DC offset test, an NF test, and nonlinearity tests such as IIP2 and IIP3.
  • FIG. 8A˜8C are block diagrams of the external source generator 310 according to different embodiments of the invention. For example, the external source generator 310 may be a single-tone generator, a dual-tone generator, and/or a reference RF transmitter, as illustrated in FIG. 8A, 8B and 8C, respectively. The DAC in FIG. 8C may be coupled to a test pattern generator not shown, or receive test pattern from the TE 200. Implementations of the signal-tone generator, dual-tone generator, and the reference RF transmitter are well-known to those skilled in the art, and the details will not be described here.
  • FIG. 9 is a schematic block diagram of an RF testing system 3009 according to an embodiment of the invention. In the RF testing system 3009, the IC 500 may be a stand-alone RF IC without a signal generator. Accordingly, the function of the signal generator is moved to the ATE 200. In other words, the test controller 220 may control the signal generator 230 internally, thereby transmitting predefined RF test patterns to the RF transmitter 120. The circuit configuration and connection of the remaining components in the RF testing system 3009 are similar to those in the RF testing system 3003, and the details can be referred to in the aforementioned embodiments of FIG. 3. Similar to the embodiment of FIG. 3, the internal loopback configuration is also selected in the RF testing system 3009. Specifically, the RF transmitter 120 receives the external RF test pattern signals from the signal generator 230 of the ATE 200. Then, the outgoing RF signal generated by the RF transmitter 120 may be internally fed back to the RF receiver 140 through the internal attenuator 130. In addition, the evaluation signal Sev1 output by the RF receiver 140 can be fed into the test analyzer 210 for test analysis.
  • FIG. 10 is a schematic block diagram of an RF testing system 3010 according to another embodiment of the invention. In the RF testing system 3010, the IC 500 may be a stand-alone RF IC without a signal generator. Accordingly, the function of the signal generator is moved to the ATE 200. In other words, the test controller 220 may control the signal generator 230 internally, thereby transmitting predefined RF test patterns to the RF transmitter 120. The circuit configuration and connection of the remaining components in the RF testing system 3010 are similar to those in the RF testing system 3004, and the details can be referred to in the aforementioned embodiments of FIG. 4. Similar to the embodiment of FIG. 4, the external loopback configuration is also selected in the RF testing system 3010. Specifically, the RF transmitter 120 receives the external RF test pattern signals from the signal generator 230 of the ATE 200 and generates the outgoing RF test signal SRF — OUT. Then, the outgoing RF test signal SRF — OUT from the RF transmitter 120 is transmitted to the testing module board 300. The RF test signal SRF — OUT is attenuated by the attenuator 320 in the testing module board 300, and the attenuated RF test signal is further fed back into the RF receiver 140 through the communication port 160. Subsequently, the evaluation signal Sev1 output by the RF receiver 140 can be fed into the test analyzer 210 for test analysis.
  • FIG. 11 is a schematic block diagram of an RF testing system 3011 according to yet another embodiment of the invention. In the RF testing system 3011, the IC 500 may be a stand-alone RF IC without a signal generator. Accordingly, the function of the signal generator is moved to the ATE 200. In other words, the test controller 220 may control the signal generator 230 internally, thereby transmitting predefined RF test patterns to the RF transmitter 120. The circuit configuration and connection of the remaining components in the RF testing system 3011 are similar to those in the RF testing system 3006, and the details can be referred to in the aforementioned embodiments of FIG. 6. Similar to the embodiment of FIG. 6, the signal converter configuration is also selected in the RF testing system 3011. Specifically, the RF transmitter 120 receives the external RF test pattern signals from the signal generator 230 of the ATE 200. Then, the outgoing RF test signal SRF — OUT from the RF transmitter 120 is transmitted to the testing module board 300. The RF test signal SRF — OUT is attenuated by the attenuator 320 in the testing module board 300, and the attenuated RF test signal is further fed into the signal converter 330 for signal conversion. Subsequently, a second evaluation signal Sev2 is generated by the signal converter 330, and is further transmitted to the test analyzer 210 of the ATE 200 through the communication port 376.
  • FIG. 12 is a schematic block diagram of an RF testing system 3012 according to still yet another embodiment of the invention. In the RF testing system 3012, the IC 500 may be a stand-alone RF IC without a signal generator. The circuit configuration and connection of the components in the RF testing system 3012 are similar to those in the RF testing system 3007 except that the signal generator 230 has been moved to the ATE 200, and the details can be referred to in the aforementioned embodiments of FIG. 7. Similar to the RF testing system 3007, the testing module board 300 is controlled by the control signals SCTRL generated by the test controller 220 of the ATE 200. Specifically, upon receiving the control signal SCTRL indicating initiation of an RF Rx test process, the external source generator 310 may start to generate the single-tone, two-tone, and modulation signals required in the RF Rx test process. Meanwhile, the switch SW4 is switched to the external source generator 310 and the switch SW3 is switched to the communication port 374, so that the generated signals from the external source generator 310 may be fed into the attenuator 320, and then the attenuated RF signals can be transmitted to the LNA 141 of the RF receiver 140 via the communication port 374, thereby evaluating the reception performance of the IC 100 in the receiver path at the test analyzer 210. Similarly, the RF receiver 140 may output the first evaluation signal Sev1 through the communication port 170 to the test analyzer 210 of the ATE 200 for test analysis. Upon receiving the evaluation signal Sev1, a test analysis of the reception performance of the IC 100 can be performed by the test analyzer 210 of the ATE 200.
  • It should be noted that the evaluation signals Sev1 and Sev2 may be in analog or digital form. In some implementations, the above-mentioned RF transmitter and RF receiver do not have DAC/ADC circuits, and the test analyzer 210 may further comprise a digitizer (not shown) to convert the incoming analog evaluation signals into digital signals, thereby performing digital signal analysis of the RF test process.
  • FIG. 13 is a schematic block diagram of an RF testing system 3013 according to still another embodiment of the invention. In the RF testing system 3013, the IC 500 may be a SOC or a stand-alone RF IC having a test controller, and the circuit configuration and connection of the components in the RF testing system 3013 are similar to those in the RF testing system 3007 except that the test controller 220 has been moved to the IC 500. In the embodiment, the test analyzer 210 of the ATE 200 is capable of initiating an RF Tx or Rx test process by issuing a command signal (i.e. a digital signal) SCMD to the test controller 220 in the IC 500, and the test controller 220 in the IC 500 may send corresponding control signals SCTRL to the components in the IC 500 and the testing module board 300 in response to the command signal SCMD. It should be noted that different RF test configurations, which are previously described in the embodiments of FIGS. 3 to 12, can be used in the RF testing system 3013, and the details can be referred to in the embodiment of FIGS. 3 to 12. Specifically, the test analyzer 210 of the ATE 200 is still responsible for receiving the evaluation signal (i.e. a low-speed analog/digital signal) from either the RF receiver 140 or the signal convertor 330 for digital signal analysis. When the evaluation signal from either the RF receiver 140 or the signal convertor 330 is in an analog form, the digitizer 240 of the ATE 200 may convert the evaluation signal into digital signals before the test analysis is performed by the test analyzer 210.
  • FIG. 14 is a schematic block diagram of an RF testing system 3014 according to still another embodiment of the invention. In the RF testing system 3014, the IC 500 may be a SOC or a stand-alone RF IC, and the circuit configuration and connection of the components in the RF testing system 3014 are similar to those in the RF testing system 3007 except that the test controller 220 has been moved to the testing module board 300. In the embodiment, the ATE 200 is capable of initiating an RF Tx or Rx test process by issuing a command signal (i.e. a digital signal) SCMD to the test controller 220 in the testing module board 300, and the test controller 220 in the testing module board 300 may send the control signals SCTRL to the corresponding components in the IC 500 and the testing module board 300 in response to the command signal SCMD. It should be noted that different RF test configurations, which are previously described in the embodiments of FIGS. 3 to 12, can be used in the RF testing system 3013, and the details can be referred to in the embodiment of FIGS. 3 to 12. Specifically, the test analyzer 210 of the ATE 200 is still responsible for receiving the evaluation signal (i.e. a low-speed analog/digital signal) from either the RF receiver 140 or the signal convertor 330 for digital signal analysis. When the evaluation signal from either the RF receiver 140 or the signal convertor 330 is in analog form, the digitizer 240 of the ATE 200 may convert the evaluation signal into digital signals before the test analysis is performed by the test analyzer 210.
  • While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims (24)

What is claimed is:
1. An integrated circuit (IC), comprising
an RF transmitter configured to generate an RF signal in response to a command signal from test equipment;
an RF receiver configured to generate an evaluation signal according to the RF signal, and report the evaluation signal to the test equipment, so that the test equipment performs a test analysis on the evaluation signal to determine a test result,
wherein the test equipment is external to the IC.
2. The IC as claimed in claim 1, wherein the evaluation signal is indicative of an electrical characteristic of the RF signal.
3. The IC as claimed in claim 1, further comprising:
an internal attenuator configured to attenuate the RF signal from the RF transmitter; and
a signal generator configured to generate predefined RF test patterns in response to the command signal from the test equipment;
wherein the RF transmitter generates the RF signal in response to the generated RF test patterns, and the RF receiver converts the attenuated RF signal into the evaluation signal.
4. The IC as claimed in claim 1, wherein the command signal is used to initiate an RF test process.
5. The IC as claimed in claim 1, further comprising a test controller configured to control the RF transmitter and the RF receiver in response to the command signal from the test equipment.
6. The IC as claimed in claim 1, being a system-on-chip (SOC) or a stand-alone RF IC.
7. The IC as claimed in claim 1, wherein the RF transmitter receives test patterns from a signal generator external to the IC, and generates the RF signal in response to the received test patterns.
8. The IC as claimed in claim 1, wherein the RF transmitter transmits the RF signal to a module circuitry external to the IC, and the RF receiver receives an attenuated RF signal from the module circuitry and generates the evaluation signal accordingly.
9. An integrated circuit (IC), comprising:
an RF transmitter configured to generate an RF signal in response to a command signal from test equipment, and transmits the RF signal to a module circuitry for performing signal conversion by the module circuitry to generate an evaluation signal, wherein the evaluation signal is reported to the test equipment, so that the test equipment performs a test analysis on the evaluation signal to determine a test result,
wherein the test equipment and the module circuitry are both external to the IC.
10. The IC as claimed in claim 9, wherein the evaluation signal is indicative of an electrical characteristic of the RF signal.
11. The IC as claimed in claim 9, further comprising:
a signal generator configured to generate predefined RF test patterns in response to the command signal from the test equipment;
wherein the RF transmitter generates the RF signal according to the generated RF test patterns from the signal generator.
12. The IC as claimed in claim 9, wherein the IC further comprises a test controller configured to control the RF transmitter and the module circuitry in response to the command signal from the test equipment.
13. The IC as claimed in claim 9, wherein the RF transmitter is further controlled by a test controller of the module circuitry in response to the command signal from the test equipment.
14. The IC as claimed in claim 9, wherein the RF transmitter receives test patterns from a signal generator external to the IC, and generates the RF signal according to the test patterns from the signal generator.
15. The IC as claimed in claim 9, being a system-on-chip (SOC) or a stand-alone RF IC.
16. An integrated circuit (IC), comprising:
an RF receiver configured to receives an RF signal from a module circuitry in response to a command signal from test equipment, generate an evaluation signal according to the received RF signal, and report the evaluation signal to the test equipment, so that the test equipment performs a test analysis on the evaluation signal to determine a test result,
wherein the module circuitry and the test equipment are both external to the IC.
17. The IC as claimed in claim 16, wherein the evaluation signal is indicative of an electrical characteristic of the RF signal.
18. The RF testing system as claimed in claim 16, wherein the RF signal received by the RF receiver is an attenuated version of an RF test signal generated by a source generator of the module circuitry.
19. The IC as claimed in claim 16, wherein the RF receiver is controlled by a test controller of the module circuitry in response to the command signal from the test
20. The IC as claimed in claim 16, further comprising a test controller configured to control the module circuitry in response to the command signal from the test equipment.
21. The IC as claimed in claim 16, being a system-on-chip (SOC) or a stand-alone RF IC.
22. Test equipment communicating with an integrated circuit (IC), comprising:
a control port configured to send a command signal to the IC for initiating a RF test process;
an input port configured to receive an evaluation signal indicative of an electrical characteristic of an RF signal of the IC, wherein the evaluation signal is a baseband signal; and
a test analyzer configured to perform a test analysis on the evaluation signal to determine a test result.
23. A radio frequency (RF) testing system, comprising:
test equipment;
a module circuitry; and
an integrated circuit (IC) configured to communicate with the module circuitry by an RF signal in response to a command signal from the test equipment, generate an evaluation signal by the RF signal, and report the evaluation signal to the test equipment, so that the test equipment performs a test analysis on the evaluation signal to determine the test result,
wherein the module circuitry is external to the IC and the test equipment.
24. A radio frequency (RF) testing system, comprising:
test equipment;
a module circuitry; and
an integrated circuit (IC) configured to communicate with the module circuitry by an RF signal in response to a command signal from the test equipment,
wherein the module circuitry generates an evaluation signal according to the RF signal from the IC, and reports the evaluation signal to the test equipment, so that the test equipment performs a test analysis on the evaluation signal to determine the test result,
wherein the module circuitry is external to the IC and the test equipment.
US14/054,213 2011-06-13 2013-10-15 Rf testing system Abandoned US20140154997A1 (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
US14/054,213 US20140154997A1 (en) 2012-11-30 2013-10-15 Rf testing system
SG2013079553A SG2013079553A (en) 2012-11-30 2013-10-25 Rf testing system
CN201310628205.XA CN103852714B (en) 2012-11-30 2013-11-29 Integrated circuit, test equipment and radio frequency test system
US14/696,807 US10110325B2 (en) 2011-06-13 2015-04-27 RF testing system
US14/953,673 US9525500B2 (en) 2011-06-13 2015-11-30 Low-cost test/calibration system and calibrated device for low-cost test/calibration system
US15/071,536 US20160197684A1 (en) 2011-06-13 2016-03-16 Rf testing system with serdes device
US15/071,513 US10069578B2 (en) 2011-06-13 2016-03-16 RF testing system with parallelized processing
US15/074,978 US10320494B2 (en) 2011-06-13 2016-03-18 RF testing system using integrated circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201261731845P 2012-11-30 2012-11-30
US14/054,213 US20140154997A1 (en) 2012-11-30 2013-10-15 Rf testing system

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US13/480,969 Continuation-In-Part US9041421B2 (en) 2011-06-13 2012-05-25 IC, circuitry, and RF BIST system

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US14/696,807 Continuation US10110325B2 (en) 2011-06-13 2015-04-27 RF testing system
US14/696,807 Continuation-In-Part US10110325B2 (en) 2011-06-13 2015-04-27 RF testing system

Publications (1)

Publication Number Publication Date
US20140154997A1 true US20140154997A1 (en) 2014-06-05

Family

ID=50825902

Family Applications (2)

Application Number Title Priority Date Filing Date
US14/054,213 Abandoned US20140154997A1 (en) 2011-06-13 2013-10-15 Rf testing system
US14/696,807 Active US10110325B2 (en) 2011-06-13 2015-04-27 RF testing system

Family Applications After (1)

Application Number Title Priority Date Filing Date
US14/696,807 Active US10110325B2 (en) 2011-06-13 2015-04-27 RF testing system

Country Status (3)

Country Link
US (2) US20140154997A1 (en)
CN (1) CN103852714B (en)
SG (1) SG2013079553A (en)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150030103A1 (en) * 2013-05-20 2015-01-29 Analog Devices, Inc. Wideband quadrature error detection and correction
US9157957B1 (en) * 2014-06-13 2015-10-13 Realtek Semiconductor Corporation PLL status detection circuit and method thereof
CN105374202A (en) * 2015-12-14 2016-03-02 四川长虹电子部品有限公司 Radio frequency remote controller automatic test system
US9300444B2 (en) 2013-07-25 2016-03-29 Analog Devices, Inc. Wideband quadrature error correction
US9331797B2 (en) * 2014-09-23 2016-05-03 Infineon Technologies Ag RF receiver with testing capability
CN109039480A (en) * 2018-08-03 2018-12-18 广州蓝豹智能科技有限公司 A kind of WIFI test method, device, terminal and storage medium
US10361746B2 (en) * 2017-12-22 2019-07-23 Renesas Electronics Corporation Semiconductor device and semiconductor system
US10396912B1 (en) 2018-08-31 2019-08-27 Nxp B.V. Method and system for a subsampling based system integrated scope to enhance sample rate and resolution
US10419046B2 (en) * 2016-05-26 2019-09-17 Mediatek Singapore Pte. Ltd Quadrature transmitter, wireless communication unit, and method for spur suppression
US10416218B2 (en) * 2017-01-31 2019-09-17 Rohde & Schwarz Gmbh & Co. Kg Testing system for performing multipaction tests on a device under test as well as a method for testing a device under test
US20200044754A1 (en) * 2018-07-31 2020-02-06 Nxp B.V. Method and system to enhance accuracy and resolution of system integrated scope using calibration data
US20220078643A1 (en) * 2019-02-19 2022-03-10 Siemens Industry Software Inc. Radio equipment test device
CN114325318A (en) * 2021-12-27 2022-04-12 厦门科塔电子有限公司 FT (FT) test system and method for RF (radio frequency) chip
US11374803B2 (en) 2020-10-16 2022-06-28 Analog Devices, Inc. Quadrature error correction for radio transceivers

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9866336B2 (en) * 2015-06-17 2018-01-09 Google Llc Phased array antenna self-calibration
CN105897350A (en) * 2016-04-22 2016-08-24 北京联盛德微电子有限责任公司 Method and apparatus for testing transmitter chip
US10302694B2 (en) * 2016-12-27 2019-05-28 Texas Instruments Incorporated Interposer based test program evaluation
KR20200081063A (en) 2018-12-27 2020-07-07 삼성전자주식회사 Apparatus and method for testing radio frequency integrated circuit in wireless communication system
CN112491436B (en) * 2019-09-12 2022-04-26 瑞昱半导体股份有限公司 Radio frequency circuit
WO2022111804A1 (en) * 2020-11-25 2022-06-02 Advantest Corporation An automated test equipment comprising a device under test loopback and an automated test system with an automated test equipment comprising a device under test loopback
CN112649779B (en) * 2020-12-31 2024-01-23 江苏南高智能装备创新中心有限公司 Evaluation method and system based on electromagnetic compatibility test and network side server

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6407566B1 (en) * 2000-04-06 2002-06-18 Micron Technology, Inc. Test module for multi-chip module simulation testing of integrated circuit packages
US6543034B1 (en) * 2001-11-30 2003-04-01 Koninklijke Philips Electronics N.V. Multi-environment testing with a responder
US20090037132A1 (en) * 2007-07-31 2009-02-05 Xiaoqing Zhou Parallel Test System
US20090201039A1 (en) * 2005-08-12 2009-08-13 National Tsing Hua University Probing system for integrated circuit device
US7679391B2 (en) * 2008-07-11 2010-03-16 Advantest Corporation Test equipment and semiconductor device
US8358147B2 (en) * 2008-03-05 2013-01-22 Stmicroelectronics S.R.L. Testing integrated circuits
US20130021048A1 (en) * 2011-06-13 2013-01-24 Media Tek Inc. Ic, circuitry, and rf bist system
US8415955B2 (en) * 2008-08-08 2013-04-09 Industrial Control & Electrical Pty Ltd Electrical test device
US9000788B2 (en) * 2008-11-27 2015-04-07 Stmicroelectronics S.R.L. Method for performing an electrical testing of electronic devices

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6201829B1 (en) 1998-04-03 2001-03-13 Adaptec, Inc. Serial/parallel GHZ transceiver with pseudo-random built in self test pattern generator
JP2002162450A (en) 2000-11-22 2002-06-07 Mitsubishi Electric Corp Testing device of semiconductor integrated circuit, and test method of the semiconductor integrated circuit
US7184466B1 (en) 2002-09-12 2007-02-27 Xilinx, Inc. Radio frequency data conveyance system including configurable integrated circuits
US7251764B2 (en) 2003-05-27 2007-07-31 International Business Machines Corporation Serializer/deserializer circuit for jitter sensitivity characterization
US7203460B2 (en) * 2003-10-10 2007-04-10 Texas Instruments Incorporated Automated test of receiver sensitivity and receiver jitter tolerance of an integrated circuit
US20060234664A1 (en) 2005-01-13 2006-10-19 Mediatek Incorporation Calibration method for suppressing second order distortion
US7873884B2 (en) * 2005-04-15 2011-01-18 University Of Florida Research Foundation, Inc. Wireless embedded test signal generation
TWI264551B (en) * 2005-05-04 2006-10-21 Univ Tsinghua System for probing integrated circuit devices
US7724842B2 (en) * 2006-06-27 2010-05-25 Freescale Semiconductor, Inc. System and method for EVM self-test
JP2008151718A (en) * 2006-12-20 2008-07-03 Yokogawa Electric Corp Semiconductor testing apparatus
US7561979B2 (en) 2007-05-10 2009-07-14 Mediatek Inc. Device and method for calibrating data processing apparatus by tuning firmware trim value
WO2009022313A2 (en) * 2007-08-16 2009-02-19 Nxp B.V. Integrated circuit with rf module, electronic device having such an ic and method for testing such a module
CN101374317B (en) 2007-08-24 2011-08-24 中兴通讯股份有限公司 Veneer radio frequency test system for dual-mode single-standby mobile terminal
CN101453279B (en) 2007-11-29 2012-09-05 纮华电子科技（上海）有限公司 Parallel test system and method for sharing standard correction gauge
US7915909B2 (en) * 2007-12-18 2011-03-29 Sibeam, Inc. RF integrated circuit test methodology and system
WO2010049853A1 (en) 2008-10-31 2010-05-06 Nxp B.V. Integrated circuit and test method therefor
CN101753227B (en) 2008-11-28 2013-03-27 英华达（上海）科技有限公司 Radio frequency (RF) testing system and method for testing RF of multiple mobile communication devices
CN101464491B (en) * 2009-01-21 2012-04-18 北京创毅视讯科技有限公司 Test method and system
US8094705B2 (en) 2009-03-12 2012-01-10 Oracle America, Inc. Fast SERDES I/O characterization
TWI392888B (en) * 2009-04-16 2013-04-11 Nat Univ Tsing Hua Probing system for integrated circuit device
US8686736B2 (en) 2010-11-23 2014-04-01 Infineon Technologies Ag System and method for testing a radio frequency integrated circuit
US20130099835A1 (en) 2011-10-25 2013-04-25 You-Wen Chang Calibration apparatus for performing phase detection/edge distance detection upon signals and related calibration method thereof
CN102495353B (en) * 2011-12-27 2014-04-09 重庆西南集成电路设计有限责任公司 Radio frequency integrated circuit test system and control method thereof
US10110328B2 (en) 2012-04-13 2018-10-23 Altera Corporation Apparatus and methods for calibrating analog circuitry in an integrated circuit

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6407566B1 (en) * 2000-04-06 2002-06-18 Micron Technology, Inc. Test module for multi-chip module simulation testing of integrated circuit packages
US6543034B1 (en) * 2001-11-30 2003-04-01 Koninklijke Philips Electronics N.V. Multi-environment testing with a responder
US20090201039A1 (en) * 2005-08-12 2009-08-13 National Tsing Hua University Probing system for integrated circuit device
US20090037132A1 (en) * 2007-07-31 2009-02-05 Xiaoqing Zhou Parallel Test System
US8358147B2 (en) * 2008-03-05 2013-01-22 Stmicroelectronics S.R.L. Testing integrated circuits
US7679391B2 (en) * 2008-07-11 2010-03-16 Advantest Corporation Test equipment and semiconductor device
US8415955B2 (en) * 2008-08-08 2013-04-09 Industrial Control & Electrical Pty Ltd Electrical test device
US9000788B2 (en) * 2008-11-27 2015-04-07 Stmicroelectronics S.R.L. Method for performing an electrical testing of electronic devices
US20130021048A1 (en) * 2011-06-13 2013-01-24 Media Tek Inc. Ic, circuitry, and rf bist system

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11012201B2 (en) * 2013-05-20 2021-05-18 Analog Devices, Inc. Wideband quadrature error detection and correction
US20150030103A1 (en) * 2013-05-20 2015-01-29 Analog Devices, Inc. Wideband quadrature error detection and correction
US9300444B2 (en) 2013-07-25 2016-03-29 Analog Devices, Inc. Wideband quadrature error correction
US9157957B1 (en) * 2014-06-13 2015-10-13 Realtek Semiconductor Corporation PLL status detection circuit and method thereof
US9331797B2 (en) * 2014-09-23 2016-05-03 Infineon Technologies Ag RF receiver with testing capability
US9485036B2 (en) * 2014-09-23 2016-11-01 Infineon Technologies Ag RF receiver with testing capability
CN105374202A (en) * 2015-12-14 2016-03-02 四川长虹电子部品有限公司 Radio frequency remote controller automatic test system
US10419046B2 (en) * 2016-05-26 2019-09-17 Mediatek Singapore Pte. Ltd Quadrature transmitter, wireless communication unit, and method for spur suppression
US10416218B2 (en) * 2017-01-31 2019-09-17 Rohde & Schwarz Gmbh & Co. Kg Testing system for performing multipaction tests on a device under test as well as a method for testing a device under test
US10361746B2 (en) * 2017-12-22 2019-07-23 Renesas Electronics Corporation Semiconductor device and semiconductor system
US10735115B2 (en) * 2018-07-31 2020-08-04 Nxp B.V. Method and system to enhance accuracy and resolution of system integrated scope using calibration data
US20200044754A1 (en) * 2018-07-31 2020-02-06 Nxp B.V. Method and system to enhance accuracy and resolution of system integrated scope using calibration data
CN109039480A (en) * 2018-08-03 2018-12-18 广州蓝豹智能科技有限公司 A kind of WIFI test method, device, terminal and storage medium
US10396912B1 (en) 2018-08-31 2019-08-27 Nxp B.V. Method and system for a subsampling based system integrated scope to enhance sample rate and resolution
US20220078643A1 (en) * 2019-02-19 2022-03-10 Siemens Industry Software Inc. Radio equipment test device
US11659418B2 (en) * 2019-02-19 2023-05-23 Siemens Industry Software Inc. Radio equipment test device
US11374803B2 (en) 2020-10-16 2022-06-28 Analog Devices, Inc. Quadrature error correction for radio transceivers
CN114325318A (en) * 2021-12-27 2022-04-12 厦门科塔电子有限公司 FT (FT) test system and method for RF (radio frequency) chip

Also Published As

Publication number Publication date
SG2013079553A (en) 2014-06-27
CN103852714B (en) 2016-11-23
US10110325B2 (en) 2018-10-23
CN103852714A (en) 2014-06-11
US20150229415A1 (en) 2015-08-13

Similar Documents

Publication Publication Date Title
US10110325B2 (en) RF testing system
US10320494B2 (en) RF testing system using integrated circuit
US9041421B2 (en) IC, circuitry, and RF BIST system
US20160197684A1 (en) Rf testing system with serdes device
US10069578B2 (en) RF testing system with parallelized processing
US7564893B2 (en) Test system and method for parallel modulation error measurement of transceivers
US7254755B2 (en) On-chip receiver sensitivity test mechanism
US8576947B2 (en) System and method for simultaneous MIMO signal testing with single vector signal analyzer
US20120294347A1 (en) Communication unit with analog test unit
Heutmaker et al. An architecture for self-test of a wireless communication system using sampled IQ modulation and boundary scan
US8711904B2 (en) Calibration method for non-ideal transceivers
US20160174094A1 (en) Radio frequency transceiver loopback testing
Erdogan et al. Detailed characterization of transceiver parameters through loop-back-based BiST
Mannath et al. Structural approach for built-in tests in RF devices
Ozev et al. Testability implications in low-cost integrated radio transceivers: a Bluetooth case study
US8942655B2 (en) Integrated circuit, wireless communication unit and method for determining quadrature imbalance
Zhang et al. Low cost multisite testing of quadruple band GSM transceivers
Peng et al. A novel RF self test for a combo SoC on digital ATE with multi-site applications
TWI707553B (en) Radio-frequency circuit
US6933868B1 (en) Testing of mixed signal integrated circuits generating analog signals from digital data elements
Dabrowski et al. Offset loopback test for IC RF transceivers
Helaly et al. A new category of software-defined instrumentation for wireless test
Ichiyama et al. A functional test of 2-GHz/4-GHz RF digital communication device using digital tester
TWI745982B (en) Test system and method thereof
TWI816333B (en) Antenna array test equipment

Legal Events

Date Code Title Description
AS Assignment

Owner name: MEDIATEK INC., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHEN, YEN-LIANG;PENG, CHUN-HSIEN;SHIH, YING-CHOU;AND OTHERS;SIGNING DATES FROM 20131213 TO 20140116;REEL/FRAME:032027/0914

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION