US20140191308A1 - Self-aligned double patterning for memory and other microelectronic devices - Google Patents
Self-aligned double patterning for memory and other microelectronic devices Download PDFInfo
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- 238000004377 microelectronic Methods 0.000 title claims abstract description 79
- 230000015654 memory Effects 0.000 title claims description 57
- 238000000059 patterning Methods 0.000 title description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims description 36
- 239000000463 material Substances 0.000 claims description 19
- 125000006850 spacer group Chemical group 0.000 claims description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 230000005641 tunneling Effects 0.000 claims description 5
- 238000000034 method Methods 0.000 description 68
- 238000012545 processing Methods 0.000 description 30
- 239000000758 substrate Substances 0.000 description 30
- 239000010408 film Substances 0.000 description 24
- 238000005530 etching Methods 0.000 description 20
- 238000004519 manufacturing process Methods 0.000 description 14
- 238000010586 diagram Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000000427 thin-film deposition Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 206010010144 Completed suicide Diseases 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- VYQRBKCKQCRYEE-UHFFFAOYSA-N ctk1a7239 Chemical compound C12=CC=CC=C2N2CC=CC3=NC=CC1=C32 VYQRBKCKQCRYEE-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005108 dry cleaning Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
Definitions
- the invention is related to a method of manufacturing a microelectronic device, and in particular but not exclusively, to a method of patterning features of such a device.
- a memory such as a random access memory (RAM) or read only memory (ROM) often includes arrayed memory cells.
- each of the memory cells is coupled to at least one bit line and an overlapping word line, and each of the memory cells include a memory element that is configured to store a logic state.
- a controller reads from and/or writes to an individual memory element by receiving and transmitting signals over the bit and word lines of the memory.
- memory cells are small and closely spaced, with some memory cells having feature sizes and inter-cell spacing on the orders of 50 nm or less. As memories become smaller, however, it becomes increasingly difficult to manufacture smaller and more closely spaced memory cells.
- FIG. 1 is a block diagram of an embodiment of a memory controller and an arrayed memory
- FIG. 2 is a partial top plan view of an embodiment of a patterned microelectronic lines that may be employed in the arrayed memory of FIG. 1 ;
- FIG. 3 is a cross-sectional side view of an embodiment of a patterned microelectronic layer that may be employed a an embodiment of the patterned microelectronic lines of FIG. 2 ;
- FIG. 4 is a cross-sectional side view of an embodiment of patterned recesses that may be employed in another embodiment of the patterned microelectronic lines of FIG. 2 ;
- FIG. 5 is a cross-sectional side view of an embodiment of a patterned layered stack that may be employed in yet other embodiment of the patterned microelectronic lines of FIG. 2 ;
- FIG. 6 is a flow diagram generally showing an embodiment of a process for transferring a pattern to one or more microelectronic layers
- FIGS. 7-10 illustrate embodiments of stages corresponding to the process of FIG. 5 ;
- FIG. 11 is a flow diagram generally showing an embodiment of a process for self-aligned patterning one or more microelectronic layers
- FIGS. 12-16 illustrate embodiments of stages corresponding to the process of FIG. 10 ;
- FIG. 17 is a flow diagram generally showing another embodiment of a process for self-aligned patterning one or more microelectronic layers.
- FIGS. 18-20 illustrate embodiments of stages corresponding to the process of FIG. 16 .
- the term “or” is an inclusive “or” operator, and is equivalent to the term “and/or,” unless the context clearly dictates otherwise.
- the term “based on” is not exclusive and allows for being based on additional factors not described, unless the context clearly dictates otherwise, in addition, throughout the specification, the meaning of “a,” “an,” and “the” include plural references. The meaning of “in” includes “in” and “on.”
- microelectronic layer includes a layer of microelectronic material employed in one or more microelectronic devices or systems thereof.
- microelectronic materials can include group IV semiconductor materials or compound semiconductor materials.
- Group IV materials include, for example, germanium, or the like.
- Compound semiconductor materials include, for example, Gallium Arsenide, Indium Phosphide, or the like.
- Microelectronic materials can also include polysilicon (or amporphous silicon), silicon oxide, silicon nitride, suicide, ceramics (e.g., silicon nitride or silicon carbide), and/or metals or metal alloys (e.g., aluminum, copper, aluminum-copper, gold, titanium, tungsten, or cobalt).
- substrate may include a structure of one or more microelectronic materials in which microelectronic devices and other components of a memory may be formed in and/or upon. Further, although primarily discussed herein in the context of silicon-based microelectronic layers and substrates, other embodiments of microelectronic layers and substrates may be employed.
- the term “feature” is used to refer to a structure that is formed in a substrate, one or more microelectronic layers, and/or one or more other layers, including photoresist layers or other mask layers.
- the term “pitch” refers to a linear length of a feature (or width) combined with a linear length of a spacing between the feature and another feature. Also, in many embodiments, a pitch is associated with a portion of pattern that is repeated, such as a repeated line and spacing or the like.
- the terms “define”, “defined”, or “defining” refer to a process associated with patterning, etching, and/or otherwise forming a size, shape, and/or a portion of a shape associated with a feature, opening, recess, or other aspect of a substrate, microelectronic layer, and/or other layer.
- the invention is related to a method for transferring a pattern to one or more microelectronic layers, such as layers in a memory or other microelectronic devices.
- a first mask layer, having a patterned feature, and a second mask layer, having another patterned feature, are formed.
- the first mask layer and the second mask layer are at least partially covered with a film, and openings are formed in the film by removing the other patterned feature of the second mask layer.
- a pattern of a microelectronic layer is then defined by patterning the patterned feature of the first mask layer through the openings in the film.
- the patterned feature of the first mask layer is defined by forming spacers that have a height corresponding to a combined thickness of the second mask layer and a photoresist layer
- the other patterned feature of the second mask layer is defined by removing a portion of the other patterned feature of the second mask layer via an anisotropic etching process.
- the invention may be employed to reduce a pitch associated with features in one or more microelectronic devices.
- the invention may be employed to reduce the pitch associated with an array of memory cells in a flash-based memory.
- the invention may be employed to enhance a pitch associated with a photoresist mask layer.
- the pitch can be reduced without requiring a change in lithographic technology.
- a next generation resolution can be realized with a current generation technology and potentially without requiring an expensive investment in a next generation technology, including next generation lithographic development tools and/or chemistries.
- pitch can be reduced while still benefiting from the patterning techniques of current generation technology.
- the patterning techniques of next generation technology typically provide less robust photoresist mask layers due to smaller critical dimension sizes (e.g., the etch rate selectively is less and/or the mask layer is required to be thinner).
- FIG. 1 shows a memory environment in which embodiments of the invention may be employed. Not all the components illustrated in the figures may be required to practice the invention, and variations in the arrangement and type of the components may be made without departing from the spirit or scope of the invention.
- memory 100 includes arrayed memory 110 and memory controller 108 .
- Arrayed memory 110 is arranged to receive arid/or transmit signals over signal/bus lines 102 .
- Arrayed memory 110 includes line/sector control circuit 112 and memory sectors 114 (identified individually as sectors 1-i).
- Memory sectors 114 can include, for example, 256 , 512 , 1024 , or more sectors having memory cells that can be individually or collectively accessed via line/sector control circuit 112 . In other examples, the number and/or arrangement of memory sectors can be different.
- sectors 114 can be referred to more generally as memory blocks, and line/sector control circuit 112 can be configured to have a configuration that is different than a bit line, word line, source gate line, and/or sector topology.
- Memory controller 108 is arranged to receive and transmit data from an upstream system controller (not shown) via addressing signal/bus line 104 and program data signal/bus line 106 .
- Memory controller 108 can include any of a variety of decoder circuits, voltage generator circuits, and/or controller circuits.
- memory controller 108 may be located on the same chip as arrayed memory 110 .
- memory controller 108 may be located on a different chip, or portions of memory controller 108 may be located on another chip or off chip.
- other implementations of memory controller 108 are possible.
- memory controller 108 can include a programmable microcontroller.
- memory 100 is a flash based memory including flash-based memory cells, such as flash-based NAND cells, NOR cells, or hybrids of the two.
- memory 100 may be another type of volatile or non-volatile memory, including, for example, a static random access memory (SRAM) or a dynamic random access memory (DRAM).
- SRAM static random access memory
- DRAM dynamic random access memory
- FIG. 2 shows a partial top plan view of an embodiment of patterned microelectronic lines that may be formed on or within a portion of substrate 220 .
- substrate 220 may form a portion of a semiconductor chip that is employed in memory 100 of FIG. 1 .
- Microelectronic lines 222 are features that may be located on and/or within substrate 220 and may be adjacent to one or more other features 224 .
- microelectronic lines 222 are located on substrate 220 ; for example, microelectronic lines 222 may be formed by a deposition process.
- microelectronic lines 222 may include any of a variety be formed within substrate; for example, microelectronic lines 222 may be etched into substrate 220 .
- individual microelectronic lines 222 have an associated pitch P 2 .
- individual features 224 have an associated pitch P 2 .
- pitch P 2 is in a range of about 20 to about 50 nm. In other embodiments, however, pitch P 2 may be less than 20 nm or greater than 50 nm. Also, while shown in FIG. 2 as having the same value of pitch, embodiments of microelectronic lines 222 and features 224 can have different pitch values.
- microelectronic lines 222 may be employed in an embodiment of memory sector 114 of FIG. 1 .
- microelectronic lines 222 may be polysilicon word lines and/or polysilicon gate source lines that are coupled to the gates of individual memory cells (not shown in FIG. 2 ) located within substrate 220 .
- microelectronic lines 222 can be arranged in a NAND configuration, a NOR configuration, a hybrid of a NAND and NOR configuration, or a different configuration.
- pitch P 2 is larger in NOR topologies than it is in NAND topologies.
- FIG. 3 shows a cross-sectional side view of an embodiment of microelectronic layer 332 and substrate 320 .
- Microelectronic layer 322 and substrate 320 may be employed in an embodiment of an individual one of microelectronic lines 222 and substrate 220 of FIG. 2 , respectively.
- microelectronic layer 332 includes patterned openings 326 having pitch P 3 .
- pitch P 3 is an embodiment of pitch P 2 of FIG. 2 .
- FIG. 4 shows a cross-sectional side view of an embodiment of recesses 422 in substrate 420 .
- recesses 422 and substrate 420 may be employed in an embodiment of an individual one of microelectronic lines 222 and substrate 220 of FIG. 2 , respectively.
- recesses 422 have an associated pitch P 4 .
- pitch P 4 is an embodiment of pitch P 2 of FIG. 2 .
- FIG. 5 shows a cross-sectional side View of an embodiment of layered stack 522 and substrate 520 .
- layered stack 522 and substrate 520 may be employed in an embodiment of an individual one of microelectronic lines 222 and substrate 220 of FIG. 2 , respectively.
- dielectric spacers 528 having pitch P 5 , separate portions of layered stack 522 .
- pitch P 5 is an embodiment of pitch P 2 of FIG. 2 .
- dielectric spacer 528 are an embodiment of features 224 of FIG. 2 .
- layered stack 522 and dielectric spacers 528 define locations of individual memory cells 530 .
- Each of memory cells 530 includes a charge trapping component 532 that is located in layered stack 522 .
- each of memory cells 530 can be coupled to a portion of polysilicon line 534 , which is also located in layered stack 522 .
- Individual memory cells 530 are configured to share source/drain regions 538 formed in substrate 520 .
- Charge trapping component 532 includes tunneling layer 540 , charge trapping layer 541 , and dielectric layer 542 .
- tunneling layer 540 provides a tunneling barrier.
- Charge trapping layer 541 may be a non-conductive layer that is configured to store a tunneled charge.
- Dielectric layer 542 electrically isolates charge trapping layer 541 from polysilicon line 534 .
- polysilicon line 534 and source/drain regions 538 are configured to provide electrical potentials for trapping charge within a charge trapping component.
- One or more portions of charge trapping component are “programmed” when trapping charge and “unprogrammed” when not trapping charge.
- embodiments of the invention can be employed to manufacture other types of devices, including other types of electrical devices, such as a capacitor, transistor, or the like; mechanical devices; as well as other types of electro-mechanical devices.
- FIG. 6 is a flow diagram generally showing one embodiment of process 650 for transferring a self-aligned pattern to one or more microelectronic layers.
- process 650 is employed to form microelectronic lines 222 of FIG. 2 .
- Process 650 begins at block 651 , where a first mask layer is formed, and a second mask layer is formed on the first mask layer.
- the first mask layer includes a first patterned feature and the second mask layer includes a second patterned feature that is located on the first patterned feature of the first mask layer.
- the first patterned feature of the first mask layer is defined by spacers having a height corresponding to a combined thickness of the second mask layer and the photoresist mask layer (described further with reference to FIGS. 10-16 ).
- the second patterned feature of the second mask layer is defined by removing a portion of the second patterned feature of the second mask layer that is covered by a photoresist mask layer (described further with reference to FIGS. 17-19 ).
- the film is a microelectronic layer that is deposited in a thin film deposition process.
- Thin film deposition processes can include, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (REND), atomic layer deposition (ALD), or the like.
- the film includes a high density plasma (HDP) oxide.
- the isolation dielectrics include a tetra-ethyl-ortho-silicate (TEOS) oxide or an ozone based TEOS.
- a chemical mechanical polishing (CMP) process can planarize a conformal film such that a surface of the second patterned second of the second mask layer is exposed through the conformal film.
- CMP chemical mechanical polishing
- a CMP process can be employed to recess the conformal film below such a surface.
- a non-conformal film includes a photoresist (PR) film, such as a spin-on or deposited photoresist film or other film.
- PR photoresist
- a non-conformal film can include spin-on-carbon or spin-on-silicon to enhance wet etch resistance.
- a conformal or non-conformal film includes another type of polymeric material.
- an etching process may be employed to remove the second patterned feature.
- the etching processes can include, for example, one or more wet and/or dry etch techniques, including chemical and/or physical etching techniques, employing, for example, isotropic or anisotropic wet and/or dry etch chemistries, reactive ion etches, and/or plasma assisted etches.
- the type of chemistry employed in the etching process may be based on the material of the first and second mask layers. For example, hydrofluoric chemistries can be employed to selectively etch silicon oxide over silicon, polysilicon, silicon nitride, or the like.
- surfaces of the second pattern feature may be exposed Through the film prior to removal.
- a CMP process, or the like may be employed to recess the film.
- an etch back process can be used to thin the film.
- a blanket etch can thin a flint to expose a surface portion of the second patterned feature.
- a bottom anti-reflective coating (BARC) etch back process can be employed to thin, a conformal photoresist mask.
- a pattern is defined in a microelectronic layer by patterning the patterned feature of the first mask layer through the openings in the film.
- An etching process may be employed to define a combined pattern that includes the first patterned feature of the first mask layer and the second patterned feature of the second mask layer transferred into the first patterned feature.
- the same etching process or a different etching process may be employed to transfer the combined pattern into a microelectronic layer.
- the film may be removed, and an etching process may form the combined pattern in a microelectronic layer positioned beneath the first mask layer.
- processing may continue to form devices or other features.
- processing may continue to form a memory, such as memory 100 of FIG. 1 , or a portion of the memory.
- a memory such as memory 100 of FIG. 1
- such devices or features may be cleaved to form individual dies or chips that may be incorporated into a packaged device or other device.
- a person skilled in the art would appreciate the various manners in which such processing and packaging may be carried out.
- simulation and/or software tools may be employed to create a specific implementation of the first patterned feature of the first mask layer and the second patterned feature of the second mask layer.
- the feature sizes of the first mask layer and the second mask layer can be designed to create a specific pitch or spacing for a combined pattern.
- High-level software code such as a register transfer logic (RTL) file, may be created and then compiled to form a netlist file.
- the netlist file may be used in turn to optimize the combined pattern.
- a physical design process may be employed in conjunction with the netlist file and a component library to create a layout file.
- the layout file may be used to create a mask file that may be provided to a device foundry to equip the foundry for manufacturing a one or more microelectronic layers containing the combined pattern.
- any of a variety of intermediary processes may be employed between individual blocks of process 650 , such as cleaning, metrology, inspection, and/or other processes.
- a variety of wet cleaning and/or dry cleaning processes may be used to prepare a substrate or remove a mask layer.
- FIGS. 7-10 illustrate various embodiments of stages corresponding to the manufacture of a patterned microelectronic line or feature.
- the various stages represent stages of manufacturing microelectronic lines 222 of FIG. 2 .
- FIG. 7 is an embodiment showing a cross-sectional side view of substrate 720 ; microelectronic layer 760 ; first mask layer 761 having, at least, first patterned features 761 a and 761 b; and second mask layer 762 having, at least, second patterned features 762 a and 762 b .
- first mask layer 761 includes a silicon nitride material or a silicon-oxy-nitride material.
- Second mask layer 762 may include a polysilicon material.
- one or more of first mask layer 761 and second mask layer 762 includes a combination of different microelectronic materials,
- the patterned features of second mask layer 762 have pitch P 7 that is at least twice as large as pitch P 2 of FIG. 2 .
- the patterned features of first mask layer 761 are separated by spacing distances S 7 to define a portion of pitch P 2 of FIG. 2 .
- the patterned features of first mask layer 761 have pitch P 7 .
- the cross-sectional side view of FIG. 7 corresponds to processing associated with block 651 of process 650 of FIG. 6 .
- FIG. 8 is an embodiment showing a cross-sectional side view of film 863 covering portions of first mask layer 761 and second mask layer 762 . As shown, portions of patterned features 762 a and 762 b project beyond film 863 , exposing surface portions 864 a and 864 b of patterned features 762 a and 762 b , respectively.
- the cross-sectional side view of FIG. 8 corresponds to processing associated with block 652 of process 650 of FIG. 6 .
- FIG. 9 is an embodiment showing a cross-sectional side view of openings 965 a and 965 h defined in film 863 after removing patterned features 762 a and 762 b . Openings 965 a and 965 b and first patterned features 761 a and 761 b define pitch P 9 .
- pitch P 9 is an embodiment of Pitch P 2 of FIG. 2 .
- the cross-sectional side view of FIG. 9 corresponds to processing associated with block 653 of process 650 of FIG. 6 .
- FIG. 10 is an embodiment-showing a cross-sectional side view of patterned features 1066 a - d defined in first mask layer 761 and having pitch P 9 of FIG. 9 .
- the cross-sectional side view of FIG. 10 corresponds to processing associated with block 654 of process 650 of FIG. 6 .
- microelectronic layer 760 of FIG. 10 may be patterned to form microelectronic lines 222 of FIG. 2 .
- first mask layer 761 is an embodiment of an individual one of microelectronic lines 222 .
- FIG. 11 is a flow diagram generally showing an embodiment of a process for self-aligned patterning of one or more microelectronic layers.
- Process 1170 may be an embodiment of one or more manufacturing steps that are carried out at block. 651 of process 650 of FIG. 6 .
- Process 1170 begins at block 1171 , where a patterned photoresist mask is formed on a hard mask.
- a patterned photoresist mask can be formed on second mask layer 762 of FIG. 7 (prior to forming features 762 a and 762 b ).
- the patterning processes can include any of a wide variety of combinations of photolithographic and/or etching processes.
- Photolithographic process can include, for example, single- or multi-step photolithographic techniques employing one or more photoresist masks, such as a photolithographic mask including UV or deep UV light sensitive materials and optionally BARC layers.
- the patterned features of the photoresist mask may be thinned by an oxygen plasma.
- such a thinning process may reduce the feature size of the patterned photoresist mask by an order of 1.25, 1.5, 1.75, 2, or more.
- a hard mask or the like may be used in lieu of or in addition to a photoresist mask layer.
- Processing continues to block 1172 , where combined features are formed in the photoresist mask and the hard mask such that the combined features each include a first section of the photoresist mask and a second section of the hard mask.
- one or more etching processes may be employed to form the combined features.
- spacers are formed adjacent to the combined features such that each spacer is adjacent to a first section of the combined feature and a second section of the combined feature.
- the spacers are formed by depositing a polymeric material and etching back the polymeric material.
- the spacers may be formed using a MotifTM post-lithography pattern enhancement system (available from LAM Research Corp., Freemont, Calif.).
- a MotifTM system can also be employed for resist shrinking carried out at block 1150 .
- a first pattern is transferred to a microelectronic layer using the combined features and the spacers formed at block 1173 as an etch mask.
- an etching process is used to define the first pattern in the microelectronic layer.
- the first pattern is formed in first mask layer 761 of FIG. 7 .
- the first pattern is formed in a different microelectronic layer.
- processing may continue. For example, in one embodiment, processing may continue to block 652 of FIG. 6 .
- FIGS. 12-16 illustrate various embodiments of stages corresponding to the manufacture of a patterned microelectronic line or feature.
- the various stages represent stages of manufacturing microelectronic lines 222 of FIG. 2 .
- FIG. 12 is an embodiment showing a cross-sectional side view of substrate 1220 , microelectronic layer 1260 , first mask layer 1261 , second mask layer 1262 , and photoresist mask layer 1280 having openings 1281 with associated pitch P 12 .
- portions of photoresist (drawn in dashed lines) mask layer can be removed by a photoresist thinning process.
- substrate 1220 , microelectronic layer 1260 , first mask layer 1261 , and second mask layer 1262 of FIG. 12 are an embodiment of substrate 720 , microelectronic layer 760 , first mask layer 761 , and second mask layer 762 of FIG. 7 , respectively.
- pitch Pp is an embodiment of pitch P 7 of FIG. 7 .
- the cross-sectional side view of FIG. 12 corresponds to processing associated with block 1171 of process 1170 of FIG. 11 .
- FIG. 13 is an embodiment showing a cross-sectional ide view of combined Features 1383 a and 1383 b each having a corresponding minimum width w 13 and including a section of photoresist mask 1280 and a section of second mask layer 1262 .
- Combined feature 1383 a includes first section 1384 a of second mask layer 1262 and second section 1385 a of photoresist mask layer 1280 .
- Combined feature 1383 b includes first section 1384 b of second mask layer 1262 and second section 1385 b of photoresist mask layer 1380 .
- the cross-sectional side view of FIG. 13 corresponds to processing associated with block 1172 of process 1170 of FIG. 11 .
- width w 13 has a value that is in range of about 10 to 30 nm. In other embodiments, however, width w 13 has a value that is less than or greater than the values in this range.
- FIG. 14 is an embodiment showing a cross-sectional side view of spacers 1486 a - c .
- Each of spacers 1486 a - c has a corresponding height h 14 and a minimum width w 14 .
- Height h 14 corresponds to a thickness of second mask layer 1262 and a thickness of photoresist mask layer 1280 .
- pitch P 14 is an embodiment of pitch P 2 of FIG. 2 .
- minimum width w 14 of FIG. 14 and minimum width w 13 of FIG. 13 define pitch P 14 .
- minimum width w 14 and spacing S 14 of spacers 1286 a - d define pitch P 14 .
- width w 14 and spacing S 14 corresponds to processing associated with block 1173 of process 1170 of FIG. 11 .
- width w 14 and spacing S 14 have values that are in range of about 10 to 30 nm. In other embodiments, however, width w 14 and spacing S14 have values that are less than and/or greater than the values in this range.
- height h14 has a value that is in a range of about 100 to 250 nm. In other embodiments, however, height h 14 has a value that is less than or greater than the values in this range.
- FIG. 15 is an embodiment showing a cross-section side view of features 1561 a and 1561 b of mask layer 1261 .
- Patterned feature 1561 a is defined by first section 1384 a and spacers 1486 a and 1486 b .
- Patterned feature 1561 b is defined by first section 1384 b and spacer 1486 c , in one embodiment, features 1561 a and 1561 b are an embodiment of patterned features 761 a and 76 tb of FIG. 7 , respectively.
- the cross-sectional side view of FIG. 15 corresponds to processing associated with block 1174 of process 1170 of FIG. 11 .
- FIG. 16 is an alternative embodiment showing a cross-sectional side view of mask layer 1688 .
- Mask layer 1688 is similar to first mask layer 1261 and second mask layer 1262 with the exception that mask layer 1688 is formed from a single microelectronic layer.
- mask layer 1688 may be formed by employing similar processing as that carried out with respect to first mask layer 1261 and second mask layer 1262 of FIGS. 12-15 ; however, a timed etch may be used to define height h 16 associated with mask layer 1688 (rather than using second mask layer 1262 of FIG. 12 as an etch stop layer).
- mask layer 1688 is polysilicon.
- mask layer 1688 is a different microelectronic material.
- the cross-sectional side view of FIG. 15 corresponds to processing associated with block 1174 of process 1170 of FIG. 11 .
- FIG. 17 is a processing flow diagram generally showing an embodiment of a process for self-aligned patterning of one or more microelectronic layers.
- Process 1790 may be an embodiment of one or more manufacturing steps that are carried' out at block 651 of process 650 of FIG. 6 .
- Process 1790 begins at block 1191 , where a second mask layer is formed on a first mask layer.
- a patterned photoresist mask is also fanned on the second mask layer.
- a patterned photoresist mask can be formed on second mask layer 762 of FIG. 7 (prior to fanning features 762 a and 762 b ).
- a hard mask, or the like may be used in lieu of or in addition to a photoresist ask layer.
- Processing continues to block 1792 , where a pattern is transferred into the first mask layer by etching the first mask layer through the second mask layer.
- the pattern may also be concurrently transferred into the second mask layer through a patterned photoresist mask.
- processing continues to block 1793 , where another pattern in the second mask layer by, removing a portion of the pattern associated with the second mask layer:
- an anisotropic etching process may be employed to remove a portion of the pattern of the second mask layer.
- the portion of the pattern may be removed by etching back second mask layer.
- the portion of the pattern of the second mask layer that is removed is located between a photoresist mask layer and the first mask layer.
- a hydrofluoric-based wet etch chemistry may be employed to remove the portion of the pattern of the second mask layer.
- processing may continue. For example, in one embodiment, processing may continue to block 652 of FIG. 6 .
- FIGS. 18-20 illustrate various embodiments of stages corresponding to the manufacture of a patterned microelectronic line or feature.
- the various stages represent stages of manufacturing microelectronic lines 222 of FIG. 2 .
- FIG. 18 is an embodiment showing a cross-sectional side view of substrate 1820 , microelectronic layer 1860 , first mask layer 1861 , second mask layer 1862 , and photoresist mask layer 1894 .
- First mask layer 1861 includes features 1861 a and 1861 b
- second mask layer 1862 includes features 1862 a and 1862 b .
- Photoresist mask layer 1894 includes openings 1895 defining the features of the first and second mask layers. Openings 1895 also define pitch P 18 .
- pitch P 18 is an embodiment of pitch P 7 of FIG. 7 .
- the cross-sectional side view of FIG. 18 corresponds to processing associated with blocks 1791 and 1792 of process 1970 of FIG. 17 .
- FIG. 19 is an embodiment showing a cross-sectional side view of portions of second mask layer 1862 removed. Undercut width w 19 , between photoresist mask layer 1894 and first mask layer 1861 , can be tailored such that pitch P 19 , is defined by width w 19 and the patterned portions of first mask layer 1861 . In one embodiment, pitch P 19 is an embodiment of pitch P 2 of FIG. 2 . In one embodiment, the cross-sectional side view of FIG. 19 corresponds to processing associated with block 1793 of process 1790 of FIG. 17 . In one embodiment, width w 19 has a value that is in range of about 10 to 30 nm. In other embodiments, however, width w 19 has a value that is less than or greater than the values in this range.
- FIG. 20 is an alternative embodiment showing a cross-sectional side view of first mask layer 2061 and portions of second mask layer 2062 removed.
- First mask layer 2061 and second mask layer 2062 may be similar to first mask layer 1861 and second mask layer 1862 of FIG. 19 , respectively, with the exception that the top-side surface of second mask layer 2062 was not covered during an anisotropic etching process.
- a photoresist layer was not covering second mask layer 2062 while a pattern was being transferred into first mask layer 1201 .
- second mask layer 2062 has a reduced thickness ⁇ t due to the anisotropic etching process.
- ⁇ t has a value that corresponds to width w 19 of FIG.
- pitch P20 is defined by ⁇ t and the patterned portions of first mask layer 2061 .
- pitch P 20 is an embodiment of pitch P 2 of FIG. 2 .
- the cross-sectional side view of FIG. 19 corresponds to processing associated with block 1793 of process 1790 of FIG. 17 .
Abstract
Description
- This application incorporates by reference herein in its entirety U.S. Non-Provisional Appl. No. 12/322,105.
- The invention is related to a method of manufacturing a microelectronic device, and in particular but not exclusively, to a method of patterning features of such a device.
- A memory, such as a random access memory (RAM) or read only memory (ROM) often includes arrayed memory cells. Typically, each of the memory cells is coupled to at least one bit line and an overlapping word line, and each of the memory cells include a memory element that is configured to store a logic state. In operation, a controller reads from and/or writes to an individual memory element by receiving and transmitting signals over the bit and word lines of the memory.
- Typically, memory cells are small and closely spaced, with some memory cells having feature sizes and inter-cell spacing on the orders of 50 nm or less. As memories become smaller, however, it becomes increasingly difficult to manufacture smaller and more closely spaced memory cells.
- Non-limiting and non-exhaustive embodiments of the invention are described with reference to the following drawings, in which:
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FIG. 1 is a block diagram of an embodiment of a memory controller and an arrayed memory; -
FIG. 2 is a partial top plan view of an embodiment of a patterned microelectronic lines that may be employed in the arrayed memory ofFIG. 1 ; -
FIG. 3 is a cross-sectional side view of an embodiment of a patterned microelectronic layer that may be employed a an embodiment of the patterned microelectronic lines ofFIG. 2 ; -
FIG. 4 is a cross-sectional side view of an embodiment of patterned recesses that may be employed in another embodiment of the patterned microelectronic lines ofFIG. 2 ; -
FIG. 5 is a cross-sectional side view of an embodiment of a patterned layered stack that may be employed in yet other embodiment of the patterned microelectronic lines ofFIG. 2 ; -
FIG. 6 is a flow diagram generally showing an embodiment of a process for transferring a pattern to one or more microelectronic layers; -
FIGS. 7-10 illustrate embodiments of stages corresponding to the process ofFIG. 5 ; -
FIG. 11 is a flow diagram generally showing an embodiment of a process for self-aligned patterning one or more microelectronic layers; -
FIGS. 12-16 illustrate embodiments of stages corresponding to the process ofFIG. 10 ; -
FIG. 17 is a flow diagram generally showing another embodiment of a process for self-aligned patterning one or more microelectronic layers; and -
FIGS. 18-20 illustrate embodiments of stages corresponding to the process ofFIG. 16 . - Various embodiments of the invention will be described in detail with reference to the drawings, where like reference numerals represent like parts and assemblies throughout the several views. Reference to various embodiments does not limit the scope of the invention, which is limited only by the scope of the claims attached hereto. Additionally, any examples set forth in this specification are not intended to be limiting and merely set forth some of the many possible embodiments for the claimed invention.
- Throughout the specification and claims, the following terms take the meanings explicitly associated herein, unless the context clearly dictates otherwise. The phrase “in one embodiment” as used herein does not necessarily refer to the same embodiment, though it may. Furthermore, the phrase “in another embodiment” as used herein does not necessarily refer to a different embodiment, although it may. Thus, as described below, various embodiments of the invention may be readily combined, without departing from the scope or spirit of the invention.
- In addition, as used herein, the term “or” is an inclusive “or” operator, and is equivalent to the term “and/or,” unless the context clearly dictates otherwise. The term “based on” is not exclusive and allows for being based on additional factors not described, unless the context clearly dictates otherwise, in addition, throughout the specification, the meaning of “a,” “an,” and “the” include plural references. The meaning of “in” includes “in” and “on.”
- As used herein the term microelectronic layer includes a layer of microelectronic material employed in one or more microelectronic devices or systems thereof. For example, microelectronic materials can include group IV semiconductor materials or compound semiconductor materials. Group IV materials include, for example, germanium, or the like. Compound semiconductor materials include, for example, Gallium Arsenide, Indium Phosphide, or the like. Microelectronic materials can also include polysilicon (or amporphous silicon), silicon oxide, silicon nitride, suicide, ceramics (e.g., silicon nitride or silicon carbide), and/or metals or metal alloys (e.g., aluminum, copper, aluminum-copper, gold, titanium, tungsten, or cobalt). As used herein the term “substrate” may include a structure of one or more microelectronic materials in which microelectronic devices and other components of a memory may be formed in and/or upon. Further, although primarily discussed herein in the context of silicon-based microelectronic layers and substrates, other embodiments of microelectronic layers and substrates may be employed.
- As used herein the term “feature” is used to refer to a structure that is formed in a substrate, one or more microelectronic layers, and/or one or more other layers, including photoresist layers or other mask layers. As used herein, the term “pitch” refers to a linear length of a feature (or width) combined with a linear length of a spacing between the feature and another feature. Also, in many embodiments, a pitch is associated with a portion of pattern that is repeated, such as a repeated line and spacing or the like. As used herein the terms “define”, “defined”, or “defining” refer to a process associated with patterning, etching, and/or otherwise forming a size, shape, and/or a portion of a shape associated with a feature, opening, recess, or other aspect of a substrate, microelectronic layer, and/or other layer.
- Briefly stated, the invention is related to a method for transferring a pattern to one or more microelectronic layers, such as layers in a memory or other microelectronic devices. A first mask layer, having a patterned feature, and a second mask layer, having another patterned feature, are formed. The first mask layer and the second mask layer are at least partially covered with a film, and openings are formed in the film by removing the other patterned feature of the second mask layer. A pattern of a microelectronic layer is then defined by patterning the patterned feature of the first mask layer through the openings in the film.
- In one embodiment, the patterned feature of the first mask layer is defined by forming spacers that have a height corresponding to a combined thickness of the second mask layer and a photoresist layer, in another embodiment, the other patterned feature of the second mask layer is defined by removing a portion of the other patterned feature of the second mask layer via an anisotropic etching process.
- In some embodiments, the invention may be employed to reduce a pitch associated with features in one or more microelectronic devices. For example, the invention may be employed to reduce the pitch associated with an array of memory cells in a flash-based memory. In one embodiment, the invention may be employed to enhance a pitch associated with a photoresist mask layer. In such an embodiment, the pitch can be reduced without requiring a change in lithographic technology. For example, a next generation resolution can be realized with a current generation technology and potentially without requiring an expensive investment in a next generation technology, including next generation lithographic development tools and/or chemistries. Also, in one embodiment, pitch can be reduced while still benefiting from the patterning techniques of current generation technology. For example, the patterning techniques of next generation technology typically provide less robust photoresist mask layers due to smaller critical dimension sizes (e.g., the etch rate selectively is less and/or the mask layer is required to be thinner).
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FIG. 1 shows a memory environment in which embodiments of the invention may be employed. Not all the components illustrated in the figures may be required to practice the invention, and variations in the arrangement and type of the components may be made without departing from the spirit or scope of the invention. - As shown,
memory 100 includesarrayed memory 110 andmemory controller 108. Arrayedmemory 110 is arranged to receive arid/or transmit signals over signal/bus lines 102. Arrayedmemory 110 includes line/sector control circuit 112 and memory sectors 114 (identified individually as sectors 1-i).Memory sectors 114 can include, for example, 256, 512, 1024, or more sectors having memory cells that can be individually or collectively accessed via line/sector control circuit 112. In other examples, the number and/or arrangement of memory sectors can be different. In one embodiment, for example,sectors 114 can be referred to more generally as memory blocks, and line/sector control circuit 112 can be configured to have a configuration that is different than a bit line, word line, source gate line, and/or sector topology. -
Memory controller 108 is arranged to receive and transmit data from an upstream system controller (not shown) via addressing signal/bus line 104 and program data signal/bus line 106.Memory controller 108 can include any of a variety of decoder circuits, voltage generator circuits, and/or controller circuits. In one embodiment,memory controller 108 may be located on the same chip as arrayedmemory 110. In another embodiment,memory controller 108 may be located on a different chip, or portions ofmemory controller 108 may be located on another chip or off chip. In other examples, other implementations ofmemory controller 108 are possible. For example,memory controller 108 can include a programmable microcontroller. - In one embodiment,
memory 100 is a flash based memory including flash-based memory cells, such as flash-based NAND cells, NOR cells, or hybrids of the two. In other embodiments,memory 100 may be another type of volatile or non-volatile memory, including, for example, a static random access memory (SRAM) or a dynamic random access memory (DRAM). -
FIG. 2 shows a partial top plan view of an embodiment of patterned microelectronic lines that may be formed on or within a portion ofsubstrate 220. In one embodiment,substrate 220 may form a portion of a semiconductor chip that is employed inmemory 100 ofFIG. 1 . -
Microelectronic lines 222 are features that may be located on and/or withinsubstrate 220 and may be adjacent to one or moreother features 224. In one embodiment,microelectronic lines 222 are located onsubstrate 220; for example,microelectronic lines 222 may be formed by a deposition process. In another embodiment,microelectronic lines 222 may include any of a variety be formed within substrate; for example,microelectronic lines 222 may be etched intosubstrate 220. - As shown in
FIG. 2 , individualmicroelectronic lines 222 have an associated pitch P2. In another embodiment,individual features 224 have an associated pitch P2. In one embodiment, pitch P2 is in a range of about 20 to about 50 nm. In other embodiments, however, pitch P2 may be less than 20 nm or greater than 50 nm. Also, while shown inFIG. 2 as having the same value of pitch, embodiments ofmicroelectronic lines 222 and features 224 can have different pitch values. - In another embodiment,
microelectronic lines 222 may be employed in an embodiment ofmemory sector 114 ofFIG. 1 . For example,microelectronic lines 222 may be polysilicon word lines and/or polysilicon gate source lines that are coupled to the gates of individual memory cells (not shown inFIG. 2 ) located withinsubstrate 220. In some embodiments,microelectronic lines 222 can be arranged in a NAND configuration, a NOR configuration, a hybrid of a NAND and NOR configuration, or a different configuration. In general, pitch P2 is larger in NOR topologies than it is in NAND topologies. -
FIG. 3 shows a cross-sectional side view of an embodiment of microelectronic layer 332 andsubstrate 320.Microelectronic layer 322 andsubstrate 320 may be employed in an embodiment of an individual one ofmicroelectronic lines 222 andsubstrate 220 ofFIG. 2 , respectively. As shown, microelectronic layer 332 includes patternedopenings 326 having pitch P3. In one embodiment, pitch P3 is an embodiment of pitch P2 ofFIG. 2 . -
FIG. 4 shows a cross-sectional side view of an embodiment ofrecesses 422 insubstrate 420. In one embodiment, recesses 422 andsubstrate 420 may be employed in an embodiment of an individual one ofmicroelectronic lines 222 andsubstrate 220 ofFIG. 2 , respectively. As shown, recesses 422 have an associated pitch P4. In one embodiment, pitch P4 is an embodiment of pitch P2 ofFIG. 2 . -
FIG. 5 shows a cross-sectional side View of an embodiment oflayered stack 522 andsubstrate 520. In one embodiment,layered stack 522 andsubstrate 520 may be employed in an embodiment of an individual one ofmicroelectronic lines 222 andsubstrate 220 ofFIG. 2 , respectively. As shown,dielectric spacers 528, having pitch P5, separate portions oflayered stack 522. In one embodiment, pitch P5 is an embodiment of pitch P2 ofFIG. 2 . In another embodiment,dielectric spacer 528 are an embodiment offeatures 224 ofFIG. 2 . - In one embodiment,
layered stack 522 anddielectric spacers 528 define locations ofindividual memory cells 530. Each ofmemory cells 530 includes a charge trapping component 532 that is located inlayered stack 522. In addition, each ofmemory cells 530 can be coupled to a portion ofpolysilicon line 534, which is also located inlayered stack 522.Individual memory cells 530 are configured to share source/drain regions 538 formed insubstrate 520. - Charge trapping component 532 includes
tunneling layer 540,charge trapping layer 541, anddielectric layer 542. In general,tunneling layer 540 provides a tunneling barrier.Charge trapping layer 541 may be a non-conductive layer that is configured to store a tunneled charge.Dielectric layer 542 electrically isolatescharge trapping layer 541 frompolysilicon line 534. - In operation,
polysilicon line 534 and source/drain regions 538 are configured to provide electrical potentials for trapping charge within a charge trapping component. One or more portions of charge trapping component are “programmed” when trapping charge and “unprogrammed” when not trapping charge. Although generally described in the context of a dual-bit or multi-bit topology, the invention is not so limited, and other embodiments of memory cells may be manufactured using the manufacturing techniques described herein. Further, embodiments of the invention can be employed to manufacture other types of devices, including other types of electrical devices, such as a capacitor, transistor, or the like; mechanical devices; as well as other types of electro-mechanical devices. -
FIG. 6 is a flow diagram generally showing one embodiment ofprocess 650 for transferring a self-aligned pattern to one or more microelectronic layers. In one embodiment,process 650 is employed to formmicroelectronic lines 222 ofFIG. 2 . -
Process 650 begins atblock 651, where a first mask layer is formed, and a second mask layer is formed on the first mask layer. The first mask layer includes a first patterned feature and the second mask layer includes a second patterned feature that is located on the first patterned feature of the first mask layer. In one embodiment, the first patterned feature of the first mask layer is defined by spacers having a height corresponding to a combined thickness of the second mask layer and the photoresist mask layer (described further with reference toFIGS. 10-16 ). In another embodiment, the second patterned feature of the second mask layer is defined by removing a portion of the second patterned feature of the second mask layer that is covered by a photoresist mask layer (described further with reference toFIGS. 17-19 ). - Processing continues to block 652, where the first mask layer and the second mask layer are at least partially covered by a film. In one embodiment, the film is a microelectronic layer that is deposited in a thin film deposition process. Thin film deposition processes can include, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (REND), atomic layer deposition (ALD), or the like. In one embodiment, the film includes a high density plasma (HDP) oxide. In another embodiment, the isolation dielectrics include a tetra-ethyl-ortho-silicate (TEOS) oxide or an ozone based TEOS. In another embodiment, a chemical mechanical polishing (CMP) process can planarize a conformal film such that a surface of the second patterned second of the second mask layer is exposed through the conformal film. For example, a CMP process can be employed to recess the conformal film below such a surface. In another embodiment, a non-conformal film includes a photoresist (PR) film, such as a spin-on or deposited photoresist film or other film. For example, a non-conformal film can include spin-on-carbon or spin-on-silicon to enhance wet etch resistance. In yet another embodiment, a conformal or non-conformal film includes another type of polymeric material.
- Processing continues to block 653, where openings are formed in the film by removing the second patterned feature of the second mask layer. In one embodiment, an etching process may be employed to remove the second patterned feature. The etching processes can include, for example, one or more wet and/or dry etch techniques, including chemical and/or physical etching techniques, employing, for example, isotropic or anisotropic wet and/or dry etch chemistries, reactive ion etches, and/or plasma assisted etches. In general, the type of chemistry employed in the etching process may be based on the material of the first and second mask layers. For example, hydrofluoric chemistries can be employed to selectively etch silicon oxide over silicon, polysilicon, silicon nitride, or the like.
- In one embodiment, surfaces of the second pattern feature may be exposed Through the film prior to removal. In one embodiment, as discussed above, a CMP process, or the like may be employed to recess the film. In another embodiment, an etch back process can be used to thin the film. For example, a blanket etch can thin a flint to expose a surface portion of the second patterned feature. In another example, a bottom anti-reflective coating (BARC) etch back process can be employed to thin, a conformal photoresist mask.
- Processing continues to block 654, where a pattern is defined in a microelectronic layer by patterning the patterned feature of the first mask layer through the openings in the film. An etching process, for example, may be employed to define a combined pattern that includes the first patterned feature of the first mask layer and the second patterned feature of the second mask layer transferred into the first patterned feature. In another embodiment, the same etching process or a different etching process may be employed to transfer the combined pattern into a microelectronic layer. For example, the film may be removed, and an etching process may form the combined pattern in a microelectronic layer positioned beneath the first mask layer.
- Although not illustrated, processing may continue to form devices or other features. For example, processing may continue to form a memory, such as
memory 100 ofFIG. 1 , or a portion of the memory. Further, such devices or features may be cleaved to form individual dies or chips that may be incorporated into a packaged device or other device. A person skilled in the art would appreciate the various manners in which such processing and packaging may be carried out. - Moreover, a variety of simulation and/or software tools may be employed to create a specific implementation of the first patterned feature of the first mask layer and the second patterned feature of the second mask layer. For example, the feature sizes of the first mask layer and the second mask layer can be designed to create a specific pitch or spacing for a combined pattern. High-level software code, such as a register transfer logic (RTL) file, may be created and then compiled to form a netlist file. The netlist file may be used in turn to optimize the combined pattern. A physical design process may be employed in conjunction with the netlist file and a component library to create a layout file. The layout file may be used to create a mask file that may be provided to a device foundry to equip the foundry for manufacturing a one or more microelectronic layers containing the combined pattern.
- Further, although not described with reference to the figures, any of a variety of intermediary processes may be employed between individual blocks of
process 650, such as cleaning, metrology, inspection, and/or other processes. For example, a variety of wet cleaning and/or dry cleaning processes may be used to prepare a substrate or remove a mask layer. -
FIGS. 7-10 illustrate various embodiments of stages corresponding to the manufacture of a patterned microelectronic line or feature. In one embodiment, the various stages represent stages of manufacturingmicroelectronic lines 222 ofFIG. 2 . -
FIG. 7 is an embodiment showing a cross-sectional side view of substrate 720;microelectronic layer 760;first mask layer 761 having, at least, firstpatterned features 761 a and 761 b; andsecond mask layer 762 having, at least, secondpatterned features first mask layer 761 includes a silicon nitride material or a silicon-oxy-nitride material.Second mask layer 762 may include a polysilicon material. In another embodiment, one or more offirst mask layer 761 andsecond mask layer 762 includes a combination of different microelectronic materials, - In one embodiment, the patterned features of
second mask layer 762 have pitch P7 that is at least twice as large as pitch P2 ofFIG. 2 . In another embodiment, the patterned features offirst mask layer 761 are separated by spacing distances S7 to define a portion of pitch P2 ofFIG. 2 . In yet another embodiment, the patterned features offirst mask layer 761 have pitch P7. In one embodiment, the cross-sectional side view ofFIG. 7 corresponds to processing associated withblock 651 ofprocess 650 ofFIG. 6 . -
FIG. 8 is an embodiment showing a cross-sectional side view offilm 863 covering portions offirst mask layer 761 andsecond mask layer 762. As shown, portions of patternedfeatures film 863, exposingsurface portions features FIG. 8 corresponds to processing associated withblock 652 ofprocess 650 ofFIG. 6 . -
FIG. 9 is an embodiment showing a cross-sectional side view ofopenings 965 a and 965 h defined infilm 863 after removing patternedfeatures Openings patterned features 761 a and 761 b define pitch P9. In one embodiment, pitch P9 is an embodiment of Pitch P2 ofFIG. 2 . In one embodiment, the cross-sectional side view ofFIG. 9 corresponds to processing associated withblock 653 ofprocess 650 ofFIG. 6 . -
FIG. 10 is an embodiment-showing a cross-sectional side view of patterned features 1066 a-d defined infirst mask layer 761 and having pitch P9 ofFIG. 9 . In one embodiment, the cross-sectional side view ofFIG. 10 corresponds to processing associated withblock 654 ofprocess 650 ofFIG. 6 . - Although not illustrated, processing may continue beyond that described in conjunction with
FIG. 6 . In one embodiment, another etching process may be employed to transfer a pattern associated with patterned features 1066 a-d intomicroelectronic layer 760. For example,microelectronic layer 760 ofFIG. 10 may be patterned to formmicroelectronic lines 222 ofFIG. 2 . In another embodiment,first mask layer 761 is an embodiment of an individual one ofmicroelectronic lines 222. -
FIG. 11 is a flow diagram generally showing an embodiment of a process for self-aligned patterning of one or more microelectronic layers.Process 1170 may be an embodiment of one or more manufacturing steps that are carried out at block. 651 ofprocess 650 ofFIG. 6 . -
Process 1170 begins atblock 1171, where a patterned photoresist mask is formed on a hard mask. For example, in one embodiment, a patterned photoresist mask can be formed onsecond mask layer 762 ofFIG. 7 (prior to formingfeatures - Processing continues to block 1172, where combined features are formed in the photoresist mask and the hard mask such that the combined features each include a first section of the photoresist mask and a second section of the hard mask. In one embodiment, one or more etching processes may be employed to form the combined features.
- Processing continues to block 1173, where spacers are formed adjacent to the combined features such that each spacer is adjacent to a first section of the combined feature and a second section of the combined feature. In one embodiment, the spacers are formed by depositing a polymeric material and etching back the polymeric material. For example, the spacers may be formed using a Motif™ post-lithography pattern enhancement system (available from LAM Research Corp., Freemont, Calif.). In another embodiment, a Motif™ system can also be employed for resist shrinking carried out at block 1150.
- Processing continues to block 1174, where a first pattern is transferred to a microelectronic layer using the combined features and the spacers formed at
block 1173 as an etch mask. In one embodiment, an etching process is used to define the first pattern in the microelectronic layer. In another embodiment, the first pattern is formed infirst mask layer 761 ofFIG. 7 . In yet another embodiment, the first pattern is formed in a different microelectronic layer. - Upon completion of
block 1174, processing may continue. For example, in one embodiment, processing may continue to block 652 ofFIG. 6 . -
FIGS. 12-16 illustrate various embodiments of stages corresponding to the manufacture of a patterned microelectronic line or feature. In one embodiment, the various stages represent stages of manufacturingmicroelectronic lines 222 ofFIG. 2 . -
FIG. 12 is an embodiment showing a cross-sectional side view ofsubstrate 1220,microelectronic layer 1260,first mask layer 1261,second mask layer 1262, andphotoresist mask layer 1280 havingopenings 1281 with associated pitch P12. In one embodiment, portions of photoresist (drawn in dashed lines) mask layer can be removed by a photoresist thinning process. - In one embodiment,
substrate 1220,microelectronic layer 1260,first mask layer 1261, andsecond mask layer 1262 ofFIG. 12 are an embodiment of substrate 720,microelectronic layer 760,first mask layer 761, andsecond mask layer 762 ofFIG. 7 , respectively. In another embodiment, pitch Pp is an embodiment of pitch P7 ofFIG. 7 . In one embodiment, the cross-sectional side view ofFIG. 12 corresponds to processing associated withblock 1171 ofprocess 1170 ofFIG. 11 . -
FIG. 13 is an embodiment showing a cross-sectional ide view of combinedFeatures photoresist mask 1280 and a section ofsecond mask layer 1262. Combinedfeature 1383 a includesfirst section 1384 a ofsecond mask layer 1262 andsecond section 1385 a ofphotoresist mask layer 1280. Combinedfeature 1383 b includesfirst section 1384 b ofsecond mask layer 1262 and second section 1385 b of photoresist mask layer 1380. In one embodiment, the cross-sectional side view ofFIG. 13 corresponds to processing associated withblock 1172 ofprocess 1170 ofFIG. 11 . In one embodiment, width w13 has a value that is in range of about 10 to 30 nm. In other embodiments, however, width w13 has a value that is less than or greater than the values in this range. -
FIG. 14 is an embodiment showing a cross-sectional side view of spacers 1486 a-c. Each of spacers 1486 a-c has a corresponding height h14 and a minimum width w14. Height h14 corresponds to a thickness ofsecond mask layer 1262 and a thickness ofphotoresist mask layer 1280. In one embodiment, pitch P14 is an embodiment of pitch P2 ofFIG. 2 . In one embodiment, minimum width w14 ofFIG. 14 and minimum width w13 ofFIG. 13 define pitch P14. In another embodiment, minimum width w14 and spacing S14 of spacers 1286 a-d define pitch P14. In one embodiment, the cross-sectional side view ofFIG. 14 corresponds to processing associated withblock 1173 ofprocess 1170 ofFIG. 11 . In one embodiment, width w14 and spacing S14 have values that are in range of about 10 to 30 nm. In other embodiments, however, width w14 and spacing S14 have values that are less than and/or greater than the values in this range. In one embodiment, height h14 has a value that is in a range of about 100 to 250 nm. In other embodiments, however, height h14 has a value that is less than or greater than the values in this range. -
FIG. 15 is an embodiment showing a cross-section side view offeatures mask layer 1261.Patterned feature 1561 a is defined byfirst section 1384 a andspacers Patterned feature 1561 b is defined byfirst section 1384 b andspacer 1486 c, in one embodiment, features 1561 a and 1561 b are an embodiment of patterned features 761 a and 76 tb ofFIG. 7 , respectively. In one embodiment, the cross-sectional side view ofFIG. 15 corresponds to processing associated withblock 1174 ofprocess 1170 ofFIG. 11 . -
FIG. 16 is an alternative embodiment showing a cross-sectional side view ofmask layer 1688.Mask layer 1688 is similar tofirst mask layer 1261 andsecond mask layer 1262 with the exception thatmask layer 1688 is formed from a single microelectronic layer. For example,mask layer 1688 may be formed by employing similar processing as that carried out with respect tofirst mask layer 1261 andsecond mask layer 1262 ofFIGS. 12-15 ; however, a timed etch may be used to define height h16 associated with mask layer 1688 (rather than usingsecond mask layer 1262 ofFIG. 12 as an etch stop layer). In one embodiment,mask layer 1688 is polysilicon. In another embodiment,mask layer 1688 is a different microelectronic material. In one embodiment, the cross-sectional side view ofFIG. 15 corresponds to processing associated withblock 1174 ofprocess 1170 ofFIG. 11 . -
FIG. 17 is a processing flow diagram generally showing an embodiment of a process for self-aligned patterning of one or more microelectronic layers. Process 1790 may be an embodiment of one or more manufacturing steps that are carried' out atblock 651 ofprocess 650 ofFIG. 6 . - Process 1790 begins at block 1191, where a second mask layer is formed on a first mask layer. In one embodiment, a patterned photoresist mask is also fanned on the second mask layer. For example, in one embodiment, a patterned photoresist mask can be formed on
second mask layer 762 ofFIG. 7 (prior to fanningfeatures - Processing continues to block 1792, where a pattern is transferred into the first mask layer by etching the first mask layer through the second mask layer. In one embodiment, the pattern may also be concurrently transferred into the second mask layer through a patterned photoresist mask.
- Processing continues to block 1793, where another pattern in the second mask layer by, removing a portion of the pattern associated with the second mask layer: In one embodiment, an anisotropic etching process may be employed to remove a portion of the pattern of the second mask layer. In one embodiment, the portion of the pattern may be removed by etching back second mask layer. In another embodiment the portion of the pattern of the second mask layer that is removed is located between a photoresist mask layer and the first mask layer. For example, if the second mask layer is a silicon oxide layer, a hydrofluoric-based wet etch chemistry may be employed to remove the portion of the pattern of the second mask layer.
- Upon completion of
block 1793, processing may continue. For example, in one embodiment, processing may continue to block 652 ofFIG. 6 . -
FIGS. 18-20 illustrate various embodiments of stages corresponding to the manufacture of a patterned microelectronic line or feature. In one embodiment, the various stages represent stages of manufacturingmicroelectronic lines 222 ofFIG. 2 . -
FIG. 18 is an embodiment showing a cross-sectional side view ofsubstrate 1820,microelectronic layer 1860,first mask layer 1861,second mask layer 1862, andphotoresist mask layer 1894.First mask layer 1861 includesfeatures second mask layer 1862 includesfeatures 1862 a and 1862 b.Photoresist mask layer 1894 includesopenings 1895 defining the features of the first and second mask layers.Openings 1895 also define pitch P18. In one embodiment,substrate 1820,microelectronic layer 1860,first mask layer 1861, andsecond mask layer 1862 ofFIG. 12 are an embodiment of substrate 720,microelectronic layer 760,first mask layer 761, andsecond mask layer 762 ofFIG. 7 , respectively. In another embodiment, pitch P18 is an embodiment of pitch P7 ofFIG. 7 . In one embodiment, the cross-sectional side view ofFIG. 18 corresponds to processing associated withblocks FIG. 17 . -
FIG. 19 is an embodiment showing a cross-sectional side view of portions ofsecond mask layer 1862 removed. Undercut width w19, betweenphotoresist mask layer 1894 andfirst mask layer 1861, can be tailored such that pitch P19, is defined by width w19 and the patterned portions offirst mask layer 1861. In one embodiment, pitch P19 is an embodiment of pitch P2 ofFIG. 2 . In one embodiment, the cross-sectional side view ofFIG. 19 corresponds to processing associated withblock 1793 of process 1790 ofFIG. 17 . In one embodiment, width w19 has a value that is in range of about 10 to 30 nm. In other embodiments, however, width w19 has a value that is less than or greater than the values in this range. -
FIG. 20 is an alternative embodiment showing a cross-sectional side view offirst mask layer 2061 and portions ofsecond mask layer 2062 removed.First mask layer 2061 andsecond mask layer 2062 may be similar tofirst mask layer 1861 andsecond mask layer 1862 ofFIG. 19 , respectively, with the exception that the top-side surface ofsecond mask layer 2062 was not covered during an anisotropic etching process. For example, a photoresist layer was not coveringsecond mask layer 2062 while a pattern was being transferred into first mask layer 1201. Accordingly,second mask layer 2062 has a reduced thickness Δt due to the anisotropic etching process. In one embodiment, Δt has a value that corresponds to width w19 ofFIG. 19 and Δt is tailored such that pitch P20 is defined by Δt and the patterned portions offirst mask layer 2061. In one embodiment, pitch P20 is an embodiment of pitch P2 ofFIG. 2 . In one embodiment, the cross-sectional side view ofFIG. 19 corresponds to processing associated withblock 1793 of process 1790 ofFIG. 17 . - The above specification, examples and data provide a description of the manufacture and use of the composition of the invention. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, the invention also resides in the claims hereinafter appended.
Claims (17)
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US12/322,105 US8680671B2 (en) | 2009-01-28 | 2009-01-28 | Self-aligned double patterning for memory and other microelectronic devices |
US14/204,373 US20140191308A1 (en) | 2009-01-28 | 2014-03-11 | Self-aligned double patterning for memory and other microelectronic devices |
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US20120085733A1 (en) * | 2010-10-07 | 2012-04-12 | Applied Materials, Inc. | Self aligned triple patterning |
KR20130015145A (en) * | 2011-08-02 | 2013-02-13 | 삼성전자주식회사 | Method of forming fine patterns for semiconductor device |
US9460963B2 (en) * | 2014-03-26 | 2016-10-04 | Globalfoundries Inc. | Self-aligned contacts and methods of fabrication |
US9536596B2 (en) | 2014-08-26 | 2017-01-03 | Qualcomm Incorporated | Three-port bit cell having increased width |
US9761450B1 (en) * | 2016-09-26 | 2017-09-12 | International Business Machines Corporation | Forming a fin cut in a hardmask |
US10170309B2 (en) * | 2017-02-15 | 2019-01-01 | Globalfoundries Inc. | Dummy pattern addition to improve CD uniformity |
US10573528B2 (en) | 2017-12-14 | 2020-02-25 | Tessera, Inc. | Two-color self-aligned double patterning (SADP) to yield static random access memory (SRAM) and dense logic |
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US20030210573A1 (en) * | 2002-05-08 | 2003-11-13 | Chang-Hyun Lee | Electrically erasable charge trap nonvolatile memory cells having erase threshold voltage that is higher than an initial threshold voltage, and methods of erasing and designing same |
US6867116B1 (en) * | 2003-11-10 | 2005-03-15 | Macronix International Co., Ltd. | Fabrication method of sub-resolution pitch for integrated circuits |
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US5328810A (en) * | 1990-05-07 | 1994-07-12 | Micron Technology, Inc. | Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic process |
US6887627B2 (en) * | 2002-04-26 | 2005-05-03 | Macronix International Co., Ltd. | Method of fabricating phase shift mask |
US7324374B2 (en) | 2003-06-20 | 2008-01-29 | Spansion Llc | Memory with a core-based virtual ground and dynamic reference sensing scheme |
US7115509B2 (en) * | 2003-11-17 | 2006-10-03 | Micron Technology, Inc. | Method for forming polysilicon local interconnects |
US7235478B2 (en) | 2005-01-12 | 2007-06-26 | Intel Corporation | Polymer spacer formation |
US7385851B1 (en) | 2006-12-22 | 2008-06-10 | Spansion Llc | Repetitive erase verify technique for flash memory devices |
US7561465B2 (en) | 2006-12-28 | 2009-07-14 | Advanced Micro Devices, Inc. | Methods and systems for recovering data in a nonvolatile memory array |
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US20030210573A1 (en) * | 2002-05-08 | 2003-11-13 | Chang-Hyun Lee | Electrically erasable charge trap nonvolatile memory cells having erase threshold voltage that is higher than an initial threshold voltage, and methods of erasing and designing same |
US6867116B1 (en) * | 2003-11-10 | 2005-03-15 | Macronix International Co., Ltd. | Fabrication method of sub-resolution pitch for integrated circuits |
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