US20140197495A1 - Semiconductor device and method of forming the same - Google Patents
Semiconductor device and method of forming the same Download PDFInfo
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- US20140197495A1 US20140197495A1 US14/218,398 US201414218398A US2014197495A1 US 20140197495 A1 US20140197495 A1 US 20140197495A1 US 201414218398 A US201414218398 A US 201414218398A US 2014197495 A1 US2014197495 A1 US 2014197495A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
Definitions
- the present invention generally relates to a semiconductor device and a method of forming the same. More specifically, the present invention relates to a semiconductor device that is used for a CMOS circuit that includes n-MOS transistors and p-MOS transistors.
- the semiconductor integrated circuit has an integration of a large number of MOS field effect transistors.
- the MOS field effect transistors that are integrated on the semiconductor integrated circuit are classified into n-MOS transistors and p-MOS transistors. Most of the n-MOS transistors and p-MOS transistors constitute CMOS circuits. Scaling down of the n-MOS transistors and p-MOS transistors are necessary for improving the high speed performances of the semiconductor device or the CMOS circuits and also for realizing large scale integration.
- NBTI negative bias temperature instability
- FIGS. 4A through 4F are fragmentary cross sectional elevation views illustrating conventional semiconductor devices in sequential steps involved in a conventional method of manufacturing the same.
- FIG. 5 is a fragmentary cross sectional elevation view illustrating the conventional semiconductor device that is formed by the conventional manufacturing method shown in FIGS. 4A through 4F .
- the conventional semiconductor device has an n-MOS transistor and a p-MOS transistor.
- the n-MOS transistor has a second gate insulating film of a second thickness Tox(NMOS).
- the p-MOS transistor has a first gate insulating film of a first thickness Tox(PMOS).
- the first thickness Tox(PMOS) is greater than the second thickness Tox(NMOS).
- isolation regions 102 are selectively formed in an upper region of a silicon substrate 101 , thereby defining active regions on the silicon substrate 101 .
- a first gate insulating film 103 is formed over the active regions on the silicon substrate 101 and the isolation regions 102 .
- the first gate insulating film 103 has a first thickness in the range of 3 nanometers to 10 nanometers.
- the silicon substrate 101 has an n-MOS transistor region 104 a and a p-MOS transistor region 104 b.
- a first resist film is applied on the first gate insulating film 103 .
- a photo-lithography process is carried out to form a first resist pattern 105 in the p-MOS transistor region 104 b.
- the first resist pattern 105 has an opening over the n-MOS transistor region 104 a.
- a wet etching process is carried out using the first resist pattern 105 as a mask to selectively remove the first gate insulating film 103 in the n-MOS transistor region 104 a, while leaving the first gate insulating film 103 in the p-MOS transistor region 104 b.
- the surface of the n-MOS transistor region 104 a of the silicon substrate 101 is shown.
- the wet etching process is carried out using an HF-based etchant.
- the first resist pattern 105 is removed.
- a thermal oxidation process is carried out to selectively form a second gate insulating film 106 on the n-MOS transistor region 104 a of the silicon substrate 101 .
- the second gate insulating film 106 has a second thickness in the range of 1 nanometer to 3 nanometers.
- the first gate insulating film 103 is formed in the p-MOS transistor region 104 b.
- the second gate insulating film 106 is formed in the n-MOS transistor region 104 a.
- the first gate insulating film 103 on the p-MOS transistor region 104 b is greater in thickness than the second gate insulating film 106 on the n-MOS transistor region 104 a.
- a thermal chemical vapor deposition process is carried out to form a non-doped polysilicon layer 108 over the first gate insulating film 103 on the p-MOS transistor region 104 b and the second gate insulating film 106 on the n-MOS transistor region 104 a.
- the non-doped polysilicon layer 108 has a thickness in the range of 50 nanometers to 100 nanometers.
- a second photo-resist film is applied on the non-doped polysilicon layer 108 .
- a lithography process is carried out to form a second resist pattern 111 on the non-doped polysilicon layer 108 .
- a dry etching process is carried out using the second resist pattern 111 as a mask to selectively remove the non-doped polysilicon layer 108 , thereby forming gate electrodes 110 a and 110 b on the second and first gate insulating films 106 and 103 in the n-MOS transistor region 104 a and the p-MOS transistor region 104 b.
- the second resist pattern 111 is removed from the gate electrodes 108 .
- a first ion-implantation of n-type dopant is carried out using the gate electrode 110 a as a mask to selectively introduce the n-type dopant into the n-MOS transistor region 104 a of the silicon substrate 101 , thereby selectively forming n-doped regions in the n-MOS transistor region 104 a.
- a second ion-implantation of p-type dopant is carried out using the gate electrode 110 b as a mask to selectively introduce the p-type dopant into the p-MOS transistor region 104 b of the silicon substrate 101 , thereby selectively forming p-doped regions in the p-MOS transistor region 104 b.
- Side wall insulating films 113 are selectively formed on the side walls of the gate electrodes 110 a and 110 b.
- the side wall insulating films 113 have a thickness in the range of 5 nanometers to 20 nanometers.
- the side wall insulating films 113 may be made of an insulator such as oxide or nitride.
- a third ion-implantation of n-type dopant is carried out using the side walls 113 and the gate electrode 110 a as a mask to selectively introduce the n-type dopant into the n-MOS transistor region 104 a of the silicon substrate 101 , thereby selectively forming n-type source and drain regions 112 a and 112 c of lightly doped drain structures in n-MOS transistor region 104 a.
- the third ion-implantation is carried out at higher acceleration energy than that of the first ion-implantation so as to introduce the n-type dopant into the deeper level than the n-doped regions, thereby forming the n-type source and drain regions 112 a and 112 c having the n-type lightly doped drain structures.
- a fourth ion-implantation of p-type dopant is carried out using the side walls 113 and the gate electrode 110 b as a mask to selectively introduce the p-type dopant into the p-MOS transistor region 104 b of the silicon substrate 101 , thereby selectively forming p-type source and drain regions 112 b and 112 d of lightly doped drain structures in p-MOS transistor region 104 b.
- the fourth ion-implantation is carried out at higher acceleration energy than that of the second ion-implantation so as to introduce the p-type dopant into the deeper level than the p-doped regions, thereby forming the p-type source and drain regions 112 b and 112 d having the p-type lightly doped drain structures.
- the gate electrode 110 a in the n-MOS transistor region 104 a is doped with the n-type dopant by the first and third ion-implantations.
- the gate electrode 110 b in the p-MOS transistor region 104 b is doped with the p-type dopant by the second and fourth ion-implantations.
- An annealing process is carried out to activate the n-type dopant and the p-type dopant in the n-type source and drain regions 112 a and 112 c and the p-type source and drain regions 112 b and 112 d.
- an inter-layer insulator 114 is formed over the first and second gate insulating films 103 and 106 and the gate electrodes 110 a and 110 b with the side wall insulating films 113 .
- Contact holes are formed in the inter-layer insulator 114 .
- the contact holes penetrate the inter-layer insulator 114 .
- the contact holes reach the n-type source and drain regions 112 a and 112 c and the p-type source and drain regions 112 b and 112 d as well as the gate electrodes 110 a and 110 b.
- Contact plugs 115 are formed in the contact holes of the inter-layer insulator 114 .
- the contact plugs 115 penetrate the inter-layer insulator 114 .
- the contact plugs 115 contact the n-type source and drain regions 112 a and 112 c and the p-type source and drain regions 112 b and 112 d.
- the contact plugs 115 contact the gate electrodes 110 a and 110 b.
- Metal interconnections 116 are formed over the inter-layer insulator 114 and the contact plugs 115 .
- the metal interconnections 116 contact the contact plugs 115 so that the metal interconnections 116 are electrically connected through the contact plugs 115 to the n-type source and drain regions 112 a and 112 c and the p-type source and drain regions 112 b and 112 d as well as to the gate electrodes 110 a and 110 b.
- a passivation film 117 is formed over the metal interconnections 116 and the inter-layer insulator 114 , thereby completing a semiconductor device having a CMOS circuit.
- Japanese Unexamined Patent Application, First Publication, No. 2-265248 discloses the source and drain regions having the lightly doped drain structure that can solve the problems that scaling down of the transistors causes field concentration near the drain thereby generating hot carriers and varying the threshold of the transistor.
- the above-described conventional semiconductor device having the CMOS circuit includes the n-MOS transistor having the second gate insulating film 106 and the p-MOS transistor having the first gate insulating film 103 .
- the n-MOS transistor has the second gate insulating film 106 of the second thickness Tox(NMOS).
- the p-MOS transistor has the first gate insulating film of the first thickness Tox(PMOS).
- the first thickness Tox(PMOS) is greater than the second thickness Tox(NMOS).
- the first gate insulating film 103 is formed over the n-MOS transistor region 104 a and the p-MOS transistor region 104 b.
- the first resist pattern 105 is formed over the gate insulating film 103 by the lithography process.
- the first resist pattern 105 has an opening that is positioned in the n-MOS transistor region 104 a.
- the first gate insulating film 103 is selectively removed from the n-MOS transistor region 104 a by using the first resist pattern 105 as a mask, while leaving the first gate insulating film 103 in the p-MOS transistor region 104 b.
- the second gate insulating film 106 is selectively formed on the n-MOS transistor region 104 a.
- a single gate insulating film with a larger uniform thickness is formed over the n-MOS transistor region 104 a and the p-MOS transistor region 104 b.
- the thick gate insulating film on the n-MOS transistor region 104 a may excessively reduce the on-current of the n-MOS transistor.
- CMOS circuits it is a primary object of the present invention to provide a semiconductor device including CMOS circuits.
- a semiconductor device may include, but is not limited to, an n-MOS transistor, and a p-MOS transistor.
- the p-MOS transistor may include, but is not limited to, a gate insulating film and a gate electrode.
- the gate electrode may have an adjacent portion that is adjacent to the gate insulating film.
- the adjacent portion may include a polysilicon that contains an n-type dopant and a p-type dopant.
- the gate electrode containing the adjacent portion of the p-MOS transistor can ensure that the p-MOS transistor be superior in NBTI reliance. In other words, the gate electrode containing the adjacent portion of the p-MOS transistor can improve the NBTI lifetime without carrying out any additional process for the gate insulating film.
- the gate electrode containing the adjacent portion can provide substantially similar effects as when the gate insulating film of the p-MOS transistor is thicker than the gate insulating film of the n-MOS transistor.
- the gate electrode containing the adjacent portion can increase the flexibility of designing the gate insulating film such as the thickness thereof. The increased flexibility can make it easier to obtain improved performance of the transistors.
- the adjacent portion has a thickness of at least 30 nanometers from the interface between the gate electrode and the gate insulating film, thereby improving the certainty of the NBTI reliance of the p-MOS transistor.
- the adjacent portion with the thickness of at least 30 nanometers contains the n-type dopant, which can reduce or prevent that the p-type dopant such as boron as introduced in the gate electrode of the p-MOS transistor is thermally diffused through the gate insulating film to the semiconductor substrate, while the heat treatment is carried out. This reduction or prevention can improve the NBTI reliance.
- the adjacent portion having the thickness of at least 30 nanometers from the interface between the gate electrode and the gate insulating film has a compositional ratio of the n-type dopant to the p-type dopant in the range of 10% to 40%.
- the adjacent portion with this compositional ratio can ensure good performance such as on-current of the p-MOS transistor and improvement of the NBTI reliance.
- the gate electrode may have a stacked structure that includes a lower portion that includes the adjacent portion, and an upper portion over the lower portion.
- the lower portion may include the polysilicon containing the n-type dopant and the p-type dopant.
- the upper portion contains the polysilicon containing the p-type dopant.
- a method of forming a semiconductor device including an n-MOS transistor and a p-MOS transistor may include, but is not limited to, the following processes.
- a gate insulating film may be formed over an n-MOS transistor region and a p-MOS transistor region of a semiconductor substrate.
- a first polysilicon layer may be formed over the gate insulating film, the first polysilicon layer containing an n-type dopant.
- a second polysilicon layer may be formed over the first polysilicon layer.
- the second polysilicon layer may be substantially free of any dopant.
- the stack of the first and second polysilicon layers is patterned to form gate electrode structures in the n-MOS transistor region and the p-MOS transistor region.
- a first ion-implantation process of an n-type dopant to the n-MOS transistor region may be carried out, thereby introducing the n-type dopant into the first and second polysilicon layers in the n-MOS transistor region and into source and drain formation regions of the semiconductor substrate in the n-MOS transistor region.
- a second ion-implantation process of a p-type dopant to the p-MOS transistor region may be carried out, thereby introducing the p-type dopant into the first and second polysilicon layers in the p-MOS transistor region and into source and drain formation regions of the semiconductor substrate in the p-MOS transistor region.
- the semiconductor device that is superior in the NBTI reliance can be formed by the simple processes.
- the method of forming the semiconductor device may further include the following processes.
- Side walls may be formed on side faces of the gate electrode structures in the n-MOS transistor region and the p-MOS transistor region, after carrying out the first and second ion-implantation processes.
- a third ion-implantation process of an n-type dopant to the n-MOS transistor region may be carried out using the side walls as a mask, thereby introducing the n-type dopant into the first and second polysilicon layers in the n-MOS transistor region and into the source and drain formation regions of the semiconductor substrate in the n-MOS transistor region.
- a fourth ion-implantation process of a p-type dopant to the p-MOS transistor region may be carried out using the side walls as a mask, thereby introducing the p-type dopant into the first and second polysilicon layers in the p-MOS transistor region and into the source and drain formation regions of the semiconductor substrate in the p-MOS transistor region.
- This structure can relax the field concentration in the vicinity of the drain of each of the n-MOS transistor and the p-MOS transistor, thereby obtaining good performance of those transistors.
- the method of forming the semiconductor device may further include the following processes.
- An annealing process for the semiconductor substrate may be carried out, after carrying out the third and fourth ion-implantation processes, so that the n-type dopant is localized near the interface between the gate electrode and the gate insulating film.
- the first ion-implantation process is carried out at a dose in the range of 1E13 atoms/cm 2 to 1E15 atoms/cm 2 .
- the concentration of the n-type dopant of the first polysilicon layer may be preferably in the range of 1E19 atoms/cm 3 to 1E21 atoms/cm 3 .
- the semiconductor device having superior NBTI reliance of the p-MOS transistor can be formed.
- the semiconductor device includes the n-MOS transistor and the p-MOS transistor.
- the p-MOS transistor may include a gate insulating film and a gate electrode.
- the gate electrode may have an adjacent portion that is adjacent to the gate insulating film.
- the adjacent portion may include a polysilicon that contains an n-type dopant and a p-type dopant.
- the gate electrode containing the adjacent portion of the p-MOS transistor can ensure that even if the gate insulating film of the n-MOS transistor has the same thickness as that of the p-MOS transistor, the semiconductor device can have similar performance to that obtained by the semiconductor device in which the gate insulating film of the p-MOS transistor is thicker than the gate insulating film of the n-MOS transistor.
- the gate electrode containing the adjacent portion of the p-MOS transistor can ensure that the p-MOS transistor be superior in NBTI reliance.
- the gate electrode containing the adjacent portion can increase the flexibility of designing the gate insulating film such as the thickness thereof. The increased flexibility can make it easier to obtain improved performance of the transistors.
- the gate electrode has a stacked structure that includes the first polysilicon layer containing the n-type dopant in the vicinity of the interface between the gate electrode and the gate insulating film, thereby allowing formation of the semiconductor device that is superior in the NBTI performance.
- the stack of the first polysilicon layer containing the n-type dopant and the second polysilicon layer substantially free of any dopant can be formed by the continuous chemical vapor deposition process with changing the reaction gas.
- the gate insulating film with the uniform thickness can be disposed over the n-MOS transistor region and the p-MOS transistor region.
- the process for forming the thickness-uniform gate insulating film is simpler than the process for forming the thickness-varying gate insulating film.
- the stack of the first and second polysilicon layers do not need any additional process such as a lithography process and an etching process for differentiating the thickness of the gate insulating film.
- the above-described gate electrode and the thickness-uniform gate electrode can allow that the CMOS circuit having high NBTI reliance is formed by the simplified processes.
- FIG. 1 is a fragmentary cross sectional elevation view illustrating a semiconductor device having CMOS circuits in accordance with a first preferred embodiment of the present invention
- FIGS. 2A through 2D are fragmentary cross sectional elevation views illustrating sequential steps involved in a method of forming the semiconductor device shown in FIG. 1 ;
- FIG. 3 is a diagram illustrating variation of the stress-voltage-applying time (t50) over the stress voltage Vgs for each of the semiconductor devices with the CMOS circuits in Example and Comparative Example;
- FIGS. 4A through 4F are fragmentary cross sectional elevation views illustrating conventional semiconductor devices in sequential steps involved in a conventional method of manufacturing the same.
- FIG. 5 is a fragmentary cross sectional elevation view illustrating the conventional semiconductor device that is formed by the conventional manufacturing method shown in FIGS. 4A through 4F .
- FIG. 1 is a fragmentary cross sectional elevation view illustrating a semiconductor device having CMOS circuits in accordance with a first preferred embodiment of the present invention.
- the semiconductor device is provided over a semiconductor substrate 1 .
- the semiconductor device has an n-MOS transistor region 2 a and a p-MOS transistor region 2 b.
- the semiconductor device includes an n-MOS transistor 4 a in the n-MOS transistor region 2 a and a p-MOS transistor 4 b in the p-MOS transistor region 2 b.
- the semiconductor substrate 1 may be made of a semiconductor containing a dopant at a predetermined concentration. In a typical case, the semiconductor substrate 1 may be made of, but is not limited to, silicon. Isolation regions 3 are selectively disposed in an upper region of the semiconductor substrate 1 . The isolation regions 3 isolate the n-MOS transistor region 2 a and the p-MOS transistor region 2 b from each other. The isolation regions 3 isolate the n-MOS transistor 4 a and the p-MOS transistor 4 b from each other. In some cases, the isolation regions 3 can be formed by a shallow trench isolation method.
- a gate insulating film 5 is provided over the n-MOS transistor region 2 a and the p-MOS transistor region 2 b of the semiconductor substrate 1 .
- the gate insulating film 5 may be made of silicon oxide.
- the gate insulating film 5 of silicon oxide can be formed by a thermal oxidation of silicon.
- the n-MOS transistor 4 a is disposed in the n-MOS transistor region 2 a.
- the p-MOS transistor 4 b is disposed in the p-MOS transistor region 2 b.
- the combination of the n-MOS transistor 4 a and the p-MOS transistor 4 b constitutes a CMOS circuit.
- the n-MOS transistor 4 a may include the gate insulating film 5 , a gate electrode 6 a, side walls 8 , a source 7 A, and a drain 7 B.
- the source 7 A has a first diffusion region 7 a and a second diffusion region 7 b.
- the second diffusion region 7 b is a lightly doped region of the source 7 A.
- the drain 7 B has a third diffusion region 7 c and a fourth diffusion region 7 c.
- the fourth diffusion region 7 d is a lightly doped region of the drain 7 B.
- the second and fourth diffusion regions 7 b and 7 d are positioned under the side walls 8 .
- the first and third diffusion regions 7 a and 7 c are positioned outside the second and fourth diffusion regions 7 b and 7 d, respectively.
- the p-MOS transistor 4 b may include the gate insulating film 5 , a gate electrode 6 b, side walls 8 , a source 7 D, and a drain 7 E.
- the source 7 D has a fifth diffusion region 7 e and a sixth diffusion region 7 f.
- the sixth diffusion region 7 f is a lightly doped region of the source 7 D.
- the drain 7 E has a seventh diffusion region 7 g and an eighth diffusion region 7 h.
- the eighth diffusion region 7 h is a lightly doped region of the drain 7 E.
- the sixth and eighth diffusion regions 7 f and 7 h are positioned under the side walls 8 .
- the fifth and seventh diffusion regions 7 e and 7 g are positioned outside the sixth and eighth diffusion regions 7 f and 7 h, respectively.
- the gate electrode 6 a may be made of a polysilicon doped with an n-type dopant.
- the side walls 8 made of an insulator are disposed on the side faces of the gate electrode 6 a.
- the gate electrode 6 a contains the n-type dopant, which may increase the on-current of the n-MOS transistor 4 a.
- the source and drain 7 A and 7 B may be constituted by the n-dopant diffusion layers.
- the n-dopant diffusion layers can be formed by diffusing an n-type dopant in the semiconductor substrate 1 .
- Each of the n-dopant diffusion layers has first and second side edges. The first side edge of the n-dopant diffusion layer is aligned in plain view to the side edge of the gate electrode 6 a. The second side edge of the n-dopant diffusion layer is bounded with the isolation region 3 . The n-dopant diffusion layer extends from the side edge of the isolation region 3 to the position that is aligned in plain view to the side edge of the gate electrode 6 a.
- the n-dopant diffusion layer that constitutes the source 7 A includes the first and second diffusion regions 7 a and 7 b.
- the second diffusion region 7 b is positioned under the side wall 8 .
- the first diffusion region 7 a is disposed between the second diffusion region 7 b and the isolation region 3 .
- the first diffusion region 7 a is greater in depth and dopant concentration than the second diffusion region 7 b.
- the source 7 A has the lightly doped drain structure.
- the n-dopant diffusion layer that constitutes the drain 7 B includes the third and fourth diffusion regions 7 c and 7 d.
- the fourth diffusion region 7 d is positioned under the side wall 8 .
- the third diffusion region 7 c is disposed between the fourth diffusion region 7 d and the isolation region 3 .
- the third diffusion region 7 c is greater in depth and dopant concentration than the fourth diffusion region 7 d.
- the drain 7 B has the lightly doped drain structure.
- the lightly doped drain structures of the source and drain 7 A and 7 B can relax field concentration near the drain 7 B. Relaxation of the field concentration can prevent generation of hot carrier, wherein the hot carrier generation is caused by the field concentration. Prevision of the hot carrier generation can prevent deterioration of performances such as threshold variation of the semiconductor device, wherein the threshold variation is caused by the hot carrier.
- the n-MOS transistor 4 a is configured so that a gate voltage is applied to the gate electrode 6 a under application of a bias voltage to between the source and drain 7 A and 7 B, leading to appearance of an n-channel region through which electron can move between the source and drain 7 A and 7 B.
- the n-channel region is adjacent to the gate insulating film 5 .
- the n-channel region extends between the second and fourth diffusion regions 7 b and 7 d.
- the gate electrode 6 b may typically be made of a polysilicon-based conductive material doped with a p-type dopant.
- the gate electrode 6 b contains the p-type dopant, which may increase the on-current of the p-MOS transistor 4 b.
- the gate electrode 6 b may also contain, in addition to the p-type dopant, an n-type dopant in at least a part adjacent to the gate insulating film 5 .
- the gate electrode 6 b may include a first part and a remaining part thereof. The first part is adjacent to the gate insulating film 5 .
- the first part of the gate electrode 6 b is disposed between the gate insulating film 5 and the remaining part of the gate electrode 6 b.
- the first part of the gate electrode 6 b contains at least the n-type dopant. Namely, the first part of the gate electrode 6 b contains the n-type dopant in addition to the p-type dopant.
- the remaining part of the gate electrode 6 b contains at least the p-type dopant.
- the first part of the gate electrode 6 b is higher in n-type dopant concentration than the remaining part of the gate electrode 6 b.
- the gate electrode 6 b has the first part that contains the n-type dopant.
- the first part is adjacent to the gate insulating film 5 .
- the n-type dopant in the first part of the gate electrode 6 b can prevent that application of a stress voltage to the gate electrode 6 b hurts the p-MOS transistor 4 b.
- the first part of the gate electrode 6 b can prevent that continuous application of a stress voltage to the gate electrode 6 b causes malfunction of the semiconductor device.
- the first part of the gate electrode 6 b can ensure high reliance to the NBTI.
- the gate electrode 6 b may have a stacked structure which includes lower and upper layers 6 c and 6 d.
- the lower layer 6 c of the gate electrode 6 b contains an n-type dopant in addition to the p-type dopant.
- the upper layer 6 d of the gate electrode 6 b may contain almost only the p-type dopant.
- the upper layer 6 d may be almost free of any n-type dopant.
- the gate electrode 6 b has the lower layer 6 c that contains the n-type dopant.
- the gate electrode 6 b is adjacent to the gate insulating film 5 .
- the n-type dopant in the lower layer 6 c of the gate electrode 6 b can prevent that application of a stress voltage to the gate electrode 6 b hurts the p-MOS transistor 4 b.
- the lower layer 6 c of the gate electrode 6 b can prevent that continuous application of a stress voltage to the gate electrode 6 b causes malfunction of the semiconductor device.
- the lower layer 6 c of the gate electrode 6 b can ensure high reliance to the NBTI.
- the lower layer 6 c that contains the n-type dopant in addition to the p-type dopant may preferably have a thickness of about 30 nanometers, which ensures improvement in the reliance of the NBTI of the p-MOS transistor 4 b.
- the adjacent portion of the gate electrode 6 b that is adjacent to the gate insulating film 5 contains the n-type dopant in addition to the p-type dopant.
- the adjacent portion of the gate electrode 6 b has the thickness of about 30 nanometers.
- the compositional ratio of n-type dopant to p-type dopant in the adjacent portion may be preferably in the range of 10% to 40%, and more preferably in the range of 30% to 40%. When the compositional ratio of n-type dopant to p-type dopant of the in the lower layer 6 c is less than 10%, it is possible that sufficient improvement in the reliance of the NBTI is not obtained.
- compositional ratio of n-type dopant to p-type dopant of the in the lower layer 6 c is more than 40%, it is possible that the performances such as the on-current of the p-MOS transistor 4 b are deteriorated.
- the side walls 8 made of an insulator are disposed on the side faces of the gate electrode 6 b.
- the source and drain 7 D and 7 E may be constituted by the p-dopant diffusion layers.
- the p-dopant diffusion layers can be formed by diffusing a p-type dopant in the semiconductor substrate 1 .
- Each of the p-dopant diffusion layers has first and second side edges. The first side edge of the p-dopant diffusion layer is aligned in plain view to the side edge of the gate electrode 6 b. The second side edge of the p-dopant diffusion layer is bounded with the isolation region 3 .
- the p-dopant diffusion layer extends from the side edge of the isolation region 3 to the position that is aligned in plain view to the side edge of the gate electrode 6 b.
- the p-dopant diffusion layer that constitutes the source 7 D includes the fifth and sixth diffusion regions 7 e and 7 f.
- the sixth diffusion region 7 f is positioned under the side wall 8 .
- the fifth diffusion region 7 e is disposed between the sixth diffusion region 7 f and the isolation region 3 .
- the fifth diffusion region 7 e is greater in depth and dopant concentration than the sixth diffusion region 7 f.
- the source 7 D has the lightly doped drain structure.
- the p-dopant diffusion layer that constitutes the drain 7 E includes the seventh and eighth diffusion regions 7 g and 7 h.
- the eighth diffusion region 7 h is positioned under the side wall 8 .
- the seventh diffusion region 7 g is disposed between the eighth diffusion region 7 h and the isolation region 3 .
- the seventh diffusion region 7 g is greater in depth and dopant concentration than the eighth diffusion region 7 h.
- the drain 7 E has the lightly doped drain structure.
- the lightly doped drain structures of the source and drain 7 D and 7 E can relax field concentration near the drain 7 E. Relaxation of the field concentration can prevent generation of hot carrier, wherein the hot carrier generation is caused by the field concentration. Prevision of the hot carrier generation can prevent deterioration of performances such as threshold variation of the semiconductor device, wherein the threshold variation is caused by the hot carrier.
- the p-MOS transistor 4 b is configured so that a gate voltage is applied to the gate electrode 6 b under application of a bias voltage to between the source and drain 7 D and 7 E, leading to appearance of a p-channel region through which electron can move between the source and drain 7 D and 7 E.
- the p-channel region is adjacent to the gate insulating film 5 .
- the p-channel region extends between the sixth and eighth diffusion regions 7 f and 7 h.
- An inter-layer insulator 9 extends over the gate insulating film 5 and the gate electrodes 6 a and 6 b with the side walls 8 .
- Contact holes 10 penetrate the inter-layer insulator 9 and the gate insulating film 5 .
- the contact holes 10 reach the first, third, fifth and seventh diffusion regions 7 a, 7 c, 7 e and 7 g.
- Contact plugs 11 fill up the contact holes 10 .
- the contact plugs 11 penetrate the inter-layer insulator 9 and the gate insulating film 5 .
- the contact plugs 11 contact the first, third, fifth and seventh diffusion regions 7 a, 7 c, 7 e and 7 g.
- the contact plugs 11 contact the source and drain 7 A and 7 B of the n-MOS transistor 4 a and the source and drain 7 D and 7 E of the p-MOS transistor 4 b.
- Interconnections 12 extend over the inter-layer insulator 9 and the contact plugs 11 .
- the interconnections 12 contact the contact plugs 11 so that the interconnections 12 are electrically connected through the contact plugs 11 to the first, third, fifth and seventh diffusion regions 7 a, 7 c, 7 e and 7 g.
- the interconnections 12 are electrically connected through the contact plugs 11 to the source and drain 7 A and 7 B of the n-MOS transistor 4 a and the source and drain 7 D and 7 E of the p-MOS transistor 4 b.
- the gate electrodes 6 a and 6 b are also connected through contact plugs to interconnections, wherein the contact plugs and the interconnections are not illustrated.
- a passivation film 13 is formed over the interconnections 12 and the inter-layer insulator 9 , thereby completing a semiconductor device having a CMOS circuit.
- FIGS. 2A through 2D are fragmentary cross sectional elevation views illustrating sequential steps involved in a method of forming the semiconductor device shown in FIG. 1 .
- a semiconductor substrate 1 is prepared.
- a shallow trench isolation process is carried out to selectively form isolation regions 3 in a shallow region of the semiconductor substrate 1 , thereby defining an n-MOS transistor region 2 a and a p-MOS transistor region 2 b.
- a thermal oxidation process is then carried out to form a gate insulating film 5 over the surface of the semiconductor substrate 1 and the isolation regions 3 .
- the gate insulating film 5 has a thickness in the range of 1 nanometer to 10 nanometers.
- a chemical vapor deposition process is carried out to form a first polysilicon layer 14 over the gate insulating film 5 .
- the first polysilicon layer 14 is doped with an n-type dopant.
- the first polysilicon layer 14 is the n-doped polysilicon layer.
- the first polysilicon layer 14 has a thickness in the range of 10 nanometers to 50 nanometers.
- a second polysilicon layer 15 that is substantially free of any dopant is formed over the first polysilicon layer 14 .
- the second polysilicon layer 15 is the non-doped polysilicon layer.
- the second polysilicon layer 15 has a thickness in the range of 50 nanometers to 100 nanometers.
- a stack of the first and second polysilicon layers 14 and 15 is formed over the gate insulating film 5 .
- concentration of the n-type dopant of the first polysilicon layer 14 will be described later.
- the ratio in thickness of the first polysilicon layer 14 to the second polysilicon layer 15 will also be described later.
- a resist film is applied on the second polysilicon layer 15 .
- a lithography process is carried out to form a first resist pattern 16 .
- the first resist pattern 16 is a pattern for forming gate electrodes of an n-MOS transistor 4 a and a p-MOS transistor 4 b.
- a dry etching process is carried out using the first resist pattern 16 as a mask to selectively remove the stack of the first and second polysilicon layers 14 and 15 , thereby forming gate structures in the n-MOS transistor region 2 a and the p-MOS transistor region 2 b.
- Each gate structure is constituted by the stack of the remaining parts of the first and second polysilicon layers 14 and 15 .
- the first resist pattern 16 is removed.
- the first resist pattern 16 is removed.
- a resist film is applied on the gate structures and the gate insulating film 5 over the n-MOS transistor region 2 a and the p-MOS transistor region 2 b.
- a lithography process is carried out to form a second resist pattern which has an opening. The opening of the second resist pattern is positioned over the n-MOS transistor region 2 a.
- a first n+-ion implantation process is carried out using the second resist pattern as a mask to selectively introduce the n+-ions into the n-MOS transistor region 2 a of the semiconductor substrate, except under the gate structure in the n-MOS transistor region 2 a, and also into the gate structure in the n-MOS transistor region 2 a.
- the second resist pattern is removed.
- a new resist film is applied on the gate structures and the gate insulating film 5 over the n-MOS transistor region 2 a and the p-MOS transistor region 2 b.
- a lithography process is carried out to form a third resist pattern which has an opening. The opening of the third resist pattern is positioned over the p-MOS transistor region 2 b.
- a first p+-ion implantation process is carried out using the third resist pattern as a mask to selectively introduce the p+-ions into the p-MOS transistor region 2 b of the semiconductor substrate, except under the gate structure in the p-MOS transistor region 2 b, and also into the gate structure in the p-MOS transistor region 2 b.
- the third resist pattern is removed.
- the n-type dopant is introduced into the first and second polysilicon layers 14 and 15 and the source and drain regions 7 A and 7 B in the semiconductor substrate 1 .
- the p-type dopant is introduced into the first and second polysilicon layers 14 and 15 and the source and drain regions 7 D and 7 E in the semiconductor substrate 1 .
- Side walls 8 are formed on the side faces of the first and second polysilicon layers 14 and 15 in the n-MOS transistor region 2 a and the p-MOS transistor region 2 b.
- the side walls 8 have a thickness in the range of 5 nanometers to 20 nanometers.
- the side walls 8 may be made of an insulator such as oxide or nitride.
- a resist film is applied on the gate structures with the side walls 8 and the gate insulating film 5 over the n-MOS transistor region 2 a and the p-MOS transistor region 2 b.
- a lithography process is carried out to form a fourth resist pattern which has an opening. The opening of the fourth resist pattern is positioned over the n-MOS transistor region 2 a.
- a second n+-ion implantation process is carried out using the fourth resist pattern as a mask to selectively introduce the n+-ions into the n-MOS transistor region 2 a of the semiconductor substrate, except under the gate structure in the n-MOS transistor region 2 a, and also into the gate structure in the n-MOS transistor region 2 a.
- the gate electrode 6 a and the source and drain 7 A and 7 B are formed in the n-MOS transistor region 2 a.
- the fourth resist pattern is removed.
- a new resist film is applied on the gate structures and the gate insulating film 5 over the n-MOS transistor region 2 a and the p-MOS transistor region 2 b.
- a lithography process is carried out to form a fifth resist pattern which has an opening.
- the opening of the fifth resist pattern is positioned over the p-MOS transistor region 2 b.
- a second p+-ion implantation process is carried out using the fifth resist pattern as a mask to selectively introduce the p+-ions into the p-MOS transistor region 2 b of the semiconductor substrate, except under the gate structure in the p-MOS transistor region 2 b, and also into the gate structure in the p-MOS transistor region 2 b.
- the gate electrode 6 b and the source and drain 7 D and 7 E are formed in the p-MOS transistor region 2 a.
- the fifth resist pattern is removed.
- the first polysilicon layer 14 has been doped with the n-type dopant before the first and second n+-ion implantation processes are carried out.
- the first polysilicon layer 14 is undoped before the first and second n+-ion implantation processes are carried out.
- the first polysilicon layer 14 of the gate electrode 6 a contains a total amount of n-type dopant that has pre-existed in the first polysilicon layer 14 and n-type dopant that is newly introduced by the first and second n+-ion implantation processes.
- the second polysilicon layer 15 of the gate electrode 6 a contains a total amount of n-type dopant that is newly introduced by the first and second n+-ion implantation processes.
- the first polysilicon layer 14 of the gate electrode 6 a is higher in n-type dopant concentration than the second polysilicon layer 15 of the gate electrode 6 a.
- the second and fourth diffusion regions 7 b and 7 d contain an amount of the n-type dopant that has been introduced by the first n+-ion implantation process.
- the first and third diffusion regions 7 a and 7 c contain a total amount of the n-type dopant that has been introduced by the first and second n+-ion implantation processes.
- the first and third diffusion regions 7 a and 7 c are higher in n-type dopant concentration than the second and fourth diffusion regions 7 b and 7 d.
- the source 7 A has the first diffusion region 7 a and the second diffusion region 7 b that is lower in n-type dopant concentration than the first diffusion region 7 a.
- the source 7 A has the lightly doped drain structure.
- the drain 7 B has the third diffusion region 7 c and the fourth diffusion region 7 d that is lower in n-type dopant concentration than the third diffusion region 7 c.
- the drain 7 B has the lightly doped drain structure.
- the first polysilicon layer 14 as the lower layer 6 c of the gate electrode 6 b contains an amount of n-type dopant that has pre-existed in the first polysilicon layer 14 and a total amount of p-type dopant that is newly introduced by the first and second p+-ion implantation processes.
- the first polysilicon layer 14 as the lower layer 6 c of the gate electrode 6 b contains not only the p-type dopant that has been introduced by the first and second p+-ion implantation processes but the n-type dopant that has pre-existed therein.
- the second polysilicon layer 15 as the upper layer 6 d of the gate electrode 6 b contains a total amount of p-type dopant that is introduced by the first and second p+-ion implantation processes.
- the first polysilicon layer 14 as the lower layer 6 c of the gate electrode 6 b is higher in n-type dopant concentration than the second polysilicon layer 15 as the upper layer 6 d of the gate electrode 6 b.
- the sixth and eighth diffusion regions 7 f and 7 h contain an amount of the p-type dopant that has been introduced by the first p+-ion implantation process.
- the fifth and seventh diffusion regions 7 e and 7 g contain a total amount of the p-type dopant that has been introduced by the first and second p+-ion implantation processes.
- the fifth and seventh diffusion regions 7 e and 7 g are higher in p-type dopant concentration than the sixth and eighth diffusion regions 7 f and 7 h.
- the source 7 D has the fifth diffusion region 7 e and the sixth diffusion region 7 f that is lower in p-type dopant concentration than the fifth diffusion region 7 e.
- the source 7 D has the lightly doped drain structure.
- the drain 7 E has the seventh diffusion region 7 g and the eighth diffusion region 7 h that is lower in p-type dopant concentration than the seventh diffusion region 7 g.
- the drain 7 E has the lightly doped drain structure.
- An anneal process is carried out to activate the n-type dopant in the gate electrode 6 a and the source and drain 7 A and 7 B as well as activate the p-type dopant in the gate electrode 6 b and the source and drain 7 D and 7 E, provided that the gate electrode 6 b has a portion adjacent to the gate insulating film 5 , and this adjacent portion contains more n-type dopant than p-type dopant.
- the temperature of the anneal is preferably in the range of 850° C. to 1050° C.
- the lower layer 6 c of the gate electrode 6 b contains the n-type dopant in addition to the p-type dopant and has the thickness of about 30 nanometers.
- the compositional ratio of n-type dopant to p-type dopant of the adjacent portion of the gate electrode 6 b may be preferably in the range of 10% to 40%, and more preferably in the range of 30% to 40%.
- the compositional ratio of n-type dopant to p-type dopant of the in the lower layer 6 c is less than 10%, it is possible that sufficient improvement in the reliance of the NBTI is not obtained.
- compositional ratio of n-type dopant to p-type dopant of the in the lower layer 6 c is more than 40%, it is possible that the performances such as the on-current of the p-MOS transistor 4 b are deteriorated.
- the concentration of the n-type dopant of the adjacent portion of the gate electrode 6 b might be controllable by controlling the concentration of the n-type dopant of the first polysilicon layer 14 and the thickness of the first polysilicon layer 14 in the process shown in FIG. 2B , wherein the adjacent portion of the gate electrode 6 b is positioned adjacent to the gate insulating film 5 .
- the dose of n-type dopant into the first polysilicon layer 14 may be preferably in the range of 1E13 atoms/cm 2 to 1E15 atoms/cm 2 , and more preferably in the range of 1E13 atoms/cm 2 to 1E14 atoms/cm 2 . If the concentration of n-type dopant of the first polysilicon layer 14 is lower than 1E13 atoms/cm 2 , then the adjacent portion of the gate electrode 6 b has a lower compositional ratio of the n-type dopant to the p-type dopant than the ratio that needs to improve the reliance of the NBTI of the p-MOS transistor 4 b.
- the concentration of n-type dopant of the first polysilicon layer 14 is higher than 1E15 atoms/cm 2 , then the adjacent portion of the gate electrode 6 b has a higher compositional ratio of the n-type dopant to the p-type dopant than the ratio that needs to ensure the performances such as on-current of the p-MOS transistor 4 b.
- the concentration of p-type dopant of the first polysilicon layer 14 may be preferably in the range of 1E19 atoms/cm 3 to 1E21 atoms/cm 3 .
- the ratio in thickness of the first polysilicon layer 14 to the second polysilicon layer 15 may be preferably in the range of 10% to 50%, and more preferably in the range of 10% to 20%. If the ratio in thickness of the first polysilicon layer 14 to the second polysilicon layer 15 is lower than 10%, then the adjacent portion of the gate electrode 6 b has a lower compositional ratio of the n-type dopant to the p-type dopant than the ratio that might need to improve the reliance of the NBTI of the p-MOS transistor 4 b.
- the adjacent portion of the gate electrode 6 b has a higher compositional ratio of the n-type dopant to the p-type dopant than the ratio that needs to ensure the performances such as on-current of the p-MOS transistor 4 b.
- an inter-layer insulator 9 , contact plugs 11 , metal interconnections 12 and a passivation film 13 are formed in the known processes, thereby completing the semiconductor device having the CMOS circuit.
- the p-MOS transistor 6 b has the adjacent portion that is adjacent to the gate insulating film 5 , where the adjacent portion contains n-type dopant in addition to p-type dopant, thereby obtaining the reliance of the NBTI.
- the semiconductor device having the CMOS circuit has the gate insulating film 5 that has a uniform thickness.
- an additional process is a process for forming the first polysilicon layer 14 , in order to obtain the CMOS circuit that is superior in the NBTI reliance.
- the stack of the first and second polysilicon layers 14 and 15 can be formed by the continuous chemical vapor deposition process with changing the reaction gas.
- the gate insulating film 5 with the uniform thickness is disposed over the n-MOS transistor region 2 a and the p-MOS transistor region 2 b.
- the process for forming the thickness-uniform gate insulating film 5 is simpler than the process for forming the thickness-varying gate insulating film.
- the above-described gate electrode 6 b and the thickness-uniform gate electrode 5 can allow that the CMOS circuit having high NBTI reliance is formed by the simplified processes.
- An isolation region was formed on a silicon substrate.
- a thermal oxidation of silicon was carried out to form a gate oxide film having a thickness of 3 nanometers.
- a thermal chemical vapor deposition process was carried out to form an n-doped polysilicon layer over the gate oxide film.
- the n-doped polysilicon layer will be hereinafter referred to as a first polysilicon layer.
- the first polysilicon layer has a thickness of 20 nanometers.
- the first polysilicon layer has a phosphorus concentration of 5E13 atoms/cm 3 .
- a thermal chemical vapor deposition process was carried out to form a non-doped polysilicon layer over the first polysilicon layer, thereby forming a polysilicon stack-layered structure over the gate oxide film.
- the non-doped polysilicon layer will be hereinafter referred to as a second polysilicon layer.
- the second polysilicon layer has a thickness of 60 nanometers.
- a photolithography process and a dry etching process were carried out to pattern the stack-layered structure of the first and second polysilicon layers, thereby forming gate electrode structures for n-MOS transistor and p-MOS transistor.
- a first n+-ion implantation process was carried out at a dose of 3E13 atoms/cm 2 to introduce phosphorus as an n-type dopant into the n-MOS transistor region. Then, a second p+-ion implantation process was carried out at a dose of 3E13 atoms/cm 2 to introduce boron as a p-type dopant into the p-MOS transistor region.
- Side walls were formed on side faces of the gate electrode structures of the first and second polysilicon layers.
- the side walls have a thickness of 20 nanometers.
- a second n+-ion implantation process was carried out at a dose of 3E15 atoms/cm 2 to introduce phosphorus as an n-type dopant into the n-MOS transistor region. Then, a second p+-ion implantation process was carried out at a dose of 3E15 atoms/cm 2 to introduce boron as a p-type dopant into the p-MOS transistor region, thereby forming gate electrodes and source and drain regions in the n-MOS transistor region and the p-MOS transistor region.
- the gate electrode in the p-MOS transistor region has an adjacent portion that is adjacent to the gate oxide film.
- the adjacent portion has a thickness of 30 nanometers.
- the adjacent portion of the gate electrode in the p-MOS transistor region has an n-type dopant concentration of 5E19 atoms/cm 3 .
- An inter-layer insulator, contact plugs, metal interconnections and a passivation film were formed in the known processes, thereby completing the semiconductor device having the CMOS circuit.
- the semiconductor device having the CMOS circuit was formed in the same processes, provided that a single layered structure of a non-doped polysilicon layer was formed by a thermal chemical vapor deposition method, instead of the stack-layered structure of the first and second polysilicon layers.
- Example and Comparative Example Each type of the semiconductor devices with the CMOS circuits in Example and Comparative Example was examined in NBTI reliance as follows.
- a stress voltage Vgs was applied to the gate electrode of the p-MOS transistor to confirm a stress-voltage-applying time (t50) that it takes to cause malfunction at 50% of the CMOS circuits under application of the stress voltage.
- Application of a stress voltage Vgs to the gate electrode of the p-MOS transistor for the stress-voltage-applying time (t50) causes at 50% malfunction of the CMOS circuits. This test was carried out by varying the stress voltage level.
- FIG. 3 is a diagram illustrating variation of the stress-voltage-applying time (t50) over the stress voltage Vgs for each of the semiconductor devices with the CMOS circuits in Example and Comparative Example.
- the real line represents the voltage-dependency of the stress-voltage-applying time (t50) of the semiconductor device in accordance with Example.
- the dotted line represents the voltage-dependency of the stress-voltage-applying time (t50) of the semiconductor device in accordance with Comparative Example.
- the semiconductor device in accordance with Example is longer in the stress-voltage-applying time (t50) than the semiconductor device in accordance with Comparative Example. This demonstrates that the semiconductor device in accordance with Example is more unlikely to cause malfunction than the semiconductor device in accordance with Comparative Example.
- the n-dopant-containing adjacent portion of the gate electrode of the p-MOS transistor can improve the NBTI reliance as much as the gate insulating film of the p-MOS transistor is thicker than the gate insulating film of the n-MOS transistor.
- the above-described structure of the gate electrode can be applied to the semiconductor device including the n-MOS transistor and the p-MOS transistor.
Abstract
Description
- This application is a continuation of application Ser. No. 12/108,554 filed on Apr. 24, 2008 which claims foreign priority to Japanese Application No. 2007-120317 filed on Apr. 27, 2007. The entire contents of each of the applications are hereby incorporated by reference.
- 1. Field of the Invention
- The present invention generally relates to a semiconductor device and a method of forming the same. More specifically, the present invention relates to a semiconductor device that is used for a CMOS circuit that includes n-MOS transistors and p-MOS transistors.
- Priority is claimed on Japanese Patent Application No. 2007-120317, filed Apr. 27, 2007, the content of which is incorporated herein by reference.
- 2. Description of the Related Art
- All patents, patent applications, patent publications, scientific articles, and the like, which will hereinafter be cited or identified in the present application, will hereby be incorporated by reference in their entirety in order to describe more fully the state of the art to which the present invention pertains.
- The semiconductor integrated circuit has an integration of a large number of MOS field effect transistors. The MOS field effect transistors that are integrated on the semiconductor integrated circuit are classified into n-MOS transistors and p-MOS transistors. Most of the n-MOS transistors and p-MOS transistors constitute CMOS circuits. Scaling down of the n-MOS transistors and p-MOS transistors are necessary for improving the high speed performances of the semiconductor device or the CMOS circuits and also for realizing large scale integration.
- Scaling down of the n-MOS transistors and p-MOS transistors needs reduction in thickness of gate insulating films in those transistors. Reduction in thickness of the gate insulating film may raise the problem with negative bias temperature instability (hereinafter referred to as NBTI) of the p-MOS transistors, resulting in decrease of the reliability of the p-MOS transistors. NBTI is the phenomenon that a negative bias voltage (Vg<0) as a stress voltage is continuously applied to the gate electrode of the p-MOS transistor, thereby increasing the threshold voltage of the p-MOS transistor and decreasing the on-current. This phenomenon may cause malfunction of the circuits. The problem in reliability with the NBTI provides the bars to reduction in thickness of the gate insulating film of the p-MOS transistor and also to improvement in high speed performance of the CMOS circuit.
- In order to countermeasure the NBTI problem, it was proposed to increase the thickness (Tox(PMOS)) of the gate insulating film of the p-MOS transistor so as to reduce the field applied to the gate insulating film of the p-MOS transistor, while unchanging the thickness (Tox(NMOS)) of the gate insulating film of the n-MOS transistor. Forming thickness-difference gate insulating films of the n-MOS transistor and the p-MOS transistor needs additional lithography process, for example, multi-oxide photo-resist process, resulting in increasing the number of manufacturing process for the semiconductor device.
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FIGS. 4A through 4F are fragmentary cross sectional elevation views illustrating conventional semiconductor devices in sequential steps involved in a conventional method of manufacturing the same.FIG. 5 is a fragmentary cross sectional elevation view illustrating the conventional semiconductor device that is formed by the conventional manufacturing method shown inFIGS. 4A through 4F . The conventional semiconductor device has an n-MOS transistor and a p-MOS transistor. The n-MOS transistor has a second gate insulating film of a second thickness Tox(NMOS). The p-MOS transistor has a first gate insulating film of a first thickness Tox(PMOS). The first thickness Tox(PMOS) is greater than the second thickness Tox(NMOS). - With reference to
FIG. 4A ,isolation regions 102 are selectively formed in an upper region of asilicon substrate 101, thereby defining active regions on thesilicon substrate 101. A first gateinsulating film 103 is formed over the active regions on thesilicon substrate 101 and theisolation regions 102. The firstgate insulating film 103 has a first thickness in the range of 3 nanometers to 10 nanometers. - With reference to
FIG. 4B , thesilicon substrate 101 has an n-MOS transistor region 104 a and a p-MOS transistor region 104 b. A first resist film is applied on the first gateinsulating film 103. A photo-lithography process is carried out to form afirst resist pattern 105 in the p-MOS transistor region 104 b. Thefirst resist pattern 105 has an opening over the n-MOS transistor region 104 a. A wet etching process is carried out using thefirst resist pattern 105 as a mask to selectively remove the firstgate insulating film 103 in the n-MOS transistor region 104 a, while leaving the first gateinsulating film 103 in the p-MOS transistor region 104 b. The surface of the n-MOS transistor region 104 a of thesilicon substrate 101 is shown. The wet etching process is carried out using an HF-based etchant. - With reference to
FIG. 4C , thefirst resist pattern 105 is removed. A thermal oxidation process is carried out to selectively form a second gateinsulating film 106 on the n-MOS transistor region 104 a of thesilicon substrate 101. The second gateinsulating film 106 has a second thickness in the range of 1 nanometer to 3 nanometers. The first gateinsulating film 103 is formed in the p-MOS transistor region 104 b. The second gateinsulating film 106 is formed in the n-MOS transistor region 104 a. The first gateinsulating film 103 on the p-MOS transistor region 104 b is greater in thickness than the second gateinsulating film 106 on the n-MOS transistor region 104 a. - With reference to
FIG. 4D , a thermal chemical vapor deposition process is carried out to form anon-doped polysilicon layer 108 over the first gateinsulating film 103 on the p-MOS transistor region 104 b and the second gateinsulating film 106 on the n-MOS transistor region 104 a. Thenon-doped polysilicon layer 108 has a thickness in the range of 50 nanometers to 100 nanometers. - With reference to
FIG. 4E , a second photo-resist film is applied on the non-dopedpolysilicon layer 108. A lithography process is carried out to form asecond resist pattern 111 on the non-dopedpolysilicon layer 108. A dry etching process is carried out using thesecond resist pattern 111 as a mask to selectively remove the non-dopedpolysilicon layer 108, thereby forminggate electrodes gate insulating films MOS transistor region 104 a and the p-MOS transistor region 104 b. - With reference to
FIG. 4F , thesecond resist pattern 111 is removed from thegate electrodes 108. A first ion-implantation of n-type dopant is carried out using thegate electrode 110 a as a mask to selectively introduce the n-type dopant into the n-MOS transistor region 104 a of thesilicon substrate 101, thereby selectively forming n-doped regions in the n-MOS transistor region 104 a. A second ion-implantation of p-type dopant is carried out using thegate electrode 110 b as a mask to selectively introduce the p-type dopant into the p-MOS transistor region 104 b of thesilicon substrate 101, thereby selectively forming p-doped regions in the p-MOS transistor region 104 b. - Side
wall insulating films 113 are selectively formed on the side walls of thegate electrodes wall insulating films 113 have a thickness in the range of 5 nanometers to 20 nanometers. The sidewall insulating films 113 may be made of an insulator such as oxide or nitride. - A third ion-implantation of n-type dopant is carried out using the
side walls 113 and thegate electrode 110 a as a mask to selectively introduce the n-type dopant into the n-MOS transistor region 104 a of thesilicon substrate 101, thereby selectively forming n-type source and drainregions MOS transistor region 104 a. The third ion-implantation is carried out at higher acceleration energy than that of the first ion-implantation so as to introduce the n-type dopant into the deeper level than the n-doped regions, thereby forming the n-type source and drainregions - A fourth ion-implantation of p-type dopant is carried out using the
side walls 113 and thegate electrode 110 b as a mask to selectively introduce the p-type dopant into the p-MOS transistor region 104 b of thesilicon substrate 101, thereby selectively forming p-type source and drainregions MOS transistor region 104 b. The fourth ion-implantation is carried out at higher acceleration energy than that of the second ion-implantation so as to introduce the p-type dopant into the deeper level than the p-doped regions, thereby forming the p-type source and drainregions - The
gate electrode 110 a in the n-MOS transistor region 104 a is doped with the n-type dopant by the first and third ion-implantations. Thegate electrode 110 b in the p-MOS transistor region 104 b is doped with the p-type dopant by the second and fourth ion-implantations. - An annealing process is carried out to activate the n-type dopant and the p-type dopant in the n-type source and drain
regions regions - With reference to
FIG. 5 , aninter-layer insulator 114 is formed over the first and secondgate insulating films gate electrodes wall insulating films 113. Contact holes are formed in theinter-layer insulator 114. The contact holes penetrate theinter-layer insulator 114. The contact holes reach the n-type source and drainregions regions gate electrodes inter-layer insulator 114. The contact plugs 115 penetrate theinter-layer insulator 114. The contact plugs 115 contact the n-type source and drainregions regions gate electrodes Metal interconnections 116 are formed over theinter-layer insulator 114 and the contact plugs 115. Themetal interconnections 116 contact the contact plugs 115 so that themetal interconnections 116 are electrically connected through the contact plugs 115 to the n-type source and drainregions regions gate electrodes passivation film 117 is formed over themetal interconnections 116 and theinter-layer insulator 114, thereby completing a semiconductor device having a CMOS circuit. - Japanese Unexamined Patent Application, First Publication, No. 2-265248 discloses the source and drain regions having the lightly doped drain structure that can solve the problems that scaling down of the transistors causes field concentration near the drain thereby generating hot carriers and varying the threshold of the transistor.
- As described above, the above-described conventional semiconductor device having the CMOS circuit includes the n-MOS transistor having the second
gate insulating film 106 and the p-MOS transistor having the firstgate insulating film 103. The n-MOS transistor has the secondgate insulating film 106 of the second thickness Tox(NMOS). The p-MOS transistor has the first gate insulating film of the first thickness Tox(PMOS). The first thickness Tox(PMOS) is greater than the second thickness Tox(NMOS). Forming the first and secondgate insulating films gate insulating film 103 is formed over the n-MOS transistor region 104 a and the p-MOS transistor region 104 b. The first resistpattern 105 is formed over thegate insulating film 103 by the lithography process. The first resistpattern 105 has an opening that is positioned in the n-MOS transistor region 104 a. The firstgate insulating film 103 is selectively removed from the n-MOS transistor region 104 a by using the first resistpattern 105 as a mask, while leaving the firstgate insulating film 103 in the p-MOS transistor region 104 b. The secondgate insulating film 106 is selectively formed on the n-MOS transistor region 104 a. The above-described additional processes increase the number of processes for manufacturing the semiconductor device. - Taking into account only the countermeasure to the NBTI problem of the p-MOS transistor, it could be proposed that, without carrying out any additional lithography processes, a single gate insulating film with a larger uniform thickness is formed over the n-
MOS transistor region 104 a and the p-MOS transistor region 104 b. The thick gate insulating film on the n-MOS transistor region 104 a may excessively reduce the on-current of the n-MOS transistor. - In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved semiconductor device and/or method of forming the same. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.
- Accordingly, it is a primary object of the present invention to provide a semiconductor device including CMOS circuits.
- It is another object of the present invention to provide a semiconductor device including CMOS circuits, which has a high reliability in NBTI.
- It is a further object of the present invention to provide a semiconductor device including CMOS circuits, which does not need a process for etching the gate insulating film.
- It is a still further object of the present invention to provide a semiconductor device including CMOS circuits, which can be formed by simplified processes.
- It is yet a further object of the present invention to provide a method of forming a semiconductor device including CMOS circuits.
- It is an additional object of the present invention to provide a method of forming a semiconductor device including CMOS circuits, which has a high reliability in NBTI.
- It is another object of the present invention to provide a method of forming a semiconductor device including CMOS circuits, which does not need a process for etching the gate insulating film.
- It is still another object of the present invention to provide a method of forming a semiconductor device including CMOS circuits by simplified processes.
- In accordance with a first aspect of the present invention, a semiconductor device may include, but is not limited to, an n-MOS transistor, and a p-MOS transistor. The p-MOS transistor may include, but is not limited to, a gate insulating film and a gate electrode. The gate electrode may have an adjacent portion that is adjacent to the gate insulating film. The adjacent portion may include a polysilicon that contains an n-type dopant and a p-type dopant.
- The gate electrode containing the adjacent portion of the p-MOS transistor can ensure that the p-MOS transistor be superior in NBTI reliance. In other words, the gate electrode containing the adjacent portion of the p-MOS transistor can improve the NBTI lifetime without carrying out any additional process for the gate insulating film. The gate electrode containing the adjacent portion can provide substantially similar effects as when the gate insulating film of the p-MOS transistor is thicker than the gate insulating film of the n-MOS transistor. The gate electrode containing the adjacent portion can increase the flexibility of designing the gate insulating film such as the thickness thereof. The increased flexibility can make it easier to obtain improved performance of the transistors.
- In some cases, the adjacent portion has a thickness of at least 30 nanometers from the interface between the gate electrode and the gate insulating film, thereby improving the certainty of the NBTI reliance of the p-MOS transistor. The adjacent portion with the thickness of at least 30 nanometers contains the n-type dopant, which can reduce or prevent that the p-type dopant such as boron as introduced in the gate electrode of the p-MOS transistor is thermally diffused through the gate insulating film to the semiconductor substrate, while the heat treatment is carried out. This reduction or prevention can improve the NBTI reliance.
- In some cases, it is preferable that the adjacent portion having the thickness of at least 30 nanometers from the interface between the gate electrode and the gate insulating film has a compositional ratio of the n-type dopant to the p-type dopant in the range of 10% to 40%. The adjacent portion with this compositional ratio can ensure good performance such as on-current of the p-MOS transistor and improvement of the NBTI reliance.
- The gate electrode may have a stacked structure that includes a lower portion that includes the adjacent portion, and an upper portion over the lower portion. The lower portion may include the polysilicon containing the n-type dopant and the p-type dopant. The upper portion contains the polysilicon containing the p-type dopant.
- In accordance with a second aspect of the present invention, a method of forming a semiconductor device including an n-MOS transistor and a p-MOS transistor may include, but is not limited to, the following processes. A gate insulating film may be formed over an n-MOS transistor region and a p-MOS transistor region of a semiconductor substrate. A first polysilicon layer may be formed over the gate insulating film, the first polysilicon layer containing an n-type dopant. A second polysilicon layer may be formed over the first polysilicon layer. The second polysilicon layer may be substantially free of any dopant. The stack of the first and second polysilicon layers is patterned to form gate electrode structures in the n-MOS transistor region and the p-MOS transistor region. A first ion-implantation process of an n-type dopant to the n-MOS transistor region may be carried out, thereby introducing the n-type dopant into the first and second polysilicon layers in the n-MOS transistor region and into source and drain formation regions of the semiconductor substrate in the n-MOS transistor region. A second ion-implantation process of a p-type dopant to the p-MOS transistor region may be carried out, thereby introducing the p-type dopant into the first and second polysilicon layers in the p-MOS transistor region and into source and drain formation regions of the semiconductor substrate in the p-MOS transistor region.
- The semiconductor device that is superior in the NBTI reliance can be formed by the simple processes.
- In some cases, the method of forming the semiconductor device may further include the following processes. Side walls may be formed on side faces of the gate electrode structures in the n-MOS transistor region and the p-MOS transistor region, after carrying out the first and second ion-implantation processes. A third ion-implantation process of an n-type dopant to the n-MOS transistor region may be carried out using the side walls as a mask, thereby introducing the n-type dopant into the first and second polysilicon layers in the n-MOS transistor region and into the source and drain formation regions of the semiconductor substrate in the n-MOS transistor region. A fourth ion-implantation process of a p-type dopant to the p-MOS transistor region may be carried out using the side walls as a mask, thereby introducing the p-type dopant into the first and second polysilicon layers in the p-MOS transistor region and into the source and drain formation regions of the semiconductor substrate in the p-MOS transistor region.
- This structure can relax the field concentration in the vicinity of the drain of each of the n-MOS transistor and the p-MOS transistor, thereby obtaining good performance of those transistors.
- In some cases, the method of forming the semiconductor device may further include the following processes. An annealing process for the semiconductor substrate may be carried out, after carrying out the third and fourth ion-implantation processes, so that the n-type dopant is localized near the interface between the gate electrode and the gate insulating film.
- In some cases, it may be preferable that the first ion-implantation process is carried out at a dose in the range of 1E13 atoms/cm2 to 1E15 atoms/cm2. The concentration of the n-type dopant of the first polysilicon layer may be preferably in the range of 1E19 atoms/cm3 to 1E21 atoms/cm3. The semiconductor device having superior NBTI reliance of the p-MOS transistor can be formed.
- In accordance with the present invention, the semiconductor device includes the n-MOS transistor and the p-MOS transistor. The p-MOS transistor may include a gate insulating film and a gate electrode. The gate electrode may have an adjacent portion that is adjacent to the gate insulating film. The adjacent portion may include a polysilicon that contains an n-type dopant and a p-type dopant.
- The gate electrode containing the adjacent portion of the p-MOS transistor can ensure that even if the gate insulating film of the n-MOS transistor has the same thickness as that of the p-MOS transistor, the semiconductor device can have similar performance to that obtained by the semiconductor device in which the gate insulating film of the p-MOS transistor is thicker than the gate insulating film of the n-MOS transistor. The gate electrode containing the adjacent portion of the p-MOS transistor can ensure that the p-MOS transistor be superior in NBTI reliance. The gate electrode containing the adjacent portion can increase the flexibility of designing the gate insulating film such as the thickness thereof. The increased flexibility can make it easier to obtain improved performance of the transistors.
- The gate electrode has a stacked structure that includes the first polysilicon layer containing the n-type dopant in the vicinity of the interface between the gate electrode and the gate insulating film, thereby allowing formation of the semiconductor device that is superior in the NBTI performance.
- The stack of the first polysilicon layer containing the n-type dopant and the second polysilicon layer substantially free of any dopant can be formed by the continuous chemical vapor deposition process with changing the reaction gas. The gate insulating film with the uniform thickness can be disposed over the n-MOS transistor region and the p-MOS transistor region. The process for forming the thickness-uniform gate insulating film is simpler than the process for forming the thickness-varying gate insulating film. The stack of the first and second polysilicon layers do not need any additional process such as a lithography process and an etching process for differentiating the thickness of the gate insulating film. The above-described gate electrode and the thickness-uniform gate electrode can allow that the CMOS circuit having high NBTI reliance is formed by the simplified processes.
- These and other objects, features, aspects, and advantages of the present invention will become apparent to those skilled in the art from the following detailed descriptions taken in conjunction with the accompanying drawings, illustrating the embodiments of the present invention.
- Referring now to the attached drawings which form a part of this original disclosure:
-
FIG. 1 is a fragmentary cross sectional elevation view illustrating a semiconductor device having CMOS circuits in accordance with a first preferred embodiment of the present invention; -
FIGS. 2A through 2D are fragmentary cross sectional elevation views illustrating sequential steps involved in a method of forming the semiconductor device shown inFIG. 1 ; -
FIG. 3 is a diagram illustrating variation of the stress-voltage-applying time (t50) over the stress voltage Vgs for each of the semiconductor devices with the CMOS circuits in Example and Comparative Example; -
FIGS. 4A through 4F are fragmentary cross sectional elevation views illustrating conventional semiconductor devices in sequential steps involved in a conventional method of manufacturing the same; and -
FIG. 5 is a fragmentary cross sectional elevation view illustrating the conventional semiconductor device that is formed by the conventional manufacturing method shown inFIGS. 4A through 4F . - Selected embodiments of the present invention will now be described with reference to the drawings. It will be apparent to those skilled in the art from this disclosure that the following descriptions of the embodiments of the present invention are provided for illustration only and not for the purpose of limiting the invention as defined by the appended claims and their equivalents.
-
FIG. 1 is a fragmentary cross sectional elevation view illustrating a semiconductor device having CMOS circuits in accordance with a first preferred embodiment of the present invention. - The semiconductor device is provided over a semiconductor substrate 1. The semiconductor device has an n-
MOS transistor region 2 a and a p-MOS transistor region 2 b. The semiconductor device includes an n-MOS transistor 4 a in the n-MOS transistor region 2 a and a p-MOS transistor 4 b in the p-MOS transistor region 2 b. - In some cases, the semiconductor substrate 1 may be made of a semiconductor containing a dopant at a predetermined concentration. In a typical case, the semiconductor substrate 1 may be made of, but is not limited to, silicon.
Isolation regions 3 are selectively disposed in an upper region of the semiconductor substrate 1. Theisolation regions 3 isolate the n-MOS transistor region 2 a and the p-MOS transistor region 2 b from each other. Theisolation regions 3 isolate the n-MOS transistor 4 a and the p-MOS transistor 4 b from each other. In some cases, theisolation regions 3 can be formed by a shallow trench isolation method. - A
gate insulating film 5 is provided over the n-MOS transistor region 2 a and the p-MOS transistor region 2 b of the semiconductor substrate 1. In some cases, thegate insulating film 5 may be made of silicon oxide. In this case, thegate insulating film 5 of silicon oxide can be formed by a thermal oxidation of silicon. - The n-
MOS transistor 4 a is disposed in the n-MOS transistor region 2 a. The p-MOS transistor 4 b is disposed in the p-MOS transistor region 2 b. The combination of the n-MOS transistor 4 a and the p-MOS transistor 4 b constitutes a CMOS circuit. - The n-
MOS transistor 4 a may include thegate insulating film 5, agate electrode 6 a,side walls 8, asource 7A, and adrain 7B. Thesource 7A has afirst diffusion region 7 a and asecond diffusion region 7 b. Thesecond diffusion region 7 b is a lightly doped region of thesource 7A. Thedrain 7B has athird diffusion region 7 c and afourth diffusion region 7 c. Thefourth diffusion region 7 d is a lightly doped region of thedrain 7B. The second andfourth diffusion regions side walls 8. The first andthird diffusion regions fourth diffusion regions - The p-
MOS transistor 4 b may include thegate insulating film 5, agate electrode 6 b,side walls 8, asource 7D, and adrain 7E. Thesource 7D has afifth diffusion region 7 e and asixth diffusion region 7 f. Thesixth diffusion region 7 f is a lightly doped region of thesource 7D. Thedrain 7E has aseventh diffusion region 7 g and aneighth diffusion region 7 h. Theeighth diffusion region 7 h is a lightly doped region of thedrain 7E. The sixth andeighth diffusion regions side walls 8. The fifth andseventh diffusion regions eighth diffusion regions - In the n-
MOS transistor region 2 a, thegate electrode 6 a may be made of a polysilicon doped with an n-type dopant. Theside walls 8 made of an insulator are disposed on the side faces of thegate electrode 6 a. Thegate electrode 6 a contains the n-type dopant, which may increase the on-current of the n-MOS transistor 4 a. - In the n-
MOS transistor region 2 a, the source and drain 7A and 7B may be constituted by the n-dopant diffusion layers. The n-dopant diffusion layers can be formed by diffusing an n-type dopant in the semiconductor substrate 1. Each of the n-dopant diffusion layers has first and second side edges. The first side edge of the n-dopant diffusion layer is aligned in plain view to the side edge of thegate electrode 6 a. The second side edge of the n-dopant diffusion layer is bounded with theisolation region 3. The n-dopant diffusion layer extends from the side edge of theisolation region 3 to the position that is aligned in plain view to the side edge of thegate electrode 6 a. - The n-dopant diffusion layer that constitutes the
source 7A includes the first andsecond diffusion regions second diffusion region 7 b is positioned under theside wall 8. Thefirst diffusion region 7 a is disposed between thesecond diffusion region 7 b and theisolation region 3. Thefirst diffusion region 7 a is greater in depth and dopant concentration than thesecond diffusion region 7 b. Thus, thesource 7A has the lightly doped drain structure. - The n-dopant diffusion layer that constitutes the
drain 7B includes the third andfourth diffusion regions fourth diffusion region 7 d is positioned under theside wall 8. Thethird diffusion region 7 c is disposed between thefourth diffusion region 7 d and theisolation region 3. Thethird diffusion region 7 c is greater in depth and dopant concentration than thefourth diffusion region 7 d. Thus, thedrain 7B has the lightly doped drain structure. - The lightly doped drain structures of the source and drain 7A and 7B can relax field concentration near the
drain 7B. Relaxation of the field concentration can prevent generation of hot carrier, wherein the hot carrier generation is caused by the field concentration. Prevision of the hot carrier generation can prevent deterioration of performances such as threshold variation of the semiconductor device, wherein the threshold variation is caused by the hot carrier. - The n-
MOS transistor 4 a is configured so that a gate voltage is applied to thegate electrode 6 a under application of a bias voltage to between the source and drain 7A and 7B, leading to appearance of an n-channel region through which electron can move between the source and drain 7A and 7B. The n-channel region is adjacent to thegate insulating film 5. The n-channel region extends between the second andfourth diffusion regions - In the p-
MOS transistor region 2 b, thegate electrode 6 b may typically be made of a polysilicon-based conductive material doped with a p-type dopant. Thegate electrode 6 b contains the p-type dopant, which may increase the on-current of the p-MOS transistor 4 b. Thegate electrode 6 b may also contain, in addition to the p-type dopant, an n-type dopant in at least a part adjacent to thegate insulating film 5. In other words, thegate electrode 6 b may include a first part and a remaining part thereof. The first part is adjacent to thegate insulating film 5. The first part of thegate electrode 6 b is disposed between thegate insulating film 5 and the remaining part of thegate electrode 6 b. The first part of thegate electrode 6 b contains at least the n-type dopant. Namely, the first part of thegate electrode 6 b contains the n-type dopant in addition to the p-type dopant. The remaining part of thegate electrode 6 b contains at least the p-type dopant. The first part of thegate electrode 6 b is higher in n-type dopant concentration than the remaining part of thegate electrode 6 b. - The
gate electrode 6 b has the first part that contains the n-type dopant. The first part is adjacent to thegate insulating film 5. The n-type dopant in the first part of thegate electrode 6 b can prevent that application of a stress voltage to thegate electrode 6 b hurts the p-MOS transistor 4 b. Thus, the first part of thegate electrode 6 b can prevent that continuous application of a stress voltage to thegate electrode 6 b causes malfunction of the semiconductor device. The first part of thegate electrode 6 b can ensure high reliance to the NBTI. - Typically, the
gate electrode 6 b may have a stacked structure which includes lower andupper layers lower layer 6 c of thegate electrode 6 b contains an n-type dopant in addition to the p-type dopant. Theupper layer 6 d of thegate electrode 6 b may contain almost only the p-type dopant. Theupper layer 6 d may be almost free of any n-type dopant. - The
gate electrode 6 b has thelower layer 6 c that contains the n-type dopant. Thegate electrode 6 b is adjacent to thegate insulating film 5. The n-type dopant in thelower layer 6 c of thegate electrode 6 b can prevent that application of a stress voltage to thegate electrode 6 b hurts the p-MOS transistor 4 b. Thus, thelower layer 6 c of thegate electrode 6 b can prevent that continuous application of a stress voltage to thegate electrode 6 b causes malfunction of the semiconductor device. Thelower layer 6 c of thegate electrode 6 b can ensure high reliance to the NBTI. - For example, the
lower layer 6 c that contains the n-type dopant in addition to the p-type dopant may preferably have a thickness of about 30 nanometers, which ensures improvement in the reliance of the NBTI of the p-MOS transistor 4 b. - For example, the adjacent portion of the
gate electrode 6 b that is adjacent to thegate insulating film 5 contains the n-type dopant in addition to the p-type dopant. The adjacent portion of thegate electrode 6 b has the thickness of about 30 nanometers. The compositional ratio of n-type dopant to p-type dopant in the adjacent portion may be preferably in the range of 10% to 40%, and more preferably in the range of 30% to 40%. When the compositional ratio of n-type dopant to p-type dopant of the in thelower layer 6 c is less than 10%, it is possible that sufficient improvement in the reliance of the NBTI is not obtained. When the compositional ratio of n-type dopant to p-type dopant of the in thelower layer 6 c is more than 40%, it is possible that the performances such as the on-current of the p-MOS transistor 4 b are deteriorated. - The
side walls 8 made of an insulator are disposed on the side faces of thegate electrode 6 b. - In the p-
MOS transistor region 2 b, the source and drain 7D and 7E may be constituted by the p-dopant diffusion layers. The p-dopant diffusion layers can be formed by diffusing a p-type dopant in the semiconductor substrate 1. Each of the p-dopant diffusion layers has first and second side edges. The first side edge of the p-dopant diffusion layer is aligned in plain view to the side edge of thegate electrode 6 b. The second side edge of the p-dopant diffusion layer is bounded with theisolation region 3. The p-dopant diffusion layer extends from the side edge of theisolation region 3 to the position that is aligned in plain view to the side edge of thegate electrode 6 b. - The p-dopant diffusion layer that constitutes the
source 7D includes the fifth andsixth diffusion regions sixth diffusion region 7 f is positioned under theside wall 8. Thefifth diffusion region 7 e is disposed between thesixth diffusion region 7 f and theisolation region 3. Thefifth diffusion region 7 e is greater in depth and dopant concentration than thesixth diffusion region 7 f. Thus, thesource 7D has the lightly doped drain structure. - The p-dopant diffusion layer that constitutes the
drain 7E includes the seventh andeighth diffusion regions eighth diffusion region 7 h is positioned under theside wall 8. Theseventh diffusion region 7 g is disposed between theeighth diffusion region 7 h and theisolation region 3. Theseventh diffusion region 7 g is greater in depth and dopant concentration than theeighth diffusion region 7 h. Thus, thedrain 7E has the lightly doped drain structure. - The lightly doped drain structures of the source and drain 7D and 7E can relax field concentration near the
drain 7E. Relaxation of the field concentration can prevent generation of hot carrier, wherein the hot carrier generation is caused by the field concentration. Prevision of the hot carrier generation can prevent deterioration of performances such as threshold variation of the semiconductor device, wherein the threshold variation is caused by the hot carrier. - The p-
MOS transistor 4 b is configured so that a gate voltage is applied to thegate electrode 6 b under application of a bias voltage to between the source and drain 7D and 7E, leading to appearance of a p-channel region through which electron can move between the source and drain 7D and 7E. The p-channel region is adjacent to thegate insulating film 5. The p-channel region extends between the sixth andeighth diffusion regions - An
inter-layer insulator 9 extends over thegate insulating film 5 and thegate electrodes side walls 8. Contact holes 10 penetrate theinter-layer insulator 9 and thegate insulating film 5. The contact holes 10 reach the first, third, fifth andseventh diffusion regions inter-layer insulator 9 and thegate insulating film 5. The contact plugs 11 contact the first, third, fifth andseventh diffusion regions MOS transistor 4 a and the source and drain 7D and 7E of the p-MOS transistor 4 b.Interconnections 12 extend over theinter-layer insulator 9 and the contact plugs 11. Theinterconnections 12 contact the contact plugs 11 so that theinterconnections 12 are electrically connected through the contact plugs 11 to the first, third, fifth andseventh diffusion regions interconnections 12 are electrically connected through the contact plugs 11 to the source and drain 7A and 7B of the n-MOS transistor 4 a and the source and drain 7D and 7E of the p-MOS transistor 4 b. Thegate electrodes passivation film 13 is formed over theinterconnections 12 and theinter-layer insulator 9, thereby completing a semiconductor device having a CMOS circuit. - A method of forming the semiconductor device with the CMOS circuit shown in
FIG. 1 will be described.FIGS. 2A through 2D are fragmentary cross sectional elevation views illustrating sequential steps involved in a method of forming the semiconductor device shown inFIG. 1 . - With reference to
FIG. 2A , a semiconductor substrate 1 is prepared. A shallow trench isolation process is carried out to selectively formisolation regions 3 in a shallow region of the semiconductor substrate 1, thereby defining an n-MOS transistor region 2 a and a p-MOS transistor region 2 b. A thermal oxidation process is then carried out to form agate insulating film 5 over the surface of the semiconductor substrate 1 and theisolation regions 3. Thegate insulating film 5 has a thickness in the range of 1 nanometer to 10 nanometers. - With reference to
FIG. 2B , a chemical vapor deposition process is carried out to form afirst polysilicon layer 14 over thegate insulating film 5. Thefirst polysilicon layer 14 is doped with an n-type dopant. Thefirst polysilicon layer 14 is the n-doped polysilicon layer. Thefirst polysilicon layer 14 has a thickness in the range of 10 nanometers to 50 nanometers. Asecond polysilicon layer 15 that is substantially free of any dopant is formed over thefirst polysilicon layer 14. Thesecond polysilicon layer 15 is the non-doped polysilicon layer. Thesecond polysilicon layer 15 has a thickness in the range of 50 nanometers to 100 nanometers. Thus, a stack of the first and second polysilicon layers 14 and 15 is formed over thegate insulating film 5. The concentration of the n-type dopant of thefirst polysilicon layer 14 will be described later. The ratio in thickness of thefirst polysilicon layer 14 to thesecond polysilicon layer 15 will also be described later. - With reference to
FIG. 2C , a resist film is applied on thesecond polysilicon layer 15. A lithography process is carried out to form a first resistpattern 16. The first resistpattern 16 is a pattern for forming gate electrodes of an n-MOS transistor 4 a and a p-MOS transistor 4 b. A dry etching process is carried out using the first resistpattern 16 as a mask to selectively remove the stack of the first and second polysilicon layers 14 and 15, thereby forming gate structures in the n-MOS transistor region 2 a and the p-MOS transistor region 2 b. Each gate structure is constituted by the stack of the remaining parts of the first and second polysilicon layers 14 and 15. - With reference to
FIG. 2D , the first resistpattern 16 is removed. The first resistpattern 16 is removed. A resist film is applied on the gate structures and thegate insulating film 5 over the n-MOS transistor region 2 a and the p-MOS transistor region 2 b. A lithography process is carried out to form a second resist pattern which has an opening. The opening of the second resist pattern is positioned over the n-MOS transistor region 2 a. A first n+-ion implantation process is carried out using the second resist pattern as a mask to selectively introduce the n+-ions into the n-MOS transistor region 2 a of the semiconductor substrate, except under the gate structure in the n-MOS transistor region 2 a, and also into the gate structure in the n-MOS transistor region 2 a. The second resist pattern is removed. - A new resist film is applied on the gate structures and the
gate insulating film 5 over the n-MOS transistor region 2 a and the p-MOS transistor region 2 b. A lithography process is carried out to form a third resist pattern which has an opening. The opening of the third resist pattern is positioned over the p-MOS transistor region 2 b. A first p+-ion implantation process is carried out using the third resist pattern as a mask to selectively introduce the p+-ions into the p-MOS transistor region 2 b of the semiconductor substrate, except under the gate structure in the p-MOS transistor region 2 b, and also into the gate structure in the p-MOS transistor region 2 b. The third resist pattern is removed. - In the n-
MOS transistor region 2 a, the n-type dopant is introduced into the first and second polysilicon layers 14 and 15 and the source anddrain regions - In the p-
MOS transistor region 2 b, the p-type dopant is introduced into the first and second polysilicon layers 14 and 15 and the source anddrain regions -
Side walls 8 are formed on the side faces of the first and second polysilicon layers 14 and 15 in the n-MOS transistor region 2 a and the p-MOS transistor region 2 b. Theside walls 8 have a thickness in the range of 5 nanometers to 20 nanometers. Theside walls 8 may be made of an insulator such as oxide or nitride. - A resist film is applied on the gate structures with the
side walls 8 and thegate insulating film 5 over the n-MOS transistor region 2 a and the p-MOS transistor region 2 b. A lithography process is carried out to form a fourth resist pattern which has an opening. The opening of the fourth resist pattern is positioned over the n-MOS transistor region 2 a. A second n+-ion implantation process is carried out using the fourth resist pattern as a mask to selectively introduce the n+-ions into the n-MOS transistor region 2 a of the semiconductor substrate, except under the gate structure in the n-MOS transistor region 2 a, and also into the gate structure in the n-MOS transistor region 2 a. As a result, thegate electrode 6 a and the source and drain 7A and 7B are formed in the n-MOS transistor region 2 a. The fourth resist pattern is removed. - A new resist film is applied on the gate structures and the
gate insulating film 5 over the n-MOS transistor region 2 a and the p-MOS transistor region 2 b. A lithography process is carried out to form a fifth resist pattern which has an opening. The opening of the fifth resist pattern is positioned over the p-MOS transistor region 2 b. A second p+-ion implantation process is carried out using the fifth resist pattern as a mask to selectively introduce the p+-ions into the p-MOS transistor region 2 b of the semiconductor substrate, except under the gate structure in the p-MOS transistor region 2 b, and also into the gate structure in the p-MOS transistor region 2 b. As a result, thegate electrode 6 b and the source and drain 7D and 7E are formed in the p-MOS transistor region 2 a. The fifth resist pattern is removed. - As described above, the
first polysilicon layer 14 has been doped with the n-type dopant before the first and second n+-ion implantation processes are carried out. Thefirst polysilicon layer 14 is undoped before the first and second n+-ion implantation processes are carried out. - In the n-
MOS transistor region 2 a, thefirst polysilicon layer 14 of thegate electrode 6 a contains a total amount of n-type dopant that has pre-existed in thefirst polysilicon layer 14 and n-type dopant that is newly introduced by the first and second n+-ion implantation processes. Thesecond polysilicon layer 15 of thegate electrode 6 a contains a total amount of n-type dopant that is newly introduced by the first and second n+-ion implantation processes. Thefirst polysilicon layer 14 of thegate electrode 6 a is higher in n-type dopant concentration than thesecond polysilicon layer 15 of thegate electrode 6 a. - In the n-
MOS transistor region 2 a, the second andfourth diffusion regions third diffusion regions third diffusion regions fourth diffusion regions source 7A has thefirst diffusion region 7 a and thesecond diffusion region 7 b that is lower in n-type dopant concentration than thefirst diffusion region 7 a. Thesource 7A has the lightly doped drain structure. Thedrain 7B has thethird diffusion region 7 c and thefourth diffusion region 7 d that is lower in n-type dopant concentration than thethird diffusion region 7 c. Thedrain 7B has the lightly doped drain structure. - In the p-
MOS transistor region 2 b, thefirst polysilicon layer 14 as thelower layer 6 c of thegate electrode 6 b contains an amount of n-type dopant that has pre-existed in thefirst polysilicon layer 14 and a total amount of p-type dopant that is newly introduced by the first and second p+-ion implantation processes. Namely, thefirst polysilicon layer 14 as thelower layer 6 c of thegate electrode 6 b contains not only the p-type dopant that has been introduced by the first and second p+-ion implantation processes but the n-type dopant that has pre-existed therein. Thesecond polysilicon layer 15 as theupper layer 6 d of thegate electrode 6 b contains a total amount of p-type dopant that is introduced by the first and second p+-ion implantation processes. Thefirst polysilicon layer 14 as thelower layer 6 c of thegate electrode 6 b is higher in n-type dopant concentration than thesecond polysilicon layer 15 as theupper layer 6 d of thegate electrode 6 b. - In the p-
MOS transistor region 2 b, the sixth andeighth diffusion regions seventh diffusion regions seventh diffusion regions eighth diffusion regions source 7D has thefifth diffusion region 7 e and thesixth diffusion region 7 f that is lower in p-type dopant concentration than thefifth diffusion region 7 e. Thesource 7D has the lightly doped drain structure. Thedrain 7E has theseventh diffusion region 7 g and theeighth diffusion region 7 h that is lower in p-type dopant concentration than theseventh diffusion region 7 g. Thedrain 7E has the lightly doped drain structure. - An anneal process is carried out to activate the n-type dopant in the
gate electrode 6 a and the source and drain 7A and 7B as well as activate the p-type dopant in thegate electrode 6 b and the source and drain 7D and 7E, provided that thegate electrode 6 b has a portion adjacent to thegate insulating film 5, and this adjacent portion contains more n-type dopant than p-type dopant. - The temperature of the anneal is preferably in the range of 850° C. to 1050° C.
- As described above, the
lower layer 6 c of thegate electrode 6 b contains the n-type dopant in addition to the p-type dopant and has the thickness of about 30 nanometers. The compositional ratio of n-type dopant to p-type dopant of the adjacent portion of thegate electrode 6 b may be preferably in the range of 10% to 40%, and more preferably in the range of 30% to 40%. When the compositional ratio of n-type dopant to p-type dopant of the in thelower layer 6 c is less than 10%, it is possible that sufficient improvement in the reliance of the NBTI is not obtained. When the compositional ratio of n-type dopant to p-type dopant of the in thelower layer 6 c is more than 40%, it is possible that the performances such as the on-current of the p-MOS transistor 4 b are deteriorated. - The concentration of the n-type dopant of the adjacent portion of the
gate electrode 6 b might be controllable by controlling the concentration of the n-type dopant of thefirst polysilicon layer 14 and the thickness of thefirst polysilicon layer 14 in the process shown inFIG. 2B , wherein the adjacent portion of thegate electrode 6 b is positioned adjacent to thegate insulating film 5. - In some cases, the dose of n-type dopant into the
first polysilicon layer 14 may be preferably in the range of 1E13 atoms/cm2 to 1E15 atoms/cm2, and more preferably in the range of 1E13 atoms/cm2 to 1E14 atoms/cm2. If the concentration of n-type dopant of thefirst polysilicon layer 14 is lower than 1E13 atoms/cm2, then the adjacent portion of thegate electrode 6 b has a lower compositional ratio of the n-type dopant to the p-type dopant than the ratio that needs to improve the reliance of the NBTI of the p-MOS transistor 4 b. If the concentration of n-type dopant of thefirst polysilicon layer 14 is higher than 1E15 atoms/cm2, then the adjacent portion of thegate electrode 6 b has a higher compositional ratio of the n-type dopant to the p-type dopant than the ratio that needs to ensure the performances such as on-current of the p-MOS transistor 4 b. In some cases, the concentration of p-type dopant of thefirst polysilicon layer 14 may be preferably in the range of 1E19 atoms/cm3 to 1E21 atoms/cm3. - The ratio in thickness of the
first polysilicon layer 14 to thesecond polysilicon layer 15 may be preferably in the range of 10% to 50%, and more preferably in the range of 10% to 20%. If the ratio in thickness of thefirst polysilicon layer 14 to thesecond polysilicon layer 15 is lower than 10%, then the adjacent portion of thegate electrode 6 b has a lower compositional ratio of the n-type dopant to the p-type dopant than the ratio that might need to improve the reliance of the NBTI of the p-MOS transistor 4 b. If the ratio in thickness of thefirst polysilicon layer 14 to thesecond polysilicon layer 15 is higher than 50%, then the adjacent portion of thegate electrode 6 b has a higher compositional ratio of the n-type dopant to the p-type dopant than the ratio that needs to ensure the performances such as on-current of the p-MOS transistor 4 b. - With reference again to
FIG. 2D , aninter-layer insulator 9, contact plugs 11,metal interconnections 12 and apassivation film 13 are formed in the known processes, thereby completing the semiconductor device having the CMOS circuit. - In the CMOS circuit, the p-
MOS transistor 6 b has the adjacent portion that is adjacent to thegate insulating film 5, where the adjacent portion contains n-type dopant in addition to p-type dopant, thereby obtaining the reliance of the NBTI. - The semiconductor device having the CMOS circuit has the
gate insulating film 5 that has a uniform thickness. In view of the method of forming the semiconductor device, an additional process is a process for forming thefirst polysilicon layer 14, in order to obtain the CMOS circuit that is superior in the NBTI reliance. The stack of the first and second polysilicon layers 14 and 15 can be formed by the continuous chemical vapor deposition process with changing the reaction gas. Thegate insulating film 5 with the uniform thickness is disposed over the n-MOS transistor region 2 a and the p-MOS transistor region 2 b. The process for forming the thickness-uniformgate insulating film 5 is simpler than the process for forming the thickness-varying gate insulating film. The above-describedgate electrode 6 b and the thickness-uniform gate electrode 5 can allow that the CMOS circuit having high NBTI reliance is formed by the simplified processes. - An isolation region was formed on a silicon substrate. A thermal oxidation of silicon was carried out to form a gate oxide film having a thickness of 3 nanometers.
- A thermal chemical vapor deposition process was carried out to form an n-doped polysilicon layer over the gate oxide film. The n-doped polysilicon layer will be hereinafter referred to as a first polysilicon layer. The first polysilicon layer has a thickness of 20 nanometers. The first polysilicon layer has a phosphorus concentration of 5E13 atoms/cm3.
- A thermal chemical vapor deposition process was carried out to form a non-doped polysilicon layer over the first polysilicon layer, thereby forming a polysilicon stack-layered structure over the gate oxide film. The non-doped polysilicon layer will be hereinafter referred to as a second polysilicon layer. The second polysilicon layer has a thickness of 60 nanometers.
- A photolithography process and a dry etching process were carried out to pattern the stack-layered structure of the first and second polysilicon layers, thereby forming gate electrode structures for n-MOS transistor and p-MOS transistor.
- A first n+-ion implantation process was carried out at a dose of 3E13 atoms/cm2 to introduce phosphorus as an n-type dopant into the n-MOS transistor region. Then, a second p+-ion implantation process was carried out at a dose of 3E13 atoms/cm2 to introduce boron as a p-type dopant into the p-MOS transistor region.
- Side walls were formed on side faces of the gate electrode structures of the first and second polysilicon layers. The side walls have a thickness of 20 nanometers.
- A second n+-ion implantation process was carried out at a dose of 3E15 atoms/cm2 to introduce phosphorus as an n-type dopant into the n-MOS transistor region. Then, a second p+-ion implantation process was carried out at a dose of 3E15 atoms/cm2 to introduce boron as a p-type dopant into the p-MOS transistor region, thereby forming gate electrodes and source and drain regions in the n-MOS transistor region and the p-MOS transistor region.
- An annealing process was carried out to heat the silicon substrate at 1000° C. The gate electrode in the p-MOS transistor region has an adjacent portion that is adjacent to the gate oxide film. The adjacent portion has a thickness of 30 nanometers. The adjacent portion of the gate electrode in the p-MOS transistor region has an n-type dopant concentration of 5E19 atoms/cm3. The compositional ratio of n-type dopant to p-type dopant of the adjacent portion is 40% (p-type dopant:n-type dopant=5:2). An inter-layer insulator, contact plugs, metal interconnections and a passivation film were formed in the known processes, thereby completing the semiconductor device having the CMOS circuit.
- The semiconductor device having the CMOS circuit was formed in the same processes, provided that a single layered structure of a non-doped polysilicon layer was formed by a thermal chemical vapor deposition method, instead of the stack-layered structure of the first and second polysilicon layers.
- Each type of the semiconductor devices with the CMOS circuits in Example and Comparative Example was examined in NBTI reliance as follows. A stress voltage Vgs was applied to the gate electrode of the p-MOS transistor to confirm a stress-voltage-applying time (t50) that it takes to cause malfunction at 50% of the CMOS circuits under application of the stress voltage. Application of a stress voltage Vgs to the gate electrode of the p-MOS transistor for the stress-voltage-applying time (t50) causes at 50% malfunction of the CMOS circuits. This test was carried out by varying the stress voltage level.
-
FIG. 3 is a diagram illustrating variation of the stress-voltage-applying time (t50) over the stress voltage Vgs for each of the semiconductor devices with the CMOS circuits in Example and Comparative Example. The real line represents the voltage-dependency of the stress-voltage-applying time (t50) of the semiconductor device in accordance with Example. The dotted line represents the voltage-dependency of the stress-voltage-applying time (t50) of the semiconductor device in accordance with Comparative Example. - The semiconductor device in accordance with Example is longer in the stress-voltage-applying time (t50) than the semiconductor device in accordance with Comparative Example. This demonstrates that the semiconductor device in accordance with Example is more unlikely to cause malfunction than the semiconductor device in accordance with Comparative Example. Thus, the n-dopant-containing adjacent portion of the gate electrode of the p-MOS transistor can improve the NBTI reliance as much as the gate insulating film of the p-MOS transistor is thicker than the gate insulating film of the n-MOS transistor.
- The above-described structure of the gate electrode can be applied to the semiconductor device including the n-MOS transistor and the p-MOS transistor.
- As used herein, the following directional terms “forward, rearward, above, downward, vertical, horizontal, below, and transverse” as well as any other similar directional terms refer to those directions of an apparatus equipped with the present invention. Accordingly, these terms, as utilized to describe the present invention should be interpreted relative to an apparatus equipped with the present invention.
- The terms of degree such as “substantially,” “about,” and “approximately” as used herein mean a reasonable amount of deviation of the modified term such that the end result is not significantly changed. For example, these terms can be construed as including a deviation of at least ±5 percents of the modified term if this deviation would not negate the meaning of the word it modifies.
- While preferred embodiments of the invention have been described and illustrated above, it should be understood that these are exemplary of the invention and are not to be considered as limiting. Additions, omissions, substitutions, and other modifications can be made without departing from the spirit or scope of the present invention. Accordingly, the invention is not to be considered as being limited by the foregoing description, and is only limited by the scope of the appended claims.
Claims (8)
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US12/108,554 US8698248B2 (en) | 2007-04-27 | 2008-04-24 | Semiconductor device and method of forming the same |
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US8120123B2 (en) | 2007-09-18 | 2012-02-21 | Samsung Electronics Co., Ltd. | Semiconductor device and method of forming the same |
DE102008047591B4 (en) | 2007-09-18 | 2019-08-14 | Samsung Electronics Co., Ltd. | A method of manufacturing a semiconductor device of reduced thickness |
KR101623123B1 (en) * | 2009-07-23 | 2016-05-23 | 삼성전자주식회사 | Semiconductor device and method of fabricating the same |
US8431955B2 (en) * | 2010-07-21 | 2013-04-30 | International Business Machines Corporation | Method and structure for balancing power and performance using fluorine and nitrogen doped substrates |
US8461034B2 (en) * | 2010-10-20 | 2013-06-11 | International Business Machines Corporation | Localized implant into active region for enhanced stress |
KR20130081505A (en) * | 2012-01-09 | 2013-07-17 | 삼성전자주식회사 | Semiconductor device, semiconductor system and fabricating method of the semiconductor device |
KR20140007609A (en) * | 2012-07-09 | 2014-01-20 | 삼성전자주식회사 | Method of manufacturing semiconductor devices |
US11749730B2 (en) * | 2021-06-14 | 2023-09-05 | Nanya Technology Corporation | Semiconductor device with contact structure and method for preparing the same |
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