US20140270122A1 - Serial Protocol for Agile Sample Rate Switching - Google Patents
Serial Protocol for Agile Sample Rate Switching Download PDFInfo
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- US20140270122A1 US20140270122A1 US14/291,696 US201414291696A US2014270122A1 US 20140270122 A1 US20140270122 A1 US 20140270122A1 US 201414291696 A US201414291696 A US 201414291696A US 2014270122 A1 US2014270122 A1 US 2014270122A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M3/00—Automatic or semi-automatic exchanges
- H04M3/005—Interface circuits for subscriber lines
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/14—Two-way operation using the same type of signal, i.e. duplex
- H04L5/1423—Two-way operation using the same type of signal, i.e. duplex for simultaneous baseband signals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0266—Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling
Definitions
- the present invention relates generally to digital communication between line-side and system-side circuits in a modem or digital access arrangement (“DAA”).
- DAA digital access arrangement
- a modern modem 100 typically includes a digital signal processor or microprocessor 102 , a coder/decoder (“codec”) 132 for converting digital signals from the DSP 102 to an analog form capable of transmission over a telephone line and for converting analog signals from the telephone line to digital form, and high-voltage (“HV”) components 130 that interface with the telephone line.
- codec coder/decoder
- HV high-voltage
- the codec function is conventionally implemented via two circuits—a system-side interface circuit (“SSIC”) 106 and a line-side interface circuit (“LSIC”) 118 , which communicate across an isolation barrier 117 .
- the SSIC 106 includes a system I/O interface 108 for communication with the DSP 102 , a conventional sigma-delta modulator 112 for converting forward-going data signals to forward-going sigma-delta signals, a conventional integrator-based sigma-delta decoder circuit for decoding reverse-going sigma-delta signals into data signals, and an isolation barrier interface circuit 114 for transmitting and receiving sigma-delta signals to and from the LSIC 118 across the isolation barrier 117 .
- the SSIC 106 may further include a protocol framing circuit 116 , which functions to organize the data transmitted and received by the isolation barrier interface circuit 114 , and a barrier clock controller 113 and associated voltage-controlled oscillator 115 , which together form a variable-rate clock generator for generating the barrier clock signal.
- a protocol framing circuit 116 which functions to organize the data transmitted and received by the isolation barrier interface circuit 114
- a barrier clock controller 113 and associated voltage-controlled oscillator 115 which together form a variable-rate clock generator for generating the barrier clock signal.
- the LSIC 118 includes an isolation barrier interface circuit 120 , a line-side sigma-delta digital-to-analog converter (“DAC”) 126 whose output is connected to a transmit buffer 128 , and a sigma-delta analog-to-digital converter (“ADC”) 122 whose input is connected to a receive buffer 124 .
- the LSIC 118 may further include a conventional clock-and-data recovery circuit 125 to derive a local clock signal from the received signals from the isolation barrier.
- Each of isolation barrier interface circuits 114 , 120 may be any suitable isolation barrier interface circuit for communication across an isolation barrier, such as that described in U.S.
- a modem complying with the CCITT v.34 standard must be capable of communicating at a variable symbol rate (or baud rate) that may range from 2400 Hz-3429 Hz, as illustrated in Table 1 below.
- the ADC 122 must have a sampling rate ranging from 7200 Hz-10,287 Hz (and as high as 11,025 Hz if the telephone signal is an analog audio signal rather than a digital modem signal).
- the sigma-delta ( ⁇ ) rate is conventionally selected so that the analog signal is oversampled at a predetermined multiple (e.g., 256) times the sampling rate.
- the sigma-delta ACD 122 must operate at a sigma-delta rate that ranges between 1.843 MHz and 2.822 MHz.
- This wide range of the required sigma-delta rate (1.843 MHz-2.822 MHz) represents a design constraint on the barrier interface (the communication link formed by interface circuits 114 and 120 and isolation barrier 117 ).
- the barrier interface the communication link formed by interface circuits 114 and 120 and isolation barrier 117 .
- the data rate of the barrier interface must be variable, depending on the sigma-delta rate.
- the desired variable data rate for the barrier interface has conventionally been obtained by varying the barrier clock rate to obtain the desired data rate.
- the DSP 102 or some other barrier clock controller 113 may set the barrier clock rate to a rate equal to two times 1.843 MHz, or 3.686 MHz, so that during each ⁇ interval, at least one forward ⁇ sample and one reverse ⁇ sample may be transmitted across the barrier interface.
- the barrier clock may be set to a rate of two times 2.634 MHz, or 5.268 MHz, again so that during each ⁇ interval, at least one forward ⁇ sample and one reverse ⁇ sample may be transmitted across the barrier interface.
- the clock rate in this simplified example would have to be able to operate over the range from 3.686 MHz to 5.268 MHz (i.e., an increase of 42%) to accommodate the full range of v.34 symbol rates.
- the barrier clock rate would have to be correspondingly increased if control and status information was to be communicated during each ⁇ interval.
- this conventional technique of varying the barrier clock as a function of the symbol rate or sigma-delta rate causes at least two difficulties. First, if the LSIC 118 derives its local clock from the barrier signals via a clock recovery circuit, the clock recovery circuit loses synchronism with the barrier signals each time the barrier clock changes. Until the clock recovery circuit re-acquires the new clock rate, the SSIC 106 and the LSIC 118 are unable to communicate. Second, the clock generating circuit in the SSIC 106 and the clock recovery circuit in the LSIC 118 are relatively complicated and expensive, because they must accommodate the entire range of clock rates across the barrier.
- the present inventors developed an innovative communication protocol and barrier interface having an approximately fixed barrier clock and capable of accommodating a variety of symbol rates, sampling rates and/or sigma-delta rates (collectively, “communication rates”). More particularly, the invention employs a variable-length frame that may be expanded or reduced to reach a desired communication rate, even though the barrier clock rate is held approximately constant.
- Each master frame preferably includes a fixed-length data portion and a variable-length dummy portion. For a fast communication rate, the variable-length dummy portion may be small, such that the overall frame length is small and many frames may be transmitted during a given time period.
- variable-length dummy portion may be large, such that the overall frame length is large and only a few frames may be transmitted during the same time period.
- the minimum frame length corresponds to the fastest communication rate
- the maximum frame length corresponds to the slowest communication rate.
- the invention further provides a method for designing an agile barrier interface.
- the barrier clock rate is preferably selected to be an approximate common multiple of the various communication rates that the barrier interface must handle.
- the frame length corresponding to each communication rate may then be obtained by dividing the barrier clock rate by the ⁇ rate.
- the invention provides an agile communication circuit capable of communicating data across a serial interface at a variety of data rates and at an approximately fixed interface clock rate.
- FIG. 1 is a block diagram depicting a communication circuit suitable for use in the invention
- FIG. 2 is a timing diagram depicting a communication protocol using a variable-length frame in accordance with the invention.
- FIG. 3 is a timing diagram depicting a further communication protocol for balancing the flux of the isolation barrier over consecutive frames in accordance with the invention.
- Padded frame 220 includes a basic frame 222 (i.e., the fixed-length data portion) and a number of padding bits 230 (the variable-length dummy portion).
- FIG. 2 depicts an example of the former case, in which the barrier interface is a single serial communication link over which both forward- and reverse-going sigma-delta data and forward- and reverse-going control information is to be transmitted during each master frame.
- the SSIC 106 transmits during time slots 201 - 208 and the LSIC 118 transmits during time slots 209 - 212 .
- each transmitted bit is preferably Manchester encoded using a conventional encoder. That is, a “0” bit is encoded as the two-bit sequence 01 and a “1” bit is encoded as the two-bit sequence 10. It should be understood that if flux-balance is not a design concern (e.g., where the isolation barrier is a capacitive barrier), such encoding is not required.
- the basic frame 222 preferably includes:
- a predetermined forward framing sequence 326 during time slots 205 - 208 (shown as NOT CF, NOT CF, CF, CF) (transmitted by either SSIC 106 or LSIC 118 );
- the barrier interface can be simplified by making the links uni-directional. If so, then the basic frame may be reduced to the sigma-delta data, control and forward framing sequence for a single direction (i.e., forward or reverse).
- the forward framing sequence may be any unique sequence of bit values that may be used to identify where a frame starts and/or ends. For example, in the protocol shown in FIG. 2 , the inverse control bit (NOT CF) in time slot 204 is repeated twice thereafter, in time slots 205 and 206 .
- This thrice-repeated value provides a unique synchronization (“sync”) pattern that may readily be identified, insofar as Manchester encoded signals (01, 10) ordinarily do not result in a three-time-slot sequence of the same values.
- a suitable detection circuit for this sync pattern may be implemented, for example, via a three-bit shift register, where each bit in the register is provided to a 3-input AND gate that outputs a signal when the thrice-repeated value is detected.
- Other frame detection techniques may also be used in lieu of the sync pattern described above. For example, a large buffer may be used to store incoming data, and the buffered data may then be statistically analyzed by a microprocessor to determine the framing, in accordance with techniques known in the art.
- Padded frame 220 preferably also includes dummy or padding bits 230 , which may be added or removed to adjust the frame size. In this way, a wide variety of data rates may be accommodated without altering the clock rate of the SSIC 180 and the LSIC 182 .
- dummy or padding bits 230 may be added or removed to adjust the frame size.
- six padding bits e.g., 0, 1, 0, 1, 0, 1
- time slots 213 - 218 are depicted in time slots 213 - 218 . These padding bits may be provided by either the SSIC 106 or the LSIC 118 after the interface has been initialized.
- FIG. 3 illustrates how an odd number of padding bits may be accommodated without disrupting the flux balance of the isolation barrier.
- the flux of the padding bits is balanced over two consecutive frames, Frame k and Frame k+1 by using alternating sequences of 0's and 1's. For example, if frame k contains the padding bit sequence [01010], frame k+1 may contain the sequence [10101].
- the invention further provides a method for designing an agile barrier interface.
- a designer selects a barrier clock rate that is an approximate common multiple of the various data rates that the barrier interface must handle.
- the designer may then calculate the frame length corresponding to each data rate, by dividing the barrier clock rate by the sigma-delta rate.
- Table 2 illustrates exemplary frame lengths and barrier clock frequencies calculated for a barrier interface capable of handling sample rates of 7200, 8000, 8229, 8400, 9000, 9600, 10,287, and 11,025 Hz, where the sigma-delta rate is selected to be 256 times the sample rate.
- one of the approximate common multiples of the above sigma-delta rates is about 33.3 MHz, which is taken as the approximately fixed barrier clock rate.
- the frame length corresponding to each sigma-delta rate may be calculated by dividing the sigma-delta rate into the frame barrier clock frequency.
- the frame length corresponding to the highest-frequency sigma-delta rate, 2.822 MHz is calculated as 33.3 MHz/2.822 MHz, or 11.8 clock cycles, which may be rounded up to 12 clock cycles, as shown in Table 2.
- the frame length corresponding to the lowest-frequency sigma-delta rate, 1.843 MHz is calculated as 33.3 MHz/1.843 MHz, yielding 18.1 clock cycles, which may be rounded down to 18 clock cycles to obtain the frame length corresponding to the 1.843 MHz sigma-delta rate.
- Table 3 illustrates an example in which a different approximate common multiple of the above sigma-delta rates is selected to be the approximately fixed barrier clock rate—namely, about 36 MHz.
- the frame length corresponding to each sigma-delta rate is calculated by dividing the sigma-delta rate into the frame barrier clock rate.
- the frame length corresponding to the highest-frequency sigma-delta rate, 2.822 MHz is calculated as 36 MHz/2.822 MHz, yielding 13 clock cycles.
- the frame length corresponding to the lowest-frequency sigma-delta rate, 1.843 MHz is calculated as 36 MHz/1.843 MHz, yielding 20 clock cycles.
- the method for designing the barrier interface may further include adjusting the approximately fixed barrier clock rate for each sigma-delta rate, whereby rounding errors that are introduced during the selection of the frame length may be corrected. More specifically, after the selection of the approximately fixed barrier clock rate and the frame lengths corresponding to the various sigma-delta rates, a customized barrier clock rate may be selected for each sigma-delta rate, by multiplying each delta sigma rate by its corresponding frame length.
- the customized barrier clock rate for a 1.843 MHz sigma-delta rate, with a length of 18 cycles may be calculated as 33.1776 MHz.
- the customized barrier clock rate for a 2.822 MHz delta sigma rate and a frame length of 12 cycles is 33.8688 MHz.
- Customized barrier clock rates may be similarly calculated for the remaining sigma-delta rates shown in Table 2. It may be seen from Table 2 that a barrier interface capable of transmitting information at symbol rates including 2400, 2743, 2800, 3000, 3200, and 3429 will preferably be capable of operation at the corresponding customized barrier clock rates shown in Table 2, which range between about 32 MHz and about 35 MHz.
- the customized barrier clock rates shown in Table 3 may be calculated in a similar manner, resulting in customized barrier clock rates of between about 35 MHz and about 37 MHz.
- the invention further provides an agile communication circuit capable of communicating data across a serial interface at a variety of data rates and at an approximately fixed interface clock rate.
- a communication circuit may be implemented using conventional modem or DAA components as shown in FIG. 1 and as described above in the Background section.
- modem processor/DSP 102 includes a circuit and/or software of a type well-known to those of ordinary skill in the art of modem design for selecting a communication rate (e.g., a desired symbol rate, sample rate, or sigma-delta rate).
- the SSIC 106 includes a system I/O interface 108 for communicating with the DSP 102 , a conventional sigma-delta modulator 112 for converting forward-going data signals to forward-going sigma-delta signals, a conventional integrator-based sigma-delta decoder circuit for decoding reverse-going sigma-delta signals into data signals, and an isolation barrier interface circuit 114 for transmitting and receiving sigma-delta signals to and from the LSIC 118 across the isolation barrier 117 .
- the SSIC 106 further includes a protocol framing circuit 116 , which buffers and organizes the data transmitted and received by the isolation barrier interface circuit 114 .
- the SSIC 106 further includes a variable-rate clock generator comprising barrier clock controller 113 and associated voltage-controlled oscillator 115 , for generating a variable-rate barrier clock signal.
- the LSIC 118 includes an isolation barrier interface circuit 120 , a line-side sigma-delta digital-to-analog converter (“DAC”) 126 whose output is connected to a transmit buffer 128 , and a sigma-delta analog-to-digital converter (“ADC”) 122 whose input is connected to a receive buffer 124 .
- the LSIC 118 may further include a clock-and-data recovery circuit 125 to derive a local clock signal from the signals received across the isolation barrier.
- modem processor/DSP 102 selects a frame length and interface clock rate for the digital isolation barrier based on a desired communication rate (i.e., modem symbol rate, sample rate, or sigma-delta rate)—e.g., by looking up the frame length and interface clock rate in a look-up table.
- Modem processor/DSP 102 then communicates the selected interface clock rate to the barrier clock controller 113 in SSIC 106 .
- the barrier clock controller 113 receives the selected interface clock rate and outputs a corresponding analog signal to the voltage controlled oscillator 115 . Based on this analog signal, the voltage-controlled oscillator produces a digital clock signal that may be used in interface circuit 114 as the isolation barrier clock.
- Modem processor/DSP 102 also communicates the selected frame length to the framer circuit 116 in interface circuit 114 .
- the framer circuit buffers data from modem processor/DSP 102 and packages the buffered data into frames having the selected frame length, by inserting an appropriate number of padding bits at the end of each basic frame.
- both the voltage-controlled oscillator in the system-side interface circuit that generates the barrier clock and the clock-and-data recovery circuit on the line-side interface circuit are enabled to run at an approximately fixed frequency. Both can stay locked to the approximately fixed frequency even when the sample rate changes. Moreover, because they only need to operate over a relatively small frequency range, they can be optimized for low-jitter performance. Finally, the sigma-delta clock in the line-side circuit may be derived directly from the frame synchronization pulse.
Abstract
Description
- This application is a continuation-in-part of U.S. patent application Ser. No. 11/159,614 filed Jun. 23, 2005 and is also a continuation-in-part of U.S. patent application Ser. No. 11/159,537 filed Jun. 23, 2005, which are incorporated by reference in their entirety.
- The present invention relates generally to digital communication between line-side and system-side circuits in a modem or digital access arrangement (“DAA”).
- A
modern modem 100, as illustrated inFIG. 1 , typically includes a digital signal processor ormicroprocessor 102, a coder/decoder (“codec”) 132 for converting digital signals from theDSP 102 to an analog form capable of transmission over a telephone line and for converting analog signals from the telephone line to digital form, and high-voltage (“HV”)components 130 that interface with the telephone line. In order to isolate theDSP 102 from voltage fluctuations on the telephone line, the codec function is conventionally implemented via two circuits—a system-side interface circuit (“SSIC”) 106 and a line-side interface circuit (“LSIC”) 118, which communicate across anisolation barrier 117. - The SSIC 106 includes a system I/
O interface 108 for communication with theDSP 102, a conventional sigma-delta modulator 112 for converting forward-going data signals to forward-going sigma-delta signals, a conventional integrator-based sigma-delta decoder circuit for decoding reverse-going sigma-delta signals into data signals, and an isolationbarrier interface circuit 114 for transmitting and receiving sigma-delta signals to and from theLSIC 118 across theisolation barrier 117. The SSIC 106 may further include aprotocol framing circuit 116, which functions to organize the data transmitted and received by the isolationbarrier interface circuit 114, and abarrier clock controller 113 and associated voltage-controlledoscillator 115, which together form a variable-rate clock generator for generating the barrier clock signal. - The LSIC 118 includes an isolation
barrier interface circuit 120, a line-side sigma-delta digital-to-analog converter (“DAC”) 126 whose output is connected to atransmit buffer 128, and a sigma-delta analog-to-digital converter (“ADC”) 122 whose input is connected to areceive buffer 124. The LSIC 118 may further include a conventional clock-and-data recovery circuit 125 to derive a local clock signal from the received signals from the isolation barrier. Each of isolationbarrier interface circuits - Conventional modems typically also must accommodate a wide variety of communication rates. For example, a modem complying with the CCITT v.34 standard must be capable of communicating at a variable symbol rate (or baud rate) that may range from 2400 Hz-3429 Hz, as illustrated in Table 1 below.
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TABLE 1 Sample rate ΣΔ Rate Application Symbol rate [Hz] [Hz] [MHz] V.34 2400 7200 1.8432 Audio N/A 8000 2.0480 V.34 2743 8228 2.1066 V.34 2800 8400 2.1504 V.34 3000 9000 2.3040 V.34 3200 9600 2.4576 V.34 3429 10287 2.6335 Audio/ N/A 11025 2.8224 optional - If the ADC sampling rate is selected to be factor of 3 times the symbol rate, the
ADC 122 must have a sampling rate ranging from 7200 Hz-10,287 Hz (and as high as 11,025 Hz if the telephone signal is an analog audio signal rather than a digital modem signal). In addition, the sigma-delta (ΣΔ) rate is conventionally selected so that the analog signal is oversampled at a predetermined multiple (e.g., 256) times the sampling rate. As such, the sigma-delta ACD 122 must operate at a sigma-delta rate that ranges between 1.843 MHz and 2.822 MHz. - This wide range of the required sigma-delta rate (1.843 MHz-2.822 MHz) represents a design constraint on the barrier interface (the communication link formed by
interface circuits SSIC 106 and theLSIC 118. In other words, the data rate of the barrier interface must be variable, depending on the sigma-delta rate. - The desired variable data rate for the barrier interface has conventionally been obtained by varying the barrier clock rate to obtain the desired data rate. In a simplified example, if the
modem 100 establishes a v.34 communication with another modem at a symbol rate of 2,400 Hz (for which a ΣΔ rate of 1.843 MHz is needed), theDSP 102 or some otherbarrier clock controller 113 may set the barrier clock rate to a rate equal to two times 1.843 MHz, or 3.686 MHz, so that during each ΣΔ interval, at least one forward ΣΔ sample and one reverse ΣΔ sample may be transmitted across the barrier interface. In contrast, if themodem 100 establishes a v.34 communication at a symbol rate of 3,429 Hz (for which a ΣΔ rate of 2.634 MHz is needed, per Table 1), the barrier clock may be set to a rate of two times 2.634 MHz, or 5.268 MHz, again so that during each ΣΔ interval, at least one forward ΣΔ sample and one reverse ΣΔ sample may be transmitted across the barrier interface. Thus, the clock rate in this simplified example would have to be able to operate over the range from 3.686 MHz to 5.268 MHz (i.e., an increase of 42%) to accommodate the full range of v.34 symbol rates. Moreover, the barrier clock rate would have to be correspondingly increased if control and status information was to be communicated during each ΣΔ interval. - Unfortunately, this conventional technique of varying the barrier clock as a function of the symbol rate or sigma-delta rate causes at least two difficulties. First, if the
LSIC 118 derives its local clock from the barrier signals via a clock recovery circuit, the clock recovery circuit loses synchronism with the barrier signals each time the barrier clock changes. Until the clock recovery circuit re-acquires the new clock rate, the SSIC 106 and the LSIC 118 are unable to communicate. Second, the clock generating circuit in the SSIC 106 and the clock recovery circuit in theLSIC 118 are relatively complicated and expensive, because they must accommodate the entire range of clock rates across the barrier. - Having identified the above difficulties associated with a variable-clock-rate barrier interface, the present inventors developed an innovative communication protocol and barrier interface having an approximately fixed barrier clock and capable of accommodating a variety of symbol rates, sampling rates and/or sigma-delta rates (collectively, “communication rates”). More particularly, the invention employs a variable-length frame that may be expanded or reduced to reach a desired communication rate, even though the barrier clock rate is held approximately constant. Each master frame preferably includes a fixed-length data portion and a variable-length dummy portion. For a fast communication rate, the variable-length dummy portion may be small, such that the overall frame length is small and many frames may be transmitted during a given time period. For a slow communication rate, the variable-length dummy portion may be large, such that the overall frame length is large and only a few frames may be transmitted during the same time period. Thus, the minimum frame length corresponds to the fastest communication rate, while the maximum frame length corresponds to the slowest communication rate.
- The invention further provides a method for designing an agile barrier interface. In particular, the barrier clock rate is preferably selected to be an approximate common multiple of the various communication rates that the barrier interface must handle. The frame length corresponding to each communication rate may then be obtained by dividing the barrier clock rate by the ΣΔ rate.
- Finally, the invention provides an agile communication circuit capable of communicating data across a serial interface at a variety of data rates and at an approximately fixed interface clock rate.
- Various embodiments of the present invention will now be described in detail in conjunction with the annexed drawings, in which:
-
FIG. 1 is a block diagram depicting a communication circuit suitable for use in the invention; -
FIG. 2 is a timing diagram depicting a communication protocol using a variable-length frame in accordance with the invention; and -
FIG. 3 is a timing diagram depicting a further communication protocol for balancing the flux of the isolation barrier over consecutive frames in accordance with the invention. - As described above, the invention employs a variable-length frame that may be expanded or reduced to reach a desired communication rate notwithstanding an approximately fixed barrier clock. An exemplary communication protocol using such a frame is depicted in
FIG. 2 . Paddedframe 220 includes a basic frame 222 (i.e., the fixed-length data portion) and a number of padding bits 230 (the variable-length dummy portion). - The specific composition of the
basic frame 222 will depend on whether the barrier interface has only a single serial communication link or multiple communication links.FIG. 2 depicts an example of the former case, in which the barrier interface is a single serial communication link over which both forward- and reverse-going sigma-delta data and forward- and reverse-going control information is to be transmitted during each master frame. In the frame shown inFIG. 2 , therefore, the SSIC 106 transmits during time slots 201-208 and theLSIC 118 transmits during time slots 209-212. - In order to preserve the flux-balance in the isolation barrier, each transmitted bit is preferably Manchester encoded using a conventional encoder. That is, a “0” bit is encoded as the two-bit sequence 01 and a “1” bit is encoded as the two-bit sequence 10. It should be understood that if flux-balance is not a design concern (e.g., where the isolation barrier is a capacitive barrier), such encoding is not required.
- As shown in
FIG. 2 , thebasic frame 222 preferably includes: - (1) a forward data bit during
time slots 201 and 202 (shown Manchester-encoded as DF, followed by NOT DF), transmitted by SSIC 106; - (2) a forward control bit during
time slots 203 and 204 (shown as CF, NOT CF), transmitted by SSIC 106; - (3) a predetermined forward framing sequence 326 during time slots 205-208 (shown as NOT CF, NOT CF, CF, CF) (transmitted by either SSIC 106 or LSIC 118);
- (4) a reverse data bit during
time slots 209 and 210 (shown as DR, NOT DR), transmitted byLSIC 118; and - (5) a reverse control bit during
time slots 211 and 212 (shown as CR, NOT CR), transmitted byLSIC 118. - It will be recognized, however, that if multiple communication links are available, then the barrier interface can be simplified by making the links uni-directional. If so, then the basic frame may be reduced to the sigma-delta data, control and forward framing sequence for a single direction (i.e., forward or reverse).
- The forward framing sequence may be any unique sequence of bit values that may be used to identify where a frame starts and/or ends. For example, in the protocol shown in
FIG. 2 , the inverse control bit (NOT CF) intime slot 204 is repeated twice thereafter, intime slots -
Padded frame 220 preferably also includes dummy orpadding bits 230, which may be added or removed to adjust the frame size. In this way, a wide variety of data rates may be accommodated without altering the clock rate of the SSIC 180 and the LSIC 182. By way of example, six padding bits (e.g., 0, 1, 0, 1, 0, 1), of alternating values in order to achieve flux balance, are depicted in time slots 213-218. These padding bits may be provided by either theSSIC 106 or theLSIC 118 after the interface has been initialized. -
FIG. 3 illustrates how an odd number of padding bits may be accommodated without disrupting the flux balance of the isolation barrier. In essence, the flux of the padding bits is balanced over two consecutive frames, Frame k and Frame k+1 by using alternating sequences of 0's and 1's. For example, if frame k contains the padding bit sequence [01010], frame k+1 may contain the sequence [10101]. - The invention further provides a method for designing an agile barrier interface. In accordance with the invention, a designer selects a barrier clock rate that is an approximate common multiple of the various data rates that the barrier interface must handle. The designer may then calculate the frame length corresponding to each data rate, by dividing the barrier clock rate by the sigma-delta rate. By way of example and not of limitation, Table 2 below illustrates exemplary frame lengths and barrier clock frequencies calculated for a barrier interface capable of handling sample rates of 7200, 8000, 8229, 8400, 9000, 9600, 10,287, and 11,025 Hz, where the sigma-delta rate is selected to be 256 times the sample rate.
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TABLE 2 Frame Symbol Sample ΣΔ Rate Length Barrier Clock Application rate [Hz] rate [Hz] [MHz] [bits] [MHz] V.34 2400 7200 1.8432 18 33.1776 Audio N/A 8000 2.0480 16 32.7680 V.34 2743 8228 2.1066 16 33.7056 V.34 2800 8400 2.1504 15 32.2560 V.34 3000 9000 2.3040 14 32.2560 V.34 3200 9600 2.4576 14 34.4064 V.34 3429 10287 2.6335 13 34.2355 Audio/ N/A 11025 2.8224 12 33.8688 optional - As reflected in Table 2, one of the approximate common multiples of the above sigma-delta rates (i.e., 1.843-2.822 MHz) is about 33.3 MHz, which is taken as the approximately fixed barrier clock rate. Given the approximately fixed frame barrier clock rate of about 33.3 MHz, the frame length corresponding to each sigma-delta rate may be calculated by dividing the sigma-delta rate into the frame barrier clock frequency. For example, the frame length corresponding to the highest-frequency sigma-delta rate, 2.822 MHz, is calculated as 33.3 MHz/2.822 MHz, or 11.8 clock cycles, which may be rounded up to 12 clock cycles, as shown in Table 2. Similarly, the frame length corresponding to the lowest-frequency sigma-delta rate, 1.843 MHz, is calculated as 33.3 MHz/1.843 MHz, yielding 18.1 clock cycles, which may be rounded down to 18 clock cycles to obtain the frame length corresponding to the 1.843 MHz sigma-delta rate.
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TABLE 3 Frame Symbol Sample ΣΔ Rate Length Barrier Clock Application rate [Hz] rate [Hz] [MHz] [bits] [MHz] V.34 2400 7200 1.8432 20 36.864 Audio N/A 8000 2.0480 18 36.864 V.34 2743 8228 2.1066 17 35.813 V.34 2800 8400 2.1504 17 36.557 V.34 3000 9000 2.3040 16 36.864 V.34 3200 9600 2.4576 15 36.864 V.34 3429 10287 2.6335 14 36.869 Audio/ N/A 11025 2.8224 13 36.691 optional - Table 3 illustrates an example in which a different approximate common multiple of the above sigma-delta rates is selected to be the approximately fixed barrier clock rate—namely, about 36 MHz. Given the approximately fixed frame barrier clock rate of about 36 MHz, the frame length corresponding to each sigma-delta rate is calculated by dividing the sigma-delta rate into the frame barrier clock rate. Thus, the frame length corresponding to the highest-frequency sigma-delta rate, 2.822 MHz, is calculated as 36 MHz/2.822 MHz, yielding 13 clock cycles. Similarly, the frame length corresponding to the lowest-frequency sigma-delta rate, 1.843 MHz, is calculated as 36 MHz/1.843 MHz, yielding 20 clock cycles.
- The method for designing the barrier interface may further include adjusting the approximately fixed barrier clock rate for each sigma-delta rate, whereby rounding errors that are introduced during the selection of the frame length may be corrected. More specifically, after the selection of the approximately fixed barrier clock rate and the frame lengths corresponding to the various sigma-delta rates, a customized barrier clock rate may be selected for each sigma-delta rate, by multiplying each delta sigma rate by its corresponding frame length. Thus, for the example of Table 2, the customized barrier clock rate for a 1.843 MHz sigma-delta rate, with a length of 18 cycles, may be calculated as 33.1776 MHz. Similarly, the customized barrier clock rate for a 2.822 MHz delta sigma rate and a frame length of 12 cycles is 33.8688 MHz. Customized barrier clock rates may be similarly calculated for the remaining sigma-delta rates shown in Table 2. It may be seen from Table 2 that a barrier interface capable of transmitting information at symbol rates including 2400, 2743, 2800, 3000, 3200, and 3429 will preferably be capable of operation at the corresponding customized barrier clock rates shown in Table 2, which range between about 32 MHz and about 35 MHz. The customized barrier clock rates shown in Table 3 may be calculated in a similar manner, resulting in customized barrier clock rates of between about 35 MHz and about 37 MHz.
- The invention further provides an agile communication circuit capable of communicating data across a serial interface at a variety of data rates and at an approximately fixed interface clock rate. Such a communication circuit may be implemented using conventional modem or DAA components as shown in
FIG. 1 and as described above in the Background section. In particular, modem processor/DSP 102 includes a circuit and/or software of a type well-known to those of ordinary skill in the art of modem design for selecting a communication rate (e.g., a desired symbol rate, sample rate, or sigma-delta rate). TheSSIC 106 includes a system I/O interface 108 for communicating with theDSP 102, a conventional sigma-delta modulator 112 for converting forward-going data signals to forward-going sigma-delta signals, a conventional integrator-based sigma-delta decoder circuit for decoding reverse-going sigma-delta signals into data signals, and an isolationbarrier interface circuit 114 for transmitting and receiving sigma-delta signals to and from theLSIC 118 across theisolation barrier 117. TheSSIC 106 further includes aprotocol framing circuit 116, which buffers and organizes the data transmitted and received by the isolationbarrier interface circuit 114. TheSSIC 106 further includes a variable-rate clock generator comprisingbarrier clock controller 113 and associated voltage-controlledoscillator 115, for generating a variable-rate barrier clock signal. - The
LSIC 118 includes an isolationbarrier interface circuit 120, a line-side sigma-delta digital-to-analog converter (“DAC”) 126 whose output is connected to a transmitbuffer 128, and a sigma-delta analog-to-digital converter (“ADC”) 122 whose input is connected to a receivebuffer 124. TheLSIC 118 may further include a clock-and-data recovery circuit 125 to derive a local clock signal from the signals received across the isolation barrier. - The agile communication circuit described above operates as follows. First, modem processor/
DSP 102 selects a frame length and interface clock rate for the digital isolation barrier based on a desired communication rate (i.e., modem symbol rate, sample rate, or sigma-delta rate)—e.g., by looking up the frame length and interface clock rate in a look-up table. Modem processor/DSP 102 then communicates the selected interface clock rate to thebarrier clock controller 113 inSSIC 106. Thebarrier clock controller 113 receives the selected interface clock rate and outputs a corresponding analog signal to the voltage controlledoscillator 115. Based on this analog signal, the voltage-controlled oscillator produces a digital clock signal that may be used ininterface circuit 114 as the isolation barrier clock. - Modem processor/
DSP 102 also communicates the selected frame length to theframer circuit 116 ininterface circuit 114. The framer circuit buffers data from modem processor/DSP 102 and packages the buffered data into frames having the selected frame length, by inserting an appropriate number of padding bits at the end of each basic frame. - The present invention provides a number of advantages over prior art isolation barrier interfaces. In particular, both the voltage-controlled oscillator in the system-side interface circuit that generates the barrier clock and the clock-and-data recovery circuit on the line-side interface circuit are enabled to run at an approximately fixed frequency. Both can stay locked to the approximately fixed frequency even when the sample rate changes. Moreover, because they only need to operate over a relatively small frequency range, they can be optimized for low-jitter performance. Finally, the sigma-delta clock in the line-side circuit may be derived directly from the frame synchronization pulse.
- Having thus described a few particular embodiments of the invention, various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications and improvements as are made obvious by this disclosure are intended to be part of this description though not expressly stated herein, and are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only, and not limiting. The invention is limited only as defined in the following claims and equivalents thereto.
Claims (20)
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US14/291,696 US20140270122A1 (en) | 2005-06-23 | 2014-05-30 | Serial Protocol for Agile Sample Rate Switching |
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US11/159,537 US7940921B2 (en) | 2005-06-23 | 2005-06-23 | Continuous power transfer scheme for two-wire serial link |
US11/159,614 US7773733B2 (en) | 2005-06-23 | 2005-06-23 | Single-transformer digital isolation barrier |
US11/206,314 US8213489B2 (en) | 2005-06-23 | 2005-08-17 | Serial protocol for agile sample rate switching |
US13/444,928 US8761236B2 (en) | 2005-06-23 | 2012-04-12 | Serial protocol for agile sample rate switching |
US14/291,696 US20140270122A1 (en) | 2005-06-23 | 2014-05-30 | Serial Protocol for Agile Sample Rate Switching |
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US14/291,696 Abandoned US20140270122A1 (en) | 2005-06-23 | 2014-05-30 | Serial Protocol for Agile Sample Rate Switching |
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US20060291545A1 (en) | 2006-12-28 |
CN104113389A (en) | 2014-10-22 |
CN102724015B (en) | 2014-07-16 |
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JP2012249313A (en) | 2012-12-13 |
CN102724015A (en) | 2012-10-10 |
CN104113389B (en) | 2016-04-27 |
US8761236B2 (en) | 2014-06-24 |
TW201315188A (en) | 2013-04-01 |
JP5908362B2 (en) | 2016-04-26 |
TWI399956B (en) | 2013-06-21 |
JP2008544697A (en) | 2008-12-04 |
TW200711423A (en) | 2007-03-16 |
TWI465089B (en) | 2014-12-11 |
JP5106389B2 (en) | 2012-12-26 |
US20120195354A1 (en) | 2012-08-02 |
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