US20150001716A1 - De-pop on-device decoupling for bga - Google Patents

De-pop on-device decoupling for bga Download PDF

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Publication number
US20150001716A1
US20150001716A1 US14/489,110 US201414489110A US2015001716A1 US 20150001716 A1 US20150001716 A1 US 20150001716A1 US 201414489110 A US201414489110 A US 201414489110A US 2015001716 A1 US2015001716 A1 US 2015001716A1
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Prior art keywords
eic
bga
package
mount device
grid
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Abandoned
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US14/489,110
Inventor
Alex Chan
Paul James Brown
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Nokia Canada Inc
RPX Corp
Nokia USA Inc
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Alcatel Lucent Canada Inc
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Priority to US14/489,110 priority Critical patent/US20150001716A1/en
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Publication of US20150001716A1 publication Critical patent/US20150001716A1/en
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Assigned to NOKIA USA INC. reassignment NOKIA USA INC. SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: PROVENANCE ASSET GROUP HOLDINGS, LLC, PROVENANCE ASSET GROUP LLC
Assigned to PROVENANCE ASSET GROUP LLC reassignment PROVENANCE ASSET GROUP LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ALCATEL LUCENT SAS, NOKIA SOLUTIONS AND NETWORKS BV, NOKIA TECHNOLOGIES OY
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Assigned to PROVENANCE ASSET GROUP LLC, PROVENANCE ASSET GROUP HOLDINGS LLC reassignment PROVENANCE ASSET GROUP LLC RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: CORTLAND CAPITAL MARKETS SERVICES LLC
Assigned to PROVENANCE ASSET GROUP HOLDINGS LLC, PROVENANCE ASSET GROUP LLC reassignment PROVENANCE ASSET GROUP HOLDINGS LLC RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: NOKIA US HOLDINGS INC.
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Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • G06F17/5068—
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6666—High-frequency adaptations for passive devices for decoupling, e.g. bypass capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13014—Shape in top view being circular or elliptic
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    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1205—Capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1206—Inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1207—Resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/206—Length ranges
    • H01L2924/20648—Length ranges larger or equal to 800 microns less than 900 microns
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
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  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

Embodiments of the invention place surface-mount devices such as decoupling capacitors, resistors or other devices directly on the underside of a ball grid array (BGA) electronic integrated circuit (EIC) package, in place of de-populated BGA pads.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This is a continuation application of U.S. application Ser. No. 13/231,609 filed Sep. 13, 2011, which is hereby incorporated by reference for all purposes as if fully set forth herein.
    • FIELD OF THE INVENTION
  • The invention is directed to Ball Grid Array (BGA) packages for use on electronic circuit cards and more specifically, improved decoupling arrangements.
    • BACKGROUND OF THE INVENTION
  • As electronic integrated circuit (EIC) packages such as Ball Grid Array (BGA) packages increase in density, in interface connection density, and in clock speed, the requirements for electrically decoupling a BGA device become more stringent. It is advantageous to place these coupling capacitors as close to the BGA pads as possible. Typical placement of surface-mount decoupling capacitors is adjacent to the BGA device on the same side of the electronic circuit board (printed circuit board or PCB) or on the opposite side of the electronic circuit board, connected by vias through the circuit board. Both of these techniques can introduce parasitic inductance due to the length of the vias and/or the routing leads.
  • Therefore, improvement to decoupling techniques for BGA devices is highly desirable.
    • SUMMARY OF THE INVENTION
  • Embodiments of the invention place surface-mount devices such as decoupling capacitors, resistors or other devices directly on the underside of a ball grid array (BGA) electronic integrated circuit (EIC) package, in place of de-populated BGA pads.
  • Some embodiments of the invention provide an electronic integrated circuit (EIC) package comprising: an EIC substrate; an array of ball grid array (BGA) pads on a first side of the EIC substrate, arranged in a grid pattern of rows and columns; and contact pads on the first side of the EIC substrate to accommodate electrical connection of a surface-mount device, wherein the surface-mount device occupies a grid location of the grid pattern in place of one or more BGA pads.
  • In some embodiments the contact pads comprise at least two adjacent contact pads.
  • In some embodiments the contact pad is connected to an adjacent BGA pad by a conductor on the first side of the EIC substrate.
  • In some embodiments the surface-mount device comprises a two-port device.
  • In some embodiments the surface-mount device comprises a decoupling capacitor.
  • In some embodiments the surface-mount device is selected from the set of: capacitor, resistor, inductor, diode, transistor, capacitor array, and resistor-capacitor circuit.
  • In some embodiments the BGA grid comprises a pitch of between about 0.4 mm×0.4 mm and about 1.27 mm×1.27 mm.
  • In some embodiments the BGA grid comprises an irregular pitch.
  • Other embodiments of the invention provide a computer-aided design tool for accommodating a surface-mount device on a first surface of a ball grid array (BGA) electronic integrated circuit (EIC) package, the tool comprising: a design tool mode to identify, in an EIC configuration of BGA pads in a grid pattern on the first side of the EIC package, at least two contact pads for forming directly on the first surface, the contact pads for direct mounting of and connection to the surface-mount device, wherein the surface-mount device occupies a grid location of the grid pattern in place of one or more BGA pads.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Some embodiments of apparatus and/or methods in accordance with embodiments of the present invention are now described, by way of example only, and with reference to the accompanying drawings in which:
  • FIG. 1 illustrates a layout of surface mount devices within a BGA grid according to embodiments of the invention
  • FIG. 2 illustrates a layout of surface mount devices within a BGA grid on an EIC substrate according to other embodiments of the invention;
  • FIG. 3A illustrates placement of surface mount devices on an EIC substrate according to an embodiment of the invention;
  • FIG. 3B illustrates placement of surface mount devices between BGA solder balls on an EIC substrate according to an embodiment of the invention; and
  • FIG. 3C illustrates placement of an EIC device on a printed circuit board according to an embodiment of the invention.
    •
  • In the figures, like features are denoted by like reference characters.
    • DETAILED DESCRIPTION
  • FIG. 1 illustrates a bottom surface layout of an electronic integrated circuit (EIC) package having BGA pads 102 arranged in a BGA grid pitch of 0.80 mm×0.80 mm. Certain BGA pads (105, 109, 115, 117) are de-populated and the resulting free space is used for placing surface- mount decoupling capacitors 104, 106, 108, 110, 112, 114, and 116. By depopulating BGA pad 105, there is room to mount a ‘0402’ package surface-mount capacitor 104. In a similar manner, BGA pad 109 is de-populated to provide room for two ‘0201’ package surface- mount capacitors 106, 108. BGA pad 115 is de-populated to provide room for three ‘01005’ package surface- mount capacitors 110, 112, 114. BGA pad 117 is de-populated to provide room for capacitor array 116 in a standard ‘0302’ surface-mount package (0.030″×0.020″). The surface-mount devices can be placed in a variety of orientations including longitudinally, laterally or diagonally with respect to the BGA grid.
  • FIG. 2 illustrates a bottom surface layout of an electronic integrated circuit (EIC) package having BGA pads 202 arranged in a BGA grid pitch of 1.00 mm×1.00 mm. BGA pad 207 is de-populated and the resulting free space is used for placing two ‘0201’ package surface- mount decoupling capacitors 204, 206. BGA pad 209 is similarly de-populated and the resulting free space is used for placing a ‘0402’ package surface-mount decoupling capacitor 209. BGA pad 211 is de-populated to provide room for capacitor array 210 in a standard ‘0302’ surface-mount package and BGA pad 215 is de-populated to provide room for placing three ‘01005’ package surface- mount decoupling capacitors 212, 213, and 214.
  • Many BGA EIC packages do not use the full array of BGA pads which can provide the flexibility to use the space for surface-mount components. This can be especially advantageous for devices such as decoupling capacitors which benefit from mounting in close proximity to BGA pads for voltage supply connections and ground connections on BGA EIC packages to minimize parasitic inductance. As the trend toward using BGA grid patterns with smaller pitches continues, such as 1.27 mm×1.27 mm, 1.0 mm×1.0 mm, 0.8 mm×0.8 mm, and 0.5 mm×0.5 mm there is less space available between BGA pads in a full BGA grid pattern for mounting surface-mount components such as standard ‘0402’ surface-mount package (0.04″×0.02″), ‘0201’ package (0.020″×0.010″) or ‘01005’ package (0.010″×0.005″). Embodiments of this invention advantageously provide for locating surface mount components in place of BGA pads at ball grid array locations. Embodiments of the invention are suited as well for BGA packages having an irregular pitch where longitudinal rows have a different pitch than lateral rows such as for example 0.8 mm×1.0 mm
  • Other embodiments contemplated by this invention include depopulating a plurality of BGA pads on a BGA EIC package in order to accommodate surface-mount devices between the remaining BGA pads.
  • Additional embodiments of this invention contemplate the use of surface-mount devices including two-port devices such as capacitors, resistors, diodes, inductors, etc. as well as multi-port devices such as capacitor arrays, resistor-capacitor combinations, as well as active devices such as transistors.
  • FIGS. 3A, 3B, 3C illustrate placement of surface-mount devices on an EIC substrate 302 relative to BGA solder spheres 314 and an electronic printed circuit board 318. The EIC has a substrate 302 and cover or overmold 304 to protect the integrated circuit. On a first surface 303 of substrate 302, are BGA pads 306 arranged in a grid pattern. BGA pad 307 is de-populated, that is, if the BGA grid pattern were full, there would be a BGA pad at location 307. By not populating BGA pad 307, there is space to accommodate surface-mount device 310. Contact pads 308 can be connected to adjacent BGA pads 306 to minimize connection distance between device 310 and the circuitry of BGA EIC 302 as discussed previously.
  • During assembly, surface-mount component 310 is placed on surface-mount pads 308 which have been previously prepared with solder paste 311. Surface-mount device 310 can be held in position with the tacky solder paste 311 on the surface mount pads and optionally by adhesive 313 between the body of device 310 and the surface 303. Additional surface mount devices are handled similarly to device 310. BGA solder balls (spheres) 314 are applied onto BGA pads 306. The balls 314 can be held in place by tacky flux as is well known in the art. The EIC package assembly 315 with surface mount devices 310, 312 and solder balls 314 is then reflow-soldered to form an electrical and mechanical bond between surface-mount device 310 and pads 308 and between BGA solder balls 314 and BGA pads 306. Solder paste 311 reflows to form solder fillets 316.
  • EIC package assembly 319 with solder balls 314 and with surface-mount device 310 can then be operationally tested as a unit to verify operation of the EIC in conjunction with device 310. Devices 310, 312 and solder fillets 316, 317 can also be easily visually inspected at this stage. Advantageously, it is easier to address any problems with the surface- mount components 310, 312 then after the EIC is mounted on a printed circuit board. These steps can be performed by the manufacturer of the EIC assembly prior to delivery to a customer who would mount the EIC assembly on an electronic printed circuit board.
  • With reference to FIG. 3C, assembly 319 can then be mounted on printed circuit board 318 and reflow soldered to bond solder balls 314 to BGA solder pads 320. Note that it is possible to mount EIC package assembly 319 with surface-mount component 310 over top of unused BGA pad 321 on printed circuit board 318. In this manner, EIC package designs having unused BGA pads (no connection) could be redesigned to accommodate surface-mount devices occupying the location of an unused BGA pad 307. Such a modified design could be used with a printed circuit board where the corresponding no-connection BGA pad 321 is still present. Otherwise, future EIC packages can be designed to optimize the location of decoupling capacitors between voltage source connections and ground connections and printed circuit boards can be designed accordingly.
  • The description and drawings merely illustrate the principles of the invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples recited herein are principally intended expressly to be only for pedagogical purposes to aid the reader in understanding the principles of the invention and the concepts contributed by the inventor(s) to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.
  • It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative circuitry embodying the principles of the invention. Numerous modifications, variations and adaptations may be made to the embodiment of the invention described above without departing from the scope of the invention, which is defined in the claims.

Claims (17)

What is claimed is:
1. An electronic integrated circuit (EIC) package comprising:
an EIC substrate;
an array of ball grid array (BGA) pads on a first side of said EIC substrate, arranged in a grid pattern of rows and columns; and
contact pads on said first side of said EIC substrate to accommodate electrical connection of a surface-mount device, wherein said surface-mount device occupies a grid location of said grid pattern in place of one or more BGA pads.
2. The EIC package of claim 1, wherein said contact pads comprise at least two adjacent contact pads.
3. The EIC package of claim 2, wherein each of the contact pads is connected to an adjacent BGA pad by a conductor on said first side of said EIC substrate.
4. The EIC package of claim 1, wherein said surface-mount device comprises a two-port device.
5. The EIC package of claim 4, wherein said surface-mount device comprises a decoupling capacitor.
6. The EIC package of claim 1, wherein said surface-mount device is selected from a set of a capacitor, a resistor, an inductor, a diode, a transistor, a capacitor array, and a resistor-capacitor circuit.
7. The EIC package of claim 1, wherein said BGA grid comprises a pitch of between about 0.4 mm×0.4 mm and about 1.27 mm×1.27 mm.
8. The EIC package of claim 7, wherein said BGA grid comprises an irregular pitch.
9. A computer-aided design tool for accommodating a surface-mount device on a first surface of a ball grid array (BGA) electronic integrated circuit (EIC) package, said tool comprising:
a design tool configured to identify, in an EIC configuration of BGA pads in a grid pattern on said first side of said EIC package, at least two contact pads for forming directly on said first surface, said contact pads for direct mounting of and connection to said surface-mount device, wherein said surface-mount device occupies a grid location of said grid pattern in place of one or more BGA pads.
10. The computer-aided design tool of claim 9, wherein each of the contact pads is connected to an adjacent BGA pad by a conductor on said first side of said EIC package.
11. The computer-aided design tool of claim 9, wherein said surface-mount device comprises a two-port device.
12. The computer-aided design tool of claim 11, wherein said surface-mount device comprises a decoupling capacitor.
13. The computer-aided design tool of claim 9, wherein said surface-mount device is selected from a set of a capacitor, a resistor, an inductor, a diode, a transistor, a capacitor array, and a resistor-capacitor circuit.
14. The computer-aided design tool of claim 9, wherein said BGA grid comprises a pitch of between about 0.4 mm×0.4 mm and about 1.27 mm×1.27 mm.
15. The computer-aided design tool of claim 14, wherein said BGA grid comprises an irregular pitch.
16. The EIC package of claim 1, wherein the surface-mount device is placed diagonally with respect to the grid pattern.
17. The computer-aided design tool of claim 9, wherein the surface-mount device is placed diagonally with respect to the grid pattern.
US14/489,110 2011-09-13 2014-09-17 De-pop on-device decoupling for bga Abandoned US20150001716A1 (en)

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