US20150097196A1 - Integrated Device Including Silicon and III-Nitride Semiconductor Devices - Google Patents
Integrated Device Including Silicon and III-Nitride Semiconductor Devices Download PDFInfo
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- US20150097196A1 US20150097196A1 US14/515,233 US201414515233A US2015097196A1 US 20150097196 A1 US20150097196 A1 US 20150097196A1 US 201414515233 A US201414515233 A US 201414515233A US 2015097196 A1 US2015097196 A1 US 2015097196A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 122
- 229910052710 silicon Inorganic materials 0.000 title claims description 35
- 239000010703 silicon Substances 0.000 title claims description 35
- 239000000463 material Substances 0.000 claims abstract description 61
- 239000000758 substrate Substances 0.000 claims abstract description 40
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 34
- 239000011229 interlayer Substances 0.000 claims description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 238000009413 insulation Methods 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 2
- 229910045601 alloy Inorganic materials 0.000 claims description 2
- 229910002704 AlGaN Inorganic materials 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 10
- 230000004888 barrier function Effects 0.000 description 8
- 229910052681 coesite Inorganic materials 0.000 description 6
- 229910052906 cristobalite Inorganic materials 0.000 description 6
- 239000010410 layer Substances 0.000 description 6
- 229910052682 stishovite Inorganic materials 0.000 description 6
- 229910052905 tridymite Inorganic materials 0.000 description 6
- 230000008901 benefit Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
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- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
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Definitions
- the present invention relates to semiconductor devices and methods for fabricating semiconductor devices.
- Some semiconductor materials such as silicon are desirable as base material for forming IC devices for, for example, driving other devices such as power MOSFETs.
- III-N semiconductor materials may are desirable for serving as a base material for power switching devices.
- One example of such a material is GaN.
- a semiconductor device includes:
- a second semiconductor device formed over the first surface and disposed lateral to the first semiconductor device
- the first semiconductor device is comprised of a first semiconductor material
- the second semiconductor device is comprised of a second semiconductor material that is different from the first semiconductor material
- the second material may have a higher band gap than the first material.
- the first material may be silicon and the second material may be a III-N semiconductor material.
- An example of a III-nitride material is GaN. While Si, SiC, sapphire, or even GaN can be used as a substrate, silicon is most preferred for economic reasons.
- the first semiconductor device may include a control IC and the second semiconductor device may be a power switching device that is controlled by the control IC.
- a device according to the present invention may further include an insulation wall disposed between the first semiconductor device and the second semiconductor device.
- the device may further include an interlayer disposed between the second semiconductor device and the common substrate.
- the common substrate may be comprised of silicon
- the first material may be comprised of silicon
- the second material may be comprised of a III-N semiconductor
- the interlayer may be comprised of a compositionally graded III-N material (e.g. AlN)
- the insulation wall may be comprised of silicon dioxide.
- the first semiconductor device may be formed in ⁇ 100> silicon that is epitaxially formed over a ⁇ 100> silicon wafer.
- the second semiconductor device is comprised of a III-N semiconductor material that is formed on a ⁇ 111> silicon body residing on a silicon dioxide body lying on the substrate.
- a method according to the present invention may include:
- the one semiconductor material may be comprised of silicon and the another semiconductor material may be comprised of a semiconductor material of a higher band gap than that of silicon.
- the one semiconductor material may be comprised of silicon and the another semiconductor material may be comprised of a III-N semiconductor material, such as a semiconductor alloy from the InAlGaN system (e.g. GaN).
- FIGS. 1-5 each shows a cross-sectional view of a portion of a wafer containing a die according to the first, second, third, fourth, and fifth embodiment of the present invention respectively.
- FIGS. 6A-6C illustrate a process for fabricating a device according to the present invention.
- FIGS. 7A-7D illustrate an alternative process for fabricating a device according to the present invention.
- FIGS. 8A-8D illustrate another alternative process for fabricating a device according to the present invention.
- a semiconductor device would include at least first semiconductor body 14 , and at least second semiconductor body 16 disposed lateral to first semiconductor body 14 .
- first semiconductor body 14 and second semiconductor body 16 are formed over common substrate 18 .
- first semiconductor body 14 is comprised of a first semiconductor material such as silicon
- second semiconductor body 16 is comprised of a second semiconductor material that is different from the first semiconductor material.
- second semiconductor material has a higher band gap than that of silicon, such a III-N semiconductor material.
- a preferred material for forming second semiconductor body 16 is GaN.
- GaN is preferred in that it can be used to form a power device such as a high electron mobility transistor (HEMT).
- a die according to the present invention an be used as a basic platform for forming a semiconductor device having a control IC formed in first semiconductor body 14 , which is made preferably from silicon, and a power device, such as a HEMT, in second semiconductor body 16 .
- substrate 18 is formed from silicon for economic reasons.
- substrate materials such as SiC or Sapphire may be used without deviating from the scope and spirit of the present invention.
- first semiconductor body 14 and substrate 18 are composed of the same material, for example, Si, while second semiconductor body 16 is comprised of another semiconductor material, for example, GaN.
- interlayer 20 can be disposed between second semiconductor body 16 and substrate 20 .
- Interlayer 20 may be required, for example, to alleviate stresses which may be caused by the dissimilarity between second semiconductor body 16 and substrate 18 .
- interlayer 20 may be composed of a composition graded GaN body.
- interlayer 20 may include more than one material body.
- interlayer 20 may include first interlayer 22 , and second interlayer 24 stacked over first interlayer 22 .
- Second semiconductor body 16 is disposed atop second interlayer 24
- first interlayer 22 is disposed atop substrate 18 .
- second semiconductor body 16 is composed of GaN
- substrate 18 and first semiconductor body 14 are composed of (100) silicon.
- the (100) silicon is particularly desired for fabricating an IC circuit.
- first interlayer 22 is composed of SiO 2
- second interlayer 24 is composed of (111).
- barrier 26 is disposed between first semiconductor body 14 and second semiconductor body 16 .
- Barrier 26 may be composed of a dielectric material such as SiO 2 or SiN, and may extend to substrate 18 , whereby it is lodged between first semiconductor body 14 and second semiconductor body 16 .
- the fourth embodiment of the present invention is similar to the first embodiment except that it also includes a barrier 26 between first semiconductor body 14 and second semiconductor body 16 .
- Barrier 26 is preferably composed of a dielectric such as SiO 2 or SiN and extends from the top surfaces of first semiconductor body 14 and second semiconductor body 16 to substrate 18 .
- the fifth embodiment of the present invention is similar to the fourth embodiment except that it includes interlayer 20 disposed between second semiconductor body 16 and substrate 18 .
- substrate 18 is preferably composed of silicon
- second semiconductor body 16 is composed of GaN
- interlayer 20 is composed of compositionally graded GaN.
- a wafer comprising substrate 18 , and a semiconductor body 30 disposed over a major surface of substrate 18 is provided.
- Substrate 18 may be composed of silicon and semiconductor body 30 may be composed of a material for forming second semiconductor bodies 16 , such as III-Nitride material, for example, GaN.
- a material body 32 for forming interlayers 20 may also be included with the wafer.
- portions of the wafer shown in FIG. 6A are removed to create a plurality of cavities 34 each reaching at least substrate 18 .
- a plurality of second semiconductor bodies 16 and interlayers 20 are also formed.
- a first semiconductor body 14 is formed in each respective cavity 34 by, for example, epitaxial growth or the like.
- silicon is epitaxially grown over the exposed surfaces at the bottom of cavities 34 by epitaxial growth to form first semiconductor bodies 14 , as seen in FIG. 6C .
- an alternative process for fabricating a device according to the present invention includes providing a wafer having a substrate 18 , and a semiconductor body 36 which is preferably comprised of a material for forming first semiconductor bodies 14 .
- substrate 18 may be composed of silicon and semiconductor body 36 may also be composed of silicon.
- semiconductor body 36 and substrate 18 a single crystal wafer of silicon may be used.
- portions of semiconductor body 36 are removed to create cavities 38 each reaching at least substrate 18 , and to form first semiconductor bodies 14 .
- barriers 26 are formed on the sidewalls of cavities 38 .
- the silicon sidewalls of cavities 38 are oxidized to form barriers 26 composed of SiO 2 .
- second semiconductor bodies 16 are formed in respective cavities 38 by epitaxial growth or the like over the exposed surface of substrate 18 at the bottom of each cavity 38 .
- a respective interlayer 20 is formed at the bottom of each respective cavity 38 over substrate 18 .
- interlayers 20 composed of compositionally graded GaN or the like may be formed prior to forming second semiconductor bodies 16 .
- a wafer that includes substrate 18 having a material stack atop thereof is provided.
- Material stack 40 includes first layer 42 , second layer 44 , and third layer 46 .
- substrate 18 is composed of (100) silicon
- first layer 42 is composed of SiO 2
- second layer 44 is composed of (111) silicon
- third layer 46 is composed of a material for forming second semiconductor bodies 16 , such a III-Nitride material, for example, GaN.
- first semiconductor bodies 14 are formed in each cavity over the exposed surface of substrate 18 at the bottom thereof.
- first semiconductor bodies 14 are formed with (100) silicon, which is a desirable material for forming IC's.
Abstract
Description
- This application is based on and claims benefit of U.S. Provisional Application No. 60/690,389, filed on Jun. 14, 2005, entitled METHODS OF COMBINING SILICON AND III-NITRIDE MATERIAL ON A SINGLE WAFER, to which a claim of priority is hereby made and the disclosure of which is incorporated herein by reference.
- The present invention relates to semiconductor devices and methods for fabricating semiconductor devices.
- Some semiconductor materials such as silicon are desirable as base material for forming IC devices for, for example, driving other devices such as power MOSFETs.
- Other materials are desirable for forming switching devices. For example, III-N semiconductor materials may are desirable for serving as a base material for power switching devices. One example of such a material is GaN.
- It is desirable to have a single die which includes one semiconductor body with optimum use for an IC application and another for power switching application so that the driver IC and the power switch may be formed in a common die.
- A semiconductor device according to the present invention includes:
- a common substrate;
- a first semiconductor device formed over a first surface of the substrate; and
- a second semiconductor device formed over the first surface and disposed lateral to the first semiconductor device;
- wherein the first semiconductor device is comprised of a first semiconductor material, and the second semiconductor device is comprised of a second semiconductor material that is different from the first semiconductor material.
- According to one aspect of the present invention the second material may have a higher band gap than the first material. Thus, for example, the first material may be silicon and the second material may be a III-N semiconductor material. An example of a III-nitride material is GaN. While Si, SiC, sapphire, or even GaN can be used as a substrate, silicon is most preferred for economic reasons.
- According to another aspect of the present invention the first semiconductor device may include a control IC and the second semiconductor device may be a power switching device that is controlled by the control IC.
- A device according to the present invention may further include an insulation wall disposed between the first semiconductor device and the second semiconductor device. In addition, the device may further include an interlayer disposed between the second semiconductor device and the common substrate.
- In one preferred embodiment, the common substrate may be comprised of silicon, the first material may be comprised of silicon, the second material may be comprised of a III-N semiconductor, the interlayer may be comprised of a compositionally graded III-N material (e.g. AlN), and the insulation wall may be comprised of silicon dioxide. Preferably, the first semiconductor device may be formed in <100> silicon that is epitaxially formed over a <100> silicon wafer. Moreover, preferably, the second semiconductor device is comprised of a III-N semiconductor material that is formed on a <111> silicon body residing on a silicon dioxide body lying on the substrate.
- A method according to the present invention may include:
- providing a semiconductor body of one semiconductor material;
- removing a portion of the semiconductor body to create a receiving region; and
- forming another semiconductor body of another semiconductor material in the receiving region.
- According to one aspect of the present invention the one semiconductor material may be comprised of silicon and the another semiconductor material may be comprised of a semiconductor material of a higher band gap than that of silicon. For example, the one semiconductor material may be comprised of silicon and the another semiconductor material may be comprised of a III-N semiconductor material, such as a semiconductor alloy from the InAlGaN system (e.g. GaN).
- Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.
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FIGS. 1-5 each shows a cross-sectional view of a portion of a wafer containing a die according to the first, second, third, fourth, and fifth embodiment of the present invention respectively. -
FIGS. 6A-6C illustrate a process for fabricating a device according to the present invention. -
FIGS. 7A-7D illustrate an alternative process for fabricating a device according to the present invention. -
FIGS. 8A-8D illustrate another alternative process for fabricating a device according to the present invention. - Referring to
FIG. 1 , there is shown a portion of awafer 10 containing a plurality of semiconductor die 12 according to the present invention. A semiconductor device according to the present invention would include at leastfirst semiconductor body 14, and at leastsecond semiconductor body 16 disposed lateral tofirst semiconductor body 14. Preferably,first semiconductor body 14 andsecond semiconductor body 16 are formed overcommon substrate 18. According to the present inventionfirst semiconductor body 14 is comprised of a first semiconductor material such as silicon, andsecond semiconductor body 16 is comprised of a second semiconductor material that is different from the first semiconductor material. For example, second semiconductor material has a higher band gap than that of silicon, such a III-N semiconductor material. A preferred material for formingsecond semiconductor body 16 is GaN. - GaN is preferred in that it can be used to form a power device such as a high electron mobility transistor (HEMT). Thus, a die according to the present invention an be used as a basic platform for forming a semiconductor device having a control IC formed in
first semiconductor body 14, which is made preferably from silicon, and a power device, such as a HEMT, insecond semiconductor body 16. - It should be noted that in the preferred
embodiment substrate 18 is formed from silicon for economic reasons. However, other substrate materials such as SiC or Sapphire may be used without deviating from the scope and spirit of the present invention. - Referring to
FIG. 2 , according to the second embodiment of the present inventionfirst semiconductor body 14 andsubstrate 18 are composed of the same material, for example, Si, whilesecond semiconductor body 16 is comprised of another semiconductor material, for example, GaN. Thus, according to the second embodiment of thepresent invention interlayer 20 can be disposed betweensecond semiconductor body 16 andsubstrate 20.Interlayer 20 may be required, for example, to alleviate stresses which may be caused by the dissimilarity betweensecond semiconductor body 16 andsubstrate 18. Thus, in the preferred embodiment in whichsecond semiconductor body 16 is composed of GaN andsubstrate 18 is composed of Si,interlayer 20 may be composed of a composition graded GaN body. - Referring next to
FIG. 3 , according to the third embodiment of the present invention,interlayer 20 may include more than one material body. Thus,interlayer 20 may includefirst interlayer 22, andsecond interlayer 24 stacked overfirst interlayer 22.Second semiconductor body 16 is disposed atopsecond interlayer 24, andfirst interlayer 22 is disposed atopsubstrate 18. In the preferred embodiment of the present invention,second semiconductor body 16 is composed of GaN, andsubstrate 18 andfirst semiconductor body 14 are composed of (100) silicon. the (100) silicon is particularly desired for fabricating an IC circuit. However, it is desired to have (111) as a base for GaN. Thus, in the preferred embodimentfirst interlayer 22 is composed of SiO2, andsecond interlayer 24 is composed of (111). As a result, according to the preferred embodiment of the first embodiment a (100) silicon body and a GaN body can be formed on a common substrate. Aninterlayer 20 having more than one material body, therefore, enables the designer to optimize the crystal orientation of the materials used. Also, preferably, in the third embodiment of thepresent invention barrier 26 is disposed betweenfirst semiconductor body 14 andsecond semiconductor body 16.Barrier 26 may be composed of a dielectric material such as SiO2 or SiN, and may extend tosubstrate 18, whereby it is lodged betweenfirst semiconductor body 14 andsecond semiconductor body 16. - Referring next to
FIG. 4 , the fourth embodiment of the present invention is similar to the first embodiment except that it also includes abarrier 26 betweenfirst semiconductor body 14 andsecond semiconductor body 16.Barrier 26 is preferably composed of a dielectric such as SiO2 or SiN and extends from the top surfaces offirst semiconductor body 14 andsecond semiconductor body 16 tosubstrate 18. - Referring next to
FIG. 5 , the fifth embodiment of the present invention is similar to the fourth embodiment except that it includesinterlayer 20 disposed betweensecond semiconductor body 16 andsubstrate 18. In the preferred embodiment of thepresent invention substrate 18 is preferably composed of silicon,second semiconductor body 16 is composed of GaN andinterlayer 20 is composed of compositionally graded GaN. - Referring now to
FIGS. 6A-6C , in a process for fabricating a device according to the present invention awafer comprising substrate 18, and asemiconductor body 30 disposed over a major surface ofsubstrate 18 is provided.Substrate 18 may be composed of silicon andsemiconductor body 30 may be composed of a material for formingsecond semiconductor bodies 16, such as III-Nitride material, for example, GaN. Note that amaterial body 32 for forminginterlayers 20 may also be included with the wafer. - Referring next to
FIG. 613 , portions of the wafer shown inFIG. 6A are removed to create a plurality ofcavities 34 each reaching atleast substrate 18. As a result, a plurality ofsecond semiconductor bodies 16 andinterlayers 20 are also formed. Thereafter, afirst semiconductor body 14 is formed in eachrespective cavity 34 by, for example, epitaxial growth or the like. Thus, in the preferred embodiment silicon is epitaxially grown over the exposed surfaces at the bottom ofcavities 34 by epitaxial growth to formfirst semiconductor bodies 14, as seen inFIG. 6C . - Referring next to
FIGS. 7A-7D , an alternative process for fabricating a device according to the present invention includes providing a wafer having asubstrate 18, and asemiconductor body 36 which is preferably comprised of a material for formingfirst semiconductor bodies 14. In the preferred embodiment,substrate 18 may be composed of silicon andsemiconductor body 36 may also be composed of silicon. Alternatively, instead ofsemiconductor body 36 andsubstrate 18, a single crystal wafer of silicon may be used. - Referring next to
FIG. 7B , portions ofsemiconductor body 36 are removed to createcavities 38 each reaching atleast substrate 18, and to formfirst semiconductor bodies 14. Thereafter,barriers 26 are formed on the sidewalls ofcavities 38. Thus, in the preferred embodiment, the silicon sidewalls ofcavities 38 are oxidized to formbarriers 26 composed of SiO2. - Referring next to
FIG. 7C , according to one alternative processsecond semiconductor bodies 16 are formed inrespective cavities 38 by epitaxial growth or the like over the exposed surface ofsubstrate 18 at the bottom of eachcavity 38. - Referring next to
FIG. 7D , in another alternate embodiment, prior to formation of second semiconductor bodies 16 arespective interlayer 20 is formed at the bottom of eachrespective cavity 38 oversubstrate 18. Thus, for example, when GaN or another III-Nitride material is selected for formingsecond semiconductor bodies 16,interlayers 20 composed of compositionally graded GaN or the like may be formed prior to formingsecond semiconductor bodies 16. - Referring next to
FIGS. 8A-8D , in yet another alternate process for fabricating a device according to the present invention, a wafer that includessubstrate 18 having a material stack atop thereof is provided.Material stack 40 includes first layer 42,second layer 44, andthird layer 46. In the preferred embodiment of the present invention,substrate 18 is composed of (100) silicon, first layer 42 is composed of SiO2,second layer 44 is composed of (111) silicon, andthird layer 46 is composed of a material for formingsecond semiconductor bodies 16, such a III-Nitride material, for example, GaN. - Referring next to
FIG. 8B , portions ofstack 40 are removed to createcavities 48 each reaching at least an exposed surface ofsubstrate 18, and to createsecond semiconductor bodies 16, andfirst interlayer 22 andsecond interlayer 24 under eachsecond semiconductor body 16. Next,barriers 26 are formed on the sidewalls of eachcavity 48 as seen inFIG. 8C .Barriers 26 may be formed of a dielectric material such as SiO2 or SiN or the like. Thereafter, afirst semiconductor body 14 is formed in each cavity over the exposed surface ofsubstrate 18 at the bottom thereof. In the preferred embodiment of the present invention,first semiconductor bodies 14 are formed with (100) silicon, which is a desirable material for forming IC's. - Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.
Claims (15)
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US11/452,549 US8866190B2 (en) | 2005-06-14 | 2006-06-14 | Methods of combining silicon and III-nitride material on a single wafer |
US14/515,233 US20150097196A1 (en) | 2005-06-14 | 2014-10-15 | Integrated Device Including Silicon and III-Nitride Semiconductor Devices |
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US9219058B2 (en) * | 2010-03-01 | 2015-12-22 | Infineon Technologies Americas Corp. | Efficient high voltage switching circuits and monolithic integration of same |
US8389348B2 (en) * | 2010-09-14 | 2013-03-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanism of forming SiC crystalline on Si substrates to allow integration of GaN and Si electronics |
US9053930B2 (en) | 2012-04-17 | 2015-06-09 | International Business Machines Corporation | Heterogeneous integration of group III nitride on silicon for advanced integrated circuits |
US9048173B2 (en) | 2012-11-15 | 2015-06-02 | International Business Machines Corporation | Dual phase gallium nitride material formation on (100) silicon |
US9099381B2 (en) | 2012-11-15 | 2015-08-04 | International Business Machines Corporation | Selective gallium nitride regrowth on (100) silicon |
JP6763703B2 (en) * | 2016-06-17 | 2020-09-30 | ラピスセミコンダクタ株式会社 | Semiconductor devices and methods for manufacturing semiconductor devices |
US10438792B2 (en) * | 2016-10-20 | 2019-10-08 | QROMIS, Inc. | Methods for integration of elemental and compound semiconductors on a ceramic substrate |
US10468454B1 (en) | 2018-04-25 | 2019-11-05 | Globalfoundries Singapore Pte. Ltd. | GaN stack acoustic reflector and method for producing the same |
US10651033B1 (en) * | 2019-01-07 | 2020-05-12 | Vanguard International Semiconductor Corporation | Semiconductor device structures and methods for manufacturing the same |
KR20210074871A (en) | 2019-12-12 | 2021-06-22 | 삼성전자주식회사 | Semiconductor device and method of fabricating the same |
US20220139709A1 (en) * | 2020-11-05 | 2022-05-05 | International Business Machines Corporation | Confined gallium nitride epitaxial layers |
CN113130297A (en) * | 2021-03-24 | 2021-07-16 | 聚能晶源(青岛)半导体材料有限公司 | Silicon-gallium nitride composite substrate, composite device and preparation method |
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