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Numéro de publicationUS20160094299 A1
Type de publicationDemande
Numéro de demandeUS 14/955,525
Date de publication31 mars 2016
Date de dépôt1 déc. 2015
Date de priorité27 juin 2013
Autre référence de publicationCN104253292A, EP2991223A1, EP2991223A4, US9634772, WO2014206271A1
Numéro de publication14955525, 955525, US 2016/0094299 A1, US 2016/094299 A1, US 20160094299 A1, US 20160094299A1, US 2016094299 A1, US 2016094299A1, US-A1-20160094299, US-A1-2016094299, US2016/0094299A1, US2016/094299A1, US20160094299 A1, US20160094299A1, US2016094299 A1, US2016094299A1
InventeursYongchao Wang, Hui Zhang, Feng Dong, Yajun Wang, Yueyun Cheng
Cessionnaire d'origineHuawei Device Co., Ltd.
Exporter la citationBiBTeX, EndNote, RefMan
Liens externes: USPTO, Cession USPTO, Espacenet
Harmonic Suppression System
US 20160094299 A1
Résumé
A harmonic suppression system, including an interface connector is connected to a common end of a first differential SPMT switch; a control port of the first differential SPMT switch is connected to a control port of a second differential SPMT switch, and a gating throw end of the first differential SPMT switch is separately connected to one end of each LC trap network in a one-to-one correspondence; the control port of the second differential SPMT switch is connected to a baseband chip, each gating throw end of the second differential SPMT switch is separately connected to the other end of each LC trap network in a one-to-one correspondence, and a common end of the second differential SPMT switch is connected to the baseband chip; the baseband chip is connected to an antenna switch; and the antenna switch is connected to a antenna.
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Revendications(9)
What is claimed is:
1. A harmonic suppression system, comprising:
an interface connector;
a baseband chip;
an antenna;
an antenna switch;
at least two LC trap networks;
a first differential single-pole multi-throw (SPMT) switch; and
a second differential single-pole multi-throw, SPMT, switch, wherein the interface connector is connected to a common end of the first differential SPMT switch,
wherein a control port of the first differential SPMT switch is connected to a control port of the second differential SPMT switch, the control port of the second differential SPMT switch is connected to the baseband chip, and each gating throw end of multiple gating throw ends of the first differential SPMT switch is connected to each gating throw end of multiple gating throw ends of the second differential SPMT switch in a one-to-one correspondence separately using each LC wave trap network of the at least two LC trap networks,
wherein a common end of the second differential SPMT switch is connected to the baseband chip,
wherein the baseband chip is connected to the antenna using the antenna switch; the baseband chip is configured to determine an operating frequency band of the antenna, and if it is determined that the operating frequency band is one of multiple preset frequency bands, send a preset gating control signal corresponding to the operating frequency band to the control port of the first differential SPMT switch and to the control port of the second differential SPMT switch, wherein each frequency band of the multiple preset frequency bands is in a one-to-one correspondence with each LC trap network of the at least two LC trap networks,
wherein the first differential SPMT switch is configured to electrically connect, according to the preset gating control signal, the interface connector and an LC trap network corresponding to the operating frequency band, and
wherein the second differential SPMT switch is configured to electrically connect, according to the preset gating control signal, the baseband chip and the LC trap network corresponding to the operating frequency band.
2. The system according to claim 1, wherein the first differential SPMT switch and the second differential SPMT switch further comprise straight-through throw ends, and a straight-through throw end of the first differential SPMT switch is connected to a straight-through throw end of the second differential SPMT switch,
wherein the baseband chip is further configured to send a straight-through control signal to the control port of the first differential SPMT switch and to the control port of the second differential SPMT switch when it is determined that the operating frequency band is not any one of the multiple preset frequency bands,
wherein the first differential SPMT switch electrically connects the interface connector and the straight-through throw end of the first differential SPMT switch according to the straight-through control signal, and
wherein the second differential SPMT switch electrically connects the baseband chip and the straight-through throw end of the second differential SPMT switch according to the straight-through control signal.
3. The system according to claim 1, wherein the baseband chip is connected to the antenna using a control port of the antenna switch, and wherein the baseband chip is further configured to send, after the operating frequency band of the antenna is determined, a preset antenna switch control signal corresponding to the operating frequency band to the control port of the antenna switch, such that the antenna switch switches a frequency band of an operating signal of the antenna to the operating frequency band according to the preset antenna switch control signal.
4. The system according to claim 2, wherein the baseband chip is connected to the antenna using a control port of the antenna switch, and wherein the baseband chip is further configured to send, after the operating frequency band of the antenna is determined, a preset antenna switch control signal corresponding to the operating frequency band to the control port of the antenna switch, such that the antenna switch switches a frequency band of an operating signal of the antenna to the operating frequency band according to the preset antenna switch control signal.
5. The system according to claim 1, wherein each LC trap network comprises:
an LC trap circuit;
a first port connected to the gating throw end of the first differential SPMT switch; and
a second port connected to the gating throw end of the second differential SPMT switch, wherein the first port comprises a first positive port and a first negative port, and the second port comprises a second positive port and a second negative port, wherein the LC trap circuit comprises a first LC trap subcircuit connected between the first positive port and the second positive port and a second LC trap subcircuit connected between the first negative port and the second negative port, wherein the first LC trap subcircuit comprises a first LC parallel circuit and a first capacitor, wherein one end of the first capacitor is connected to a low electrical level, wherein the other end of the first capacitor is connected to the first positive port and to one end of the first LC parallel circuit, and wherein the other end of the first LC parallel circuit is connected to the second positive port, wherein the second LC trap subcircuit comprises a second LC parallel circuit and a second capacitor, wherein one end of the second capacitor is connected to a low electrical level, wherein the other end of the second capacitor is connected to the first negative port and to one end of the second LC parallel circuit, wherein the other end of the second LC parallel circuit is connected to the second negative port, wherein an inductor in the first LC parallel circuit and an inductor in the second LC parallel circuit are the same in parameter, wherein a capacitor in the first LC parallel circuit and a capacitor in the second LC parallel circuit are the same in parameter, and wherein the first capacitor and the second capacitor are the same in parameter.
6. The system according to claim 2, wherein each LC trap network comprises:
an LC trap circuit;
a first port connected to the gating throw end of the first differential SPMT switch; and
a second port connected to the gating throw end of the second differential SPMT switch, wherein the first port comprises a first positive port and a first negative port, and the second port comprises a second positive port and a second negative port, wherein the LC trap circuit comprises a first LC trap subcircuit connected between the first positive port and the second positive port and a second LC trap subcircuit connected between the first negative port and the second negative port, wherein the first LC trap subcircuit comprises a first LC parallel circuit and a first capacitor, wherein one end of the first capacitor is connected to a low electrical level, wherein the other end of the first capacitor is connected to the first positive port and to one end of the first LC parallel circuit, wherein the other end of the first LC parallel circuit is connected to the second positive port, wherein the second LC trap subcircuit comprises a second LC parallel circuit and a second capacitor, wherein one end of the second capacitor is connected to a low electrical level, wherein the other end of the second capacitor is connected to the first negative port and to one end of the second LC parallel circuit, wherein the other end of the second LC parallel circuit is connected to the second negative port, wherein an inductor in the first LC parallel circuit and an inductor in the second LC parallel circuit are the same in parameter, wherein a capacitor in the first LC parallel circuit and a capacitor in the second LC parallel circuit are the same in parameter, and wherein the first capacitor and the second capacitor are the same in parameter.
7. The system according to claim 3, wherein each LC trap network comprises:
an LC trap circuit;
a first port connected to the gating throw end of the first differential SPMT switch; and
a second port connected to the gating throw end of the second differential SPMT switch, wherein the first port comprises a first positive port and a first negative port, and the second port comprises a second positive port and a second negative port, wherein the LC trap circuit comprises a first LC trap subcircuit connected between the first positive port and the second positive port and a second LC trap subcircuit connected between the first negative port and the second negative port, wherein the first LC trap subcircuit comprises a first LC parallel circuit and a first capacitor, wherein one end of the first capacitor is connected to a low electrical level, wherein the other end of the first capacitor is connected to the first positive port and to one end of the first LC parallel circuit, wherein the other end of the first LC parallel circuit is connected to the second positive port, wherein the second LC trap subcircuit comprises a second LC parallel circuit and a second capacitor, wherein one end of the second capacitor is connected to a low electrical level, wherein the other end of the second capacitor is connected to the first negative port and to one end of the second LC parallel circuit, wherein the other end of the second LC parallel circuit is connected to the second negative port, wherein an inductor in the first LC parallel circuit and an inductor in the second LC parallel circuit are the same in parameter, wherein a capacitor in the first LC parallel circuit and a capacitor in the second LC parallel circuit are the same in parameter, and wherein the first capacitor and the second capacitor are the same in parameter.
8. The system according to claim 4, wherein each LC trap network comprises:
an LC trap circuit;
a first port connected to the gating throw end of the first differential SPMT switch; and
a second port connected to the gating throw end of the second differential SPMT switch, wherein the first port comprises a first positive port and a first negative port, and the second port comprises a second positive port and a second negative port, wherein the LC trap circuit comprises a first LC trap subcircuit connected between the first positive port and the second positive port and a second LC trap subcircuit connected between the first negative port and the second negative port, wherein the first LC trap subcircuit comprises a first LC parallel circuit and a first capacitor, wherein one end of the first capacitor is connected to a low electrical level, wherein the other end of the first capacitor is connected to the first positive port and to one end of the first LC parallel circuit, wherein the other end of the first LC parallel circuit is connected to the second positive port, wherein the second LC trap subcircuit comprises a second LC parallel circuit and a second capacitor, wherein one end of the second capacitor is connected to a low electrical level, wherein the other end of the second capacitor is connected to the first negative port and to one end of the second LC parallel circuit, wherein the other end of the second LC parallel circuit is connected to the second negative port, wherein an inductor in the first LC parallel circuit and an inductor in the second LC parallel circuit are the same in parameter, wherein a capacitor in the first LC parallel circuit and a capacitor in the second LC parallel circuit are the same in parameter, and wherein the first capacitor and the second capacitor are the same in parameter.
9. The system according to claim 1, wherein the interface connector is a Universal Serial Bus (USB) connector.
Description
    CROSS-REFERENCE TO RELATED APPLICATION
  • [0001]
    This application is a continuation of International Application No. PCT/CN2014/080589, filed on Jun. 24, 2014, which claims priority to Chinese Patent Application No. 201310271810.6, filed on Jun. 27, 2013, both of which are hereby incorporated by reference in their entireties.
  • TECHNICAL FIELD
  • [0002]
    The present disclosure relates to the field of communications technologies, and in particular, to a harmonic suppression system.
  • BACKGROUND
  • [0003]
    Due to a trend of miniaturization of current mobile broadband products and an increasingly complicated electromagnetic environment around an antenna, an antenna signal is generally subject to interference from a second harmonic. For that reason, signal interference caused by the second harmonic may be generally suppressed by setting an LC (inductor-capacitor) trap network. FIG. 1 is a schematic structural diagram of an existing harmonic suppression system. As shown in FIG. 1, the system includes an interface connector 11, an LC trap network 12, a baseband chip 13, an antenna switch 14, and an antenna 15, where the LC trap network 12 is connected between the interface connector 11 and the baseband chip 13, and configured to suppress a second harmonic that occurs when an operating frequency band of the antenna 15 is a frequency band corresponding to the LC trap network 12; and the antenna switch 14 is connected between the baseband chip 13 and the antenna 15, and configured to enable the baseband chip 13 to control the operating frequency band of the antenna 15 using the antenna switch 14.
  • [0004]
    As shown in FIG. 1, suppression of a second harmonic in a case of this frequency band can be implemented using this solution only when the operating frequency band of the antenna 15 is the frequency band corresponding to the LC trap network 12. However, the operating frequency band of the antenna 15 may generally cover multiple frequency bands; therefore, based on the foregoing existing solution, when the operating frequency band of the antenna 15 is another frequency band, suppression of a second harmonic in a case of the another frequency band cannot be implemented using the LC trap network 12.
  • SUMMARY
  • [0005]
    The present disclosure provides a harmonic suppression system configured to resolve a problem that suppression of a second harmonic cannot be implemented on multiple frequency bands using an existing harmonic suppression solution.
  • [0006]
    According to a first aspect, the present disclosure provides a harmonic suppression system, including an interface connector, a baseband chip, an antenna, and an antenna switch, where the system further includes at least two LC trap networks, a first differential single-pole multi-throw (SPMT) switch, and a second differential single-pole multi-throw SPMT switch, where the interface connector is connected to a common end of the first differential SPMT switch; a control port of the first differential SPMT switch is connected to a control port of the second differential SPMT switch, and each gating throw end of multiple gating throw ends of the first differential SPMT switch is separately connected to one end of each LC trap network of the at least two LC trap networks in a one-to-one correspondence; the control port of the second differential SPMT switch is connected to the baseband chip, each gating throw end of multiple gating throw ends of the second differential SPMT switch is separately connected to the other end of each LC trap network of the at least two LC trap networks in a one-to-one correspondence, and a common end of the second differential SPMT switch is connected to the baseband chip; the baseband chip is connected to the antenna switch, and the antenna switch is connected to the antenna; the baseband chip is configured to determine an operating frequency band of the antenna, and if it is determined that the operating frequency band is one of multiple preset frequency bands, send a preset gating control signal corresponding to the operating frequency band to the control port of the first differential SPMT switch and to the control port of the second differential SPMT switch, where each frequency band of the multiple frequency bands is in a one-to-one correspondence with each LC trap network of the at least two LC trap networks; the first differential SPMT switch is configured to electrically connect, according to the gating control signal, the interface connector and an LC trap network corresponding to the operating frequency band; and the second differential SPMT switch is configured to electrically connect, according to the gating control signal, the baseband chip and the LC trap network corresponding to the operating frequency band.
  • [0007]
    According to the first aspect, in a first implementable manner of the first aspect, the first differential SPMT switch and the second differential SPMT switch further include straight-through throw ends, and a straight-through throw end of the first differential SPMT switch is connected to a straight-through throw end of the second differential SPMT switch; the baseband chip is further configured to, if it is determined that the operating frequency band is not any one of the multiple frequency bands, send a straight-through control signal to the control port of the first differential SPMT switch and to the control port of the second differential SPMT switch; the first differential SPMT switch electrically connects the interface connector and the straight-through throw end of the first differential SPMT switch according to the straight-through control signal; and the second differential SPMT switch electrically connects the baseband chip and the straight-through throw end of the second differential SPMT switch according to the straight-through control signal.
  • [0008]
    According to the first aspect or the first implementable manner of the first aspect, in a second implementable manner of the first aspect, the baseband chip is further configured to send, after the operating frequency band of the antenna is determined, a preset antenna switch control signal corresponding to the operating frequency band to a control port of the antenna switch, so that the antenna switch switches a frequency band of an operating signal of the antenna to the operating frequency band according to the antenna switch control signal.
  • [0009]
    According to the first aspect or either of the first two implementable manners of the first aspect, in a third implementable manner of the first aspect, each LC trap network includes an LC trap circuit, a first port connected to the gating throw end of the first differential SPMT switch, and a second port connected to the gating throw end of the second differential SPMT switch, where the first port includes a first positive port and a first negative port, and the second port includes a second positive port and a second negative port; the LC trap circuit includes a first LC trap subcircuit connected between the first positive port and the second positive port and a second LC trap subcircuit connected between the first negative port and the second negative port; the first LC trap subcircuit includes a first LC parallel circuit and a first capacitor, one end of the first capacitor is connected to a low electrical level, the other end of the first capacitor is connected to the first positive port and to one end of the first LC parallel circuit, and the other end of the first LC parallel circuit is connected to the second positive port; and the second LC trap subcircuit includes a second LC parallel circuit and a second capacitor, one end of the second capacitor is connected to a low electrical level, the other end of the second capacitor is connected to the first negative port and to one end of the second LC parallel circuit, and the other end of the second LC parallel circuit is connected to the second negative port, where an inductor in the first LC parallel circuit and an inductor in the second LC parallel circuit are the same in parameter, a capacitor in the first LC parallel circuit and a capacitor in the second LC parallel circuit are the same in parameter, and the first capacitor and the second capacitor are the same in parameter.
  • [0010]
    According to the first aspect or one of the first three implementable manners of the first aspect, in a fourth implementable manner of the first aspect, the interface connector is a universal serial bus (USB) connector.
  • [0011]
    According to the harmonic suppression system provided by the present disclosure, a gating control signal corresponding to a current operating frequency band of an antenna is sent to a first differential SPMT switch and a second differential SPMT switch, and therefore, an LC trap network that is corresponding to the operating frequency band and set between an interface connector and a baseband chip is electrically connected by controlling turning on and turning off of the first differential SPMT switch and the second differential SPMT switch, so that for multiple different operating frequency bands of the antenna, suppression of a second harmonic may be implemented using corresponding LC trap networks.
  • BRIEF DESCRIPTION OF DRAWINGS
  • [0012]
    FIG. 1 is a schematic structural diagram of an existing harmonic suppression system;
  • [0013]
    FIG. 2 is a schematic structural diagram of a harmonic suppression system according to Embodiment 1 of the present disclosure;
  • [0014]
    FIG. 3 is a schematic structural diagram of another harmonic suppression system according to Embodiment 2 of the present disclosure; and
  • [0015]
    FIG. 4 is a schematic structural diagram of an LC trap network 23 according to any embodiment of the present disclosure.
  • DESCRIPTION OF EMBODIMENTS
  • [0016]
    To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the following clearly and completely describes the technical solutions in the embodiments of the present disclosure with reference to the accompanying drawings in the embodiments of the present disclosure. The described embodiments are some but not all of the embodiments of the present disclosure. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.
  • [0017]
    FIG. 2 is a schematic structural diagram of a harmonic suppression system according to Embodiment 1 of the present disclosure. As shown in FIG. 2, the system includes an interface connector 21, a baseband chip 22, at least two LC trap networks 23, an antenna 24, a first differential SPMT switch 25, a second differential SPMT switch 26, and an antenna switch 27, where the interface connector 21 is connected to a common end 251 of the first differential SPMT switch 25; a control port 252 of the first differential SPMT switch 25 is connected to a control port 262 of the second differential SPMT switch 26, and each gating throw end of multiple gating throw ends 253 of the first differential SPMT switch 25 is separately connected to one end of each LC trap network of the at least two LC trap networks 23 in a one-to-one correspondence; the control port 262 of the second differential SPMT switch 26 is connected to the baseband chip 22, each gating throw end of multiple gating throw ends 263 of the second differential SPMT switch 26 is separately connected to the other end of each LC trap network of the at least two LC trap networks 23 in a one-to-one correspondence, and a common end 261 of the second differential SPMT switch 26 is connected to the baseband chip 22; the baseband chip 22 is connected to the antenna switch 27, and the antenna switch 27 is connected to the antenna 24; the baseband chip 22 is configured to determine an operating frequency band of the antenna 24, and if it is determined that the operating frequency band is one of multiple preset frequency bands, send a preset gating control signal corresponding to the operating frequency band to the control port 252 of the first differential SPMT switch 25 and to the control port 262 of the second differential SPMT switch 26, where each frequency band of the multiple frequency bands is in a one-to-one correspondence with each LC trap network of the at least two LC trap networks 23; the first differential SPMT switch 25 is configured to electrically connect, according to the gating control signal corresponding to the operating frequency band, the interface connector 21 and an LC trap network corresponding to the operating frequency band; and the second differential SPMT switch 26 is configured to electrically connect, according to the gating control signal corresponding to the operating frequency band, the baseband chip 22 and the LC trap network corresponding to the operating frequency band.
  • [0018]
    The interface connector 21 may be a USB connector, or a Secure Digital Input and Output card (SDIO) connector, which is not limited herein in the embodiment.
  • [0019]
    After the baseband chip 22 determines the operating frequency band of the antenna 24, if the operating frequency band is one of the multiple preset frequency bands that are in a one-to-one correspondence with the multiple LC trap networks 23, that is, among the multiple LC trap networks 23, there is an LC trap network corresponding to the operating frequency band, the baseband chip 22 may send the gating control signal to the control port 252 of the first differential SPMT switch 25 and to the control port 262 of the second differential SPMT switch 26; the first differential SPMT switch 25, under a control of the gating control signal, electrically connects the common end 251 of the first differential SPMT switch 25 and a gating throw end that is corresponding to the gating control signal and that is of the multiple gating throw ends 253 of the first differential SPMT switch 25, and the gating throw end that is corresponding to the gating control signal and of the first differential SPMT switch 25 is connected to the one end of the LC trap network corresponding to the operating frequency band; and the second differential SPMT switch 26, under a control of the gating control signal, electrically connects the common end 261 of the second differential SPMT switch 26 and a gating throw end that is corresponding to the gating control signal and that is of the multiple gating throw ends 263 of the second differential SPMT switch 26, and the gating throw end that is corresponding to the gating control signal and of the second differential SPMT switch 26 is connected to the other end of the LC trap network corresponding to the operating frequency band.
  • [0020]
    The LC trap network corresponding to the operating frequency band is connected between the interface connector 21 and the baseband chip 22 using the first differential SPMT switch 25 and the second differential SPMT switch 26, and further a second harmonic in a case of the operating frequency band is effectively suppressed using the LC trap network corresponding to the operating frequency band.
  • [0021]
    In an actual application, which frequency bands are supported by an antenna is preset when the antenna is designed and manufactured. Correspondingly, a method for determining an operating frequency band of the antenna 24 may generally include using, by the baseband chip 22 according to a frequency band supported by a communications network that currently needs establish a communication connection, the frequency band supported by the communications network as the operating frequency band of the antenna 24.
  • [0022]
    It should be noted that the figure shows only a specific implementation manner of the embodiment, and does not impose any limitations on the embodiment. For example, a quantity of LC trap networks 23 in the embodiment includes but is not limited to two shown in the figure, and correspondingly, a quantity of gating throw ends that are of the first differential SPMT switch 25 and that are of the second differential SPMT switch 26 is not limited to a quantity shown in the figure, either.
  • [0023]
    In an actual application, although an LC trap network may implement suppression of a second harmonic, due to a circuit characteristic of the LC trap network itself, when the LC trap network is set, an undesirable phenomenon such as deterioration of an eye diagram of a signal or an increase of intersymbol interference generally occurs; in addition, a capacitor and an inductor that are on the LC trap network are generally not ideal devices; therefore, corresponding equivalent direct current resistance exists, which also causes unnecessary signal attenuation. In addition, in an actual application, a second harmonic phenomenon generally occurs only when an operating frequency band is a low-frequency band; therefore, when an operating frequency band of an antenna is in a high-frequency band, generally, it is not required to perform suppression of a second harmonic.
  • [0024]
    Therefore, in order to avoid the foregoing series of problems caused by an LC trap network that is still set when suppression of a second harmonic is not required to be performed on an antenna, optionally, FIG. 3 is a schematic structural diagram of another harmonic suppression system according to Embodiment 2 of the present disclosure. As shown in FIG. 3, according to the harmonic suppression system described in Embodiment 1, the first differential SPMT switch 25 and the second differential SPMT switch 26 further include straight-through throw ends, and a straight-through throw end 254 of the first differential SPMT switch 25 is connected to a straight-through throw end 264 of the second differential SPMT switch 26; the baseband chip 22 is further configured to send, after the operating frequency band of the antenna is determined, if it is determined that the operating frequency band is not any one of the multiple frequency bands, a straight-through control signal to the control port 252 of the first differential SPMT switch 25 and to the control port 262 of the second differential SPMT switch 26; the first differential SPMT switch 25 electrically connects the interface connector 21 and the straight-through throw end 254 of the first differential SPMT switch 25 according to the straight-through control signal; and the second differential SPMT switch 26 electrically connects the baseband chip 22 and the straight-through throw end 264 of the second differential SPMT switch 26 according to the straight-through control signal. After the operating frequency band of the antenna 24 is determined, if the operating frequency band is not any one of the multiple frequency bands, that is, among the multiple LC trap networks 23, there is no LC trap network corresponding to the frequency band, the baseband chip 22 may send the straight-through control signal to the first differential SPMT switch 25 and to the second differential SPMT switch 26, where the straight-through control signal is used to enable the first differential SPMT switch 25 and the second differential SPMT switch 26 to electrically connect, under a control of the straight-through control signal, the straight-through throw end 254 of the first differential SPMT switch 25 and the straight-through throw end 264 that is of the second differential SPMT switch 26 and that is directly connected to the straight-through throw end 254, so that no LC trap network is connected between the interface connector 21 and the baseband chip 22 using the first differential SPMT switch 25 and the second differential SPMT switch 26.
  • [0025]
    In addition, in an actual application, after the baseband chip 22 determines the operating frequency band of the antenna 24, in order to control the operating frequency band of the antenna 24, optionally, in another implementable manner of the embodiment or Embodiment 1, the baseband chip 22 is further configured to send, after the operating frequency band of the antenna 24 is determined, a preset antenna switch control signal corresponding to the operating frequency band to the antenna switch 27, so that the antenna switch 27 switches a frequency band of an operating signal of the antenna 24 to the operating frequency band according to the antenna switch control signal.
  • [0026]
    The baseband chip 22 is connected to a control port 271 of the antenna switch 27, and is configured to send, after the operating frequency band of the antenna 24 is determined, the preset antenna switch control signal corresponding to the operating frequency band to the control port 271 of the antenna switch 27.
  • [0027]
    Further, FIG. 4 is a schematic structural diagram of the LC trap network 23 according to any embodiment of the present disclosure. In any one of the foregoing embodiments, each LC trap network 23 may include an LC trap circuit, a first port 41 connected to a gating throw end of the first differential SPMT switch 25, and a second port 42 connected to a gating throw end of the second differential SPMT switch 26, where the first port 41 includes a first positive port and a first negative port, and the second port 42 includes a second positive port and a second negative port; the LC trap circuit includes a first LC trap subcircuit 43 connected between the first positive port and the second positive port and a second LC trap subcircuit 44 connected between the first negative port and the second negative port; the first LC trap subcircuit 43 includes a first LC parallel circuit and a first capacitor C1, one end of C1 is connected to a low electrical level, the other end of C1 is connected to the first positive port and to one end of the first LC parallel circuit, and the other end of the first LC parallel circuit is connected to the second positive port; and the second LC trap subcircuit 44 includes a second LC parallel circuit and a second capacitor C2, one end of C2 is connected to a low electrical level, the other end of C2 is connected to the first negative port and to one end of the second LC parallel circuit, and the other end of the second LC parallel circuit is connected to the second negative port.
  • [0028]
    An inductor in the first LC parallel circuit and an inductor in the second LC parallel circuit are the same in parameter, a capacitor in the first LC parallel circuit and a capacitor in the second LC parallel circuit are the same in parameter, and the first capacitor and the second capacitor are the same in parameter.
  • [0029]
    Parameters of the devices in the LC trap circuit may be determined according to the operating frequency band, and a specific method for determining is not described herein again. The LC parallel circuit includes a capacitor and an inductor, and the capacitor and the inductor are in parallel.
  • [0030]
    Persons of ordinary skill in the art may understand that all or some of the steps of the foregoing method embodiments may be implemented by a program instructing relevant hardware. The program may be stored in a computer-readable storage medium. When the program runs, the steps of the method embodiments are performed. The foregoing storage medium includes any medium that can store program code, such as a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disc.
  • [0031]
    Finally, it should be noted that the foregoing embodiments are merely intended for describing the technical solutions of the present disclosure, but not for limiting the present disclosure. Although the present disclosure is described in detail with reference to the foregoing embodiments, persons of ordinary skill in the art should understand that they may still make modifications to the technical solutions described in the foregoing embodiments or make equivalent replacements to some or all technical features thereof, without departing from the scope of the technical solutions of the embodiments of the present disclosure.
Classifications
Classification internationaleH04B15/00, H01R13/73
Classification coopérativeH03J5/24, H01R13/73, H04B15/00
Événements juridiques
DateCodeÉvénementDescription
12 févr. 2016ASAssignment
Owner name: HUAWEI DEVICE CO., LTD., CHINA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WANG, YONGCHAO;ZHANG, HUI;DONG, FENG;AND OTHERS;SIGNING DATES FROM 20150924 TO 20150926;REEL/FRAME:037728/0310