US2954433A - Multiple error correction circuitry - Google Patents

Description

Sept. 27, 1960 w. D. LEWIS ETAL MULTIPLE ERROR CORRECTION OIRCUITRY 2 Sheets-Sheet l Filed Oct, 30, 1957 W D, EW/5 /NvE/voRs A C ROSE ATTORNEY Sept. 27, 1960 w. D. I Ewxs ET AL MULTIPLE ERROR CORRECTION CIRCUITRY 2 Shee'cs--Sheetl 2 Filed Oct. 30, 1957 Shaq W A na ATTORNEY MULTIPLE ERRURJC 1': zs; lC'llION CIRCUI'IRY Filed Oct. k30, 1957, Sel'. No. 693,452

l :6 Claims. (Cl. 178-23) This invention relates to digita-l error detection and correction circuits. Y

In the :transmission of digital signals over imperfect data links, it is often desirable to detect or correct errors in transmission. In the most elementary circuits of this type, each digit may be sent twice to provide error detection, or Ieach digit may be sent three/times to permit error correction on a two-outofthree basis. More sophisticated error detection and correction circuits involving less redundancy have .also been proposed. Thus, for example, :as disclosed in RW. Hamrning et al. Reissue Patent 23,601, granted December 23, 1952, an additional check digit may be added to a binary code gro-up to make the sum of the digits odd or even. Such an additional digit is called a parity check digit. At the receiver, :a change in parity indicates that an error has been introduced in the code group. Through the use of additional parity check digits, the erroneous digit may be uniquely identified and corrected. Another disclosure relating to :digital error detection and cor-V rect-ion appears in `an article entitled, Error Free Cod-V ing by Peter Elias, pages 29 through 37, Transactions of the LRE., Professional Group on Information Theory-4, September, 1954.

It has recently been determined that errors tend to occur in bursts. Thus, for example, -iflthe normal rate of errors on .a given data link is 1 Iin 100,000, the proba' bility of the occurrence of a second error immediately after the first is much larger. For example, the' probability may be in :the order of 1 in 10. In a simple detection circuit Iusing Ione parity .check digit for a group of binary signals, double errors would remain undetected, because both the original code group and theV erroneous code group would both be odd or even. In addition, many of the circuits of .the prior art are relatively diicult to instrument, and the error correction circuits have characteristically required aV relatively high ratio of check digits to information digits.` i

It is an objectof the inventor to improve and simplify error detection or correction circuitry.

Another object of the invento-r is to increase the error correction capabilities of data processing or transmitting apparatus.

In one illustrative embodiment of the present invention, the foregoing objects may be obtained through the use of two groups of parity check digits. As more fully set forth in application Serial No. 693,415 1, tilednOctober 3G, 1957, of W. D. Lewis, the first `group of parity check checks the parity of successive interleaved groups of information digits which are spaced apart by a predetermined number of :digits which may be designated N; the second vgroup of parity check digi-ts checks sets ot interleaved digits which are spaced N +1 digits apart. Thus, each informatiQIl. digit is includedl in two indeendent parity checks, permitting immediate correction of single errors. In addition, we have discovered that it is possible to correct certain multiple errors and to detect many bursts of errors.

resins In accordance with a feature of the invention, a dat-a handling system for ldigital signals including redundancy includes circuitry for identifying a group of digits in which are possibly included multiple errors, an additional circuit for identifying adjacent digits in the group of possibly erroneous digits, .and circuitry for correctling these adjacent digits.

In accordance with another feature of lthe invention, the decoder in a `digital data processing system includes circuitry for detecting the position of single errors and associated circuitry for .detecting the position of multiple errors, and additional circuitry responsive to ythe presence of multiple errors :Eor enabling the multiple error posi tion Vdetect-ion circuitry.

A complete understanding of this invention and of these and various `other features thereof may be gai-ned from consideration of the following detailed description, `and the accompanying drawing, in which:

Figs. 1 and -2 are diagrams indicating the parity check groups included in "a representative example ofthe instrumentation of the invention; Y

Fig. 3 is -a diagram indicating the serial mode of operation of the present data processing apparatus;

Fig. 4 -i-s a logic Vcircuit diagram of an encoder ot the type described in the priorly mentioned Lewis application and which may be utilized to provide the check signals for employment `in embodiments of the present invention;

5 is a logic circuit diagram of a decoder in accordance with one illustrative embodiment of the invention, which may be remployed with the encoder of Fig. 4; and

Fig. 6 is a pulse diagram indicating the mode of operation Yof the circuit of lFig. 5.

In the drawing, Figs. 1 and 2 are diagrams indicating the code groups which are employed in one illustrative `irnpiementation of the invention. AIn Figs. l and 2, 'the symbols I1 through i9 represent information digits, andV the symbols vC111 through C16 represent 'check digits. Although the example chosen for illustration utilizes only nine information digits and seven additional check digits for the sake of simplicity, the' present invention is applicable to situations in which iarger numbers of information and check digits are included in blocks of binary information.

In Fig. 1, the check=digit C10 indicates the parity of the infomation digits yI1, I4, and I7. This may be expressed mathematically by either of the following .two equations. i 1 4 11+I4+I7+Cw=1 MOd 2 (2) Equation 1 set forth above represents even parity conditions, and Equation?. set forth above represents odd parity condition. The expressions 0 Mod 2 and l Mod 2 are mathematical expressions indicating that the sum is even or odd, respectively. Withregard to the array shown Iin Fig. l, it may be noted that the digits .checked by C10 are spaced three digits apart. Similarly, the check groups vcorresponding to` vthe second and third horizontal rows in Fig. l include digits which are `also spaced three digits apart. 1

Fig. 2 shows a second array of parity check groups which are formed by adding the check `digits C13 through C16 to a re-arranged version of the first twelve digits of the code group. In Fig. 2, the check groups indicated by the horizontal rows each include four digitsy which are spaced four digits apart. Thus, the check digit C13 forms a parity group with digits I1, l5, and I9, and the additional check digits C14, C15, and C16 are ychosen to in theY second, third, and fourth rows, respectively, of

the matrix of Fig. 2.

iPatented Sept. 27, 19d@Y The diagram of Fig. 3 is designed to indicate the serial mode of operation employed in the illustrative circuit implementation of the present invention. In Fig. 3, the sixteen binary `digits are shown as the digits I1 through I9 and C111 through C16 in the upper horizontal row. In the second row of Fig. 3, a series of symbols representing information vand check digits have been added. The horizontal line with -four downwardly extending arrows indicates a parity check group corresponding to the first row in Fig. 1. In this example, C11, has been chosen to give an even parity check. Thus, with the sum of digits I1, I4 and I7 being even, the check digit C10 must be equal to 0. IfIq were changed from a 0 to a 1, the check digit C11, would also be a l to make the sum even. The line having four upwardly extending arrows corresponds to the check group which appears in the third row of Fig. 2. In this case, the sum of the digits I3, I1, and C11 is- 1, and is odd, so C15 must also be a l to produce an even sum. The other parity check digits C11 through C14 and C16 are formed in the manner indicated above for check digits C10 and C15.

In serial binary data processing apparatus, binary information is characteristically represented by the presence or Vabsence of pulses in successive digit periods. These digit periods, numbered 1 through 16, are indicated at the bottom of Fig. 3. The pulse train shown in Fig. 3 includes a pulse in those digit periods in which a "1 appears in the binary representation, and has no pulse present in digit periods in which a 0 appears in the binary representation. The complete pulse train shown in Fig. 3 therefore corresponds to the binary code group shown directly above the pulse train.

. In Fig. 4 there is depicted a serial binary data processing circuit as disclosed in the application of W. D. Lewis cited above and which performs the encoding function vdescribed in connection with Figs. 1 through 3. In the logic circuit diagrams of Figs. 4 and 5, a number of logic circuit building blocks are employed. These may take any of many known forms. For example, they may be implemented in accordance with an article by I. H. Felker entitled, Regenerative Amplier for Digital Computer Applications, which appeared at pages 1584 through 1596 of the November 1952 issue of the Pro'- ceedings of the I.R.E., volume 40, No. 11.

Some of the building blocks Vwhich are employed include the AND unit, which produces output signals when all input leads are energized; the OR unit, Vwhich produces output pulses when any `or all input leads are energized; and the inhibit unit which has at least one normal input lead and an inhibiting input lead marked by a small semicircle at the point where it isv connected td the block representing the inhibit unit. A pulse applied toa single normal input lead is transmitted through the inhibit unit, while a pulse applied to the inhibiting input lead overrides other input signals and blocks output signals. In serial digital computing circuits, delay circuits having delay equal to various numbers of digit periods are often required. Such circuits are indicated by logic blocks including the letter D and a number indicating the number of digit periods of delay provided by the delay line. A memory unit, as disclosed in the Felker article, may include a delay loop having `one digit period of delay. It can be set to either the O state or the l state. When it is in the O state, no output pulses are produced; however, when it is in the 1 state, circulating pulses produce output pulses in successive digit periods until the memory unit is reset to the 0 state. An exclusive- OR circuit is empldyed as a block in the present circuits. Such a circuit produces an output signal when Veither of its two input leads is energized but not when both of them are energized. It may be implemented, for example, through the use of two parallel inhibit units having their output leads connected to anOR circuit. Each input lead is connected to a normal input Yof one ,'4 of the inhibit units and an inhibiting input terminal of the other circuit.

In the circuits of Figs. 4 and 5 it will be assumed that properly timed pulses are available in any desired digit period. These pulses may, for example, be obtained through the use of a sixteen-stage ring counter connected to the output of a master timing pulse source. Properly timed word pulses appearing once every sixteen digit periods in any desired time slot are then available at the output leads of the ring counter. As disclosed in the Felker article, it is also conventional to employ master timing, or clockf pulses for timing in connection with many of the logic circuit components.

In Fig. 4, information digits are supplied from the signal source 12. The input digital signals are in the form of a pulse train in the iirst nine digit periods of the sixteen-digit period word shown in Fig. 3. The input information is applied to the delay loop 14 including the exclusive-OR circuit 16, the inhibit unit 18, the delay circuit 211, and the pulse regenerator 22. It is to be understood that the pulse regenerator may be included in one of the logic circuits. In addition, it is assumed that the logic and pulse regeneration circuitry introduces no delay, and that all of the delay is introduced by the delay line 20. The delay loop 14 therefore includes three digit periods of delay.

As the input information digits circulate through the delay loop 14, parity check information is developed in the following manner. In the rst digit period, information digit I1 is applied to input lead 24 of the exclusive- OR circuit 16. Following three digit periods, the pulse representing the digit I1 appears at the other input 26 to the exclusive-OR circuit 16. Simultaneously with the arrival of signal I1 on lead 26, the fourth information pulse I4 appears at input lead 24 to the circuit 16. In View of the coincident inputs on leads Z4 and 26, no output signal appears at the output of the OR circuit. Following three more digit periods, input signal I, appears on lead 24 and is combined with the sum Mod 2 of digits I1 and I1. yIn View of the fact that information digit I7 is a 0, the resulting sum Mod 2 ofdigits I1, I4, and I7 is still equal to 0.

During the digitperiods between the calculation of the sum as mentioned above, other parity check digits are also being computed. While the exclusive-OR circuit 16 is performing logic operations on infomation appearing at leads 24 and 26, additional parity information is stored in the delay circuit 20. Following the application of the iinal information digit I9 to the exelusive-OR circuit '16, the three check digits C10, C11, and C12 are stored in the delay circuit 20. At this point, three pulses `designated word pulses 10, 11, and 12 are applied to input lead 28 of the AND circuit 30. The

Vthree check bits C10, C11, and C12 are therefore gated through AND circuit 30, and are combined with the original nine information digits in the OR circuit 32. The additional check digits C13 through C16 are developed in the delay loop 34, which includes substantially Ythe same components as are included in delay loop 14.

However, the delay circuit 36 included in delay loop 34 has four digit periods of delay, as contrasted with the three `digit periods of delay included in circuit 20 associated with delay loop 14. This corresponds to the sampling of every fourth digit period indicated in Fig. 2, as contrasted with the sampling of every third digit period indicated in Fig. 1. Following the development of 4check bits C13 through C16, fthe check information is gated out of delay loop 34 by the application of four pulses in digit periods 13, 14, 15, and 16 to control Ylead 38 associated with AND unit 40. The check digits C13 through C16 are combined with the `information digits and the other cheek digits in the OR circuit 42.

The output ylead 44 from the OR circuit 42 is coupled to a data link which is subject to noise or other disaos-maa tortion. This data link may include a long transmission channel, for example, oran imperfect memory circuit associated with a dataprocessing system.

Fig. is a logic circuit showing one illustrative instrumentation of a decoder in laccordance with our invention for use with the encoder circuit of Fig. 4. In Fig. 5, the received signal is coupled from theinput lead 46 to three branch circuits 48, 50, and 52. `The logic circuitry associated with lead 48 determines the validity of the parity check groups including check digits C111, C11, and C12. Similarly, the logic circuitry asscciated with lead 50 checks the validity of .parity check groups associated with digits C13 through C16.

Concurrent output signals from the two checking circuits are indicated by output signals trom the AND Vcircuit 54. These output signals are utilized to correct the input signals in a manner to 4be described in detail below. In brief, howeveg, it may Ibe noted that the received signals have been routed on lead 52 through the sixteen digit delay unit 60 and the one digit delay unit 134 to the exclusive-OR circuit 58. Signals from the output of AND unit 54 Iare coupled through logic circuits to the OR -unit 114. Correction pulses at the-output of the OR unit 114 are applied to the exclusive-OR circuit S8, and correct erroneously received digital sigua'ls by reversing the bit which is applied on lead 52 to logic unit 58 concurrently with the correction pulse.

In accordance with the present invention, both -single errors and the most common form of multiple errors may be corrected. This is in contrast'to the decoder disclosed in W. D. Lewis application Serial No. 693,451, noted above, in which single Verrorsv are corrected and many vmultiple errors are detected. The correotion of both single errors and adjacent double errors e is accomplished `advantageously in the circuit of Fig. 5 through the use `of error identification and correction circuitry which operates in two distinct modes. The error identification circuits are connected between AND circuit 54 `and OR circuit 114. VWhen single errors'are present, output pulses from AND circuit54are transmitted directly through inhibit unit 116, and the one digit delay unit 112 to the ORacircuit 114. -When multiple errors'occur, however, the inhibit unit 1w isblocked and signals from AND unit S4 are `transmitted through the circuit including AND ilnit M8 and the 'two'de'lay circuits '126 and 128. This last Vmentioned circuit is responsive to successive pulses 'at the output of AND circuit 54 to correct adjacent errors-inthe received code group.

The operation of the parity group circuits associated with leads 48 and y5t) will now be'considered in `somewhat greater detail, partly by reference to Pig. 6. 'Later in the detailed description consideration will be given to the distinct modes of operation of the error detection and correction circuits when single `and multiple errors are present. Initially, it will be assumed that digit 5 has been received incorrectly. As indicated in Figs. '1

and 2, this produces an error linthe check group yincluding digit C11, and in the check group i-inclu'dingdigit C13. At the output, the 'parity group check circuit associated with lead 48 includes the delay loop 64 which is similar in its mode of operation to the 'delay loop 14 of Fig. 4. However, it is operated for one additional cycle of threedigit periods to include the check bits C111 through C12. Because yan even parity check is employed, the absence of signals at lead 66 duringr digit periods 13, 14, vand 15, when the parity group check information is gated out, indicates that no errors have been introduced into the `transmitted code group. However, any of the code groups` include an erroneous digit, `a Ypulse 'appears in the corresponding time slot. Thus, -for example, a pulse on lead 66 during digit period 14 indicates an error in the group including check digit C11. Similarly, errors in Athe parity check groups shown in the first and third rows of Fig. v1 would proi6 l duce pulseson lead 6'6duriug'digit periods I3 and. 15, respectively. Y

These error marking pulses are transferred to the delay loop68, land are circulated in this loop during the next =word period. Assuming, as mentioned above, that information digit I5 has been received incorrectly, a pulse appears on lead 66 during digit period 14, is transferred to delay loop 68, and appears on lead 70 during digit periods 2, 5, 8, and l1 of the next subsequent word. This pulse pattern on lead 70 is shown by the shaded pulses in the upper pulse train in the diagram ou? Fig. 6.

The parity check group circuit `associated with lead 56 includes a rst delay .loop 72 and a second delay loop 74. The delay loop 72 correspondsto the delay loop 34 of Fig. 4 in much the same manner that the delay loop .34 corresponds to the delay loop 114 in Fig. 4. Accordingly, all sixteen digits in the transmitted code group are applied to the four-digit period delay loop 72, and the pulses indicating errors in successive parity check groups are transferred to delay loop 74 on lead 76 during digit periods l, V 2, 3, and 4 of the next subsequent word period. The delay loop 74 has four digit periods of delay, and indications of erroneous digits are circulatedin delay loop 74 in much the same manner as in delay loop 6?. 1rFollowing the assumption that the digit I5 was changed inthe course of transmission from the encoder of Fig. 4 to the decoder of Fig. 5, the parity check group shown in the first row of Fig. 2 andV associated with check digit C13 produces a parity check failure. This failure produces a pulse Vduring the frst digit period on lead 76. This pulse is circulated in delay loop 74 and appears on lead 78 in the rst, fifth, ninth yand thirteenth digit periods. This group of pulses appears as the shaded set of pulses in the lower pulse train in Fig. 6.

In comparing the two sets of shaded pulses shown in Fig. V6, it may be seen that `a coincidence of the shaded pulses on leads 7@ and 7S occurs only during digit period 5. Accordingly, with reference to Fig. 5 a pulse appears at the output of the AND circuit 54 only during the fifth digit period. It is again noted that the incoming pulse group` has been delayed sixteen digit periods by the delay circuit '60 and an additional digit'period by delay circuit 134. Accordingly, with the output 'pulse yfrom AND circuit S4 passing through the one digit period delay unit 112, digit I5 appears on lead 52 tat Yoneinput of the exclusive-OR circuit 58 concurrently with the pulse from the AND circuit V54. The binary value of digit l5, is therefore changed, and va. corrected pulse group is applied to the output channel 80.

As mentioned above, the circuit of Fig. 5 also includes arrangements for correcting adjacent double errors in accordance with the present invention. The underlying concept behind the mode of oper-ation of the double error correction circuit of Fig. 5 may best be understood by reference to the diagrams of fFigs. 1 and 2. It will Ybe assumed, for the purposes of the following discussiomthat the successive information digits rI5 and I6 have been changed in the course of transmission. With these two digits in error, the check groups including digits' C11 and C12 will have a parity failure, as Will the check groups including the check digits C13 and C11. it has been shown above'that the check group error detection circuits -are capable of determining in which check group errors occur. However, in examining the second two rows of Fig. l and the iirst vtwo rows ofFig. 2, it is-apparent that there is insuflicient data available to permit the correction of any given pair of digits. Thus, for example, in addition to the consecutive digits 'I5 and vL; which cause the failure of the four parity check groups including digits C11, C12, C13 and C11, respectively, errors in digits I2 and I9 couldfalso liave produced this combination of parity group failures. It is, however, known that multiple errors arevmost likely -to occur dur-ing successive digit periods. The circuitofFig. 5 -is designed -7 to take advantage of this fact and to correct successive digits included among a group of possibly erroneous digits. Thus, for example, in the case discussed above,

the circuit of Fig.- is designed to correct digits 5 and 6 and to leave unchanged the other two possibly erroneous I2 and I9. I

Concerning the operation of the circuit of Fig. 5, the transfer of parity check pulses from delay loop 64 to delay loop 68 and from delay loop 72 to delay loop 74 has been discussed above. Normally, the number of pulses included in either of these transfer operations indicates the number of errors in a received code group. The number of pulses transferred from loop 64 to loop 68 is registered in counter 34, and the number of pulses transferred -from loop 72 to loop 74 is registered counter 86. Signals from counters 34 and 86 are employed both to control the multiple error correction circuitry mentioned above and to energize the alarm circuit 90. Pulses are supplied on lead 92 during the fth digit period of each word to reset the counter circuits 34 and 86.

The alarm circuit 90 is energized when multiple errors are detected which `are beyond the correction capabilities of the circuit of Fig. 5. Thus, because the circuit of Fig. 5 is incapable of correcting any triple or quadruple errors, the third stage of both counters and the fourth stage of counter 36 are coupled to OR circuit SS at the input to the alarm circuit 90. The alarm circuit 00 is also energized, if the double errors which occur are not the adjacent double errors which can be corrected.

Returning to the matter of the correction of adjacent errors, the energization of the second stage of the counter circuit S4 is detected by the AND circuit 104. The state of the second stage of the counter circuit is sampled by the application of a pulse to input lead 106 of the AND circuit 104 during digit period l. An output pulse from AND circuit 104 sets memory circuit 108 to the l state. In this condition output pulses are produced during digit periods l through of the following word period. It may be noted that a reset pulse is applied to the reset input of the memory circuit 108 during digit period l6 of each word. The one-digit period delay circuit 107 and the OR circuit 111 are included at the output of memory circuit 10S to provide an output pulse at control point 109 during digit period 16 of any word in which memory unit 108 is energized. Y

Upon the energization of the memory circuit 108, the circuitry interconnecting the AND circuit 54 and the eX- clusive-OR circuit 58 is changed, so that only successive pulses from the AND circuit 54 are gated through to the exclusive-OR circuit 58. In the absence of pulses from memory circuit 108, each pulse from the AND circuit 54 is gated through the inhibit circuit 110, the one-digit delay circuit 112, and the OR circuit 114, to the eX- clusive-OR circuit 58, in the manner discussed above.` Upon the occurrence of a series of pulses at the output of the memory circuit 108, however, the inhibiting input terminal 116 of inhibit unit 110 is enabled to block the flow of single pulses through the circuit chain mentioned above. In addition, the AND circuit 118 is enabled by the application of input pulses tto lead 120. Single pulses from the AND circuit 54 are not gated through AND circuit 118 in View of the'requirement that all three input leads 120, 122, and 124 must be energized to produce an output pulse. The one-digit delay circuit 126 coupled between leads 122 and 124 establishes the requirement of two successive output pulses from AND circuit 54 for the energization of AND circuit 118. When two consecu-l tive pulses occur, one pulse is transmitted through AND unilt 118. Through the use of the additional one-digit period delay circuit 128, the single output pulse fromv the additional one-digit period delay circuit 134 is provided in the digital input circuit 52 to the correction circuit 58. Y Y

.The mode of operationof the circuit of lFig. 5 upon the occurrence of a double error is indicated in Fig. 6. It is still assumed that information digits `I5 and I6 were erroneously received at the decoder of Fig. 5. Pairs of pulses, as indicated by all of the pulses in the upper pulse train of Fig. 6, therefore appear on lead 70 at the input to the AND-circuit 54. Similarly, thepairs of shaded and unshaded pulses shown in the lower pulse train of Fig. 6 appear on lead 7S at the input to the AND circuit 54. It may be noted that coincident pulses appear on leads 70 and 78 during digit periods 2, 5, 6, and 9 ,as well as during digit period 14, thus corroborat- 'ing the original analysis of Figs. l and 2. However, because two error pulses are transferred from delay loop 64 to delayloop 6?, the counter circuit 8-4 is set to its second state. The memory circuit 108'is therefore energized, and the error correction circuitry isset to its double error correction mode of operation. Under these conditions, only the successive pulses in digit periods 5 and 6 are effectively transmitted through to the eX- clusive-OR circuit 58 in Fig. 5. Accordingly, the desired correction of information digits I5 and I6 is effected.

It is possible that double errors which are not consecutive may occur with-in a code group. Thus, for example, if information digits I1 and I3 are erroneously transmitted, no consecutive output pulses appear at the output of the AND circuit `54. Under circumstances of this type, it is desir-able to apply a signal to the check violation alarm circuit 90. This is accomplished by circuitry including the four-digit Vdelay circuit 1,42, the OR circuit 144, the memory circuit 146, and the AND circuit 148.

In general, the mode of operation of this circuit involves the registration of signal combinations in which two or more errors occur in the memory circuit 146. If a double error is corrected, as `indicated by a pulse on lead from the AND circuit 118, the memory circuit 146 is reset to 0. If no pulse is applied to lead 150, a. word period pulse in the sixteenth digit period transmits a signal through the AND circuit 148 and the OR circuit 88 to the alarm circuit 90. The memory circuit 146 is reset to the 0 stateby a word pulse in the first digit period applied to the OR circuit 152 and thus to the set 0 input of the memory circuit 146. The fourdigit delay circuit 142 is provided to delay the signals from the second stage of counter 84 and to permit full utilization of output signals from the AND circuit 118 without requiring many additional logic circuits.

In the encoder and decoder circuits of Figs. 4 and 5, it is assumed that synchronization signals are applied to both of the two circuits, with the master control being located at one terminal and a synchronization channel being provided. Alternatively, special synchronization signals may be sent over the information channel, and circuitry may be provided in accordance with conventional practice to maintain synchronism of encoder and decoder circuits.

In the example of the invention shown in the drawings and discussed above, the original group of information digits number nine, and the digits of the final code group number sixteen. Thus, in the selected example, nine information digits and seven check digits are included in each code group. The redundancy of a message made up of such code groups is unnecessarily high, and can readily be reduced by increasing the size of the array. In this regard, it is particularly to be noted that increasing the size of the array requires only that the delay of a relatively small number of delay circuits'be increased.

It may also be noted that the selected number of information digits is the square of an integer. This selection is made to reduce the redundancy of the completed message, as the ratio of check digits to total Vdigits `is roughly proportional to the ratio of one-half the periphery of a rectangle (representing the matrix) to the area of the rectangle. Thus, in Fig. l -it would be possible to use a matrix of information digits which is not square. However, if the original array departs signiiicantly from a square the redundancy of the message tends to increase for matrices including a given number of digits.

`ln the foregoing description of Fig. 5, it has been demonstrated that the higher probability of consecutive errors as compared with errors which are spaced apart by a few digit periods may be utilized to provide information for the optimum reconstitution of erroneous received digital signals. lit -is evident that the same principle may be utilized to modify other systems which are designed for single error correction and multiple error detection, for example, by the addition of circuitry for at least correcting double adjacent errors.

It is to be understood that the above-described arrangements are illustrative of the application of the principles of the invention. Numerous other arrangements may be devised by those skilled in the art Without departing from the spirit and scope of the invention.

What is claimed is:

l. A digital decoder circuit comprising first and second error check circuits, a correction circuit, means for applying received signals to said first and second check circuits and to said correction circuit, said iirst check circuit including a first register having a predetermined length and means for circulating error signals derived from a received message in said iirst register, said second check circuit including a second register having a different predetermined length and means for circulating error signals derived from a received message in said second register, single error detection means responsive to the simultaneous occurrence of error signals at the outputs of both said iirst and said second registers for actuating said correction circuit, normally disabled adjacent error detection means responsive to the simultaneous occurrence of consecutive error signals at the outputs of both said first and said second registers for actuating said correction circuit, and means including a counter for disabling said single error detection means and enabling said adjacent error detection means upon the occurrence of double errors.

2. In a decoder for digital messages including redundancy, means for identifying a group of digits in which are possibly included multiple errors, means for further identifying adjacent erroneous digits in said group of possibly erroneous digits, and means for correcting said adjacent digits.

3. A digital decoder circuit comprising rst and second error check circuits, a correction circuit, means for apply-- cuit, said first check circuit including a first delay loop having a predetermined number of digit periods of delay and means for circulating error signals derived `from a received message in said iirst delay loop, said second check circuit including a second delay loop having a different predetermined number of digit periods of delay and means for circulating error signals derived from a received message in said second delay loop, single error detection means responsive to the simultaneous occurrence of error signals at the outputs of both said rst and said second delay loops for actuating said correction circuit, normally disabled double error detection means responsive -to the simultaneous occurrence of consecutive error signals at the outputs of both said rst and said second delay loops for actuating said correction circuit, and means for disabling said single error detection means and enabling said double error detection means upon the occurrence of double errors.

4. In combination, a decoder for receiving digital signals including information digits and parity check digits, correction circuit means, parity check circuitry for identifying the position of a single erroneous digit in a group of received digital signals and for actuating said correction circuit means to correct the erroneous digit, and partity check circuitry for identifying the positions of a group of digits in which are possibly included multiple errors, and means for identifying adjacent erroneous digits in said group and for actuating said correction circuit means in accordance With said last-mentioned identiiication.

5. An error correcting and detecting circuit comprising means for recognizing the occurrence of a single,

erroneous digit in a train of digits, means for recognizing the occurrence of multiple erroneous digits in a single group of digits, means for correcting said single erroneous digit and said multiple erroneous digits if occurring in successive digit intervals, an alarm circuit, and means for References Cited inthe le of this patent UNITED STATES PATENTS

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