US3353105A

US3353105A - Logical electric circuits

Info

Publication number: US3353105A
Application number: US357594A
Authority: US
Inventors: Allmark Reginald Hugh; Ellison James Raymond
Original assignee: English Electric Co Ltd
Current assignee: English Electric Co Ltd
Priority date: 1963-04-11
Filing date: 1964-04-06
Publication date: 1967-11-14
Anticipated expiration: 1984-11-14
Also published as: NL6403816A; GB1089541A

Description

9 14, 1967 I R. H. ALLMARK EIFAL 3,

LOGICAL ELECTRIC CIRCUITS Filed April 6, 1964 I 2 Sheets-Sheet 1 VARIABLE IMPEDANCE DEVICES FIG.1

' VARIABLE IMPEDANCE DEVICE FIG.2

United States Patent M 3,353,105 LOGICAL ELECTRKC CIRCUITS Reginald Hugh Allmark and James Raymond Ellison,

Stoke-on-Trent, England, assignors to The English Electric Company Limited, London, England, a British company Filed Apr. 6, 1964, Ser. No. 357,594 Claims priority, application Great Britain, Apr. 11, 1963, 14,518/63 7 Claims. (Cl. 328-91) This invention relates to logical electric circuits for producing output signals representing desired logical combinations of binary input signals. Such circuits are used in data processing apparatus.

According to the present invention a logical electric circuit comprises a ferro-magnetic core having linked with an aperture thereof a primary winding for energisation by current pulses from a current source, an inhibit winding for controlling at alternatively a high or a low value the magnetic flux that may be set up by magnetisation provided by the primary winding, and a secondary winding for producing output E.M.F.s in response to changes in such magnetic flux, and controllable impedance means for connection in circuit with the inhibit winding for presenting in response to a predetermined input condition at input terminals of the impedance means a high impedance to the flow of current induced in the inhibit winding, the impedance means otherwise presenting a low impedance to the flow of such induced current, and each output being representative of the negation of an operand or a logical combination of operands of which the said predetermined input condition at the input terminals of the impedance means is representative.

Means may be provided for applying to one end of the secondary winding a predetermined bias potential representative of a second operand or predetermined logical combination of operands and sensed so that on the induction of an output in the secondary winding the potential of the other end of the secondary winding changes temporarily to a value representative of the logical AND combination of the aforesaid operands or predetermined logical combination of operands.

According to a preferred feature of the present invention there is included a second and similar ferromagnetic core having linked therewith a primary winding (hereafter called the second primary winding) connected in series with the first mentioned primary winding (hereafter called the first primary winding) for energisation by the said current pulses, and an inhibit winding (hereafter called the second inhibit winding) for controlling alternatively at a high or a low value the magnetic flux that may be set up by magnetisation provided by the second primary winding, and a second controllable impedance means for connection in circuit with this second inhibit winding for presenting in response to a predetermined input condition at input terminals of this second impedance means a low impedance to the flow of current induced in the second inhibit winding, the second impedance means otherwise presenting a high impedance to the flow of such induced current, and the said predetermined input condition at the terminals of the second impedance means being representative of the negation of the predetermined input condition at the input terminals of the first-mentioned impedance means.

According to another preferred feature of the present invention the two cores may have linking with their respective apertures two similar parts of a tertiary winding for producing a second output signal, the two parts of the tertiary winding contributing equally to the output signal. In such a logical electric circuit, when the pre- 3,353,105 Patented Nov. 14, 1967 determined input condition at the input terminals of the first impedance means is representative of a predetermined logical AND combination of first and second operands and the predetermined input condition at the input terminals of the second impedance means is representative of a predetermined logical AND combination of the negations of the first and second operands, the said second output signal is representative of the equivalence of the first and second operands.

According to another preferred feature of the present invention, a logical electric circuit may comprise a plurality of pairs of ferro-magnetic cores, each core having linked with an aperture thereof a primary winding for energisation by current pulses from a current source, and an inhibit winding for controlling alternatively at a high or a low value the magnetic flux that may be set up by magnetisation provided by the associated primary winding, and a plurality of controllable impedance means connected in series with the several inhibit windings respectively, each pair of controllable impedance means associated with the two inhibit windings of each pair of cores being arranged to present in response to a predetermined input condition at input terminals of the two impedance means high and low impedances respectively to the flow of currents induced in the respective associated inhibit windings, the two impedance means otherwise presenting low and high impedances respectively to the flow of such induced currents, and a plurality of electric windings each of which is linked with one or with both apertures of an associated pair of cores for producing output signals dependent on desired logical combinations of binary operand signals applied to the input terminals of the various pairs of impedance means.

By way of example several logical electric circuits according to the present invention will now be described with reference to the accompanying drawings in which:

FIG. 1 shows diagrammatically a circuit by which the logical AND function A -B-C is produced;

FIG. 2 shows diagrammatically a circuit by which the logical AND function A -C is produced;

FIG. 3 shows diagrammatically a circuit by which the logical equivalence and non-equivalence functions AEB and A B are produced; and

FIG. 4 shows diagrammatically a circuit which is suitable for use as one stage of a parallel binary multiplier of a data processing apparatus.

In the drawings an aperture or hole in a pulse transformer ferro-magnetic core is symbolically shown as a dotted line. The dot notation is used to indicate the senses in which the windings are wound with respect to one another, the electric polarity induced in a winding with respect to its dot being the same as the electric polarity in the inducing winding with respect to its dot. Another notation adopted for this description is that an input terminal is indicated by a spot and an output terminal by a circle.

In FIG. 1 the logical electric circuit includes a pulse transformer whose ferro-magnetic core has an aperture H0 with which are linked a primary winding P0, a secondary winding S0 and an inhibit winding It). The secondary winding S0 is connected in an output circuit between a first input terminal and an output terminal, whilst the inhibit winding 10 is connected in an inhibit circuit which includes a controllable impedance means. This controllable impedance means takes the form of two parallelconnected circuits each of which includes a diode and a gate. Each gate has an input terminal, and these will be referred to as the second and third input terminals.

In operation, the primary circuit is energized when desired with drive" current pulses from a pulse generator (not shown), and input potentials are applied to the input terminals to represent the condition, as shown, of the binary operand C at the first input terminal, and of the negations of the binary operands A and B at the second and third input terminals. If either or both of the gates in the inhibit circuit are closed the inhibit winding will be short-circuited, and no output will be induced in. the. secondary winding. Thus, by controlling the gates in accordance with the input binary signals representing the respective negations K and? an E.M.F. will be induced in the secondary winding only when X and H are both absent; that is to say the secondary pulse will represent the binary AND function A.B. Also since a bias is applied to the secondary winding S0, representing the additional binary operand C, the output voltage will either exceed or not a predetermined level on the occurrence of a drive pulse in the primary circuit, so that the logical AND combination or function A.B.C. willbe represented by whether or not the voltage at the output terminal exceeds the predetermined level.

It will be readily appreciated from the above that the inhibit winding has the effect of controlling in dependence on its own energisation the magnitude of the magnetic flux due to the primary winding energisation alternatively at a high value or a low value, and that the energisation of the inhibit winding'in turn depends on the impedance presented by the controllable impedance means to the flow of current induced in the inhibit winding by the magnetic flux. It will also be appreciated that the impedance presented by the controllable impedance means will be alternatively of a high or a low value, being normally of the low value, but-ofthe high value in response to the unique input condition at the said second and third input terminals which occurs when both X and Bare represented by the zero state input signal.

Preferably the currentpulses supplied to theprimary winding P have a magnitude'such thatthe maximum magnetisation of the core is restricted so as to prevent any appreciable saturation of the coretaking place.

7 The logical electric circuit of FIG. 2 includes two pulse transformers whose ferro-magnetic cores have apertures H1 and H2. Linked-with the aperture H1 of the. first transformer are a. primary winding P1, a secondary-windingSl, and an inhibit winding Il. The secondary winding is connected in'an' output circuit between an output terminal and an input terminal to which isapplied as shown an input signal representative of the operand C, whilst the inhibit winding is connected in an inhibit circuit which includes a controllable impedance means comprising in series azdiode and a gate for. enabling the anode of the diode to be held at earth potential in the presence at its input terminal of an input signal representative of the ONE state ofthe negation- K.

Linked with the second aperture H2 of the second transformer is a primary Winding P2 andan inhibit winding 12; The primary winding is constructed in series with the primary winding P1 for energisationbyv the same current pulses, whilst the inhibit windingIZ is connected in series with a' controllable impedance means which, comprises a diode connected in series with a gate for enabling the anode of the diode to be held at earth potential in the presence at its input terminal of an input signal representingthe ONE state of the operand A.

In operation the circuit functions in a manner analogous to that of the circuit of FIG. 1 to produce an output signal representative of the logicalcombination A.C., just as the circuit of FIG. 1. would produce if the gate controlled by the negation I? were maintained permanentlyopen.

Itwill be observedth-at since the controllable impedance means connected in circuit with the two inhibit: windings respectively are controlled in dependence uponinput: signals which represent respectively the operand A and its negation K, whatever the state of the operand one of the inhibit windings will be-short-circuited and the other opencircuited. Hencethe'etfective impedance of-theprimary winding-circuit to drive current pulses is constant regardless of whether the operand A has the ZERO or UNIT state. This is a highly advantageous feature in cases where the pulse generator for supplying the primary winding circuit is a voltage pulse generator, since the impedance of the primary winding circuit can never fall below a predetermined value.

The two pulse transformers may if desired be made with cores which are constituted by a single ferro-magnetic member having appropriate apertures and windings so that the action of one transformer is not interfered with magnetically by the action of the other transformer.

The logical electric circuit of FIG. 3' includes four generally similar pulse transformers whose ferro-magnetic cores have apertures H3 to H6. Linked with each such aperture are a primary winding (P3 to P6), an inhibit winding (I3 to 16), and a secondary winding. The primarywindings are all connected in series for energisation by the same drive current pulses, and the secondary windings of the first pair of transformers are connected in series to form a first secondary winding circuit S2, whilst the secondary windings of the second pair of transformers are connected in series to form a second secondary winding circuit S3. I

The inhibit windings are connected in separate inhibit circuits each of which includes a separate controllable impedance means. Each such controllable impedance means comprises two parallel connected circuitseach of which includes in series a diode and a gate having. an input terminal. Input signalsrepresentative of the states of the operands A and B and of their negations K and H are applied to the respective pairs of input terminals of the two controllable impedance means associated with theinhibit windings I3 and I4, whilst input signals representative of the states of K and B, andof A and E are applied to the, respective pairs of input terminals of the'twowcontrollable impedance means associated with the inhibit windings I5 and I6.

In operation irrespective of the states. of the operands A and B there willalways be one, and one only, of the inhibit windings 13 to I6 which is. not short-circuited, so that on the occurrence of adrive current pulse in the. primary winding circuit an E.M.F. willbe inducedin the secondary winding circuit which is linked with the aperture with which that particular inhibit winding is linked. It can be shown. that byv varying the impedance of the I3 inhibit circuit in accordance with A and B, of the I4 inhibit circuit in accordance with K and 1?, of the 15 circuit in accordance with Kand B, and of the. I6 circuit in accordance with A and H, an output E.M.F. will be produced by the first secondary winding circuit S2 when the operands A and B are equivalent, and by the secondsecondary winding circuit S3 when. the operands A and=Bare not equivalent. This circuit also provides substantially constant impedance to circuit pulses in the primary circuit.

If desired, the cores of the transformers in this circuit may be composed of two pieces offerro-magnetic material each having two apertures, or a single piece having four apertures. In such cases the windings S2 and S3 are wound on the arms separating the apertures H3 and'H4, and H5 and H6 respectively.

The logical electrical circuit of FIG. 4 includes" four pulse transformers having apertures H7 to H10. Linked with-the-apertures H7 andHS are primary windings P7, P8, inhibit windings I7, I8, and secondary'windings S4, S5, whilst linked equally with both such apertures H7, H8 are secondary windingcir-cuits S6, S7. Linked with the apertures H9 and H 10 are primary windings P9, P10" and inhibit windings I9, I10; whilst, linking equally with both the apertures H9 and H10 are secondary winding circuits S8 and S9.

The primary windings P7 to P10 are all connectedin series for energisationby'thesame current pulses, whilst the inhibit windings are connected in separate inhibit circuits each of which includes a separate controllable impedance means. Each such controllable impedance means comprises two parallel connected circuits each of which includes in series a diode and a gate having an input terminal. Input signals representative of the states of the operands S and M and of their negations S and M are applied to the respective pairs of input terminals of the two controllable impedance means associated with the inhibit windings I7 and 18, whilst input signals representative of the states of S and M and of S and M are applied to the respective pairs of input terminals of the two controllable impedance means associated with the inhibit windings I9 and Ill).

Input signals representative of the states of the operand C and its negation 6 are applied to the input terminals of the secondary winding circuits S6 and S9, and S7 and S8 .respectively as shown.

Four output terminals T1 to T4 are connected through diodes with the various secondary windings and secondary winding circuits, the terminal T1 being connected to the secondary winding circuits S6 and S8, terminal T2 being connected with the secondary winding circuits S7 and S9, terminal T3 being connected with the secondary winding S4 and the secondary winding circuit S8, and terminal T4 being connected with secondary winding S5 and secondary winding circuit S9.

In operation irrespective of the states of the operands S and M there will always be one, and one only, of the inhibit windings I7 to I which is not short-circuited, so that on the occurrence of a drive current pulse in the primary winding circuit E.M.F.s will be induced in the secondary windings and secondary winding circuits which are linked with the aperture with which that particular in hibit winding is linked.

From the afore'going description with reference to FIGS. 1 to 3 it will be appreciated that when the primary winding circuit carries a current pulse output signals dependent on the various states of the following logical combinations of operands and their negations will be produced:

From S4 Ell 1 From S5 S.M From S6 C(SEM) From S7 @(SEM) From S8 @(SiM) From S9 C(S #M) It should be noted that S+M is different from SM only when S=M=1 and in this case S.M will provide the CARRY signal; a similar argument applies to the CARRY signal.

As in the circuit described wtih reference to FIG. 3 the transformer cores may consist of one or more pieces of ferro-magnetic material having a total of four apertures.

In a parallel binary multiplier having r stages 4r transformers are required. These may have 41' single cores each having an aperture or a single core piece having 4r apertures or convenient intermediate subdivisions may be made.

As mentioned in connection with the circuit of FIG. 1, it is preferable in the circuits of FIGS. 2-4 that the drive current pulses have a magnitude limited so that the maximum magnetisation of the cores is restricted so as to prevent any appreciable saturation of the cores occurring.

Many other logical electric circuits using the ideas explained above may be devised. However, in order to present a constant impedance to the drive current pulses applied to such circuits there should be for each aperture linked by an inhibit winding another aperture linked by another inhibit winding whose impedance is controlled in accordance with the negation of the operand, or logical combination of operands, in accordance with which the impedance of the first mentioned inhibit winding is controlled.

What we claim as our invention and desire to secure by Letters Patent is:

1. A logic device comprising:

a magnetizable core;

a drive winding coupled to the core;

means for regularly applying drive pulses to the drive winding;

an inhibit winding coupled to the core;

a variable impedance means connected across the inhibit winding and controllable in response to an input signal to assume a high or a low impedance state;

an output winding coupled to the core; and

a source of logical signals connected to the output winding;

the core being switched by the drive pulses only if the variable impedance means is in the high impedance state and a true output signal being produced only if the core is switched and the signal produce-d by said source of logical signals is simultaneously true.

2. A logic device in accordance with claim 1 and further comprising at least one further variable impedance means similar to and connected in parallel with said variable impedance means.

3. A logic device in accordance with claim 1 and further comprising:

at least one further inhibit winding coupled to the core; and,

for each further inhibit winding, at least one further variable impedance means similar to said variable impedance means and connected thereacross.

4. A logic system comprising:

a first logic device comprising;

a magnetizable core, a drive winding coupled to the core, an inhibit winding coupled to the core, a variable impedance device connected across the inhibit winding and controllable in response to an input signal to assume a high or low impedance state, and an output winding coupled to the core; a second logic device comprising;

a magnetizable core, a drive winding coupled to the core, an inhibit winding coupled to the core, and a variable impedance device connected across the inhibit winding and controllable in response to the complement of said input signal to assume a high or low impedance state; and means for regularly supplying drive pulses at and having the drive windings of the first and second logic devices connected in series thereacross.

5. A logic system comprising:

a first logic device which comprises;

a magnetizable core,

a drive winding coupled to the core,

an inhibit winding coupled to the core,

first and second variable impedance devices connected in parallel across the inhibit winding and respectively to assume high or'low impedance states; a third logic device which comprises;

a magnetizable core, an inhibit winding coupled to the core, and first and second variable impedance devices connected in parallel across the inhibit win'ding'and controllable in response to the complement of the first input signal and the second input signal respectively to assume high or low impedance states; a fourth logic device which comprises;

a magnetizable core, a drive winding'coupled to the'core, an inhibit Winding coupled to the core, andfirst and second variable impedance devices connected in parallel across the inhibit winding and controllable in response to the complements of the first and secondinput signals respectively to assume'high or' low inputstates; and drive means for regularly supplying drive pulses and having the drive windings of the. first, second, third and fourth logic devices: connected in series thereacross. 6. A logic system in accordance-with claim .5, wherein each of said second, third; and fourth logic devicesfhas" a respective first output windingcoupled to its respective core, and the first output winding of the first'and second logic devices are connected in series, and

the first output windings of the third and fourth logic devices are connected in series.

7. A logic system in accordance with claim: 6; and wherein each of. the first and second logic devices isprovided with a respective second output. Winding and a respective third output winding'coupledto its respective core;

9 L) t and each of the third and fourth logic devices is provided with' a respective second output winding coupled to its respective core;

the" second output windings of the first and second logic devices being:serially connected together, and

thesecondoutput windingsof: the third'and fourth logic devices being serially connected together;v and further comprising meanscforapplyingathird input signal to the serial connection of the first output windings of' the first and second logic devices, and tothe serial connection of the secondvout ut windings of; the' third and fourth logic devices; means for applying the complement of the third input signal to the serial connection of the second output windings'of the first and second logic devices,

and to the serial connection of the first output.

windingsv of. the-third and fourth logic devices; a'first diode OR gateito which the serial connection of the first output windings of the first and second logic devices andtheserial connection of the first output windings. of the third and fourth logic devices are connected; i

a second. diode OR gate to which the. serial connectionof the second output windings of thefirst and second logic devices and the serial connection of the second output. windingsof the third andfourth logic devices are connected;

a third'diode OR gate to which thethird output winding of thefirst logic device. and the. serialconnecttion: of the first output windings of the third and fourth logic devices are connected; and

a fourth diode OR gate to whichlthe third output winding of the second logic device and the serial connection of the secondoutput windings of the third and fourth logic devices are connected;

References Cited UNITED? STATES PATENTS 2,846,667 8/1958 Goodwell et a1 307-88' 3,089,861 5 /1963 Overn et al 30788.5- 3,09-1;961 5 /19 6} Overn et a1. 307-885 3,182,249 5/1965 Pahlavan 3235O ARTHUR GAIUSS, Prim'ar'y'Examiiier. B, P. DAVIS, Assistant Examiner.

Claims

1. A LOGIC DEVICE COMPRISING: A MAGNETIZABLE CORE; A DRIVE WINDING COUPLED TO THE CORE; MEANS FOR REGULARLY APPLYING DRIVE PULSES TO THE DRIVE WINDING; AN INHIBIT WINDING COUPLED TO THE CORE; A VARIABLE IMPEDANCE MEANS CONNECTED ACROSS THE INHIBIT WINDING AND CONTROLLABLE IN RESPONSE TO AN INPUT SIGNAL TO ASSUME A HIGH OR LOW IMPEDANCE STATE; AN OUTPUT WINDING COUPLED TO THE CORE; AND A SOURCE OF LOGIC SIGNALS CONNECTED TO THE OUTPUT WINDING;