US3449724A - Control system for interleave memory - Google Patents

Control system for interleave memory Download PDF

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Publication number
US3449724A
US3449724A US578745A US3449724DA US3449724A US 3449724 A US3449724 A US 3449724A US 578745 A US578745 A US 578745A US 3449724D A US3449724D A US 3449724DA US 3449724 A US3449724 A US 3449724A
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United States
Prior art keywords
control system
interleave memory
boland
june
sheet
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Expired - Lifetime
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US578745A
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Lawrence J Boland
John V Mizzi
John W Smith
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International Business Machines Corp
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International Business Machines Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G06F13/1631—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests through address comparison
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Definitions

  • FIG. 10A CONTROL SYSTEM FOR INTERLEAVE MEMORY

Description

June 10, 1969 L..J. BOLAND Fr-A ,7
CONTROL SYSTEM FOR INTERLEAVE MEMORY Filed Sept. 12, 1966 Sheet of '20 F IG.1 mun STORAGE m LEXTENDED "All" STORAGE L l I I T I T I CPU STORAGE nPxR SELECTOR SELECTOR SELECTOR SELECTOR BHWEL cm sELRIsELR CHANNEL CHANNEL CHANNEL CHANNEL OPERATOR'S sue sue CONSOLE cm CNNL 122 122 124 TAPE TAPE [mun DRUM Us PRINTER CU q CU cu cu K J 123 H W PRINTER m1 120 12s L svmcn 'i onuu DRUM mm 108 mm STORE STDRE CELL SHARED FILE msc con ECTION m9 oggg LE TONMER "R CHANNEL 1 umrs SYSTEM 12e PRINTER 1os CONNECTION fi cu PRINTER ami" 112 114 116 10a CARD mus msmv msmv RE AD/PUNCH cu cu urms b 110 113 i MANUAL msmv \\H6 PRINTER 1/0 ums me PRINTER MANUAL INVENTORS 115 LAWRENCE J. BOLAND READ/PUNCH JOHN B.mzz| \1 0 JDHN w. SMITH ATTORNEY June 10, 1969 J. BOLAND 3,449,724
(IONTROL SYSTEM FOR INTERLEAVE MEMORY Filed Sept. 12. 1966 Sheet 3 or '70 FIG. 2
' mm E STORAGE u s m ws m 454 1 E PSCE I u '1 mm! nscE SPF N 1 I 43a 1 456 438 iuuu STORAGE mm 439 cousoLE OPERAWRS CONSOLE June 10, 1969 L. J. BOLAND 3,449,724
CONTROL SYSTEM FOR INTERLEAVE MEMORY Sheet Filed Sept. 12, 1966 T0 I/O UNITS mm STORAGE SPF FIXEO POINT BB D-R I BOX 1024 BITS BITS TO SELECTOR CHANNEL I22 CONSOLE June 10, 1969 L. J. BOLAND ETAL CONTROL SYSTEM FOR INTERLEAVE MEMORY Sheet 01"70 Filed Sept. 12, 1966 FIG.4
I 0 T R 5 1 I N 1 TI 4 I! a GR in E K F. T R P c c S n l. s 5 0 YA T 9 v F L1 2 M .r 4 0 W M IG w t-E I m 9 T X E T 0 R E w l R 6 v v B I m 4 2 3 2 2 00 I K 2 4. 1 fl 4 51. N i l- E i B Y l E u on nu m d A lll v 5 d l h 1 x r r I. 4 q T vn vn w I T v 2 T 6 I! I: 4 6 T L 0 In 2 Id 5 6 5 6 I .I 1| N an T "a" M m 0 5 I 1 L l- 2 R R R on on U U V E E N 6 H r. H E T Duo R V 5 H F 5 F F 6 F rf F I 00 T I. F 6 F F I! 5 F F F. ..l r... N P P U 5 W U U U I. U U U A D 0 n M B B B B B B a R c E E E T T l v 7| l T T T T P s s S S 5 s S s 0 T flu m m m m m m m m w 6 I] r' lllillllllllllllllllllulllllllillllllllllll June 10, 1969 L. J. BOLAND ETA!- CONTROL SYSTEM FOR INTERLEAVE MEMORY Filed Sept. 12, 19 6 sheet i or 90 FIG. 4A A I mom GPR BUS A 164- 465 FROM GPR BUS B f IEI 414 2 no li/n z I m *I I SELECT SELECT I RUA at I FROM I [H M 3F4x2Pu 143 I I i W 1RUMLWREG]\\LTEHP#31 E E 4?? I I 337 TO GPR E T0 mun STORAGE I l I] I E :1 I I Ewan I E E T0 IR I .C a
335 -4 mom FXPU 44s 4 I f I 302 -4 FROM FLFU 442 I M "1 I F I E rxus nos I E coum COUNT I 6 203 ws I I l I E I I Sheet 6 L. J. BOLAND ET AL NEG: w
CONTROL SYSTEM FOR INTERLEAVE MEMORY June 10, 1969 Filed Sept 12, 1966 P22: mo:
xom H :2:
June 10, 1969 L. J. BOLAND ETAL CONTROL SYSTEM FOR INTERLEAVE MEMORY Filed Sept. 12, 1966 Sheet 6 of '70 FIG. 6B
BBUS/ A BU5// 472 235 CANO ems 5a3 3a1 I GSA CARRY sum 303/,
I rm 4" 545 344 1 i cvn BINARY SIGN 43o L. L 406 364 H W w 426 I |ovER4'soEc0oE] moms 1m 1 smmcs mm DECODE gsToRE BUS 350 I F m CODE FROM 22 smrm TO sum om BUFFERS 244 5pm 32 POSITIONS 452 mm DETEOT'O" LEFT mm 05mm men CONTROL SYSTEM FOR INTERLEAVE MEMORY Sheet Filed Sept. 12. 1966 5. 23. so a; ass; i 2. :2 :2 2. a: a: H N is 5 a; 5:3: E 22 225:2 :2 2. $3 :2 ass; l3 E n we. .5; g. :2 2 IL 32 8. a: E: H page; on a: 3:5 :5 Eu: 5:2: 3:0; Ill! z; E: m E :5 52: 23155;: a 5 22 5; n m: a 2: E 0 N2. E N E :N I o N: Q w u .2 :5 E2223 :22. 3 M E :a 3:2: 52 w: E22 ass: A o: A F a: mo :2 3 20 N6; IlllIlllllllllll m of 70 CPU Sheet ll SCE EMS CCC
MPXR
CHNI. 106
5 EL R CH NL June 10, 1969 Filed Sept. 12, 1966 1 I l I I FIG. 9 260- L 266 BUS CONTROL SAB EMS
I REG BUS PRIORITY NHL | A HUS [MSCE ICCCINTFCE OUEUE HOUSE- KEEPING CPU ccc
CTRL
STACK (ADR) (MARK) QUEUE CCC INTFCE EMS m 1 June 10, 1969 L. J. BOLAND ETAL 3,44 9,724
CONTROL SYSTEM FOR INTERLEAVE MEMORY FIG. 10A
June 10, 1969 L. J. BOLAND ETAL EIONTROL SYSTEM FOR INTERLEAVE MEMORY Filed Sept. 12, 1966 Sheet 3 of 70 y ,KJ 7- KO r I I 1 a I S j r g o 3 5 LL a: 1- w i U :2 L 4 g I 3 1 A v A (Di N 1 5 STORE 3 O; 3 'j SPF v S q M FETCH 0 2 Lu *w .J
I 1 cum] 'Z: ,9 1 SHAL L 5 a i m E j I A ns I 2 mn PROT 5 I E l 2 q r H X o J 4 z m 1 0') N I J i 3 EL 4 Q E w H LD 12 E 3 r a E a: g E I i J l E 3:: m 5 N m z s Q H o v 4 2- L4 r I Sheet June 10, 1969 1.. J. BOLAND ETAL CONTROL SYSTEM FOR INTERLEAVE MEMORY Filed Sept. 12, 1966 2: a .r m a: M. a:@ mo 2: 5;; m s5 025 (is IL g :10; i a: 51%
FIG. 190
June 10, 1969 1.. J. BOLAND ETAL 3,44 9,724
CONTROL SYSTEM FOR INTERLEAVE MEMORY Filed Sept. 12. 1966 Sheet of 70 June 10, 1969 L. J. BOLAND ErAL CONTROL SYSTEM FOR INTERL'EAVB MEMORY Sheet Filed Sept 12. 1966 won. mom.
won? 82 :2
mo mo $02 53: 22 Q52 E09 52 mtg ZQ E2 QEQ $5, 2%.:
June 10, 1969 J. BOLAND ETAL CONTROL SYSTEM YQR INTERLEAVE MEMORY Sheet /9 Q1" 70 Filed Sept. 12, 1966 as E 82 1 4 $3 $3 :2 v6. QC 2m 2; miow ONE
US578745A 1966-09-12 1966-09-12 Control system for interleave memory Expired - Lifetime US3449724A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US57874566A 1966-09-12 1966-09-12
US57874466A 1966-09-12 1966-09-12

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US578744A Expired - Lifetime US3449723A (en) 1966-09-12 1966-09-12 Control system for interleave memory

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DE (1) DE1549479B1 (en)
FR (1) FR1538070A (en)
GB (1) GB1151041A (en)

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3593315A (en) * 1969-09-17 1971-07-13 Burroughs Corp Method and apparatus for deallocating small memory spaces assigned to a computer program
US3638198A (en) * 1969-07-09 1972-01-25 Burroughs Corp Priority resolution network for input/output exchange
US3694074A (en) * 1970-03-05 1972-09-26 Robert W Huboi Photographic printing system
US3918031A (en) * 1971-10-26 1975-11-04 Texas Instruments Inc Dual mode bulk memory extension system for a data processing
US4048623A (en) * 1974-09-25 1977-09-13 Data General Corporation Data processing system
US4176394A (en) * 1977-06-13 1979-11-27 Sperry Rand Corporation Apparatus for maintaining a history of the most recently executed instructions in a digital computer
WO1983001133A1 (en) * 1981-09-21 1983-03-31 Racal Data Communications Inc Microprocessor with memory having interleaved address inputs and interleaved instruction and data outputs
US4484262A (en) * 1979-01-09 1984-11-20 Sullivan Herbert W Shared memory computer method and apparatus
EP0023213B1 (en) * 1979-01-09 1985-11-06 Sullivan Computer Corporation Shared memory computer apparatus
US4688188A (en) * 1984-01-24 1987-08-18 International Computers Limited Data storage apparatus for storing groups of data with read and write request detection
EP0244540A2 (en) 1986-05-05 1987-11-11 Silicon Graphics, Inc. Write request buffering apparatus
US4707781A (en) * 1979-01-09 1987-11-17 Chopp Computer Corp. Shared memory computer method and apparatus
US4922794A (en) * 1987-02-06 1990-05-08 Yamaha Corporation Electronic musical instrument having external memory devices
US4953079A (en) * 1988-03-24 1990-08-28 Gould Inc. Cache memory address modifier for dynamic alteration of cache block fetch sequence
US5043868A (en) * 1984-02-24 1991-08-27 Fujitsu Limited System for by-pass control in pipeline operation of computer
US5325523A (en) * 1991-04-10 1994-06-28 International Business Machines Corporation Method for deleting objects from library resident optical disks by accumulating pending delete requests
US20080189479A1 (en) * 2007-02-02 2008-08-07 Sigmatel, Inc. Device, system and method for controlling memory operations

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3699530A (en) * 1970-12-30 1972-10-17 Ibm Input/output system with dedicated channel buffering
US4228500A (en) * 1978-03-27 1980-10-14 Honeywell Information Systems Inc. Command stacking apparatus for use in a memory controller
US4729093A (en) * 1984-09-26 1988-03-01 Motorola, Inc. Microcomputer which prioritizes instruction prefetch requests and data operand requests
JPS62180470A (en) * 1986-02-04 1987-08-07 Hitachi Ltd Vector processor
US5278800A (en) * 1991-10-31 1994-01-11 International Business Machines Corporation Memory system and unique memory chip allowing island interlace
US5701434A (en) * 1995-03-16 1997-12-23 Hitachi, Ltd. Interleave memory controller with a common access queue
US5692121A (en) * 1995-04-14 1997-11-25 International Business Machines Corporation Recovery unit for mirrored processors

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3061192A (en) * 1958-08-18 1962-10-30 Sylvania Electric Prod Data processing system
US3200380A (en) * 1961-02-16 1965-08-10 Burroughs Corp Data processing system
US3234524A (en) * 1962-05-28 1966-02-08 Ibm Push-down memory

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3029414A (en) * 1958-08-11 1962-04-10 Honeywell Regulator Co Information handling apparatus
USRE26087E (en) * 1959-12-30 1966-09-20 Multi-computer system including multiplexed memories. lookahead, and address interleaving features
US3242467A (en) * 1960-06-07 1966-03-22 Ibm Temporary storage register
US3312943A (en) * 1963-02-28 1967-04-04 Westinghouse Electric Corp Computer organization

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3061192A (en) * 1958-08-18 1962-10-30 Sylvania Electric Prod Data processing system
US3200380A (en) * 1961-02-16 1965-08-10 Burroughs Corp Data processing system
US3234524A (en) * 1962-05-28 1966-02-08 Ibm Push-down memory

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3638198A (en) * 1969-07-09 1972-01-25 Burroughs Corp Priority resolution network for input/output exchange
US3593315A (en) * 1969-09-17 1971-07-13 Burroughs Corp Method and apparatus for deallocating small memory spaces assigned to a computer program
US3694074A (en) * 1970-03-05 1972-09-26 Robert W Huboi Photographic printing system
US3918031A (en) * 1971-10-26 1975-11-04 Texas Instruments Inc Dual mode bulk memory extension system for a data processing
US4048623A (en) * 1974-09-25 1977-09-13 Data General Corporation Data processing system
US4176394A (en) * 1977-06-13 1979-11-27 Sperry Rand Corporation Apparatus for maintaining a history of the most recently executed instructions in a digital computer
EP0023213B1 (en) * 1979-01-09 1985-11-06 Sullivan Computer Corporation Shared memory computer apparatus
US4484262A (en) * 1979-01-09 1984-11-20 Sullivan Herbert W Shared memory computer method and apparatus
US4707781A (en) * 1979-01-09 1987-11-17 Chopp Computer Corp. Shared memory computer method and apparatus
WO1983001133A1 (en) * 1981-09-21 1983-03-31 Racal Data Communications Inc Microprocessor with memory having interleaved address inputs and interleaved instruction and data outputs
US4688188A (en) * 1984-01-24 1987-08-18 International Computers Limited Data storage apparatus for storing groups of data with read and write request detection
AU567390B2 (en) * 1984-01-24 1987-11-19 International Computers Limited Data storage apparatus with nibble mode facility
US5043868A (en) * 1984-02-24 1991-08-27 Fujitsu Limited System for by-pass control in pipeline operation of computer
EP0244540A2 (en) 1986-05-05 1987-11-11 Silicon Graphics, Inc. Write request buffering apparatus
US4805098A (en) * 1986-05-05 1989-02-14 Mips Computer Systems, Inc. Write buffer
US4922794A (en) * 1987-02-06 1990-05-08 Yamaha Corporation Electronic musical instrument having external memory devices
US4953079A (en) * 1988-03-24 1990-08-28 Gould Inc. Cache memory address modifier for dynamic alteration of cache block fetch sequence
US5325523A (en) * 1991-04-10 1994-06-28 International Business Machines Corporation Method for deleting objects from library resident optical disks by accumulating pending delete requests
US20080189479A1 (en) * 2007-02-02 2008-08-07 Sigmatel, Inc. Device, system and method for controlling memory operations

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Publication number Publication date
FR1538070A (en) 1968-08-30
DE1549479B1 (en) 1971-06-03
GB1151041A (en) 1969-05-07
US3449723A (en) 1969-06-10

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