US3643420A

US3643420A - Clock system

Info

Publication number: US3643420A
Application number: US866322A
Authority: US
Inventors: Arthur W Haydon
Original assignee: Tri Tech Inc
Current assignee: Tri Tech Inc
Priority date: 1969-10-14
Filing date: 1969-10-14
Publication date: 1972-02-22
Anticipated expiration: 1989-02-22

Abstract

A master-slave clock system for use with a source of alternating current of uniform frequency with translates the frequency of the source into readable time by dividing or counting the frequency into submultiples, by distributing clock pulses to the slave clocks at this submultiple frequency and by using stepper motors in each clock to intermittently advance the clock a predetermined discrete step in response to receipt of each clock pulse. In certain embodiments, in which no more than one slave clock operates at the same time, the pulses are distributed to the successive clocks in sequence. In other embodiments all of the slave clocks advance simultaneously. In certain embodiments each slave clock includes a trigger circuit which momentarily connects a direct current power source in the clock across the clock''s stepper motor on receipt of a pulse, and low power rectified current is fed to this source between the pulses. The entire system requires only one to two watts of power for its operation. The system is uniquely suitable for use with a standby power source which continues to drive the slave clocks in the event of a power failure or other interruption of the incoming signal.

Description

Elnite States Haydon 1 Feb. 22, 1972 [54] CLOCK SYSTEM [72] Inventor: Arthur W. Haydon, Middlebury, Conn. [57] ABSTRACT A master-slave clock system for use with a source of altemat- [73] Asslgnee Waterbury Conn? ing current of uniform frequency with translates the frequency [22] Filed: Oct. 14, 1969 of the source into readable time by dividing or counting the frequency into submultiples, by distributing clock pulses to [21] Appl- 866,322 the slave clocks at this submultiple frequency and by using stepper motors in each clock to intermittently advance the [52 US. Cl ..ss/24, 58/25 clock a Predetemined discrete step in response receipt of 51] Int. Cl. ..G04 13/02, G04C 13/04 each clock P certain embdimemsy in which [58] held of Search ..3l8/8 41, 138 259, 385, 396- than Slave at the Same time the Pulses are 58/23 26 28 33 distributed to the successive clocks in sequence. In other em- I bodiments all of the slave clocks advance simultaneously. In [56] References Cited certain embodiments each slave clock includes a trigger circuit which momentarily connects a direct current power UNITED STATES PATENTS source in the clock across the clocks stepper motor on receipt of a pulse, and low power rectified current is fed to this source 3,469,390 9/ 1969 ZImmer ..58/24 X between the pulses. The entire System requires only one to two 2994,184 8/1961 Stout "58/24 watts of power for its operation. The system is uniquely suita- 2,67l,13l 3/1954 Johnson ..58/24 X ble for use with a Standby power Source which continues to drive the slave clocks in the event of a power failure or other Primary Exammer-Rrchard B. Wilkinson interruption of the incoming signaL Assistant Examiner-Edith C. Simmons Attomey-Lee C. Robinson, Jr. 17 Claims, 7 Drawing Figures I I' i "I I I 30 I I2 PULSING I UNIT 32 I 8 I I2 I STAN D-BY POWER SUPPLY I I I I l I I I I I I l I I I I l l I I I4- I I 1 I I l I I l I I I I I I I I l I l I MASTER ---"'UNIT I CLOCK SYSTEM BACKGROUND This invention relates to clock systems and more particularly to clock systems whose timekeeping ability is dependent upon the frequency of an alternating current source.

While of general applicability to timekeeping systems, the present invention is particularly well suited for use in systems including a master unit and one or more secondary or slave units. The master unit, which may or may not incorporate visible time indicating indicia, controls the operation of the various slave units in the system.

l-leretofore, clock systems of this type have generally employed synchronous motors in the individual clocks to translate the frequency of the current source into readable time. Such motors, however, must run continuously to keep in step with the frequency and in so doing consume considerably more power than is needed for timekeeping purposes. In addition, the motors normally operate at a speed much faster than necessary and thus require a large amount of gearing down to drive the hands of the clock at the right speed. The high speed of the motors increases wear and tear on both the motors and the gears with an attendant increase in maintenance costs. A standard 60 cycles per second l-volt synchronous clock motor, for example, consumes about 24% watts, runs at 3,600 r.p.m. and must be geared down by a factor of 3,600 to l r.p.m. if the clock has a second hand, and sometimes even further if no second hand is used.

One general object of this invention therefore is to provide a new and improved clock system whose timekeeping ability is dependent upon the frequency of an alternating current power source and which has much lower power requirements than many prior clock systems.

Another object of the invention is to provide such a clock system with a higher degree of reliability and lower maintenance requirements than many prior clock systems.

A further object of the invention is to provide a clock system of the character indicated which may be quickly and easily electrically reset to the correct time after restoration of power following an electrical power failure.

Another object of this invention is to provide anew and improved clock system of the type which includes a master timekeeping unit and one or more secondary or slave" units wherein the power required to operate the entire system is commensurate with that conventionally used to drive a single clock.

A still further object of the invention is to provide a clock system which gets its timekeeping ability from a standard alternating current source but which can also be used with a small inexpensive standby alternating current source when the standard source fails.

Still another object of the invention is to provide a clock system which is inexpensive to manufacture, relatively simple in design and thoroughly reliable in operation.

Additional objects of the invention will become more apparent from the following summary and detailed description of certain preferred embodiments of the invention in connection with the drawings and the appended claims.

BRIEF SUMMARY OF THE INVENTION The present invention utilizes the concept of reducing the frequency of an alternating current source of timing intelligence and then using this reduced frequency to intermittently drive a stepper motor in each clock. The stepper motor advances the clock a predetermined discrete step in response to each pulse received. This concept is carried out by providing a clock system having an electromechanical or electronic portion for generating clock pulses at a. predetermined frequency from a standard line current source, from which the system gets its timing intelligence, and for distributing these pulses to the slave clocks in the system. By intermittently moving the clocks hands in accordance with the pulses received, the stepper motor translates the timing intelligence of the source frequency into readable time.

One advantage of this system is that it is particularly well adapted for use with the 60 cycles per second (hereinafter c.p.s.") alternating line current power available from local utility companies. Virtually all the major and many, if not most, of the other utility companies in the United States are members of a nationwide power network whose frequency is maintained at 60 c.p.s. within a tolerance of 10.2 c.p.s. on an instantaneous basis and 10.25 c.p.s. in 24 hours. This network customarily holds any accumulated drift of the network frequency within fixed limits by comparing the frequency with time signals from the Bureau of Standards in Washington, DC. Though a clock system according to the invention can also be operated from other sources of timing intelligence, e.g., a crystal oscillator type of source, a tuning fork, a good quality resistance-capacitance circuit or some other source, such sources are generally subject to greater drift problems and have other disadvantages.

By using a stepper motor which runs only intermittently to translate the line frequency into readable time and by using a voltage reducing transformer to operate these motors at a low voltage, such as 12, 20 or 32 volts, for example, the system exhibits substantial economies and safety features when compared with -volt clocks. The power required to operate the entire system is no greater than that used in conventional systems to drive a single clock, and the motors in the new system give off an extremely small amount of heat. Any fire hazard from operation of the motors is thus reduced, and the low voltage applied to the clocks minimizes the hazards of electrical shock. The system also has less stringent requirements for the reduction gear trains of the individual motors, the number of mechanical parts being substantially reduced.

Also, because of the systems low power requirements it is compatible with a small inexpensive standby time base source which supplies power to the individual clocks when the normal source of timing intelligence is interrupted for one reason or another.

In certain preferred embodiments generation of the pulses for the system is accomplished by an electronic frequency divider network which typically delivers one pulse per second or one pulse per minute to each clock. In other preferred embodiments a series of reed switches are connected in the circuits leading to the individual clocks, and a synchronous motor is used to rotate a permanent magnet which actuates the switches in sequence at the desired frequency. Similarly, a rotating mirror and a suitable light source may be used to activate one or more photocells to produce the pulses. Other devices, such as ring counters, Hall Effect semiconductors, signal coils in conjunction with a rotating magnet, etc., also may be employed to produce such pulses. Preferably, the shape of the pulses is of the sinusoidal or square wave type and may comprise spaced full or rectified half cycles. Other pulse shapes also may be used if desired.

The term clock, as used herein, means any sort of time indicating, controlling or recording mechanism such as a clock with dial and hands, a digital clock, a time switch, a repeat cycle timer, a time delay relay, an elapsed time indicator, a chart drive, or other instrument where the essential function of the mechanism is dependent on timing intelligence.

The present invention, as well as further objects and features thereof, will become more fully apparent from the following detailed description of certain preferred embodiments, when read with reference to the accompanying drawings.

BRIEF SUMMARY OF THE DRAWINGS FIG. 1 is a schematic block diagram of a clock system according to one preferred embodiment of the invention.

FIG. 2 is an exploded perspective view of one of the clocks shown in FIG. 1.

FIG. 3 is a schematic circuit diagram of an electromechanical pulsing circuit for the embodiment of FIG. 1, together with associated components.

FIG. 4 is a schematic block diagram of a clock system according to a second preferred embodiment of the invention.

FIG. 5 is a schematic block diagram of a clock system according to a third preferred embodiment of the invention.

FIG. 6 is a schematic diagram of an electrical circuit in the individual clocks of FIG. 5.

FIG. 7 is a block diagram of a clock system according to a fourth preferred embodiment of the invention.

DETAILED DESCRIPTION Referring to FIG. 1 of the drawings, there is shown a clock system which comprises a master unit 11) and a series of remotely located slave units 12. The master unit may or may not include appropriate time-indicating indicia, while each of the slave units is in the form of a clock. The unit 10 is effective to generate clock pulses at a uniform frequency dependent on the frequency f of an alternating current source 16 such as that available from the local power company. The first of the generated pulses is transmitted to one clock, the next pulse to a second clock and the next to a third clock, etc. In this embodiment the unit 10 illustratively is constructed to send out one pulse for every 6 cycles of current (i.e., 10 pulses per second with a 60 c.p.s. input). The system with such a unit 7 can handle up to 10 slave clocks each of which steps its second hand forward 1 full second for each pulse received. All of the slave clocks operate in sequence, and no more than'one clock is advancing at any one instant.

Depending on the frequencies of the generated pulses, a substantially larger number of slave clocks with second hands can be accommodated in a single system. If no second hand is required, the capacity of the system can be enlarged to 60 times the number of second hand type clocks. Since no more than one clock motor operates at any one instant, even with as many as 1,800 clocks the power required by the system does not need to exceed 1 to 2 watts. In many instances elapsed time indicator clocks require pulses even less frequently, for example, once every 6 minutes or even once an hour, depending on the time indication required. Whatever the spacing between the pulses delivered to each clock motor, in this embodiment the system generates and distributes one pulse to one clock and then a second pulse to another clock and a third pulse to a third clock, etc., until all the clocks have received a pulse and the sequence is begun again.

The master unit 10 comprises a voltage reducing transformer 14, which illustratively is adapted for use with the substantially constant 110-125 volt 60-c.p.s. signal from the current source 16, and a pulsing circuit 18. The transformer 14 steps the voltage of the source 16 down to, say, 12 volts and feeds it into the circuit 18. The circuit 18 has a common terminal and a plurality of output terminals 32 and gives off pulses at a uniform frequency n controlled by the source 16. The frequency n is less than the source frequency f and preferably comprises a submultiple of the source frequency, such that the ratio f/n equals an integer greater than one. No more than one output terminal 32 disseminates a pulse at any one instant.

Each of the slave clocks 12 is connected to a different terminal 32 and to the common terminal 30. As best shown in FIG. 2, each clock 12 includes a stepper motor 34 having an output pinion 36, reduction gearing 37 interconnecting the motor shaft and the pinion, a clock face 40 and clock hands 42 which are mounted in front of the face and are connected to the pinion 36 by additional reduction gearing 38. The motor 34 illustratively comprises a two-wire stepper motor of the type disclosed in copending U.S. Pat. application Ser. No. 819,562, filed Apr. 28, 1969, by Arthur W. Haydon, now U.S. Pat. No. 3,495,107, although other types of twoand threewire stepper motors also may be employed with good results.

The secondary winding of the transformer 14 is connected to a rectifier circuit shown schematically at 45 (FIG. 3). The

rectifier 45 converts the low-voltage alternating current signal from the secondary to a low-level direct current signal, and this latter signal appears at the

output terminals

46 and 47 of the rectifier. The output terminal 46 leads to the common terminal 30 of the pulsing circuit 18, while the output terminal 47 is connected to one of the normally open contacts of each of a series of sealed reed switches 50..The reed switches 50 are of conventional construction and each includes a pair of spacedapart contact elements sealed in opposite ends of an evacuated glass envelope. One of the switches 50 is provided for each of the slave clocks 12, and the free contact of each switch is electrically connected to the corresponding slave clock through the appropriate output terminal 32.

Supported in close juxtaposition with the reed switches 50 is a synchronous motor 52. The motor 52 illustratively is of the type disclosed in U.S. Pat. application Ser. No. 617,529, filed Feb. 21, 1967, by Arthur W. Haydon, and is supplied with power from the alternating current source 16. A permanent magnet 54 of ferrite or other suitable material is mounted on the output shaft of the motor 52 for rotation therewith. The reed switches 50 are disposed in a semicircular array around the axis of the motor shaft and are positioned in sufficient proximity to the magnet 54 such that the contacts of each switch momentarily close as the north pole of the magnet moves past the switch.

The synchronous motor 52 includes the usual gear train (not visible in FIG. 3) to reduce the rotational speed of the output-shaft and the permanent magnet 54 to the desired level. The frequency at which the north pole of the magnet 54 moves past each of the reed switches 50 is controlled by but is substantially less than the frequency of the alternating current source 16. As the north pole passes each switch, the switch contacts close to transmit a low-level direct current pulse from the rectifier circuit 45 to the corresponding slave clock 12. These clock pulses are disseminated to the individual slave clocks in sequence, where they are received by the stepper motors 34 (FIG. 2). The arrangement is such that first one motor 34, then the next motor 34, etc., are energized to sequentially drive each of the clocks 12 in predetermined discrete steps. The clocks are advanced in accordance with the timing intelligence of the alternating current source 16 to provide an accurate indication of the correct time.

In some cases the master unit includes only a single-reed switch. The single switch is periodically closed at the desired frequency by the rotating permanent magnet to supply clock pulses to all of the slave clocks simultaneously.

In certain advantageous embodiments of the invention, an auxiliary or standby power supply 56 (FIG. I) is maintained in electrical circuit relationship with the pulsing circuit 18. Although a wide variety of standby power supplies may be employed for this purpose, one particularly advantageous supply is disclosed in U.S. Pat. application Ser. No. 837,774, filed June 30, 1969, by Arthur W. Haydon. Power supplies of this character include a battery or other direct current source and are effective to produce an alternating waveform at an extremely precise and constant frequency. The connection between the supply 56 and the pulsing circuit 18 includes a normally closed relay 58. During normal operation of the system, the relay 58 is maintained in its energized or open condition by the alternating current signal from the source 16, thus preventing the transmission of auxiliary power to the pulsing circuit 18. In the event of a power failure or other interruption in the signal from the source 16, the relay moves to its closed position to furnish standby power from the supply 56 to the pulsing-circuit. With this arrangement, the individual slave clocks 12 continue to advance during the interruption.

In several embodiments of the invention, the clock pulses are produced electronically. Referring to FIG. 4, for example, there is shown a clock system which includes an alternating current source 66 connected to a voltage reducing transformer 67 in a master unit 68. The source 66 and the transformer 67 are generally similar to the source 116 and the transformer 14 (FIG. 1) described heretofore, and the output from the secondary winding of the transformer comprises a lowlevel alternating current signal of reduced voltage.

This signal is led to a storage counter shown schematically at 70. The counter 70 is effective to generate low-level direct current pulses at a uniform predetermined frequency which is a subrnultiple of the frequency of the incoming alternating current signal. The counter 70 illustratively produces one pulse for every 6 cycles of the incoming signal.

The clock pulses produced by the storage counter 70 are fed to an electronic ring counter circuit 72 within the master unit 68. The pulses enter the circuit 72 through an input terminal 74, and the circuit includes two

additional input terminals

75 and 76 which respectively receive positive and negative direct current from the secondary of the transformer 67. Thus, the transformer 67 supplies its low-level alternating current output signal to two

rectifier circuits

78 and 79, and these circuits convert the signals into low-level direct current signals of opposite polarity which are supplied to the

input terminals

75 and 76.

The ring counter 72 has a plurality of output terminals 80 which are respectively connected to the stepper motors within the slave clock units 82. As will be understood, the ring counter 72 distributes the low-level clock pulses to the successive units 82 in sequence and at a frequency corresponding to the frequency of the pulses emanating from the storage counter 70. In one arrangement the counter 70 produces 10 pulses per second which are distributed by the counter 72 among the output terminal pairs 80. Each outgoing pulse is of IOU-millisecond duration, and with 10 slave clocks in the system the stepper motor of each clock receives one pulse per second. The stepper motors successively advance the various clocks in predetermined discrete steps. It of course will be apparent that these figures are but illustrative, and that the frequency, pulse duration, number of slave clocks and other parameters of the system may vary widely without departing from the spirit or scope of the invention.

One advantage of the slave clock units used in the embodiments of FIGS. 14 lies in the fact that they include no electrical or other components other than a stepper motor and a very simple reduction gearing system to advance the clocks movement a predetermined amount when the clock motor receives a pulse.

Referring to FIGS. 5 and 6, there is shown an electronically controlled clock system in accordance with a further illustrative embodiment of the invention. The system of these figures includes a master unit 100 and a plurality of slave clocks 102. The master unit 100 comprises a voltage reducing transformer 104 which is electrically connected between an alternating current source 106 and a pulsing network 108. Network 108 is effective to electronically count the cycles from the alternating current source 106 and to generate a clock pulse each time a predetermined number of cycles have been counted. The generated pulses are distributed simultaneously to all the slave clocks 102 in the system. The slave clocks thus advance together in step.

The pulsing network 108 includes a buffer, amplifier and clipper device 110 which is supplied with a reduced voltage AC signal, illustratively volts, from the secondary of the transformer 104. Connected in series with the output of the device 110 are six bistable flip-flops 112. As will be understood, each of the flip-flops 112 has two stable states, and each flip-flop remains in one or the other of these states until caused to change by the application of a signal to the corresponding input terminal.

The output of each of the fliptops 112 is supplied to a NOT AND gate and reset network 114. Generally speaking, a NOT AND gate is a circuit having n=1 or more inputs and which has an output if and only if signals are simultaneously applied to inputs 1 to n and no signal is applied to the remaining inputs. The NOT AND gate shown in FIG. 5 has at least six inputs, one from each of the flip-flops 112, and is effective to produce a negative output pulse if and only if signals are simultaneously applied to it from flip-flops three through six and no signals are applied from flip-flops one and two.

In order to advance all the slave clocks 102 together simultaneously without transmitting a large pulse of energy from the master unit 100 to the clocks, each of the clocks 102 is provided with a trigger circuit 116 (FIG. 6) and a direct current power source 118. Each clock 102 additionally includes a stepper motor 120 of the type discussed above in connection with FIG. 2. The power source 118 comprises a rechargeable battery. The trigger circuit 116 includes a plurality of transistors, resistors and diodes connected in circuit with each other to momentarily connect the battery across the motor 120 whenever a pulse is received from the gate and reset device 114. With this construction the function of the trigger circuit is to connect and disconnect the battery to the motor and to charge the battery in the interval between the signals from the device 114. The power to operate the motor comes from the battery.

In operation, the transformer 104 (FIG. 5) steps the incoming sinusoidal wave from the source 106 down to the illustrative l5-volt level and transmits the wave to the buffer, amplifier and clipper circuit 110 within the pulsing network 108. The circuit 110 amplifies the wave, shapes it into a square wave and then transmits it directly to the flip-flop portion of the network 108. Because the flip-flops 112 are connected in series, the first one turns either on or off (depending on its initial state) with each cycle of the current. The second flip-flop turns on or off each time the first one turns off (i.e., every 2 cycles of current). Similarly, the fourth flip-flop turns on or off every 8 cycles of current in response to the third fiip-fiops turning off, the fifth flip-flop turns on or off every 16 cycles of current in response to the fourth one turning off and the sixth flip-flop turns on or off every 32 cycles of current in response to the fifth ones turning off.

Thus, as each cycle is fed into the divider network 108 one or more of the flip-flops 112 changes its state. The device is so constructed and arranged that only on the 60th cycle will the third through sixth flip-flops be on" or conducting and the first and second off or not conducting to enable the AND NOT portion of the device 114. During the time the slave clocks 102 are quiescent, the device 114 sends out a constant low-level DC signal to supply power to each of the trigger circuits 116 and thus charge the batteries 118. However, when the flip-flops are in their enabling condition, the AND NOT portion of the device cuts off the flow of power to the triggers and sends out a negative pulse signal simultaneously to all the clocks. Thereafter, and before the next cycle of current has started, the reset portion of the device resets all the flip-flops to an off" or nonconducting state, and the counting begins again. Thus, this embodiment is constructed to provide a one pulse per second output to the clocks 102. If the clocks have no second hands and one pulse per minute is desired, a second pulsing network similar to the first and driven by its one pulse per second output may be added to the circuit.

When a negative pulse is transmitted from the device 114 to the clocks 102, a transistor T in the trigger circuit 116 for each clock permits current to flow momentarily from the corresponding battery 118 through the clock motor 120. All of the motors 120 advance their clocks simultaneously a predetermined discrete step. If desired, a capacitor (not shown) may be substituted for the battery 118, in which even the low-level rectified current charges the capacitor and the capacitor in turn discharges across the motor. One advantage of using a battery in place of a capacitor, however, is that a battery-powered alarm device (not shown) may be added to each slave clock. One desirable feature of this arrangement is that such a device may be set and triggered locally at the slave clock location completely independently of the master unit.

Another advantage of the embodiment of FIGS. 5 and 6 is that all the slave clocks are connected to the master unit in parallel by a single pair of wires. In addition, with a capacitor or rechargeable battery in each of the slave clocks, low-level rectified power from the line is fed to these sources continuously during the interval between pulses to charge the capacitors or keep the batteries fully charged as the case may be. The clock pulses preferably are sent out over the same pair of lines as the low-level rectified power.

In some embodiments, each clock pulse delivered by the master unit is large enough to drive the clock motors directly. These latter embodiments customarily include one large direct current source (e.g., a battery or a capacitor) in the master unit instead of separate ones in each slave clock. Regardless of where the direct current source is put, the power consumption of the clocks still averages out to only l or 2 watts.

Referring now more particularly to FIG. 7, there is shown a master unit 200 which generates pulses as described heretofore but which also includes a radio transmitter 210 for conveying the pulses to a series of slave clocks 202 by a low-level radio signal rather than by direct wiring. This signal is simultaneously received by a radio receiver 218 in each clock which actuates a trigger circuit (not shown in FIG. 6) within the clock to advance it a predetermined step. Thus all the clocks advance together simultaneously.

The master unit 200 comprises a voltage reducing transformer 204, an alternating current source 206, a pulsing network 208'and the radio transmitter 210. The transformer 204, current source 206 and pulsing network are all similar to those described in connection with the embodiment of FIGS. Sand 6, with the latter including a buffer, amplifier and clipper 212 in series with six flip-flops 214 and a NOT AND gate and reset device 216. In the embodiment of FIG. 7, however, the clocks 202 are not connected to the master unit 200 by any wires but are cordless. With the exception of the radio receiving device 218, the clocks 202 are generally similar to those of the clocks 102 of FIGS. 5 and 6 and include a trigger circuit, a battery and a stepper motor for advancing the clocks one step in response to the receipt of each pulse.

It should be noted that though the invention has been described in connection with stepper motors, local utility company alternating current power, electromechanical and electronic pulsing networks, etc., in any given system certain of these devices may be replaced by others which perform a similar function. Thus, though stepper motors are preferred for intermittent operation and stepwise advancement of each clock in the system, other motors responsive to clock pulses, such as stepping relays, for example, also may be used in the system. Similarly, in addition to the alternatives mentioned hereinbefore to generate and distribute the pulses, other electromechanical or electronic pulsing circuits, such as a commutator and brushes, or a diode matrix, for example, can be used. The generation and sequential distribution of pulses also may be accomplished in various other ways in accordance with the invention.

Although in the embodiments described above the slave clocks are located remotely from the master unit, in other embodiments a master unit and one or more clocks are all packaged together in a single housing. In addition, though the transmission of timing intelligence from the master unit to the secondary clocks has been described heretofore as involving a negative pulse, positive pulses may also be used as well as other methods of transmitting such information, for example, reversing the polarity of a circuit, interrupting the circuit to the secondary clocks or delivering a high-frequency signal to each clock.

It also should be noted that each of the clock systems which has been described is particularly well suited, because of its low-power requirements, for operation with secondary sources of timing intelligence, such as that disclosed in copending application Ser. No. 837,774, referred to above, for example. By connecting the secondary source to a suitable amplifier and by using a spring-operated relay or other device responsive to an interruption in line current, the source is automatically connected to the system, and the system will continue operating without noticeable interruption.

Another advantage of a clock system according to the invention is that by inserting appropriate circuitry in the master unit the time indication of any one or all of the secondary clocks may be adjusted to show the correct time. Thus, if one or more clocks is slow, an appropriate number of additional pulses derived from the alternating current source may be transmitted to the clock(s) to correct the situation. Similarly, if one or more clocks is fast, the delivery of pulses to those clocks may be interrupted for a period of time sufiicient to bring the clocks back into a condition in which they indicate the proper time. Other means for resetting the clocks also may be used where desired.

Still another advantage of the system is that in clocks having only minute and hour hands the gear ratio between the stepper motor and the minute hand is so low that with the current off the minute hand can be set manually without a friction device between the motor and the hand. The stepper motor may be provided with a permanent magnet rotor which acts as a detent to hold the hands in the position in which they are set until the next pulse advances the rotor a predetermined discrete step.

The terms and expressions which have been employed are used as terms of description and not of limitation, and there is no intention in the use of such terms and expressions of excluding any equivalents of the features shown and described or portions thereof, but it is recognized that various modifications are possible within the scope of the invention.

What is claimed is:

l. A clock system for use with a source of timing intelligence having an alternating current signal of predetermined uniform frequency, said system comprising a master unit responsive to the frequency of said signal for producing clock pulses at a uniform frequency less than the signal frequency, a plurality of clock units each including a clock and a stepper motor having a rotor which advances its clock a predetermined discrete step in response to each clock pulse delivered to it, and means for distributing clock pulses from the master unit to said stepper motors, to advance said clocks in accordance with the timing intelligence of said source.

2. A clock system for use with a source of timing intelligence having an alternating current signal of predetermined uniform frequency, said system comprising a master unit responsive to the frequency of said signal for producing clock pulses at a uniform frequency less than the signal frequency, a plurality of clock units each including a clock and a stepper motor which advances its clock a predetermined discrete step in response to each clock pulse delivered to it, and means for distributing clock pulses from the master unit to said stepper motors, to advance said clocks in accordance with the timing intelligence of said source, said master unit delivering said clock pulses in succession to said clock units so that only one unit receives a pulse at any given time.

3. A clock system according to claim 1 wherein said master unit delivers each of said clock pulses to said clock units simultaneously.

4. For use with a source of timing intelligence having an alternating current signal of predetermined uniform frequency f a clock system comprising means for generating clock pulses at a uniform frequency n less than f and determined by the frequency of said source, a plurality of clocks each including a stepper motor having a rotor which advances its clock a predetermined discrete step in response to each clock pulse delivered to it, and means for delivering clock pulses from the pulse generating means to the stepper motors to advance said clocks in accordance with the timing intelligence of said source.

5. For use with a source of timing intelligence having an alternating current signal of uniform frequencyf. a clock system comprising a plurality of clocks each including stepping means for advancing its clock a predetermined step in response to a clock pulse delivered to it, means including a plurality of switching'devices in electrical circuit relationship with said source, one of said switching devices being provided for each of said clocks, means responsive to the frequency f of the alternating current source for actuating said switching devices at a uniform frequency n, where f/n equals an integer, to generate clock pulses at said frequency n, and means for delivering the generated pulses to the stepping means of said clocks to advance said clocks in accordance with the timing intelligence of said source.

6. A clock system according to claim 5, further comprising auxiliary power means responsive to the interruption of the signal from said source for supplying power to the switching devices and their actuating means.

7. A clock system according to claim 5, wherein said switching devices comprise reed switches, and the actuating means comprises magnetic means for operating said switches.

8. For use with a source of timing intelligence comprising a source of alternating current of uniform frequency f, a clock system comprising means responsive to the frequency of said source for producing clock pulses at spaced-apart intervals and at a frequency n, where n is not greater than f, a plurality of clocks each including pulse responsive means, a direct current power source and circuit means for advancing its clock a predetermined discrete step in response to each clock pulse delivered to it, and means for delivering clock pulses from the pulse producing means to said pulse responsive means, to advance said clocks in accordance with the timing intelligence of said alternating current source.

9. A clock system according to claim 8, wherein said direct current power source comprises a battery.

10. A clock system according to claim 9, wherein said battery is rechargeable, and there are means for charging said battery during the intervals between clock pulses.

11. For use with a source of timing intelligence comprising a source of alternating current of uniform frequency and of substantially constant voltage, a clock system comprising a master unit for producing clock pulsesat a frequency and voltage which are less than the frequency and voltage, respectively, of said source, a plurality of clock units each including a clock and a stepper motor for advancing its clock a predetermined discrete step in response to each clock pulse delivered to it, means for delivering said clock pulses to said stepper motors, to advance said clocks in accordance with the timing intelligence of said source, means for storing energy from said source during the intervals between clock pulses, the stored energy being applied to the stepper motors in response to said pulses, and auxiliary power means responsive to the interruption of the current from said source for supplying power to said master unit and thereby continuing the advance of said clocks during said interruption.

12. For use with a source of timing intelligence comprising a source of alternating current of uniform frequency and of substantially constant voltage, a clock system comprising a master unit for producing clock pulses at a frequency and voltage which are less than the frequency and voltage, respectively, of said source, a plurality of clock units each including a clock and a stepper motor for advancing its clock a predetermined discrete step in response to each clock pulse delivered to it, means for delivering said clock pulses to said stepper motors, to advance said clocks in accordance with the timing intelligence of said source, each of said clock units including a supply of direct current and a trigger circuit responsive to the receipt of each clock pulse for momentarily connecting said supply to the corresponding stepper motor, and auxiliary power means responsive to the interruption of the current from said source for supplying power to said master unit and thereby continuing the advance of said clocks during said interruption.

13. For use with a source of timing intelligence comprising alternating current power of predetermined uniform frequency f from the local utility company, a clock system comprising a plurality of clocks each including pulse responsive means for advancing its clock a predetermined discrete step in response M to each clock pulse delivered to it, means responsive to the frequency of said source for generating and delivering clock pulses to each of said clocks at a uniform frequency n where f/n equals an integer greater than I, and means for storing energy from said source during the intervals between clock pulses, the stored energy being applied to the pulse responsive means of each clock during the delivery of said pulses thereto. 14. A clock system for use with a source of timing intelligence having an alternating current signal of predetermined uniform frequency and of substantially constant voltage, said system comprising: a master unit including circuit means for converting the alternating current signal from said source to a series of clock pulses at a frequency and voltage less than the alternating current frequency and voltage, respectively; a plurality of clock units remotely located with respect to said master unit, each of said clock units having time indicating means and a stepper motor for advancing the indicating means a predetermined discrete step; means for delivering low-level clock pulses from said master unit to each of said clock units, to advance said stepper motors and hence said time indicating means in accordance with the timing intelligence of said source; and means for storing energy from said source during the intervals between clock pulses, the stored energy being applied to the stepper motors in response to said pulses.

15. A clock system according to claim 14, wherein the pulse delivering means includes a plurality of flip-flop circuits for transmitting said clock pulses to said clock units.

16. A clock system for use with a source of timing intelligence having an alternating current signal of predetennined uniform frequency and of substantially constant voltage, said system comprising: a master unit including circuit means for converting the alternating current signal from said source to a direct current signal of substantially reduced voltage, and switching means responsive to the frequency of the alternating current for periodically modifying said direct current signal to produce a series of low-level clock pulses at a uniform frequency less than the alternating current frequency; a plurality of clock units remotely located with respect to said master unit, each of said clock units having time indicating means and a stepper motor having a rotor for advancing the indicating means a predetermined discrete step; means for delivering low-level clock pulses from said master unit to the stepper motors in each of said clock units; and means for storing energy from said source during the intervals between clock pulses, the stored energy being applied to the stepper motors in response to said pulses, to advance said time indicating means in accordance with the timing intelligence of said source.

17. A clock system for use with a source of timing intelligence having an alternating current signal of predetermined uniform frequency and of substantially constant voltage, said system comprising: a master unit including circuit means for converting the alternating current signal from said source to a series of low-level clock pulses at a uniform frequency and voltage less than the alternating current frequency and voltage, respectively; a plurality of clock units remotely located with respect to said master unit, each of said clock units having time indicating means, a stepper motor having a rotor for advancing the indicating means a predetermined discrete step, a direct current power source for supplying power to the stepper motor, and a radio receiving device for driving the stepper motor; and radio transmission means for delivering low-level clock pulses from said master unit to the radio receiving device in each of said clock units, to advance said stepper motors and hence said time indicating means in accordance with the timing intelligence of said source.

Claims

1. A clock system for use with a source of timing intelligence having an alternating current signal of predetermined uniform frequency, said system comprising a master unit responsive to the frequency of said signal for producing clock pulses at a uniform frequency less than the signal frequency, a plurality of clock units each including a clock and a stepper motor having a rotor which advances its clock a predetermined discrete step in response to each clock pulse delivered to it, and means for distributing clock pulses from the master unit to said stepper motors, to advance said clocks in accordance with the timing intelligence of said source.

5. For use with a source of timing intelligence having an alternating current signal of uniform frequency f, a clock system comprising a plurality of clocks each including stepping means for advancing its clock a predetermined step in response to a clock pulse delivered to it, means including a plurality of switching devices in electrical circuit relationship with said source, one of said switching devices being provided for each of said clocks, means responsive to the frequency f of the alternating current source for actuating said switching devices at a uniform frequency n, where f/n equals an integer, to generate clock pulses at said frequency n, and means for delivering the generated pulses to the stepping means of said clocks to advance said clocks in accordance with the timing intelligence of said source.

11. For use with a source of timing intelligence comprising a source of alternating current of uniform frequency and of substantially constant voltage, a clock system comprising a master unit for producing clock pulses at a frequency and voltage which are less than the frequency and voltage, respectively, of said source, a plurality of clock units each including a clock and a stepper motor for advancing its clock a predetermined discrete step in response to each clock pulse delivered to it, means for delivering said clock pulses to said stepper motors, to advance said clocks in accordance with the timing intelligence of said source, means for storing energy from said source during the intervals between clock pulses, the stored energy being applied to the stepper motors in response to said pulses, and auxiliary power means responsive to the interruption of the current from said source for supplying power to said master unit and thereby continuing the advance of said clocks during said interruption.

13. For use with a source of timing intelligence comprising alternating current power of predetermined uniform frequency f from the local utility company, a clock system comprising a plurality of clocks each including pulse responsive means for advancing its clock a predetermined discrete step in response to each clock pulse delivered to it, means responsive to the frequency of said source for generating and delivering clock pulses to each of said clocks at a uniform frequency n where f/n equals an integer greater than 1, and means for storing energy from said source during the intervals between clOck pulses, the stored energy being applied to the pulse responsive means of each clock during the delivery of said pulses thereto.

14. A clock system for use with a source of timing intelligence having an alternating current signal of predetermined uniform frequency and of substantially constant voltage, said system comprising: a master unit including circuit means for converting the alternating current signal from said source to a series of clock pulses at a frequency and voltage less than the alternating current frequency and voltage, respectively; a plurality of clock units remotely located with respect to said master unit, each of said clock units having time indicating means and a stepper motor for advancing the indicating means a predetermined discrete step; means for delivering low-level clock pulses from said master unit to each of said clock units, to advance said stepper motors and hence said time indicating means in accordance with the timing intelligence of said source; and means for storing energy from said source during the intervals between clock pulses, the stored energy being applied to the stepper motors in response to said pulses.

16. A clock system for use with a source of timing intelligence having an alternating current signal of predetermined uniform frequency and of substantially constant voltage, said system comprising: a master unit including circuit means for converting the alternating current signal from said source to a direct current signal of substantially reduced voltage, and switching means responsive to the frequency of the alternating current for periodically modifying said direct current signal to produce a series of low-level clock pulses at a uniform frequency less than the alternating current frequency; a plurality of clock units remotely located with respect to said master unit, each of said clock units having time indicating means and a stepper motor having a rotor for advancing the indicating means a predetermined discrete step; means for delivering low-level clock pulses from said master unit to the stepper motors in each of said clock units; and means for storing energy from said source during the intervals between clock pulses, the stored energy being applied to the stepper motors in response to said pulses, to advance said time indicating means in accordance with the timing intelligence of said source.