US3646523A - Computer - Google Patents

Abstract

A computer is disclosed wherein the machine language thereof is a particular formal system, i.e., the ''''calculus of lambda conversion.'''' Such machine language is the language of the ''''well-formed'''' formulas of the aforementioned lambda calculus whereby the theoretical properties of the lambda calculus are implemented in the computer. Consequently, the computer is capable of computing all computable functions with time and space being the only limitations. The nerve center of the system is termed a tablet which in one implementation may essentially consist of an array of high-speed registers, each one large enough to hold a primitive term together with its designator. The nodes of a tree given by some formula corresponds to rows in the tablet and the branches extending from the nodes correspond to columns in the tablet. In one embodiment, the tablet has three columns for the branches and can have a fourth column which holds the tree addresses of the nodes. Associative techniques permit access to a row upon a match with the contents of the data or designator fields of one or more columns. The basic unit of information consists of the contents of a complete row of the tablet, such unit being termed a ''''message.'''' The tablet, functioning as a central communication device, communicates with functional units, memory units, and input-output units, the latter issuing and accepting messages, or merging them with existing ones when the units obtain access to the tablet. The invention contemplates either the accessing by the units of the whole tablet, one after another in a fixed sequence, or the accessing by each unit of only a subset of the tablet, all units simultaneously accessing discrete subsets respectively. In order to render all messages available to all units, all of the messages are circulated, i.e., shifted through the whole tablet.

Description

United States Patent Berkling I Feb. 29, 1972 [54] COMPUTER [72] Inventor: Klaus Juergen Berkllng, Granite Springs,

[73] Assignee: International Business Machines Corporation, Armonk, N.Y.

[22] Filed: Sept. 24, 1969 [21] Appl. No.: 860,473

[52] US. Cl. ..340/172.5 [51] Int. [58] Field of [56] References Cited OTH ER PUBLICATIONS Schaffner, The Circulating Page Loose System, A New Solution for Data Processing, Research Report No. 15, Published by Smithsonian Astrophysical Observatory, Dec. I966 Primary Examiner-Raulfe B. Zache Assistant Examiner-Ronald F. Chapuran Attorney-Hamlin and .Iancin and Isidore Match [57] ABSTRACT of the well-formed formulas of the aforementioned lambda calculus whereby the theoretical properties of the lambda calculus are implemented in the computer. Consequently, the computer is capable of computing all computable functions with time and space being the only limitations. The nerve center of the system is termed a tablet which in one implementation may essentially consist of an array of high-speed registers, each one large enough to hold a primitive term together with its designator. The nodes of a tree given by some formula corresponds to rows in the tablet and the branches extending from the nodes correspond to columns in the tablet. In one embodiment, the tablet has three columns for the branches and can have a fourth column which holds the tree addresses of the nodes. Associative techniques permit access to a row upon a match with the contents of the data or designator fields of one or more columnsf'l'he basic unit of information consists of the contents of a complete row of the tablet, such unit being termed a message." The tablet, functioning as a central communication device, communicates with functional units, memory units, and input-output units, the latter issuing and accepting messages, or merging them with existing ones when the units obtain access to the tablet. The invention contemplates either the accessing by the units of the whole tablet, one after another in a fixed sequence, or the accessing by each unit of only a subset of the tablet, all units simultaneously accessing discrete subsets respectively. In order to render all messages available to all units, all of the messages are circulated, i.c., shifted through the whole tablet.

14 Claims, 133 Drawing Figures IIIPUT STORE "D- 5T0li IP UP BETA MINI-LOGIC lIlITII-LOGIC OUTPUT UIII'I' UNIT 1 IIIIIT mm II T IlIIlT IIIIIT I UIIIT ll IIIIIY LINEAR MEMORY PATENTEDFEBZH 1912 3,646,523

SHEET 0311183 FIG. 4 FIG. 5

STRUCTURES TREE STRUCTURE FUNCTIONS 0N U RELATIONS 0N U LINEAR STRUCTURE NATURAL NUMBERS (((D-EHCHAH-BH) SHH)"HH/S(O')"O'1,0'N SUU-m'O' cr creT FIG. 6 FIG. 7

TREE ADDRESSING VERSUS MACHINE LANGUAGE MAPPING OF TREE STRUCTURES SYNTAX:

FORWD' (ADDRESS t t P1 W 1 1,1

P4 t t,t,t P3 t {PRIMITIVE 151111} 5 En SEMANTTCS1 ))(q .m)p)) {Pl,.,,., P11} DATA 1111111 TFO ....O' m=MEMORY SIZE 3 'rnloq m 511s M2 5115 PAIENTEDFEBZS I972 3.646523 SHEET mm 83 FIG. 8

SYSTEM ARCHITECTURE TABLET= )Lv 25 M "X EXJZ NA MX L 3 )5 2,, 5

x123 A if I I I ml 1 l I FUNCTIONAL UNITS FIG. 9 FIG. 10

I SA'ACCEPTANCE STATE,

SE-ERROR STATE STATE DIAGRAM FOR neVf'lxkeVt S, SUCCESSOR FUNCTION=V1'xVf*VfST(S,l\,n)-nk Ta (TRTT '(P.T1)UNDEF|NE0T0= =UNDEFINED PAIENTEDrwzsmrz 3,646,523

SHEET CBUF 83 FIG. 15

CH RAC 2L E AINPUIER pusuooww I T J STACK I I I I L J J N0 U DPERATION PRIME I PRIME I H v I4 I W I l I W I I I I I I I l I I I l I I I L L I i J L L 5 S L J; J

TABLET COMMUNICATION REGISTERS PAIENIEDFEB29 I972 SHEET CSUF 83 PAIENIEDFEBZB m2 3,646,523

SHEET 10 0F 83 FIG. 17C

PATENTEUFEBZS I972 3.646.523

sum 11 (1F 83 FIG. 17D

PAIENTEnmszs :912 3,646,523

SHEET 13 [1F 83 FIG.17F

READ COMPLETE COMPLETE PATENTEDFEBZSIBTZ 3,646,523

SHEET 150? 83 ASSOCIATIVE MEMORY CONTROL F I 19A wRITE A SELECT) F.

READ SELJECT 162" l I A 446 A FIF IL I 5 CA3 A Z A A Z v A j READ sE EcT FF J T *1 0 IIRITE A A 2 TIcIsII A READ SELIECT TI T I F. I 0 WRITE cA-I A A A SELECT) M 1L M W q A l READ W VVVV q SELECT) T T FF I52 A J I 0 65-1 A A I Y WRITE REIII) I IRITE PAHZNTEDFEBZSIQYZ 3.646.523

SHEET 15 [1F 83 FIG. 19B ASSOCIATIVE DATA MEMORY PLANE WORD 1 WORD1 WORD 1 BiT#1 BIT#2 B|T#161 worm 2 WORD 2 WORD 2 BIT#I BIT# 2 B1T# 161 WORD :1 WORD 3 WORD a BIT #1 BIT#2 a11#1s1 WORD 4 wono 4 wono 4 B11 1 1111111 2 BIT#16I 1 w 111 I i (DATA 01-2 PULSE 13 1111 11111 MJ 10 1111s 11111 10 10011 f 011-2 1 11151 15 11111111 1011 1111 11 51101 111 s111c11n 111115 101001 FOR INPUT MESSAGE FAIENIEUFEBZSIBTZ 3,646,523

QHEET 17UF 83 ASSOCIATIVE MEMORY VACANCY BIT STORAGE ELEMENT (BIT 1 INITIAL RESET wans SELECT 0 FIG. 21 fiw MISMMEL 4Q;Assoc|m 7 1 0 READ sum W sum 3610 /3 ASSOCIATIVE M EMORY STORAGE ELEMENT(B|T 2161) w WRITE SELECT ASSOCIATE

Claims (14)

1. A computer comprising: input channel means for forming the input entering into said computer into meaningful tokens, said tokens comprising three portions, viz, a descriptor for indicating the class of the token, the body, and a delimiter for indicating the end of the token, the classes of said tokens including integers, truth values, function constants which include functions from numbers to numbers, functions from number to truth values and functions from truth values to truth values, output device names, variable names, binding variables definition labels, defined expression names, conditional indicators, leFt parenthesis, and right parenthesis; a plurality of functional units for carrying out data-processing operations; central communication means for receiving from and providing information to said functional units in accordance with the calculus of lambda conversion; and linear memory means for containing a copy of a program throughout its execution.

2. A computer comprising: data-processing means for constituting the calculus of lambda conversion as the machine language of said computer, said last names means comprising: means for receiving input into said computer character by character in the form of fully parenthesized expressions, said expressions respectively representing programs; input means for forming said character-by-character input into meaningful tokens, each of said tokens including a descriptor portion for indicating the class of token, a body and a delimiter for indicating the end of the token; linear memory means for containing said tokens in said program form; central communication means; storage means for controlling the storing and fetching of data from said memory; node-assembling means for building said parenthesized expressions into program trees in said central communication means, said trees respectively comprising differing level nodes followed by n successor functions; means for evaluating variable nodes in said trees; said central communication means communicating with said input, storage, node assembling and variable more evaluating means by receiving messages therefrom and providing messages therefor; and second means for effecting the processing of data in said first means in accordance with said calculus.

3. A computer as defined in claim 2 wherein said data-processing means further includes: arithmetic logic means for carrying out arithmetic and logical operations in said computer; and output means for providing the results of the processing of data in said computer.

4. A computer comprising: data-processing means for constituting the calculus of lambda conversion as the machine language of said computer, said last named means comprising: central communication means; input means for receiving balanced parenthesis formulas character by character and for reassembling said characters into meaningful strings; linear memory means for containing the characters of said formulas in respective consecutive locations therein, said characters being placed in said memory to form said formulas; said input means being operative to place messages in said central communication means; storage means for effecting the storage of information in said memory, said storage means being operative to place messages in and receive messages from said central communication means relative to the storing and fetching of information from said memory; node-assembling means for assembling a formula as a program tree comprising successive level nodes in said central communication means, said node-assembling means being operative to place messages in and receive messages from said central communication means; beta conversion means for effecting a beta conversion of the elements of said trees in accordance with the beta conversion rule of said calculus, said beta conversion means being operative to place messages in and receive messages from said central communication means; and ''''UP'''' means for effecting the sending up of information to said nodes, said last-named means being operative to place messages in and receive messages from said central communications means.

5. A computer as defined in claim 4 wherein said data-processing means further includes: arithmetic and logic means for carrying out arithmetic and logical operations, said last named means being operative to place messages in and receive messages from said central communication means; and output means for effecting the output of the results which eNsue from the processing of said respective expressions, said output means being operative to place messages in and receive messages from said central communication means.

6. A computer as defined in claim 5 wherein the input hereinto is a formula of a balanced parenthesis form, said formula comprising strings of symbols respectively forming logical groups which are tokens, each of said tokens comprising a descriptor for indicating the type of token, a token body and a delimiter for indicating the end of the token; said descriptors including integers floating-point numbers, numbers of chosen numerical systems, truth values, the bodies of tokens having truth value descripters being true (T) or false (F), function constants comprising functions from numbers to numbers, functions from numbers to truth value, and functions from truth values to truth values, output device names, variable names, binding variable, definition labels, defined expression names, conditioned indicators, left parenthesis, and right parenthesis.

7. A computer as defined in claim 6 wherein said central communication means is an associative memory comprising an array of registers, each of said registers having a length of one word, the nodes of a tree given by a formula corresponding to rows in said central communication means, the branches emanating from the nodes corresponding to columns in the central communicating means, a tablet row for receiving a tablet entry comprising a first plus n following words to form an n-ary tree, said first word holding the node label of the tree node the entry is for, said n words holding tokens under said node.

8. A computer as defined in claim 7 wherein said input means comprises: a first register for receiving an input token character by character and for containing the address in linear memory to which said token is to go: a second register for receiving tokens other than left parentheses and conditional indicators, and their respective memory address from said first register, a token receiving a prime in said card second register provided that the next token is a right parenthesis; a third register for forming a central communication means entry; a pushdown stack for holding left parenthesis and conditional indicator tokens until the location of the nonright parenthesis token following there matching right parenthesis is known; a fourth register for receiving words from and providing words to said pushdown stack; and a fifth register for holding the information for the last left parenthesis or conditional indicator for which the matching right parenthesis is found.

9. A computer as defined in claim 7 wherein said node assembler means comprises means responsive to a message therefor in said central communication means which includes a node label, a blank or back pointer, a node assembler operation code, a location in said linear memory and a token retrieved from a chosen location in said linear memory for placing messages in said central communication means in response to the combination of the code assembler operation code and the token in said message for said node assembler means, said messages placed by said node assembler means in said central communication being inserted into rows of said central communication means.

10. A computer as defined in claim 7 wherein said beta conversion means includes means for scanning said central communications means for variable nodes and means for looking up the value of a variable through back pointers.

11. A computer as defined in claim 7 wherein said ''''UP'''' means includes means to ascertain the tree position of said nodes in a program formula; and means for checking as to whether the value expression for a variable evaluates to a complex expression.

12. A computer comprising: an associative memory; for handling programs and data in tree form, to effect the traversal, transformation and copying of trees whereby said trees are caused to collapse and grow; means for effecting general substitution procedures such that end points of branches of trees are replaced by trees recursively, in accordance with the lambda calculus, whereby subtrees are designated to be constituted for said end points, using variables in accordance with said lambda calculus. means for generating linear strings of symbols from trees; means for generating trees from linear input strings; means for storing a tree whereby tree structures are intrinsic to the addresses of nodes, said associative memory holding said tree addresses and for causing coordinate memory addresses to be interpreted as tree addresses; shift register means; and means to compute predecessor and successor functions on said tree addresses with said shift register means.

13. A central communication means for a computer comprising; a matrix of registers, each of said registers being capable of containing n words, each of said words comprising m bytes; said registers being arranged in k conceptually horizontal planes, each of said planes comprising a like amount of said registers, said registers defining the rows of said planes, corresponding bits in said registers defining the columns in said planes, corresponding registers in each of said k planes being conceptually vertically disposed in registration whereby each row of said matrix is a conceptually vertical planar array comprising k registers; and means for effecting the transferring of information through said matrix from register to register in respective opposite directions in adjacent ones of said planes whereby information is circulated through said matrix in a serpentine manner to effectively provide a multiple rank shift register.

14. A central communication means as defined in claim 13 and further including associative circuit means for enabling each of said conceptually vertical planar arrays of registers to function as respective associative memories.

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