US3660767A - Frequency divider circuit system - Google Patents
Frequency divider circuit system Download PDFInfo
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- US3660767A US3660767A US886131A US3660767DA US3660767A US 3660767 A US3660767 A US 3660767A US 886131 A US886131 A US 886131A US 3660767D A US3660767D A US 3660767DA US 3660767 A US3660767 A US 3660767A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B19/00—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
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- ABSTRACT A frequency divider wherein the pulse input having been delayed by a predetermined time interval is impressed upon a plurality of cascade connected flip flops, and the output from each of the flip-flops is fed to an AND gate to which is also fed the input which has not passed through the delay circuit to produce a resultant AND output to be fed back to each of the required flip-flops, thereby increasing the upper limit of the frequency to be divided and practically eliminating the danger ofa malfunction in the system.
- the switch R is closed, the lagging feed-back pulse i,,,,, occasions the pulse timing shown at (a), (b) and (c) in FIG.
- Influence of the time lag of 1 is most pronounced at the first stage, and the second and the third stages will also be influenced if the time lag is greater than l/fl,, or if the repetition frequency of the input pulse signal is increased, thus causing malfunctioning. Also, the greater the number of flip-flop stages, the more the time lag of i is increased to promote malfunctioning. Thus, the upper limit of the frequency to be divided depends upon the switching and delay time for each flip-flop and is decreased with an increasing number of stages.
- FIG. 3 At (a) of FIG. 3 is shown the case where the delay time of the feed-back pulse from the last stage exceeds the pulse period of the input, at (b) is shown the case where the delay time is less than the pulse period, and at (c) is shown the case with the shortest delay time, for which the resolution is the highest.
- An object of the present invention accordingly, is to provide a frequency divider which will not be subject to malfunctioning, even with highly repetitive input signal pulses. Another object of the invention is to provide a variable frequency divider wherein the obtained control pulse is used as the feed-back pulse. A further object of the invention is to provide frequency divider capable of high-speed carry by using the obtained control pulse as the carry pulse.
- FIG. 1 is a block diagram of a prior art feed-back type frequency divider
- FIG. 2 is a timing chart of the pulses involve in the system shown in FIG. 1;
- FIG. 3 is a timing chart showing the influence of the delay involved in the system of FIG. 1; 1
- FIG. 4 is a block diagram of one embodiment of the variable frequency divider according to the invention.
- FIG. 5 is a timing chart of the pulses involved in the system shown in FIG. 4;
- FIG. 6 is a block diagram of another embodiment of the frequency divider capable of high-speed operation in accordance with the invention.
- FIG. 7 is a timing chart involved in the system shown in FIG. 6.
- a frequency divider comprising a delay circuit for delaying the input signal, a counter circuit including a plurality of flip-flops connected in cascade, and an AND circuit for forming the logical product of the output from each of the flip-flops and the non-delayed input signal.
- the output from each of the stages is fed to an AND gate 6 to which is also fed the non-delayed input to produce an AND output to be fed through a corresponding one of the gate circuits R to R,, back to each of the respective stages.
- a frequency dividing ratio setting circuit H controls the on-or-ofi' function of the gates R to R,, in accordance with the control input.
- FIG. 5 at (a) are shown the input pulses, at (b) are shown the input pulses having passed through the delay circuit T, and at (c), (d), (e) and (f) are shown outputs from the respective flipflops F F F and F
- At the AND gate G is available a pulse output shown at (g).
- the flip-flops F F and F are provided with associated AND gates G G and 6;, so as to gate these flip-flops respectively from the previous stage flip-flops and actuate flip-flops F, F and F by the delayed input signal, so that the delay time for each of them is constant all through at At. However, for the next stage F and so on the delay time is progressively increased to 2A1, 3At,
- the provision of the AND gate G has the effect that notwithstanding the great time lag of i behind i,,, the pulse output from the gate G leads in its timing with respectto an input clock pulse appearing out of the delay circuit T 2" cycles after the input pulse corresponding to the feed-back pulse i by a time interval prescribed by the delay circuit, so that the situations shown at (a) and (b) in FIG. 3 will never take place and malfunctioning is absolutely eliminated.
- a feed-back pulse and an input pulse will happen to be completely coincident at one of the cascade connected stages in the counter chain; that is, the two pulses will happen to be simultaneously impressed upon one flip-flop.
- one of the impressed pulses is disregarded by the flipflop, which is thus forced to assume either a set or a re-set stable state, whereby either one or both of the states of both the input and feed-back pulses previous to their entry into the flipflop in question are interrupted as in i at (c) in FIG. 3, thus resulting in malfunctioning of the counter chain.
- the flip-flop in each stage should be responsive to both input and feed-back pulses so as to keep their state before their impression upon the following stage from being accidentally interrupted.
- the feed-back pulse to each stage suitably leads the input pulse to that stage as shown at (a) to (g) inclusive in FIG. 3, so that there is no possibility of coincidence of both pulses giving rise to malfunctioning.
- FIG. 6 shows another embodiment of the invention, with FIG. 7 illustrating the timing involved. It enables high-speed decimal carry by feeding the output from the flip-flop F the output from flip-flop F and the input to AND gate G whose output triggers flip-flop F thus reducing the delay occurring through the cascade connection of the decimal counter circuits.
- FIG. 7 at (a) is shown the input, at (b) is shown the input having passed through delay circuit T, at (c) is shown the output from flip-flop F at (d), (e) and (f) are shown the respective outputs from flip flop F F and F,, at (g) is shown the output from AND gate G of the system without delay circuit T, and at (h) is shown the output from AND gate T of the system provided with a delay circuit T.
- the pulse signal shown at (b) in FIG. 7 is subject to gating with the signals shown at (c) and (f), so that satisfactory carry pulses cannot be obtained, as is shown at (g) in FIG. 7.
- the pulse signal shown at (a) in FIG. 7 is subject to gating with the signals shown at (c) and (f) in FIG. 7, so that satisfactory carry pulses can be obtained.
- a frequency divider comprising:
- means including a delay circuit, for delaying an input pulse signal applied to said frequency divider;
- a counter circuit including a plurality of cascade connected means applying the delayed input pulse signal to at least a portion of said plurality of flip-flops;
- means including an AND circuit for producing an AND product of the non-delayed input pulse signal and the outputs of said plurality of flip-flops;
- means including a plurality of gate circuits, each connected to a corresponding one of said plurality of flip-flops, for selectively applying the output of said AND circuit to said corresponding one of said plurality of flip-flops.
- a frequency divider according to claim 1 further comprising a second AND circuit, having said delayed input pulse signal as a first input and the output of a first of said cascade connected flip-flops as a second input, the output of said second AND circuit being connected to the input of a second of said cascade connected flip-flops.
- a frequency divider comprising:
- means including a delay circuit, for delaying an input pulse signal
- a first counter circuit including a plurality of cascade conmeans applying the delayed input pulse signal to at least a portion of said plurality of flip-flops;
- a second counter circuit including at least one flip-flop
- means including an AND circuit, for producing an AND product of the non-delayed input pulse signal and the output of said first counter circuit; and means applying the output of said AND circuit to the input of said second counter circuit.
Abstract
A frequency divider wherein the pulse input having been delayed by a predetermined time interval is impressed upon a plurality of cascade connected flip-flops, and the output from each of the flip-flops is fed to an AND gate to which is also fed the input which has not passed through the delay circuit to produce a resultant AND output to be fed back to each of the required flipflops, thereby increasing the upper limit of the frequency to be divided and practically eliminating the danger of a malfunction in the system.
Description
United States Patent Yoshino et a].
451 May 2,1972
[54] FREQUENCY DIVIDER CIRCUIT 22 Filed: Dec. 18,1969
[21] AppLNo; 886,131
[52] US. Cl ..328/l5, 328/42, 328/48,
328/39 51 Int. Cl. 1103b 19/00 [58] Field ofSearch ..328/15,42,48,39,25-30, 328/49; 307/225, 226; 331/51 [56] References Cited UNITED STATES PATENTS 2,924,816 2/1960 Schreiber ..328/42 3,041,476 6/1962 Parker.... ....328/42 3.064890 11/1962 Butler..... ....328/42 3.076.601 2/1963 Goetz .328/42 3.212.010 10/1965 Podlesny. .307/325 3.268.740 8/1966 Rywak ..328/42 INPUT CONTROL INPU T 3,300,724 1/1967 Cutair 328/48 3,369,183 2/1968 Mesterm, .328/48 3,408,595 10/1968 Hillman 307/227 3,518,553 6/1970 l-lo et a1. ..328/48 OTHER PUBLICATlONS Arithmetic Operations in Digital Computers," Richards Nostrand Company NJ 2- 55 (p. 195- 197) Schmookler, Delay Free Counter IBM Tech. Disclosur Bull. (p. 929- 932) Vol. 7 No. 10 March 1965 Primary Examiner-Donald D. Forrer Assistant Examiner-12. E Hart Atl0rIm v-Stevens, Davis, Miller & Mosher [57] ABSTRACT A frequency divider wherein the pulse input having been delayed by a predetermined time interval is impressed upon a plurality of cascade connected flip flops, and the output from each of the flip-flops is fed to an AND gate to which is also fed the input which has not passed through the delay circuit to produce a resultant AND output to be fed back to each of the required flip-flops, thereby increasing the upper limit of the frequency to be divided and practically eliminating the danger ofa malfunction in the system.
3 Claims, 7 Drawing Figures PATENTEDMAY 2 I972 3,660,767
saw 2 BF 3 INPUT CONTROL INPUT ILJLJLHJLJTJULI'LJLJL PATENTEDMAY 21972 SHEET 3 BF 3 l/vPur Q FREQUENCY DIVIDER CIRCUIT SYSTEM This invention'relates to frequency dividers having flipflops.
In prior art binary feed-back type frequency dividers the time required for input pulses to propagate through a long counter chain resulted in a time lag of the output feed-back pulse from the last stage for determining the frequency dividing ration behind the corresponding input pulse.
Therefore, when the frequency dividing ratio is an odd number, the output feed-back pulse is impressed upon the first stage to increase the resolving time of the flip-flop of this stage, which increases the possibility of a malfunctioning for inputs of higher repetition frequencies. When the time lag of the feed-back pulse is extremely short, either one of the input pulse and the feed-back pulse which occasionally coincides with the input pulse at a stage is disregarded by the flip-flop of that stage to result in a malfunction. This is discussed in connection with a prior art frequency divider circuit shown in FIG. 1. Flip-flops F F F F and F, are connected in cascade and switches R R R R are provided in the feed-back circuits for the respective flip-flops. By appropriate operation of the switches, the feed-back pulse from the last stage F, is selectively impressed upon each stage to determine the frequency dividing ratio of the frequency divider. It is desirable for the appearance of the output feed-back pulse i,, to lag behind a pulse which appears 2" cycles after the input pulse i, by an interval which is less than one period of the input pulse train. Actually, i lags i by a dead time t,,= nAt, where A! is a time lag for each of the flip-flop stages F to F,,. Thus, when the switch R is closed, the lagging feed-back pulse i,,,, occasions the pulse timing shown at (a), (b) and (c) in FIG. 3, with the pulse period of the input pulse signal being l/fl, for a repetition frequencyf The smaller t l/f is, the higher is the resolution of the first-stage flip-flop that is required. The resolution herein refers to a minimum value of the pulse period for the proper functioning of the flip-flop.
Influence of the time lag of 1",, is most pronounced at the first stage, and the second and the third stages will also be influenced if the time lag is greater than l/fl,, or if the repetition frequency of the input pulse signal is increased, thus causing malfunctioning. Also, the greater the number of flip-flop stages, the more the time lag of i is increased to promote malfunctioning. Thus, the upper limit of the frequency to be divided depends upon the switching and delay time for each flip-flop and is decreased with an increasing number of stages.
The foregoing will be seen from FIG. 3. At (a) of FIG. 3 is shown the case where the delay time of the feed-back pulse from the last stage exceeds the pulse period of the input, at (b) is shown the case where the delay time is less than the pulse period, and at (c) is shown the case with the shortest delay time, for which the resolution is the highest.
An object of the present invention, accordingly, is to provide a frequency divider which will not be subject to malfunctioning, even with highly repetitive input signal pulses. Another object of the invention is to provide a variable frequency divider wherein the obtained control pulse is used as the feed-back pulse. A further object of the invention is to provide frequency divider capable of high-speed carry by using the obtained control pulse as the carry pulse.
The invention will now be described in conjunction with the preferred embodiments thereof with reference to the accompanying drawing, in which:
FIG. 1 is a block diagram of a prior art feed-back type frequency divider;
FIG. 2 is a timing chart of the pulses involve in the system shown in FIG. 1;
FIG. 3 is a timing chart showing the influence of the delay involved in the system of FIG. 1; 1
FIG. 4 is a block diagram of one embodiment of the variable frequency divider according to the invention;
FIG. 5 is a timing chart of the pulses involved in the system shown in FIG. 4;
FIG. 6 is a block diagram of another embodiment of the frequency divider capable of high-speed operation in accordance with the invention; and
FIG. 7 is a timing chart involved in the system shown in FIG. 6.
According to the features of the invention there is provided a frequency divider comprising a delay circuit for delaying the input signal, a counter circuit including a plurality of flip-flops connected in cascade, and an AND circuit for forming the logical product of the output from each of the flip-flops and the non-delayed input signal. Referring now to the drawing, particularly to FIG. 4 showing a preferred embodiment of the invention, the input signal is fed through a delay circuit T to flipflops F to F, connected in cascade and individually constituting the respective stages of the counter circuit. The output from each of the stages is fed to an AND gate 6 to which is also fed the non-delayed input to produce an AND output to be fed through a corresponding one of the gate circuits R to R,, back to each of the respective stages. A frequency dividing ratio setting circuit H controls the on-or-ofi' function of the gates R to R,, in accordance with the control input. In FIG. 5, at (a) are shown the input pulses, at (b) are shown the input pulses having passed through the delay circuit T, and at (c), (d), (e) and (f) are shown outputs from the respective flipflops F F F and F At the AND gate G is available a pulse output shown at (g).
The flip-flops F F and F are provided with associated AND gates G G and 6;, so as to gate these flip-flops respectively from the previous stage flip-flops and actuate flip-flops F, F and F by the delayed input signal, so that the delay time for each of them is constant all through at At. However, for the next stage F and so on the delay time is progressively increased to 2A1, 3At,
As is seen, the provision of the AND gate G has the effect that notwithstanding the great time lag of i behind i,,, the pulse output from the gate G leads in its timing with respectto an input clock pulse appearing out of the delay circuit T 2" cycles after the input pulse corresponding to the feed-back pulse i by a time interval prescribed by the delay circuit, so that the situations shown at (a) and (b) in FIG. 3 will never take place and malfunctioning is absolutely eliminated.
For the situation as shown at (c) in FIG. 3, i.e., without the delay circuitT, a feed-back pulse and an input pulse will happen to be completely coincident at one of the cascade connected stages in the counter chain; that is, the two pulses will happen to be simultaneously impressed upon one flip-flop. As a result, one of the impressed pulses is disregarded by the flipflop, which is thus forced to assume either a set or a re-set stable state, whereby either one or both of the states of both the input and feed-back pulses previous to their entry into the flipflop in question are interrupted as in i at (c) in FIG. 3, thus resulting in malfunctioning of the counter chain. In practice the flip-flop in each stage should be responsive to both input and feed-back pulses so as to keep their state before their impression upon the following stage from being accidentally interrupted.
In the system according to the invention the feed-back pulse to each stage suitably leads the input pulse to that stage as shown at (a) to (g) inclusive in FIG. 3, so that there is no possibility of coincidence of both pulses giving rise to malfunctioning.
It will also be apparent from that shown at (h) to (l) inclusive in FIG. 5 that the delay circuit T makes it possible to eliminate malfunctioning of the system which would otherwise occur as a result of doubling an equivalent feed-back pulse,
output from the flip-flop F, the output from the AND gate G of the system without the delay circuit T, and the output from the AND gate G of the system having the delay circuit T.
FIG. 6 shows another embodiment of the invention, with FIG. 7 illustrating the timing involved. It enables high-speed decimal carry by feeding the output from the flip-flop F the output from flip-flop F and the input to AND gate G whose output triggers flip-flop F thus reducing the delay occurring through the cascade connection of the decimal counter circuits.
In FIG. 7, at (a) is shown the input, at (b) is shown the input having passed through delay circuit T, at (c) is shown the output from flip-flop F at (d), (e) and (f) are shown the respective outputs from flip flop F F and F,,, at (g) is shown the output from AND gate G of the system without delay circuit T, and at (h) is shown the output from AND gate T of the system provided with a delay circuit T. Without the delay circuit T, the pulse signal shown at (b) in FIG. 7 is subject to gating with the signals shown at (c) and (f), so that satisfactory carry pulses cannot be obtained, as is shown at (g) in FIG. 7. On the other hand, with the delay circuit the pulse signal shown at (a) in FIG. 7 is subject to gating with the signals shown at (c) and (f) in FIG. 7, so that satisfactory carry pulses can be obtained.
As has been described in the foregoing by-the provision of an AND circuit and delay circuit it is possible to have a frequency divider practically free from any malfunctioning.
' What is claimed is:
1. A frequency divider, comprising:
means, including a delay circuit, for delaying an input pulse signal applied to said frequency divider;
a counter circuit including a plurality of cascade connected means applying the delayed input pulse signal to at least a portion of said plurality of flip-flops;
means, including an AND circuit for producing an AND product of the non-delayed input pulse signal and the outputs of said plurality of flip-flops; and
means, including a plurality of gate circuits, each connected to a corresponding one of said plurality of flip-flops, for selectively applying the output of said AND circuit to said corresponding one of said plurality of flip-flops.
2. A frequency divider according to claim 1, further comprising a second AND circuit, having said delayed input pulse signal as a first input and the output of a first of said cascade connected flip-flops as a second input, the output of said second AND circuit being connected to the input of a second of said cascade connected flip-flops.
3. A frequency divider, comprising:
means, including a delay circuit, for delaying an input pulse signal;
a first counter circuit including a plurality of cascade conmeans applying the delayed input pulse signal to at least a portion of said plurality of flip-flops;
a second counter circuit including at least one flip-flop;
means, including an AND circuit, for producing an AND product of the non-delayed input pulse signal and the output of said first counter circuit; and means applying the output of said AND circuit to the input of said second counter circuit.
Claims (3)
1. A frequency divider, comprising: means, including a delay circuit, for delaying an input pulse signal applied to said frequency divider; a counter circuit including a plurality of cascade connected flip-flops; means applying the delayed input pulse signal to at least a portion of said plurality of flip-flops; means, including an AND circuit for producing an AND product of the non-delayed input pulse signal and the outputs of said plurality of flip-flops; and means, including a plurality of gate circuits, each connected to a corresponding one of said plurality of flip-flops, for selectively applying the output of said AND circuit to said corresponding one of said plurality of flip-flops.
2. A frequency divider according to claim 1, further comprising a second AND circuit, having said delayed input pulse signal as a first input and the output of a first of said cascade connected flip-flops as a second input, the output of said second AND circuit being connected to the input of a second of said cascade connected flip-flops.
3. A frequency divider, comprising: means, including a delay circuit, for delaying an input pulse signal; a first counter circuit including a plurality of cascade connected flip-flops; means applying the delayed input pulse signal to at least a portion of said plurality of flip-flops; a second counter circuit including at least one flip-flop; means, including an AND circuit, for producing an AND product of the non-delayed input pulse signal and the output of said first counter circuit; and means applying the output of said AND circuit to the input of said second counter circuit.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US88613169A | 1969-12-18 | 1969-12-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| US3660767A true US3660767A (en) | 1972-05-02 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US886131A Expired - Lifetime US3660767A (en) | 1969-12-18 | 1969-12-18 | Frequency divider circuit system |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3761824A (en) * | 1970-11-25 | 1973-09-25 | Siemens Ag | Pulse frequency divider |
| US4109210A (en) * | 1976-02-28 | 1978-08-22 | Itt Industries, Incorporated | Method of generating a variable train of pulses |
| US5144450A (en) * | 1990-02-27 | 1992-09-01 | Sony Corporation | Auto focus frequency conversion filter for ccd imagers having different numbers of pixels |
| US5532633A (en) * | 1993-12-03 | 1996-07-02 | Nec Corporaton | Clock generating circuit generating a plurality of non-overlapping clock signals |
| US5952863A (en) * | 1996-12-09 | 1999-09-14 | Texas Instruments Incorporated | Circuit and method for generating non-overlapping clock signals for an integrated circuit |
| US20090128133A1 (en) * | 2007-11-20 | 2009-05-21 | Boerstler David W | Duty Cycle Measurement Method and Apparatus for Various Signals Throughout an Integrated Circuit Device |
| US20090138834A1 (en) * | 2007-11-20 | 2009-05-28 | International Business Machines Corporation | Structure for a Duty Cycle Measurement Circuit |
| US20100052651A1 (en) * | 2008-08-28 | 2010-03-04 | Advantest Corporation | Pulse width measurement circuit |
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| US2924816A (en) * | 1956-09-14 | 1960-02-09 | Technicolor Corp | Electronic counter |
| US3041476A (en) * | 1958-04-23 | 1962-06-26 | Decca Record Co Ltd | Registers for binary digital information |
| US3064890A (en) * | 1961-05-29 | 1962-11-20 | Bell Telephone Labor Inc | Parallel input fast carry binary counter with feedback resetting means |
| US3076601A (en) * | 1959-08-27 | 1963-02-05 | Bell Telephone Labor Inc | Electronic binary counter and converter |
| US3212010A (en) * | 1963-02-25 | 1965-10-12 | Gen Motors Corp | Increasing frequency pulse generator for indicating predetermined time intervals by the number of output pulses |
| US3268740A (en) * | 1963-11-06 | 1966-08-23 | Northern Electric Co | Shift register with additional storage means connected between register stages for establishing temporary master-slave relationship |
| US3300724A (en) * | 1964-03-09 | 1967-01-24 | Ibm | Data register with particular intrastage feedback and transfer means between stages to automatically advance data |
| US3369183A (en) * | 1964-07-11 | 1968-02-13 | Telefunken Patent | Binary frequency divider circuit having externally adjustable frequency selection means and reset means |
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| US3518553A (en) * | 1968-02-08 | 1970-06-30 | Sylvania Electric Prod | Programmable frequency divider |
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| US2924816A (en) * | 1956-09-14 | 1960-02-09 | Technicolor Corp | Electronic counter |
| US3041476A (en) * | 1958-04-23 | 1962-06-26 | Decca Record Co Ltd | Registers for binary digital information |
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| US3300724A (en) * | 1964-03-09 | 1967-01-24 | Ibm | Data register with particular intrastage feedback and transfer means between stages to automatically advance data |
| US3369183A (en) * | 1964-07-11 | 1968-02-13 | Telefunken Patent | Binary frequency divider circuit having externally adjustable frequency selection means and reset means |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3761824A (en) * | 1970-11-25 | 1973-09-25 | Siemens Ag | Pulse frequency divider |
| US4109210A (en) * | 1976-02-28 | 1978-08-22 | Itt Industries, Incorporated | Method of generating a variable train of pulses |
| US5144450A (en) * | 1990-02-27 | 1992-09-01 | Sony Corporation | Auto focus frequency conversion filter for ccd imagers having different numbers of pixels |
| US5532633A (en) * | 1993-12-03 | 1996-07-02 | Nec Corporaton | Clock generating circuit generating a plurality of non-overlapping clock signals |
| US5952863A (en) * | 1996-12-09 | 1999-09-14 | Texas Instruments Incorporated | Circuit and method for generating non-overlapping clock signals for an integrated circuit |
| US20090128133A1 (en) * | 2007-11-20 | 2009-05-21 | Boerstler David W | Duty Cycle Measurement Method and Apparatus for Various Signals Throughout an Integrated Circuit Device |
| US20090138834A1 (en) * | 2007-11-20 | 2009-05-28 | International Business Machines Corporation | Structure for a Duty Cycle Measurement Circuit |
| US7895005B2 (en) * | 2007-11-20 | 2011-02-22 | International Business Machines Corporation | Duty cycle measurement for various signals throughout an integrated circuit device |
| US7917318B2 (en) * | 2007-11-20 | 2011-03-29 | International Business Machines Corporation | Structure for a duty cycle measurement circuit |
| US20100052651A1 (en) * | 2008-08-28 | 2010-03-04 | Advantest Corporation | Pulse width measurement circuit |
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