US3671956A

US3671956A - Display system

Info

Publication number: US3671956A
Application number: US806624A
Authority: US
Inventors: Thomas D Kegelman; Peter R Williams
Original assignee: Computer Optics Inc
Current assignee: Computer Optics Inc
Priority date: 1969-03-12
Filing date: 1969-03-12
Publication date: 1972-06-20
Anticipated expiration: 1989-06-20
Also published as: GB1303184A; GB1303183A; BE747184A; FR2037939A5; NL7003542A; DE2010936A1; JPS4919926B1; GB1303181A; CH539896A

Abstract

A multiple beam alpha-numeric display system wherein a plurality of text lines are formed simultaneously with the top segments of the characters in a text line being formed on a first pass and successively lower segments being formed in subsequent passes. A non linear vertical sweep is used to compress the interline spacing of horizontal traces within a text line and to increase the interline spacing between text lines. To minimize display distortion, the multiple electron beams are oriented to cross one another at the center of the deflection yokes.

Description

United States Patent Kegelman et al. [4 1 June 20, 1972 [$4] DISPLAY SYSTEM 3,388,391 6/1968 Clark .340 324 3,400,377 9/1968 Lee .340/324 x [72] lnventors. Thomas D. Kegelman, Ridgefield; Peter R.

Williams, Wilton, both of Com 3,423,749 l/l969 Newcomb .340 324 3,449,620 6/1969 Caron et al. ..340 324 x [73] Assignee: Computer Optics, Inc., Bethel, Conn.

[22] Filed: March 12, 1969 [21] Appl. No.: 806,624

[52] US. Cl. .340/324 A, 315/13, 315/26 [51] Int. Cl. ..G06f 3/14 [58] Field 01 Search ..340/324.1, 324 A, 172.5; 315/13, 26

[56] References Cited UNITED STATES PATENTS 3,345,458 /1967 Cole ct a1. ..340/324 A X 3,503,063 3/1970 Starr ..340/324 A 3,140,473 7/1964 Gafi'ney ...340/324 X 3,284,663 1 1/1966 Stocker ..340/324 X J/IB 956 (York Hap/Z 0/7/41 Primary Examiner-David L. Trafton ArtorneyMorgan, Finnegan, Durham & Pine 57 ABSTRACT A multiple beam alpha-numeric display system wherein a plurality of text lines are formed simultaneously with the top segments of the characters in a text line being formed on a first pass and successively lower segments being formed in subsequent passes. A non linear vertical sweep is used to compress the interline spacing of horizontal traces within a text line and to increase the interline spacing between text lines. To minimize display distortion, the multiple electron beams are oriented to cross one another at the center of the deflection yokes.

22 Claims, 10 Drawing Figures Gnu 8 l DGIC 24' 57,46: DIM Y 4 H DRIVE l/OP/Za ll S WEEP D/DDLA" SWEEP this application relates to subject matter in application Ser. No. 806,472 filed Mar. 12, 1969 now U.S.'Pat. No. 3,622,809.

BACKGROUND OF THE INVENTION .ment remotely located relative to the main computer assembly. For example, a stockbroker may have a desk top unit connected to the main computer assembly by telephone lines .so that infonnation such as current price quotations or backgrounddata for a corporation can be requested by means of a keyboard and, the requested data received from the computer can be displayed on a cathode ray tube. Corporate executives can be similarly equipped to obtain up-to-date inventory, sales, or customer data. Instantaneous cathode ray readout is preferable to print-out systems in many cases but, to date, systems capable of producing substantial quantities of data on an instantaneous read-out have not been readily available.

The existing high density, high quality, instantaneous dis play systems capable of producing 2,000 or more alpha-numeric characters are exceedingly costly and, as a result, cannot be economically justified in many installationswhere substantial read-out information is desired. The display systems of more moderate cost severely sacrifice the character display capability or character definition or both and often present display distortions disturbing to the viewer.

The general object of this invention is to provide a moderate cost, high density, display system with negligible distortion.

BRIEF SUMMARYOF THE INVENTION In the system according to the invention, the scanning sequence consists of successive horizontal traces formed by means of an electron beam which gradually moves from the top to the bottom of the display, much the same as in a conventional television scanning pattern. A horizontal line of characters, referred to as a text line, is formedby a plurality of adjacent horizontal traces, twenty horizontal traces per text line having been ,found to provide excellent character definition. The top segments of each of the characters of atext line are formed during the first pass and successively-lower segments are formed on subsequent passes. A horizontal line is divided up according to the number of characters on the line appearing in successive character slots and each character slot is then, further divided into character increments, twenty four horizontal increments per character having been found to produce excellent character definition. However, there can be considerable variation in the number of successive traces and horizontal increments which are used in making up the characters acceptable to the viewer.

The system is arranged to operate at conventional television scanning rates so that maximum use can be made of the low cost, highly developed television components. Systems operating at higher scanning rates require custom designed and custom built components which are considerably more costly not only because of their custom nature but also because the cost of components generally tends to increase as a cube function according to the increases in the operating frequencies and bandwidth. In a conventional television scanning pattern there are a total of 525 horizontal lines (500 usable lines) and a complete frame, consisting of two interlaced display fields, is produced 30 times per second. Successive horizontal traces occur at a rate of 15.75 kilohertz and each horizontal trace has a duration of approximately 64 micro-seconds of which 50-55 micro-seconds is usable.

In the system according to the invention, each text line consists of I characters and, therefore, successive characters formed in a horizontal trace occur at a rate of approximately 2 megahertz. Control circuitry operating at a 2 megahertz rate is commercially available at moderate cost. Each character is further broken down into as many as 24 horizontal increments and if on-off control of the electron'beam were to be achieved in conventional fashion, the control logic would have to operate at a rate higher than 40 megahertz. However, according to the invention, the character generation logic works in combination with a delay line to achieve the desired incremental control functions without resorting to unduly high operating frequencies.

If the scanning pattern includes 500 usable lines and 20 lines are used per text line, there is a total possibility of 25 text lines which, at characters per text line, provides a total display capability of 2,500 characters. This can be achieved if the need for blank lines between text lines is eliminated. According to the invention a non-linear vertical sweep is utilized to compress the interline spacing between horizontal traces within the text lines and to increase the interline spacing between the text lines. It should be noted that character definition is a function of the number of horizontal traces per text line and the number of horizontal increments per character. As a result, reducing the interline spacing reduces the size of the character and increases the number of characters which can be displayed, but this does not sacrifice the character definition.

According to the invention the number ,of available characters can be further substantially increased without sacrificing character definition or increasing the operating frequency or bandwidth of the system through the use of a unique multiple beam scanning arrangement. A two beam system, for example, would increase the number of available display characters from 2,500 to 5,000 and a three beam system would increase the number to 7,500.

In order to minimize distortion, the transverse displacement between the individual beamsis minimized at the point where the beams pass through the deflection yokes. If the beams are arranged to cross one another approximately at the center of the deflection yokes, the transverse displacement is substantially eliminated. The angular displacement of the beam is less critical than the transverse displacement as far as display distortion is concerned. The angular displacement, nevertheless, is minimized by arranging the beams to provide adjacent text lines of the display. Since adjacent text lines of the display are formed by different beams, any distortion created by the multiple beam system does not occur within a text line where it would be noticable and disturbing to the viewer, but instead occurs between text lines where it is generally not noticed.

The vertical sweep for the multiple beam system is nonlinear such that the interline spacing of horizontal traces in a text line is compressed into a fraction of the space which would otherwise be occupied by a text line. In the three beam system the first three text lines are formed simultaneously and then the vertical deflection circuitry drops the three beams down to form the next group of text lines, etc.

In order to reduce flicker of the display, all of the odd lines are produced during one vertical sweep and the even'lines are produced during the next vertical sweep. As a result, the beams cover the screen from top to bottom 60 times per second even though the complete frame is provided only 30 times per second.

BRIEF DESCRIPTION OF DRAWINGS FIG. 6 is a block diagram illustrating the overall control logic for the system;

FIG. 7 is a schematic diagram of the character generation logic and related circuits utilized in the formation of the letter as illustrated in FIGS. 4 and and FIG. 8 illustrates the manner in which the even and odd fields are interlaced.

ORGANIZATION OF DISPLAY The organization of the alpha-numeric display on the viewing screen is shown in FIG. 1 for a three gun cathode ray system using a tube generally as shown in FIG. 2. The cathode ray tube includes an evacuated glass envelope 1 having a phosphor coated surface 2 inside the tube at the enlarged viewing end 3. The electron guns designated A, B and C, respectively, are located within the tube at the end opposite the screen. The three guns are vertically aligned and oriented so that the respective beams cross at point 5 in the center of the vertical and horizontal deflection yokes 4. The vertical orientation of the guns is such that trace A produced by gun A forms the first text line on the screen, while trace B from electron gun B forms the second text line and trace C from electron gun C forms the third text line, as indicated in FIG. 1. Thus, traces A, B and C are actually quite close together, the actual spacing corresponding to the relative spacing of adjacent text lines.

In the illustrative embodiment each text line consists of twenty successive horizontal traces. The upper 16 traces are used in the formation of upper case letters and numerals, and the lower four lines are utilized to form the stems of lower case letters such as f, g, j, p, q and y. The horizontal sweep frequency is 15.75 kilohertz and, therefore, the time allocated for a horizontal trace is 64 microseconds. The control logic for the system divides the horizontal sweep into 128 character slots and, hence, the individual characters appear at a rate of 2.016 megahertz. It is necessary to provide time for return of the electron beam from left to right following each horizontal sweep and therefore only approximately 100 of the 128 characters are actually used.

After the formation of the first text block consisting of three successive text lines, the vertical deflection signal drops all three beams simultaneously to a position where they form the second text block likewise consisting of three text lines. Successive text blocks are then formed in similar fashion. Since there are twenty horizontal traces per text line and a total of 525 horizontal traces forming a complete frame for each gun, there is a total possibility of 26 text blocks. However, in order to provide sufficient time for vertical retrace of the electron beams, at least one of the text blocks would be lost.

A complete frame consisting of 525 lines per electron gun is provided 30 times per second. To reduce flicker of the display, all of the odd lines are provided first to form an odd field and then all of the even lines are formed to provide an even field. Each field consists of 262.5 lines and a vertical scan from top to bottom of the screen occurs at a rate of 60 times per second.

The manner in which the interlace is achieved is shown generally in FIG. 8, which for simplicity only shows the scanning pattern for one of the beams. The first line begins in the upper left corner and moves to the right under control of the horizontal sweep and also moves downwardly slightly under influence of the vertical sweep. Successive parallel lines 2-262 are then formed gradually moving down the screen, these being referred to as odd lines of the odd field even though numbered consecutively in FIG. 8. Line 263 is split between the bottom and top of the scanning pattern. In other words, line 263 reaches the bottom of the pattern half way through the horizontal trace, at which time the vertical sweep circuit returns the beam to the top pattern. The second half of line 263 therefore is located just above the right portion of line 1. The next line, line 264, is midway between lines 1 and 2. Successive lines of the even field are interlaced between lines of the odd field in similar fashion. After another 262.5 lines a total of 525 lines will have been completed and the beam is in the lower right corner of the scanning pattern at which time the vertical and horizontal sweep circuits return the beam to the upper left corner to begin a new frame. The first text line (following the line numbering system in FIG. 8) would consist of lines 1-10 of the odd field and lines 264-273 of the even field.

The vertical sweep signal is shown in FIG. 3A having a fundamental frequency of 60 hertz and being in the form of a linear ramp signal repeatedly going from negative to positive. The 60 hertz fundamental frequency corresponds exactly to the formation of 262.5 horizontal traces on the screen. Superimposed upon the vertical sweep signal is a diddle sweep signal as shown in FIG. 3B. The diddle sweep is a linear ramp signal, going repeatedly from positive to negative. The period of each ramp signal corresponds exactly to the time required for the formation of 10 horizontal traces, this being the horizontal traces of a text line formed during either the odd or even field. The diddle sweep is synchronized with the formation of the text lines and the period of each ramp signal is therefore 640 microseconds. The effect of the combined sweep signal as shown in FIG. 3C is to reduce the slope of the vertical sweep for the duration of each text line. The amplitude of the diddle sweep signal is adjusted to reduce the slope by somewhat more than a factor of three to thereby compress the horizontal traces making up a text line into a space somewhat less than a third of that otherwise occupied. The number of horizontal traces making up a text line remains the same and, therefore, even though the character becomes smaller, there is no material sacrifice in character definition. By compressing the text lines in this fashion, space is provided for text lines provided by the other electron guns of the system.

The manner in which the individual characters are produced is illustrated in FIGS. 4 and 5. In these figures the capital letter 0" is formed on a grid consisting of 16 vertically separated traces designated Y -Y with each horizontal trace broken into twenty four horizontal increments designated X,-X The electrical signals applied to the grid of the electron gun are shown in FIG. 5 and the resulting visible display is shown in FIG. 4. During the first horizontal trace Y,, the electron gun is ofi during increments X to X is on during increments X to X and is off during increments X to K The result is a visible segment a as shown in FIG. 4. During the second horizontal trace Y the beam is off during increments X,-X X and X X but is on during increments X -X and X -X to provide the segments b shown in FIG. 4. On the third horizontal trace Y the beam is off during segments X X X X, X ,X and is on during segments X X and X -X to provide the segments c shown in Hg. 4. During the fourth horizontal trace Y, the electron beam is off during segments X,X X X,-,, X -X and is on during segments X,-X-, and X -X to provide the segments d shown in FIG. 4. During the fifth horizontal trace the electron beam is off during segments X,-X X -X and X -X and is on during segments X -,-X and X -X to provide the segments e shown in FIG. 4. During horizontal traces Y through Y the beam is off during segments X,, X X and X to provide the sections f shown in FIG. 4. Sections g, h, i, j and k in FIG. 4 are formed respectively during the 12th through 16th horizontal traces Y -Y these segments being formed in a fashion similar to the formation of sections c, d, c, b and a respectively.

CONTROL SYSTEM The control system for achieving a display as shown in FIGS. 1 and 4 is shown in block diagram form in FIG. 6.

The timing for the entire system is controlled by a clock pulse source 20 operating at a frequency of 2.016 megahertz, this being the rate at which the segments of successive characters are produced during a horizontal trace. The output of clock 20 passes through a six stage binary counter 21 to reduce the frequency to 31.5 kilohertz and then passes through a binary stage 22 to produce a 15.75 kilohertz signal, the latter being used to control the horizontal sweep and related functions. The 31.5 kilohertz signal from counter 21 is supplied to a ten stage binery counter 23 which, in turn, is coupled to

logic circuits

24 and 25 which detect the 520th and 525th counts respectively. Since the 31.5 kilohertz signal has a frequency twice the frequency of the horizontal sweep, the 525th count corresponds exactly to 262.5 horizontal lines and provides the control signal for the vertical drive at the 60 hertz rate. The output signal from circuit 25 is used to reset counter 23 upon occurrence of the 525th count.

The 15.75 kilohertz signal from counter 22 is supplied to a horizontal drive circuit 27 which provides a drive pulse for triggering successive linear ramp signals by means of a horizontal sweep circuit 28 which, in turn, drives a horizontal deflection amplifier 29. The 60 hertz signal developed by logic circuit 25 is supplied to a vertical drive circuit 27 which provides the pulses for triggering a vertical sweep circuit 38. The output of the vertical sweep circuit is supplied to a vertical deflection amplifier 39 where it is combined with a diddle sweep signal.

The incoming data for the system is stored in a circulating memory 30 which consists of a delay line in series with an amplifier to form a closed circulating loop. Also included in the circulating memory is control logic for organizing the received data for proper location within the circulating memory and address logic for designating the various stored signal locations. The introduction of data into the memory, or the removal of data from the memory, is controlled by the 2.016 megahertz clock 20. The time delay within the circulating memory is sufficient to provide storage capacity for the characters of the entire display frame, each character being in a six bit code.

Registers 31-36 provide temporary storage for data while being used in character generation. Each register has a capability of storing six bit character designations for an entire 128 character text line. The Channel 1A register 31, for example, includes six parallel 128 stage registers. The circulating memory 30 is preferably arranged to provide serial transfer of data into the registers which can be achieved by organizing all the data for the text line with the most significant bits first and ending with all the least significant bits. During the transfer of data into register 31, the six individual 128 stage shift registers can be connected in series and the data from the circulating memory passed via AND gate 41 in serial fashion. When the register is loaded, the six bit designation of the first character of the text line appears on six parallel output lines from the channel 1A register, the parallel output of the register being indicated by the parallel line arrow. These outputs are coupled to character generation logic unit 70 via multiple AND gates 51 capable of gating each of the individual parallel outputs. Advance pulses are supplied to register 31 via AND circuit 61 from clock 20, such that each time an advance pulse is applied the six bits of the next character designation appear at the outputs which are coupled to the character generation logic. The registers are designed so that data can be recirculated within the register as many times as desired.

Registers

32 and 33 are similarly constructed and operate in a similar fashion. The registers receive data in serial fashion via AND

gates

42, 43 and are coupled to the character generation logic 70 via multiple AND

gates

52 and 53, respectively. Advance pulses are received via AND gate 61. Registers 31-33 make up the A channel registers and provide temporary storage for data of an entire text block. The B channel registers 34-36 are also similarly constructed and operate in a similar fashion. They receive data in serial form via AND circuits 44 and 46 and are coupled to the character generation logic via multiple AND circuits 54-56. Advance pulses are supplied from clock 20 at the 2.016 megahertz rate via AND circuit62.

The A and B channel registers operate alternatively so that one set of registers can be used to control the character generation logic during formation of a text block, while the other set of registers is receiving data from circulating memory 30. This control over the operation of the A and B channel registers is achieved by means of flip-flop circuit 60. When the flip-flop circuit is in the I state, multiple AND circuits 51-53 are enabled thereby coupling the A channel registers to the character generation logic, and AND gate 61 is enabled to permit the advance pulses from clock 20 to pass into registers 31-33. At the same time AND circuits 44-46 are enabled so that data can be transferred from the circulating memory into the B channel registers. On the other hand, when flip-flop circuit 60 is in the 0 state, advance pulses are supplied to the B channel registers via AND gate 62 and the B channel registers are coupled to the character generation logic via multiple AND circuits 54-56 whereas the circulating memory is coupled to the A channel registers via AND circuits 41-43.

The Y-odd and Y-even registers and 81 are each ten stage recirculating shift registers utilized to circulate a single bit which designates the successive horizontal lines of the odd and even fields respectively. During the formation of the even field, register 80 designates the ten successive lines of a text line whereas during formation of the odd field the 10 successive lines of a text line are designated by shift register 81, thereby making up the total of 20 lines per text line. The ten parallel outputs of register 80 are coupled to the character generation logic via multiple AND gates whereas the 10 individual outputs of register 81 are similarly coupled to the character generation logic via multiple AND gates 86. Advance pulses are supplied to the advance inputs A" of

registers

80 and 81 from counter 22 via AND

circuits

83 and 84 respectively. Flip-flop circuit 82 receives a signal from count logic 25 which is applied to the binery input of the flip-flop circuit so that the flip-flop changes state in synchronism with the beginning of each successive field. The flip-flop circuit is in the 1 state during formation of the odd field and therefore AND circuit 83 is enabled to apply the advance pulses to register 80, and multiple AND gates 85 are also enabled thereby coupling the output of register 80 to the character generation logic. Flip-flop circuit 82 is in the 0 state during formation of the even field and in this state flip-flop circuit 82 enables AND circuit 84 so that advance pulses are supplied from counter 22 to register 81 via AND circuit 84, and the flip-flop circuit also enables multiple AND gates 86 to couple the output of register 81 and the character generation logic.

Pulses are supplied to the reset inputs R" of

registers

80 and 81 to insure that the registers begin the stepping sequence on the initial line during the formation of the first text block. For the odd field register 80 should commence the counting sequence on line 1 (as designated in FIG. 8) which coincides with commencement of the vertical sweepfAccordingly, the reset pulse for register 80 is derived from count logic circuit 25 which produces the pulse which triggers the vertical sweep. Thereafter, the register advances in repetitive 10 step sequences during the formation of 26 successive text blocks, i.e. lines 1-260 of the scanning pattern.

For the even field the counting sequence of registers 81 should commence after a one-half line delay following commencement of the vertical sweep, i.e. at the beginning of line 264 as designated in FIG. 8. The half line delay is provided by flip-flop circuit 90 and associated AND gate 91. The signal developed by count logic circuit 25 signifies commencement of a vertical sweep at the beginning of the even field, and this signal is applied to the set input of flip-flop circuit 90 to place the flip-flop circuit in the 1 state. Flip-flop circuit 90 is connected to condition AND circuit 91 when in the 1 state. Upon commencement of the next horizontal trace which coincides with commencement of line 264, the pulse developed by counter 22 passes through conditioned AND gate 91 to reset register 81. The same pulse is also applied to the reset input of flip-flop circuit 90 to return the flip-flop circuit to the 0 state. Accordingly, register 81 commences its counting sequence on line 264 and thereafter repeatedly counts in a ten step sequence during formation of the twenty six text blocks of the even field.

When the circulating bit in either the Y-odd or Y-even registers 80 or 81 returns to the first stage of the register a pulse is developed by means of OR circuit 87 signifying that the lines forming a text block have been completed and the formation of a new text block is about to commence. The output of OR circuit 87 is coupled to the binery input of flip-flop circuit 60 to change the state of the flip-flop circuit so that a different one of the A or B channel registers is coupled to the character generation logic for formation of the next text block. The output of OR circuit 87 is also supplied to circulating memory 30 to initiate transfer ofa new set of data into that one of the A or B channel registers not then connected to the character generation logic. In addition, the output of OR circuit 87 is coupled to diddle drive circuit 88 which develops a pulse for triggering a new diddle sweep via circuit 89 so that the diddle sweeps are in exact synchronism with the formation of the successive text blocks. The diddle sweep circuit 89 provides the linear ramp signal as shown in FIG. 3B and the output of the sweep circuit is supplied to amplifier 39 where it is combined with the vertical sweep signal developed by circuit 38. The signal at the output of amplifier 39 is supplied to the vertical deflection coils and corresponds to the signal shown in FIG. 3C.

The character generation logic and associated channel gates 71-73 and delay line 74 are described more fully hereinafter in connection with FIG. 7. Basically, the character generation logic receives signals from either the A channel registers 31-33 or the B channel registers 34-36 designating the character (in six bit code) then being formed, and at the same time the character generation logic receives a signal from either register 80 or 81 indicating the particular line of the text block then being formed. In response to these inputs the character generation logic energizes selective ones of 24 output lines per channel according to the on-off control desired for a particular electron gun. If, for example, electron gun A is to form line Y of the letter (see FIGS. 4 and either register 31 or 34 would designate the letter O in six bit code and the Y-odd register energize its first output corresponding to line Y,. The 24 output lines from character generation logic 70 which are coupled to channel one gates 71 are designated X1-X24 (corresponding to the X1-X24 designations in FIGS. 4 and 5) of which lines X8-X17 would be energized for line Y in the formation of the letter 0". The channel one gates include twenty four individual AND gates connected respectively to successive ones of lines Xl-X24 and to 24 successive outputs of a 24 stage delay line 74. The output of the 2.016 megahertz clock 20 is coupled to delay line 74 and the delay line provides 24 successively delayed pulses in the 50 nanosecond interval between successive clock pulses. The successively delayed pulses provided by delay line 74 pass through the AND gates corresponding to energized lines X8-X17 to thereby enable electron gun A to provide the character segment a as shown in FIG. 4. The output of the channel one gates is supplied to an amplifier 75 which, in turn, is coupled to the grid of electron gun A. Registers 32 and 35 in similar fashion operate in combination with the channel two gates 72 and amplifier 76, and registers 33 and 36 operate in conjunction with the channel three gates 73 and amplifier 77.

Since some of the horizontal traces cannot be used in the character generation, namely lines 261-263 and 524-525, it is desirable to provide blanking circuitry since the remainder of the control circuitry is in continuous operation and otherwise would provide meaningless displays on these lines. The completion of line 260 and line 523 occurs when count logic 24 provides a pulse and the output of logic circuit 24 is therefore connected to the set" input of flip-flop circuit 92. When flip-flop circuit 92 is in the 1 state it activates a blanking circuit 78 which, in turn, is coupled to disable amplifiers 75-77. Flip-flop circuit 92 i2 returned to the 0 state upon commencement of the first line at the top of either the odd or even field. For the odd field this occurs when flip-flop circuit 82 changes to the I state, and for the even field this occurs when AND circuit 91 produces a pulse. Therefore, these signals are applied to the reset" input of flip-flop circuit 92 via an OR circuit 93.

In addition to lines 261-263 and 524-525 at the ends of the display fields it is necessary to blank the horizontal traces which occur during the vertical retrace. This can be achieved by either extending the blanking interval to include horizontal lines at the top of the display or by arranging the memory so that the first text block is blank.

CHARACTER GENERATION CIRCUITRY The character generation circuitry for the system disclosed in FIG. 6 is shown in more detail in FIG. 7. For simplicity, only a portion of the complete character generation logic is shown, namely that portion used in the formation of the capital letter 0 corresponding to the illustrations in FIGS. 4 and 5. However, it is to be understood that a complete set of alpha-numeric characters can be developed according to the concepts illustrated in FIG. 7. Also, for simplification, only the logic for one channel is illustrated. AND gates 101-110 and OR circuit 111 correspond for example, to the channel one gates 71 in FIG. 6, and would be duplicated for other channels.

Delay line 74 can be of any suitable design capable of being triggered at a 2.016 megahertz rate and of dividing the approximately 50 nanosecond interval between triggering pulses into 24 successively delayed pulses without significant deterioration of pulse width or amplitude. A suitable delay line is disclosed in co-pending application, Ser. No. 806,472, filed on even date herewith, now U.S. Pat. No. 3,622,809, and incorporated herein by reference. The delay line disclosed in the corresponding application includes a series ofinverting amplifier stages connected in cascade, the pulse passing down the amplifier chain being delayed by the successive turn-on time delays of each successive stage. The amplifier stages are connected to associated AND gates such as AND gates 101-110 in FIG. 7 so that the leading edge of the pulse passing down the amplifier chain controls both the enabling and disabling of the AND gates. As a result, the pulse width of the pulse passing down the amplifier chain may vary, but since the leading edge of the pulse controls both the enabling and disabling of the associated AND gates, the combination provides delayed pulses wherein the pulse width does not vary. With this circuit arrangement each of the AND gates 101-110 has two inputs derived from delay line 74 and a third input which is one of the lines X,X from the character generation logic.

When a pulse from the 2.016 megahertz clock is applied to delay line 74, the pulse ripples through the successive amplifier stages enabling and disabling the gates 101-110 in succession. Successively delayed output pulses are developed by those of AND gates 101-110 which also receive an energizing signal from the associated line X,X The outputs from AND circuits 101-110 are coupled to separate inputs of OR circuit 111 which, in turn, is coupled to one ofthe amplifiers 75-77.

AND

gates

180 and 181 are complementary AND gates which are utilized to determine when the outputs of on of the registers 31-36 designate the letter O. The six bit code for the letter O is, for example 001 l l 1. AND gate 180 is used to detect the presence of the ones and AND gate 181 is used to detect the presence of the zeros. When both AND

gates

180 and 181 detect the presence of the appropriate inputs designating the letter 0", they produce corresponding output signals causing AND circuit 182 to produce an output. AND circuit 182 is, in turn, coupled to enable AND gates 151-156.

The respective outputs of the Y-odd and Y-even registers and 81 (FIG. 6) are connected to respective inputs of OR circuits 141-146 as designated in FIG. 7. The 10 successive outputs of the Y-odd register are designated Y,, Y Y Y Y Y Y Y Y Y and the 10 successive outputs of the Y-even register 81 are Y Y Y Y Y Y Y Y, and Y When AND gates 151-157 are enabled, OR circuits 141-146 are coupled to amplifiers 161-166 respectively, which, in turn, are connected to lines 171-176.

Some of the AND gates connected to delay line 74 have been eliminated to simplify the illustration, only AND gates 9 ,,,,-108, I09 and 110 coupled to the lines X,-X and X and X respectively being shown. It is to be understood that additional AND gates in the complete system between gates 108 g and 109 would be similarly connected to lines designated X -X The connections of lines 171-176 to the various X lines aredesignated for each line toward the right in FIG. 7. Accordingly, line 171 is connected to lines X X X X X X X and X as designated. Of these connections only the connections to lines X X X X and X via OR circuits 122-125 and 129,- respectively, are specifically shown in FIG. 7. In similar fashion lines 172-176 are connected to the X lines designated in FIG. 7 via the OR circuits 121-130. OR circuits 121-130 would also receive similar inputs from character generation logic for other characters. 0, they produce corresponding output signals causing AND circuit 182 to produce an output. AND circuit 182 is, in turn, coupled to enable AND gates 151-156.

The respective outputs of the Y-odd and Y-even registers 80 and 81 (FIG. 6) are connected to respective inputs of OR circuits 141-146 as designated in FIG. 7. The 10 successive outputs of the Y-odd register are designated Y Y Y Y-,, Y,, Y Y Y Y Y and the 10 successive outputs of the Y-even register 81 are Y Y Y Y Y Y Y Y,,,, Y and Y When AND gates 151-157 are enabled, OR circuits 141-146 are coupled to amplifiers 161-166 respectively, which, in turn, are connected to lines 171-176.

Some of the AND gates connected to delay line 74 have been eliminated to simplify the illustration, only AND gates 101-108, 109 and 110 coupled to the lines X,-X and X and X respectively being shown. It is to be understood that additional AND gates in the complete system between

gates

108 and 109 would be similarly connected to lines designated X X The connections of lines 171-176 to the various X lines are designated for each line toward the right in FIG. 7. Accordingly, line 171 is connected to lines X X X X X X X and X as designated. Of these connections only the connections to lines X X X X and X via OR circuits 122-125 and 129, respectively, are specifically shown in FIG. 7. In similar fashion lines 172-176 are connected to the X lines designated in FIG. 7 via the OR circuits 121-130. OR circuits 121-130 would also receive similar inputs from character generation logic for other characters.

In operation, if the letter O is designated and AND gates 151-156 are enabled, the letter would be generated on the display screen. When line Y is energized producing an output from OR circuit 142, indicating that the first horizontal trace of a text line is being formed, a signal is developed which passes through AND gate 152 and amplifier 162 to energize line 172. Line 172 is, in turn, coupled to lines X -X to enable the associated AND circuits coupled to delay lines 74. During the first seven pulses which are applied to AND gates associated with non-energized lines X X-,, no output pulses would be produced. Thereafter, when the delay line enables the AND circuits associated with lines X -X energized from line 172, corresponding output signals are produced and these successive signals are combined in OR circuit 111 to provide a continuous energization signal during the corresponding interval. Thereafter, the delay line enables AND gates associated with lines X X but these lines are not energized and, therefore, the corresponding output pulses are not produced. The result is the segment a shown in FIG. 4.

Because of the interlace arrangement in the overall system, the next line which would be produced would be the third line Y;,. When line Y is energized a signal is produced on the output of OR circuit 144 which, in turn, energizes line 174. Line 174 energizes lines X -X and X,,-X to provide output pulses on corresponding intervals to thereby develop segments 0 as shown in FIG. 4. Thereafter, the remaining odd lines of the text line are formed in succession. Subsequently, when the even field is being formed, the lines Y Y Y etc. will be energized in succession to thereby complete development of the letter 0"on the viewing screen.

OPERATION OF THE SYSTEM In order to describe the operation of the overall system, it is necessary to assume certain initial conditions since the system operates in continuous fashion. Assume that flip-flop circuit 60 is in the 1 state, and that the A registers 31-33 are loaded with data for the formation of the first text block. Flip-flop circuit 82 is assumed to be in the 1 state indicating that the odd field is going to be formed and that, therefore, the Y-odd register is active. The Y-odd register is assumed to be in its reset state with the Y output thereof being energized. Flipflop circuits and 92 are both in the 0 state. Upon commencement, the horizontal, vertical, and diddle sweeps start simultaneously.

These assumed conditions correspond to the beginning of the scanning pattern for a display frame on the screen.

As the electron beams of the three guns'move horizontally forming the first set of horizontal traces, the A channel registers 31-33 receive advance pulses from clock 20 advancing the data in these registers so that the 128 character designations of the text line appear at the output of the registers in sequence. For each character designation a pulse is supplied to delay line 74 which, in turn, develops pulses through channel gates 71-73 to turn on and turn off electron guns A, B and C for appropriate increments during the formation of each successive character. This control is achieved by means of the character generation logic which has activated selective ones of the gates in channel gate circuits 71-73 according to the character designations provided by registers 31-33. The first set of horizontal traces are completed in 64 microseconds at which time the upper segments of all characters in the first three text lines (first text block) have been formed on the screen.

Upon completion of the first set of horizontal traces, the A channel registers 31-33 have recirculated the data and the data has therefore returned to its initial position with the first character designations of the text lines appearing at the outputs of the registers. Accordingly,the data in the A channel registers is ready for commencement of a second set of horizontal traces. At this time counter 22 provides a pulse which is supplied to horizontal drive circuit 27 to trigger a new horizontal sweep. The same pulse is also applied to register 80 via AND circuit 83 to advance the register to the next horizontal line designation. Since the entire scanning pattern consists of two interlaced fields, the next horizontal line designation provided by register 80 is line Y The second set of horizontal traces corresponding to line Y of the first text block is then formed according to the successive character designations under control of A channel registers31-33 as further broken into successive horizontal increments by means of delay line 74, character generation logic 70 and the channel gate circuits 71-73.

Thereafter, the remaining eight sets of odd lines of the first text block are completed in succession. Upon completion of the text block, counter 22 again provides a pulse which triggers a new horizontal sweep and advances register 80. Register 80, which has previously reached a full count, resets in response to this pulse and provides an output pulse via OR circuit 87. This output pulse is applied to diddle drive circuit 88 to trigger a new diddle sweep which drops the three beams into a lower position for formation of the second text block. The pulse from OR circuit 87 also shifts flip-flop circuit 60 to the 0 state so that the B registers 34-36 are coupled to the character generation logic 70. These B registers have previously been loaded with data from circulating memory 30 for formation of the second text block. The pulse from OR circuit 87 also goes to circulating memory 30 to initiate the transfer of data for the third text block into A registers 31-33. The system then proceeds to form the second text block and thereafter continues in similar fashion to form the remainder of 26' text blocks of the odd field.

During formation of the 26th text block, data for the first text block is loaded into the A channel registers 31-33. After completion of the 26th text block, the system attempts to continue with the formation of a 27th text block using the data supplied for the first text block. However, upon completion of the 26th text block, count logic circuit 24 produces a pulse which places flip-flop circuit 92 in the 1 state to disable amplifiers 75-77 via blanking circuit 78. Therefore, the abortive attempt of the system to produce a 27th text block is of no effect.

Shortly thereafter, count logic circuit 25 provides a pulse signifying the completion of 262.5 lines of the scanning pattern, this being the end of the odd field. The pulse from logic circuit 25 is supplied to vertical drive circuit 37 to trigger and a new vertical sweep and to flip-flop circuit 90 to place this circuit in the 1 state. The next pulse provided by counter 22 occurs upon commencement of line 264 which is the uppermost complete line of the even field. The pulse from counter 22 triggers a new horizontal sweep via circuits 27-29, passes through AND circuit 91 to reset register 81, and passes through OR circuit 93 to reset flip-flop circuit 92 to again enable amplifiers 75-77. When register 81 is reset, its output designates lines Y which is the uppermost line of the first text block in the even field.

Since text data for the first text block has previously been loaded into the A channel registers 31-33, the system proceeds to form the even lines of the first text block under control of Y-even register 81. These lines interlace with the previously formed odd lines to thereby complete the twenty lines of the first text group. Thereafter, successive odd lines of successive text groups are formed and upon completion of the 26th text group, logic circuit 24 produces a pulse which again disables amplifiers 75-77.

Upon completion of 262.5 lines of the even field, logic circuit 25 again produces a pulse which signifies both the end of the even field and the end of a frame consisting of 525 complete lines. This pulse from logic circuit 25 is applied to the vertical drive circuit 37 to trigger a new vertical sweep and is also applied to reset register 80. The same pulse returns flipflop circuit 82 to the 1 state which, in turn, resets flip-flop circuit 92 via OR circuit 93. Data for the first text block has previously been loaded into A registers 31-33. Thus, the sequence is complete and has returned to the starting point and, therefore, the system automatically commences producing another frame.

Although only one illustrative embodiment has been described in detail in the foregoing specification, it should be obvious that there are numerous variations in the circuit configurations and operating sequences which are within the scope of the contemplated invention. Although the system has been described as an alpha-numeric display system, the concepts of the invention can be used to provide other types of displays controlled by coded data. The invention is more particularly defined in the appended claims.

We claim:

1. An instantaneous alpha-numeric visual read-out system comprising a phosphor screen visible to viewers;

means providing at least one electron beam adapted for scanning said screen;

horizontal and vertical deflection means for controlling the position of said electron beam on said screen;

a horizontal deflection drive circuit for energizing said horizontal deflection means to obtain repetitive horizontal traces of said electron beam across said screen;

means controlling the intensity of said electron beam in synchronism with said horizontal traces to achieve successive text line displays on said screen, each text line display including a plurality of successive horizontal traces; and

a vertical deflection drive circuit for energizing said vertical deflection means to compress the interline spacing within a text line and to increase the interline spacing between text lines including circuit means for generating a vertical sweep signal,

circuit means for generating a diddle sweep signal with a repetition period corresponding to the number of horizontal traces which occur during a vertical sweep of said vertical sweep signal, and

circuit means for combining said vertical sweep signal and said diddle sweep signal and applying the combined signal to said deflection means.

2. Apparatus according to claim 1 comprising a plurality of electron beams each adapted for scanning said screen, the positions of said beams being controlled by said horizontal and vertical deflection means.

3. Apparatus according to claim 2 wherein said beams are oriented to cross one another substantially at the center of said horizontal and vertical deflection means.

4. Apparatus according to claim 2 wherein said beams are angularly separated to form adjacent text line displays on said screen.

5. An instantaneous alpha-numeric visual read-out system comprising a phosphor screen visible to viewers;

means providing a plurality of electron beams each adapted to scan said screen;

horizontal and vertical deflection means for controlling the positions of said beams on said screen, said electron beams being oriented to cross one another substantially at the center of said horizontal and vertical deflection means;

a horizontal deflection drive circuit for energizing said horizontal deflection means to obtain repetitive horizontal traces of said beams across said screen;

means individually controlling the intensity of said electron beams in synchronism with said horizontal traces to achieve successive multi-line text displays on said screen; and

a vertical deflection drive circuit for energizing said vertical deflection means to move said beams vertically to achieve the desired interline spacing between horizontal traces.

6. Apparatus according to claim 5 wherein said means providing a plurality of electron beams comprises a plurality of separate electron guns oriented to produce electron beams which cross substantially at the center of said horizontal and vertical deflection means.

7. Apparatus according to claim 5 wherein each of said multi-line text displays is produced by a single one ofsaid electron beams.

8. Apparatus according to claim 5 wherein said vertical deflection drive circuit so energizes said vertical deflection means that the interline scan spacing within said text lines is less than the interline scan spacing between text lines.

9. Apparatus according to claim 5 wherein said deflection drive circuits and means controlling intensity of said electron beams are arranged to provide a plurality of interlaced frames making up a complete scanning frame.

10. An instantaneous alpha-numeric read-out system comprising a cathode ray tube including at least one electron beam;

a memory for storing coded data designating the characters of a display frame;

a pair of alternately operable registers coupled to said memory each capable of storing coded data designating characters to be displayed in a text line on said cathode ray tube;

a pulse source connected to said alternately operable registers to advance said data in one of said registers for providing successive character designations at a rate controlled by said pulse source while the other of said registers receives data from said memory;

circuit means for providing successive horizontal trace designations for traces of said electron beam;

character generation circuit means operatively connected to said cathode ray tube, said alternately operable registers and said circuit means to control the intensity of said electron beam according to said successive horizontal trace and character designations; horizontal deflection circuit means coupled to said cathode ray tube to control the horizontal position of said electron beam;

first counter means connected to said pulse source and operative to produce an output pulse after receiving a predetermined number of pulses from said pulse source,

said first counter means being connected to said horizontal deflection circuit means to trigger successive horizontal sweeps of said electron beam, and

being connected to said circuit means to advance said circuit means for successive horizontal trace designations;

vertical deflection circuit means coupled to said cathode ray tube to control the vertical position of said electron beam; and

second counter means coupled to said pulse source and said vertical deflection circuit means to trigger successive vertical sweeps of said electron beam in response to a predetermined number of pulses from said pulse source.

11. Apparatus according to claim wherein the total number of horizontal traces of a display frame is an odd number and wherein said second counter means produces a pulse triggering a new vertical sweep each time one half the total number of horizontal traces of a display frame have been completed to provide two interlaced display fields per display frame.

12. Apparatus according to claim 11 wherein the pulse produced by said second counter means occur at a 60 hertz rate.

13. Apparatus according to claim 12 wherein said output pulses from said first counter means occur at a 15.75 kilohertz rate.

14. Apparatus according to claim 13 wherein the total number of horizontal traces of a display in 525 and the number of horizontal traces in a display field is 262.5.

15. Apparatus according to claim 10 wherein said alpha-numeric displays appear in successive text lines, each text line including a predetermined number of successive horizontal traces formed by said electron beam; and wherein said circuit means for providing successive horizontal trace designations resets each time said predetermined number of horizontal traces have been designated.

16. Apparatus according to claim 15 wherein said vertical deflection circuit means provides a linear vertical sweep signal; and further comprising a diddle sweep circuit operatively coupled to said vertical deflection circuit means to superimpose a diddle sweep signal upon said vertical sweep signal, said diddle sweep circuit being coupled to said circuit means and operative to initiate anew diddle sweep each time said circuit means is reset.

17. Apparatus according to claim 10 wherein said cathode ray tube includes a plurality of electron beams and wherein the system includes a separate pair of alternately operable registers for storing coded data designating successive characters for each of said electron beams, one register at a time of each of said pairs being advanced by pulses from said pulse source.

18. Apparatus according to claim 10 wherein said plurality of electron beams simultaneously -form adjacent text lines of characters on said cathode ray tube.

19. Apparatus according to claim 10 wherein the cathode ray tube display consists of a plurality of interlaced fields and wherein said circuit means for providing successive horizontal trace designations includes a separate register for each of said fields.

20. An instantaneous read-out system comprising:

a phosphor screen visible to viewers;

means providing at least one electron beam adapted for scanning said screen;

a horizontal deflection drive circuit for energizing said horizontal deflection means to obtain repetitive horizontal traces of said electron beam across said screen, each horizontal trace being divided into a predetermined number of horizontal increments; storage means for storing coded data designating the characters of a display frame,;

a pair of alternately operable registers coupled to said storage means each capable of storing coded data for designating characters of a complete text line display;

circuit means coupled to said registers to advance the data in one of said registers in synchronism with the movement of said electron beam during each horizontal trace while the other of said registers is connected to receive data from said storage means;

decoding means coupled to the one of said registers being advanced in synchronism with said electron beam for designating selected ones of said horizontal increments for display according to the coded character then designated;

means coupled to said storage means and said means providing said electron beam to control said beam in onoff fashion according to the horizontal increments designated for display; and

a vertical deflection drive circuit for energizing said vertical deflection means. 1

21. An instantaneous alpha-numeric visual read-out system comprising a phosphor screen visible to viewers;

means providing a plurality of electron beams each adapted to scan said screen;

means individually controlling the intensity of said electron beams in synchronism with said horizontal traces to achieve successive multi-line displays on said screen, wherein each of said multi-line text displays being produced by a single one of said electron beams, and said electron beams simultaneously produce a group of adjacent text lines corresponding to the number of electron beams in the apparatus; and

22. An instantaneous alpha-numeric visual read-out system comprising a phosphor screen visible to viewers;

means providing a plurality of electron beams each adapted to scan said screen;

means individually controlling the intensity of said electron beams in synchronism with said horizontal traces to achieve successive multi-line text displays on said screen;

a vertical deflection drive circuit for energizing said vertical deflection means to move said beams vertically to achieve the desired interline spacing between horizontal traces; and wherein said vertical deflection drive circuit so energizes said vertical deflection means that the interline scan within said text lines is less than the interline scan spacing between text lines, and

Claims

1. An instantaneous alpha-numeric visual read-out system comprising a phosphor screen visible to viewers; means providing at least one electron beam adapted for scanning said screen; horizontal and vertical deflection means for controlling the position of said electron beam on said screen; a horizontal deflection drive circuit for energizing said horizontal deflection means to obtain repetitive horizontal traces of said electron beam across said screen; means controlling the intensity of said electron beam in synchronism with said horizontal traces to achieve successive text line displays on said screen, each text line display including a plurality of successive horizontal traces; and a vertical deflection drive circuit for energizing said vertical deflection means to compress the interline spacing within a text line and to increase the interline spacing between text lines including circuit means for generating a vertical sweep signal, circuit means for generating a diddle sweep signal with a repetition period corresponding to the number of horizontal traces which occur during a vertical sweep of said vertical sweep signal, and circuit means for combining said vertical sweep signal and said diddle sweep signal and applying the combined signal to said deflection means.

5. An instantaneous alpha-numeric visual read-out system comprising a phosphor screen visible to viewers; means providing a plurality of electron beams each adapted to scan said screen; horizontal and vertical deflection means for controlling the positions of said beams on said screen, said electron beams being oriented to cross one another substantially at the center of said horizontal and vertical deflection means; a horizontal deflection drive circuit for energizing said horizontal deflection means to obtain repetitive horizontal traces of said beams across said screen; means individually controlling the intensity of said electron beams in synchronism with said horizontal traces to achieve successive multi-line text displays on said screen; and a vertical deflection drive circuit for energizing said vertical deflection means to move said beams vertically to achieve the desired interline spacing between horizontal traces.

7. Apparatus according to claim 5 wherein each of said multi-line text displays is produced by a single one of said electron beams.

10. An instantaneous alpha-numeric read-out system comprising a cathode ray tube including at least one electron beam; a memory for storing coded data designating the characters of a display frame; a pair of alternately operable registers coupled to said memory each capable of storing coded data designating characters to be displayed in a text line on said cathode ray tube; a pulse source connected to said alternately operable registers to advance said data in one of said registers for providing successive character designations at a rate controlled by said pulse source while the other of said registers receives data from said memory; circuit means for providing successive horizontal trace designations for traces of said electron beam; character generation circuit means operatively connected to said cathode ray tube, said alternately operable registers and said circuit means to control the intensity of said electron beam according to said successive horizontal trace and character designations; horizontal deflection circuit means coupled to said cathode ray tube to control the horizontal position of said electron beam; first counter means connected to said pulse source and operative to produce an output pulse after receiving a predetermined number of pulses from said pulse source, said first counter means being connected to said horizontal deflection circuit means to trigger successive horizontal sweeps of said electron beam, and being connected to said circuit means to advance said circuit means for successive horizontal trace designations; vertical deflection circuit means coupled to said cathode ray tube to control the vertical position of said electron beam; and second counter means coupled to said pulse source and said vertical deflection circuit means to trigger successive vertical sweeps of said electron beam in response to a predetermined number of pulses from said pulse source.

11. Apparatus according to claim 10 wherein the total number of horizontal traces of a display frame is an odd number and wherein said second counter means produces a pulse triggering a new vertical sweep each time one-half the total number of horizontal traces of a display frame have been completed to provide two interlaced display fields per display frame.

16. Apparatus according to claim 15 wherein said vertical deflection circuit means provides a linear vertical sweep signal; and further comprising a diddle sweep circuit operatively coupled to said vertical deflection circuit means to superimpose a diddle sweep signal upon said vertical sweep signal, said diddle sweep circuit being coupled to said circuit means and operative to initiate a new diddle sweep each time said circuit means is reset.

18. Apparatus according to claim 10 wherein said plurality of electron beams simultaneously form adjacent text lines of characters on said cathode ray tube.

20. An instantaneous read-out system comprising: a phosphor screen visible to viewers; means providing at least one electron beam adapted for scanning said screen; horizontal and vertical deflection means for controlling the position of said electron beam on said screen; a horizontal deflection drive circuit for energizing said horizontal deflection means to obtain repetitive horizontal traces of said electron beam across said screen, each horizontal trace being divided into a predetermined number of horizontal increments; storage means for storing coded data designating the characters of a display frame,; a pair of alternately operable registers coupled to said storage means each capable of storing coded data for designating characters of a complete text line display; circuit means coupled to said registers to advance the data in one of said registers in synchronism with the movement of said electron beam during each horizontal trace while the other of said registers is connected to receive data from said storage means; decoding means coupled to the one of said registers being advanced in synchronism with said electron beam for designating selected ones of said horizontal increments for display according to the coded character then designated; means coupled to said storage means and said means providing said electron beam to control said beam in on-off fashion according to the horizontal increments designated for display; and a vertical deflection drive circuit for energizing said vertical deflection means.

21. An instantaneous alpha-numeric visual read-out system comprising a phosphor screen visible to viewers; means providing a plurality of electron beams each adapted to scan said screen; horizontal and vertical deflection means for controlling the positions of said beams on said screen, said electron beams being oriented to cross one another substantially at the center of said horizontal and vertical deflection means; a horizontal deflection drive circuit for energizing said horizontal deflection means to obtain repetitive horizontal traces of said beams across said screen; means individually controlling the intensity of said electron beams in synchronism with said horizontal traces to achieve successive multi-line Displays on said screen, wherein each of said multi-line text displays being produced by a single one of said electron beams, and said electron beams simultaneously produce a group of adjacent text lines corresponding to the number of electron beams in the apparatus; and a vertical deflection drive circuit for energizing said vertical deflection means to move said beams vertically to achieve the desired interline spacing between horizontal traces.

22. An instantaneous alpha-numeric visual read-out system comprising a phosphor screen visible to viewers; means providing a plurality of electron beams each adapted to scan said screen; horizontal and vertical deflection means for controlling the positions of said beams on said screen, said electron beams being oriented to cross one another substantially at the center of said horizontal and vertical deflection means; a horizontal deflection drive circuit for energizing said horizontal deflection means to obtain repetitive horizontal traces of said beams across said screen; means individually controlling the intensity of said electron beams in synchronism with said horizontal traces to achieve successive multi-line text displays on said screen; a vertical deflection drive circuit for energizing said vertical deflection means to move said beams vertically to achieve the desired interline spacing between horizontal traces; and wherein said vertical deflection drive circuit so energizes said vertical deflection means that the interline scan within said text lines is less than the interline scan spacing between text lines, and said electron beams simultaneously produce a group of adjacent text lines equal to the number of electron beams in the apparatus and wherein the interline scan spacing between text lines is greater than the space occupied by a group of adjacent text lines.